Disclosure of Invention
The present invention aims to provide a general PMU structure supporting RISC-V instruction set, by which the area increase and the power consumption waste caused by the flexibility of PMU (power consumption control unit) can be reduced as much as possible while the problems presented in the above-mentioned background art can be solved.
In order to achieve the above purpose, the invention provides a general PMU structure supporting RISC-V instruction set, which is configured in a chip and comprises a PMU special register, an SRAM control module, a fetching module, a RSICV instruction set decoding execution module and a general register module;
The PMU special register control module is used for controlling the starting address and the decoding mode of the instruction fetching module, and is also used for triggering a wake-up source, converting the wake-up source into a corresponding starting signal after the wake-up source arrives, and controlling the whole PMU to enter a power-on program;
the SRAM control module is used for carrying reset contents of the PMU special register module and the general register module into an SRAM in the SRAM when the chip is in initial power-on state for first starting of the PMU, releasing registers of the PMU special register module and the general register module after carrying is completed, storing instructions corresponding to a RISC-V instruction set by the SRAM control module after the chip is started, and placing the instructions required by waking up into the SRAM in the SRAM before the chip is in a sleep state;
the RSICV instruction set decoding execution module is used for decoding an RSIC-V instruction set, executing corresponding operations simultaneously, including fetching data from a general register module and fetching a jump command, flushing a pipeline for part of jump commands, and inputting and outputting a power management control signal if the corresponding instruction exists after the corresponding operation is executed;
the general register module is used for sending the reset value and the default value to the SRAM control module when the chip is in an initial starting stage, and is used for caching intermediate variables operated by the RSIC-V instruction set when the chip is in a normal working stage.
Preferably, the special register control module for PMU stores the start control instruction of PMU without affecting the function of the register during the initialization process, and when the chip is started, the partial register is released and used as the function register.
Preferably, the working stage of the chip comprises an initial starting stage and a preparation stage for entering a sleep stage;
When the chip is in the initial start-up phase:
The SRAM control module carries reset values of the general register module and the PMU special register into the SRAM and releases the register to enter a normal mode, then the SRAM control module controls the instruction taking module to take the instruction, then the instruction taking module receives data and sends the data to the RSICV instruction set decoding execution module to decode and execute the instruction, and finally the RSICV instruction set decoding execution module outputs a power management control signal to finish the power-on work of the chip;
When the chip is in preparation for entering sleep stage:
The chip core writes the related instructions of sleep and wake-up into a PMU special register and synchronizes the related instructions into the SRAM through the SRAM control module; the core of the chip writes a sleep starting signal and an instruction fetch address, the PMU enters instruction fetch decoding execution, and the chip enters a sleep state through a power management control signal;
If the operation triggering the wake-up source exists, the PMU special register receives the wake-up source and configures the instruction fetching module to fetch the instruction from the wake-up initial address, the instruction fetching module receives the data and sends the data to the RSICV instruction set decoding execution module to decode and execute the instruction, the chip enters a normal working state, and then the chip works normally.
Compared with the prior art, the invention has the beneficial effects that:
The invention supports the PMU (power management unit) framework of RSICV instruction set, which can solve the problem of inflexibility of ASIC circuit, and eliminates unnecessary logic and function, reduces area and power consumption cost to the greatest extent, and the PMU (power management unit) module of the structure can be used as IP and multiplexed into a plurality of different projects.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
As shown in fig. 1, the PMU (power management unit) supported by the present invention includes the following modules:
a pmu specific register control module, the module comprising the following functions inside:
and a special register in the PMU (power management unit) for controlling the functions of starting address and decoding mode of the instruction fetching module.
B. meanwhile, during the initialization process, part of registers which do not affect functions are used for storing starting control instructions of PMUs (power management units). When the start-up is completed, the part of the register is released and continues to be used as a functional register.
C. the trigger for the wake-up source is converted into a corresponding initial signal after the wake-up source arrives, and the whole PMU (power management unit) is controlled to enter a power-on program.
D. The module has an interface for directly writing into a memory in the static random access memory control module, and data can be written into the memory by continuously writing into a certain address in the module.
2. SRAM static random access memory control:
a. During initial power up, the module will transfer the reset contents of the PMU specific register module and the general purpose register module to the internal memory for the first start-up of the PMU (power management module). And releasing the two module registers after the carrying is completed.
B. when the start is completed, the module is mainly used for storing instructions corresponding to RISC-V instruction sets. The instructions needed to wake up are placed into the memory before the system on chip is in a sleep state. When the wake-up source arrives, the instruction fetching module fetches instructions from the specified address into the wake-up program.
3. The instruction fetching module is mainly used for fetching corresponding instructions from the SRAM and sending the instructions to the RSICV decoding execution module for decoding execution operation. The start signal and start address of the block are generated by a PMU-specific register block.
RSICV instruction set decode execution module:
a. the module is used for decoding RSICV instruction sets, and the design only supports the most basic I instruction set in consideration of the power consumption area.
B. meanwhile, the module executes corresponding operations, including fetching data from the general register module and fetching commands such as jump.
C. for a partial jump command, the pipeline will be flushed.
D. after the corresponding operation is executed, if a corresponding instruction exists, the module controls the input and output of the power management signal.
5. General register module:
a. At start-up, the module will send a reset default to the SRAM (static random access memory) control module.
B. The module is used for caching RSICV intermediate variables of instruction operation in normal operation.
Further, as shown in FIG. 2, embodiments of the present invention also provide for implementing steps using a general PMU architecture that supports the RISC-V instruction set, as follows:
When power is on:
an SRAM (static random access memory) control module handles the reset values of general purpose registers and PMU specific registers into the SRAM and releases these registers into normal mode.
And b, controlling the fetching module to start fetching by the SRAM (static random access memory) control module.
C. the instruction fetching module receives the data and sends the data to the RSICV instruction set decoding execution module for instruction decoding and execution.
D. And controlling the power management signal to finish the power-on work of the chip.
The chip is ready to enter a sleep state:
a. the core of the chip writes the sleep and wake related instructions into PMU specific registers and synchronizes to SRAM (static random access memory) through the module.
B. The core of the chip writes the sleep start signal and the instruction fetch address, and the PMU (power management unit) enters the instruction fetch decoding execution and makes the chip enter the sleep state through the power management control signal.
Note that this step may be completely powered off after completion.
C. Triggering a wake-up source, and receiving the wake-up source by the PMU special register and configuring the instruction fetching module to fetch the instruction from the wake-up starting address.
D. After the instruction is fetched, decoded and executed, the chip enters a normal working state.
E. The chip works normally.
The invention supports the PMU (power management unit) architecture of RSICV instruction set, which can solve the problem of inflexibility of ASIC circuit, and eliminates unnecessary logic and function and reduces area and power consumption cost to the greatest extent compared with core directly using RISC-V. And the PMU (power management unit) module of this structure can be multiplexed into a plurality of different items as IP.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.