Detailed Description
The terminology used in the following embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
Fig. 1 is a schematic structural diagram of an electronic device 100 according to an embodiment of the present application. As shown in fig. 1, the electronic device 100 includes a processor 11, a display 13, a memory 14, a wireless communication module 15, and an audio module 16.
The processor 11 includes one or more processing units such as a central processing unit (central processing unit, CPU), a modem processor, a graphics processor (graphics processing unit, GPU), a data processor (Data Processing Unit, DPU), an image signal processor (IMAGE SIGNAL processor, ISP), a controller, a video codec, a digital signal processor (DIGITAL SIGNAL processor, DSP), a baseband processor, a neural network processor (neural-network processing unit, NPU), and the like. In an embodiment of the application, the processor 11 includes a display processor 12, such as a mobile display processor (mobile display processor, MDP). The display processor 12 is used for processing the image data and sending the processed image data to the display screen 13 for display.
The display 13 is for display. The display 13 includes a display panel. The display panel may employ a Liquid Crystal Display (LCD) CRYSTAL DISPLAY, an organic light-emitting diode (OLED), an active-matrix organic LIGHT EMITTING diode (AMOLED), a flexible light-emitting diode (flex), miniled, microled, micro-OLED, a quantum dot LIGHT EMITTING diodes (QLED), or the like. Preferably, the electronic device 100 uses a display processor 12 that matches the type of display 13 to achieve the best display.
The memory 14 includes one or more random access memories (random access memory, RAM) and one or more non-volatile memories (NVM). The RAM may be directly read from and written to by the processor 11, may be used to store an operating system or other executable programs that are running, may also be used to store data for users and applications, and the like. The NVM may also store executable programs and store data for users and applications. Executable programs and data stored in the NVM may be loaded in advance into RAM for direct reading and writing by the processor 11.
The wireless communication module 15 may provide wireless communication solutions including 2G/3G/4G/5G, wireless fidelity (WIRELESS FIDELITY, wi-Fi) network, bluetooth (BT), global navigation satellite system (global navigation SATELLITE SYSTEM, GNSS), frequency modulation (frequency modulation, FM), near Field Communication (NFC), infrared (IR) and the like applied to the electronic device 100 to provide wireless communication services to users.
The audio module 16 includes speakers, receivers, microphones, earphone interfaces, etc. for converting digital audio information into analog audio signal output and also for converting analog audio input into digital audio signals.
The processor 11 comprises one or more interfaces. The processor 11 may communicate with other components of the electronic device 100 (e.g., the display 13, the memory 14, etc.) through the interfaces described above. Such interfaces include, but are not limited to, an integrated circuit (inter-INTEGRATED CIRCUIT, I2C) interface, an integrated circuit built-in audio (inter-INTEGRATED CIRCUIT SOUND, I2S) interface, a pulse code modulation (pulse code modulation, PCM) interface, a universal asynchronous receiver transmitter (universal asynchronous receiver/transmitter, UART) interface, a mobile industry processor interface (mobile industry processor interface, MIPI), a general-purpose input/output (GPIO) interface, a subscriber identity module (subscriber identity module, SIM) interface, and/or a universal serial bus (universal serial bus, USB) interface, among others. Typically, the display processor 12 communicates with the display 13 via MIPI, e.g., the display processor 12 sends processed image data to the display 13 via MIPI for display.
It will be appreciated that the structural schematic diagram shown in fig. 1 does not constitute a specific limitation on the electronic device 100. The electronic device 100 may also include additional components such as external memory interfaces, universal serial bus (universal serial bus, USB) interfaces, keys, motors, indicators, cameras, subscriber identity module (subscriber identification module, SIM) card interfaces, sensor modules, and the like. The sensor module may include, among other things, a pressure sensor, a gyroscope sensor, a barometric sensor, a magnetic sensor, an acceleration sensor, a distance sensor, a proximity light sensor, a fingerprint sensor, a temperature sensor, a touch sensor, an ambient light sensor, a bone conduction sensor, etc. The embodiments of the present application are not limited in this regard.
Refresh rate-the number of images displayed per second by the display 13. Electronic devices 100 such as mobile phones and tablet computers typically dynamically adjust refresh rates for reducing power consumption and extending endurance. For example, the electronic device 100 may automatically adjust the refresh rate of the display screen according to the remaining power, the refresh rate requirement of the running application, and other factors.
For example, the electronic device 100 may set a default refresh rate of 90Hz, the electronic device 100 may set the refresh rate to 60Hz when detecting that the remaining power is less than or equal to a preset value, and the electronic device 100 may set the refresh rate to 120Hz when detecting that the gaming application is started and the remaining power is greater than the preset value.
On the basis of dynamically adjusting the refresh rate, the electronic device 100 may further execute any methods to further reduce power consumption, and prolong the endurance time, which is a problem that needs to be solved by the developer.
The higher the data transfer rate between the display processor 12 and the display screen 13, the higher the clock frequency of the display processor 12 and the higher the power consumption of the electronic device 100. In view of this, the embodiment of the application provides a data transmission method.
By implementing the method, the electronic device 100 can detect the target scene, and after the target scene is detected, the electronic device 100 can reduce the data transmission rate between the display processor 12 and the display screen 13, thereby reducing the clock frequency of the display processor 12, further reducing the power consumption of the electronic device 100, and prolonging the endurance time.
In an embodiment of the present application, executable program codes for implementing the data transmission method of the present application may be stored in the NVM. After the electronic device 100 is powered up, the electronic device 100 can load the executable program code stored in the NVM into RAM as described above. Thus, the electronic device 100 may detect the target scene, determine the target clock frequency according to the target scene, set the clock frequency of the display processor 12 to the target clock frequency, and update the data transmission rate between the display processor 12 and the display screen 13 correspondingly.
The electronic device 100 may be, but is not limited to, a cell phone, a tablet computer, a desktop computer, a laptop computer, a handheld computer, a notebook computer, an ultra-mobile personal computer (UMPC), a netbook, a cellular phone, a Personal Digital Assistant (PDA), an augmented reality (augmented reality, AR) device, a Virtual Reality (VR) device, an artificial intelligence (ARTIFICIAL INTELLIGENCE, AI) device, a wearable device, a vehicle-mounted device, a smart home device, and/or a smart city device, among other electronic devices configured with or connected to the display 13. The embodiment of the present application is not particularly limited as to the specific type of the electronic device 100.
Fig. 2 is a flowchart of a data transmission method according to an embodiment of the present application.
S201, detecting a target scene.
Preferably, the target scene is a low-power consumption scene, such as a super power saving scene, a screen-off display scene, and the like. Typically, an off-screen display scene is displayed, for example, in an all-weather display (always on display, AOD). In an off-screen display scenario, the electronic device 100 may continue to display some basic information, such as time, weather, notifications, etc., using the display 13.
The electronic device 100 may detect the target scene by detecting a preset user operation matching the target scene, and further enter the target scene by setting related parameters and states. For example, the electronic device 100 may detect a user operation acting on the super power saving control, and in response to the above operation, the electronic device 100 may start a super power saving application to enter a super power saving scene. For another example, electronic device 100 may detect a user operation on a power key, and in response to the operation, electronic device 100 may launch an AOD application into an AOD scene.
Fig. 3A-3C are schematic views of a set of user interfaces for entering super provincial scenes provided by an embodiment of the present application.
Fig. 3A is a setup interface of the electronic device 100 according to an embodiment of the present application. The settings interface includes a number of settings options such as WLAN, bluetooth, mobile network, battery, etc. As shown in fig. 3A, the electronic apparatus 100 may detect a user operation acting on a battery option, and in response to the above operation, the electronic apparatus 100 may display the battery setting interface shown in fig. 3B. The battery setup interface includes a plurality of battery mode options, such as performance mode, power saving mode, super power saving mode. The user can set the working mode of the electronic device 100 through the above battery mode option, so as to improve the performance or prolong the endurance, so as to meet different requirements of the user.
Referring to fig. 3B-3C, the electronic device 100 may detect a user operation acting in a super power saving mode, and in response to the operation, the electronic device 100 may start a super power saving application and enter a super power saving scene. Through the super power saving application, the electronic device 100 can switch to a dark mode, close the screen off display, limit the mobile phone performance, limit the number of applications used, change the desktop theme, close the background application, close or limit the positioning service, wireless fidelity (WIRELESS FIDELITY, wi-Fi), bluetooth and other wireless connection functions, reduce the operations such as screen brightness and the like, reduce the power consumption, and prolong the endurance time.
Referring to fig. 3C, after the super power saving application is started, the electronic device 100 may display the super power saving desktop. Preferably, the background of the super power-saving desktop is dark, and only preset application icons allowing running are displayed in the super power-saving desktop.
Fig. 4A-4B are schematic views of another set of user interfaces for entering super provincial scenes provided by embodiments of the present application.
Fig. 4A is a table top of the electronic device 100 in the non-super power saving mode according to the embodiment of the application. As shown in fig. 4A, the electronic apparatus 100 may detect a slide-down operation from the upper right edge of the screen, and in response to the above operation, the electronic apparatus 100 may display the control center interface shown in fig. 4B. The control center interface includes a plurality of shortcut controls such as WLAN, bluetooth, flashlight, personal hot spot, etc. The user can quickly and conveniently modify the related settings through the shortcut control. As shown in fig. 4B, the control center interface also includes a shortcut control 401. The shortcut control 401 may be used to turn on or off super power savings. When a user operation on the shortcut control 401 is detected, the electronic device 100 may launch a super power saving application, entering a super power saving scene. Referring to fig. 3C, in the super power saving landscape, the electronic device 100 may display a super power saving desktop.
Fig. 5A-5E are schematic diagrams of a set of user interfaces into an AOD scene provided by an embodiment of the present application.
Referring to fig. 5A, the electronic apparatus 100 may detect a user operation for the display and brightness options, and in response to the above operation, the electronic apparatus 100 may display the display and brightness setting interface shown in fig. 5B. The display and brightness setting interface includes an off-screen display option. As shown in fig. 5B, the electronic apparatus 100 may detect a user operation acting on the off-screen display option, and in response to the above operation, the electronic apparatus 100 may display the off-screen display setting interface shown in fig. 5C.
The off-screen display setup interface includes a switch 501. Referring to fig. 5C, electronic device 100 may detect a user operation acting on switch 501, and in response to the operation, electronic device 100 may launch an AOD application into an AOD scene. Referring to fig. 5D, after turning on the AOD, the electronic device 100 may detect a user operation acting on the key 502, and in response to the operation, the electronic device 100 may make an off-screen display. Referring to fig. 5E, the electronic device 100 may display basic information of time, date, etc. in a partial area of the screen.
S202, determining a target clock frequency corresponding to the target scene, and setting the clock frequency of the display processor 12 to the target clock frequency.
The electronic device 100 may be pre-configured with a clock profile. The clock configuration file records a plurality of target scenes, and the clock frequency of the display processor corresponding to each target scene, namely the target clock frequency. According to the load of different target scenes, the response sensitivity, the performance requirement and the attention degree of the user to the electronic equipment 100 in different target scenes are different, and the electronic equipment 100 can match different clock frequencies for different target scenes, so that the display requirement of the target scenes can be met, the power consumption can be reduced as much as possible, and the endurance time can be prolonged.
After detecting the target scene, the electronic device 100 may obtain the target clock frequency of the display processor 12 corresponding to the target scene through the clock configuration file. For example, after detecting the super power saving scene, the electronic device 100 may obtain the target clock frequency of the display processor 12 corresponding to the super power saving scene, for example, 0.33GHz through the clock configuration file, and after detecting the AOD scene, the electronic device 100 may obtain the target clock frequency of the display processor 12 corresponding to the AOD scene, for example, 0.15GHz through the clock configuration file.
The electronic device 100 may then set the clock frequency of the display processor 12 to the target clock frequency described above. For example, after determining the target clock frequency of 0.33GHz, electronic device 100 may set the clock frequency of display processor 12 (e.g., MDP) to 0.33GHz.
In some embodiments, display processor 12 opens an interface to set the clock frequency of display processor 12, at which point a developer may set the clock frequency of display processor 12 to the target clock frequency directly through the interface.
In other embodiments, display processor 12 does not have an interface to set the clock frequency of display processor 12. At this time, the developer may also set the clock frequency of the display processor 12 by setting the MIPI rate. MIPI Rate in MIPI, the amount of data transmitted per second, in bps/Lane.
Fig. 6A is a schematic diagram showing clock frequency and MIPI rate of the processor 12 according to an embodiment of the present application. Where the abscissa represents the clock frequency (GHz) of the display processor 12 and the ordinate represents the MIPI rate (bps/lane).
As shown in fig. 6A, the higher the clock frequency of the display processor 12, the higher the MIPI rate, and one clock frequency may correspond to a plurality of MIPI rates. For example, when the clock frequency of the display processor 12 is 0.33GHz, the MIPI rate may be 1Gbps/lane or 1.2Gbps/lane. The display processor 12 may adaptively adjust its own clock frequency based on the MIPI rate. Thus, the developer may set the clock frequency of the display processor 12 by setting the MIPI rate.
By way of example, when the electronic device 100 needs to set the clock frequency of the display processor 12 to 0.6GHz, the electronic device 100 may set the MIPI rate to 1.55Gbps/lane. According to the new MIPI rate of 1.55Gbps/Lane, display processor 12 may adaptively adjust its own clock frequency to 0.6GHz to match the new MIPI rate of 1.55Gbps/Lane.
It will be appreciated that when the clock frequency of the display processor 12 is directly set through the interface, after the clock frequency of the display processor 12 is set to the target clock frequency, the electronic device 100 also needs to adaptively set the MIPI rate to match the updated clock frequency of the display processor 12, so as to further reduce power consumption and increase the endurance time.
S203, updating the transmission time.
Transmission time TRANSFER TIME is the time at which the display processor 12 sends the processed image data to the display 13 for display via MIPI. The higher the MIPI rate, the less transmission time is required to transmit image data of the same specification to the display screen 13. I.e. the MIPI rate is inversely related to the transmission time.
After setting the clock frequency of the display processor 12 to the target clock frequency, the electronic device 100 may update the transmission time to match the updated MIPI rate. The electronic device 100 may determine a transmission time matching the updated MIPI rate by looking up a table. The matching MIPI rates and transmission times in the table may be empirically determined by the developer.
Referring to table 1, table 1 is a set of matched MIPI rates and transmission times provided by embodiments of the application.
TABLE 1
As shown in table 1, for example, after the MIPI rate is set to 0.6Gbps/lane (referring to fig. 6A, the clock frequency of the corresponding display processor 12 is 0.15 GHz), the electronic device 100 may update the transmission time to 15.83ms.
Fig. 6B is a transmission time waveform diagram according to an embodiment of the present application.
As shown in fig. 6B, the transmission time of the electronic device 100 may be set to 7.9ms, for example, before decreasing the MIPI rate by decreasing the clock frequency of the display processor 12. Before the 3 rd tear effect (TEARING EFFECT) signal arrives, the electronic device 100 may decrease the clock frequency of the display processor 12, decrease the MIPI rate, and update the transmission time according to the method shown in fig. 2. Illustratively, the electronic device 100 may update the transmission time to 15.83ms. Then, upon arrival of the 3 rd TE signal, the display processor 12 may send image data to the display screen at a new transmission time of 15.83ms.
In some embodiments, the target scene, such as a super power saving scene, an off screen display scene, etc., that triggers updating of the clock frequency of the display processor 12 is also the target scene that triggers dynamic adjustment of the refresh rate. At this time, after detecting the target scene, the electronic device 100 may simultaneously adjust the refresh rate of the display screen 13 and the clock frequency of the display processor 12, reducing power consumption to a greater extent by reducing the refresh rate and the clock frequency.
Taking the super power saving scenario as an example, after the super power saving scenario is detected, the electronic device 100 may determine, according to the method shown in fig. 2, on one hand, a clock frequency of the display processor 12 corresponding to the super power saving scenario, for example, 0.33GHz, update the clock frequency of the display processor 12 from 0.6GHz (first clock frequency) to 0.33GHz (second clock frequency), correspondingly update the MIPI rate between the display processor 12 and the display screen 13 from 1.5Gbps/lane (first MIPI rate) to 1.002Gbps/lane (second MIPI rate), update the transmission duration from 3.33ms (first transmission duration) to 7.9ms (second transmission duration), and on the other hand, the electronic device 100 may determine, according to a preset dynamic adjustment refresh rate method, a refresh rate corresponding to the super power saving scenario, for example, 60Hz, update the refresh rate of the display screen 13 from 90Hz (first refresh rate) to 60Hz (second refresh rate).
In other embodiments, the one or more target scenes that trigger updating the clock frequency of display processor 12 are not target scenes that trigger dynamically adjusting the refresh rate. At this time, after detecting the target scene triggering the update of the clock frequency of the display processor 12, the electronic device 100 adjusts only the clock frequency of the display processor 12, improving the flexibility of the power consumption policy.
By way of example, assume that an AOD scene is the target scene that triggers updating of the display processor 12 clock frequency, and not the target scene that triggers dynamic adjustment of refresh rate. At this time, after detecting the AOD scene, according to the method shown in FIG. 2, the electronic device 100 may determine a clock frequency of the display processor 12 corresponding to the AOD scene, for example, 0.15GHz, update the clock frequency of the display processor 12 from 0.6GHz (first clock frequency) to 0.15GHz (second clock frequency), correspondingly update the MIPI rate between the display processor 12 and the display screen 13 from 1.5Gbps/lane (first MIPI rate) to 0.6Gbps/lane (second MIPI rate), update the transmission duration from 3.33ms (first transmission duration) to 15.83ms (second transmission duration), and based on the AOD scene not triggering the target scene to dynamically adjust the refresh rate, the electronic device 100 may not update the refresh rate of the display screen 13 if other conditions remain unchanged, for example, the refresh rate of the display screen 13 is 60Hz until the AOD scene is detected, and the refresh rate of the display screen 13 continues to be kept at 60Hz after the AOD scene is detected.
Fig. 7A is a software configuration diagram of the electronic device 100 according to the embodiment of the present invention.
The software system of the electronic device 100 may employ a layered architecture, such as an Android system architecture. As shown in fig. 7A, the electronic device 100 adopting the Android system architecture includes an application Layer (Application Layer, abbreviated as application Layer), an application Framework Layer (Framework Layer, FWK), a hardware abstraction Layer (Hardware Abstract Layer, HAL), and a kernel Layer (KERNEL LAYER).
The application layer includes a package of a series of applications. In the embodiment of the application, the application layer at least comprises super power saving application and AOD application. In addition, the application layer may further include applications such as cameras, gallery, calendar, phone calls, music, video, short messages, etc., which are not illustrated herein.
The framework layer provides an application programming interface (application programming interface, API) and programming framework for applications at the application layer. As shown in fig. 7A, in an embodiment of the present application, the frame layer includes at least an image composition module (Surfaceflinger, SF) for rendering and compositing images. The framework layer may also include a window manager, content provider, view system, phone manager, resource manager, notification manager, etc., which are not further illustrated herein.
As shown in fig. 7A, the hardware abstraction layer includes a hardware synthesizer (Hardware Composer, HWC). HWC may provide hardware acceleration support for SF to achieve efficient display composition processing. The kernel layer includes a screen toolkit (LCDkit), a Spatial Database engine driver (Spatial Database ENGINE DRIVER, SDE DRIVER).
In an embodiment of the application, a developer may preset a clock profile at LCDKIT. Referring to table 2, the clock profile may record the following clock configuration information:
TABLE 2
| Scene(s) | Label (tag) | Clock frequency (clock frequency) |
| Defaults to | 1 | 0.6GHz |
| Super power saving | 2 | 0.33GHz |
| AOD | 3 | 0.15GHz |
| ...... | ...... | ...... |
After entering the target scenario according to the user operation, the system application implementing the target scenario may send a clock switching instruction to SDE DRIVER through SF, HWC. The instruction may carry a clock tag matching the target scene, for example, "1"/"2"/"3" shown in table 2, etc. Then SDE DRIVER may obtain a target clock frequency from a preset clock profile that matches the clock tag carried in the instruction, and SDE DRIVER may then instruct display processor 12 (e.g., MDP) to switch the clock frequency to the target clock frequency. Referring to S202, in the case of setting the clock frequency of the display processor 12 by setting the MIPI rate, SDE DRIVER may determine and update the MIPI rate that matches the above-described target clock frequency after determining the target clock frequency, and then, based on the relationship between the clock frequency of the display processor 12 and the MIPI rate, bring the clock frequency of the display processor 12 to the above-described target clock frequency. The display processor 12 then processes the image data at the target clock frequency and sends the processed image to the display screen for display.
For example, after the super power saving is started, the super power saving application implementing the super power saving function may send a clock switching instruction to SDE DRIVER through SF and HWC. At this time, the clock switching instruction may carry a clock tag "2" matching with the super power saving scene. By looking up the clock configuration file shown in Table 2, SDE DRIVER can determine the target clock frequency of 0.33GHz for clock tag "2". Then SDE DRIVER may instruct the MDP to switch the clock frequency to the target clock frequency of 0.33GHz.
Illustratively, after starting the AOD, the AOD application sends clock switching instructions to SDE DRIVER, also through SF, HWC. At this time, the clock switching instruction may carry a clock tag "3" that matches the AOD scene. By looking up the clock configuration file shown in Table 2, SDE DRIVER can determine the target clock frequency of 0.15GHz for clock tag "3". Then SDE DRIVER may instruct the MDP to switch the clock frequency to the target clock frequency of 0.15GHz.
In some embodiments, the clock configuration file may also be set in SDE DRIVER, so that SDE DRIVER may read the clock configuration information in the clock configuration file at any time.
Fig. 7B is a software architecture diagram of another electronic device 100 according to an embodiment of the invention.
As shown in fig. 7B, the software module executing "identify clock tag, determine target clock frequency" may also be HWC, and the clock profile may also be preset in HWC.
Specifically, after entering the target low power consumption scenario according to the user operation, after receiving the application layer sending clock switching instruction from the SF, the HWC may obtain, in response to the clock switching instruction, a clock tag carried in the clock switching instruction, for example, "1"/"2"/"3" shown in table 1, and so on. The HWC may then obtain a target clock frequency from a preset clock profile that matches the clock tag carried in the instruction, instructing the display processor 12 to switch the clock frequency to the target clock frequency.
For example, after the super power saving is started, the super power saving application implementing the super power saving function may send a clock switching instruction to the HWC through the SF. At this time, the clock switching instruction may carry a clock tag "2" matching with the super power saving scene. In response to the clock switching instruction described above, the HWC may look up the clock configuration file shown in Table 1 to determine the target clock frequency for clock tag "2", e.g., 0.33GHz. The HWC may then instruct the MDP to switch the clock frequency to the target clock frequency of 0.33GHz.
The first time Zhong Jiekou set_mode1 () provided by the HWC may determine the value of the MIPI rate, time of transmission, etc. related parameter that matches it based on the clock frequency of a given display processor 12, i.e., set_mode1 () may be used to modify the clock frequency of the display processor 12 and the MIPI rate, time of transmission, etc. related parameter that is related to the clock frequency of the display processor 12. For example, after determining the target clock frequency of 0.33GHz, the HWC may instruct the MDP via set_Mod1 (0.33) to switch the clock frequency to 0.33GHz, and update the MIPI rate to 1.002Gbps/lane matching the clock frequency of 0.33GHz, and update the transmission duration to 7.9ms matching the clock frequencies of 0.33GHz and the MIPI rate of 1.002 Gbps/lane.
The HWC is also provided with a second clock interface set_mod2 (). set_mode2 () can determine the value of the MIPI rate, transmission time, etc. related parameters that match it based on a given MIPI clock frequency, i.e., set_mode2 () can be used to modify the MIPI clock frequency and the MIPI rate, transmission time, etc. related parameters related to the MIPI clock frequency. The electronic device 100 may also set MIPI clock frequency and MIPI rate, transmission time, etc. by set_mod2 (), and cause the clock frequency of the display processor 12 to be updated to the target clock frequency indicated by the clock profile based on the relationship between the clock frequency of the display processor 12 and MIPI rate.
Compared to SDE DRIVER shown in fig. 7A, the electronic device 100 can update the clock frequency of the display processor, the MIPI rate, the transmission time, and other related parameters at one time through the first clock interface Zhong Jiekou and the second clock interface provided by the HWC, so as to save signaling expenditure and avoid omission.
Fig. 8A is a timing chart of a data transmission method according to an embodiment of the present application.
S300, starting a target application.
The electronic device 100 may start the target application through a preset user operation matched with the target scene, and enter the target scene. For example, referring to the user interfaces shown in fig. 3A-3C and fig. 4A-4B, the electronic device 100 may launch a super power save application into a super power save scene according to a user operation on the super power save control. For another example, referring to the user interfaces shown in fig. 5A-5E, after enabling the off-screen display, electronic device 100 may launch an AOD application into an AOD scene according to a user operation on a power key.
S301, the target application issues a clock switching instruction to SDE DRIVER. The clock switching instruction carries a clock label matched with the target application.
As shown in fig. 7A, the target application may issue a clock switching instruction carrying a corresponding clock tag to the kernel layer SDE DRIVER through the SF of the framework layer and the HWC of the hardware abstraction layer. For example, after the super power saving application is started, the super power saving application may send a clock switching instruction to SDE DRIVER through SF, HWC. At this time, the clock switching instruction issued by the super power saving application may carry a clock tag "2" matching the super power saving application. After launching the AOD application, the AOD application may send a clock switching instruction to SDE DRIVER via SF, HWC. At this time, the clock switching instruction issued by the AOD application may carry a clock tag "3" that matches the AOD application.
S302, the SDE Driver determines a target clock frequency according to the clock label.
In response to the clock switch instruction SDE DRIVER may obtain the clock profile. As shown in fig. 7A, in one embodiment, a clock profile is preset in LCDKIT modules. At this point SDE DRIVER may obtain the clock profile to LCDKIT.
After the clock configuration file is obtained, SDE DRIVER may query the clock configuration file to determine a target clock frequency corresponding to the clock tag carried in the clock switching instruction. For example, SDE DRIVER may determine, according to the clock configuration file, that the target clock frequency corresponding to the clock tag "2" is 0.33GHz when the clock tag carried in the clock switching instruction is "2", and SDE DRIVER may determine, according to the clock configuration file, that the target clock frequency corresponding to the clock tag "3" is 0.15GHz when the clock tag carried in the clock switching instruction is "3".
S303.sde Driver issues a clock switching instruction carrying the target clock frequency to display processor 12, instructing display processor 12 to switch to the target clock frequency.
For example, SDE DRIVER may issue a clock switching instruction to display processor 12 after determining the target clock frequency of 0.33GHz. At this time, the clock switching instruction may carry the target clock frequency of 0.33GHz. By default, the clock frequency of the display processor 12, e.g., MDP, may be 0.6GHz. In response to the above-described clock switching instruction, display processor 12 may switch the clock frequency from 0.6GHz to 0.33GHz.
Referring to S202, in the case of setting the clock frequency of the display processor 12 by setting the MIPI rate, SDE DRIVER may determine the MIPI rate (refer to fig. 6A) that matches the above-described target clock frequency after determining the target clock frequency, and thus determine the MIPI clock frequency. Wherein, the
MIPI rate = 2 x MIPI clock frequency
For example, when SDE DRIVER needs to set the clock frequency of the display processor 12 to 0.33GHz, SDE DRIVER may determine that the MIPI rate is 1.002GHz and thus the MIPI clock frequency is 0.501GHz according to the relationship between the clock frequency of the display processor 12 and the MIPI rate shown in FIG. 6A. Then SDE DRIVER updates the clock frequency of MIPI to 0.501GHz.
S304, updating the transmission time.
Referring to table 1, the electronic device 100 may determine the transmission time matched with the updated target clock frequency and MIPI rate through a table lookup, which will not be described herein.
S305, the display processor 12 processes and displays the image data according to the updated clock frequency and transmission time.
Fig. 8B is a timing chart of another data transmission method according to an embodiment of the present application.
S310, starting a target application.
S311, the target application issues a clock switching instruction to the HWC. The clock switching instruction carries a clock label matched with the target application.
For example, after the super power saving application is started, the super power saving application may send a clock switching instruction to the HWC through the SF. At this time, the clock switching instruction issued by the super power saving application may carry a clock tag "2" matching the super power saving application.
S312, the HWC determines the target clock frequency according to the clock tag.
As shown in fig. 7B, in response to the clock switching instruction, the HWC may obtain a clock profile, determine a target clock frequency corresponding to the clock tag carried in the clock switching instruction, e.g., a target clock frequency of 0.33GHz matching clock tag "2".
S313.hwc sets the clock frequency of the display processor, and related parameters such as MIPI rate, transmission time, etc., through set_mod1 () or set_mod2 (). With specific reference to the description of fig. 7B, details are not repeated here.
S314, the display processor processes and displays the image data according to the updated clock frequency, transmission time and the like.
Further, the electronic device 100 may also perform finer scene classification on the target scene. For one target scenario, the electronic device 100 may set different clock frequencies of the display processor 12 to further save power consumption and extend endurance.
Accordingly, the clock profile may also include more tags that match different clock frequencies. The application can issue different labels according to the specific scene where the application is currently located, and then different clock frequencies are set.
TABLE 3 Table 3
As shown in table 3, the clock labels that can be sent by the super power saving application include "2.1", "2.2". The clock frequency corresponding to the clock label 2.1 is 0.33GHz, and the clock frequency corresponding to the clock label 2.2 is 0.5GHz. The clock labels that the AOD application can send include "3.1", "3.2". The clock frequency corresponding to the clock label '3.1' is 0.15GHz, and the clock frequency corresponding to the clock label '3.2' is 0.3GHz.
Specifically, in some embodiments, the electronic device 100 may identify applications that are running in super power saving scenarios. The electronic device 100 may boost the clock frequency of the display processor 12 when the display-intensive applications are running, and the electronic device 100 may restore the clock frequency of the display processor 12 to the lowest clock frequency in the super power saving scenario when no display-intensive applications are running.
Fig. 9 is a flowchart of another data transmission method according to an embodiment of the present application.
S401, detecting a super power saving scene.
S402, determining the minimum clock frequency of the super power saving scene, and setting the clock frequency of the display processor 12 to the minimum clock frequency.
In the embodiment of the application, after the super power-saving application is started, the super power-saving application can firstly issue a clock switching instruction carrying a clock tag of 2.1. Taking the software structure shown in fig. 7B as an example, in response to the above instruction, the HWC may determine the target clock frequency of 0.33GHz of the clock tag "2.1", that is, the minimum clock frequency in the super power saving scene (including the target clock frequencies of 0.33GHz and 0.5 GHz), and then the HWC may switch the clock frequency of the display processor 12 to the target clock frequency of 0.33GHz through set_mode1 () or set_mode2 (), and update the relevant parameters such as the transmission time and the like to match the target clock frequency.
S404, under the super power saving scene, the start-up of the display intensive application is detected.
Display-intensive applications refer to applications that require frequent updates of display content, including but not limited to gaming applications, camera applications, video applications, image editing applications, and the like. In the super power saving scenario, a user's operation to open one or more display-intensive applications may be detected at the electronic device 100.
S405, determining a target clock frequency when the display intensive application is running, and setting the clock frequency of the display processor 12 to the target clock frequency.
After detecting the start of the display-intensive application, for example, after detecting the start of the camera application, the super power-saving application may issue a new clock switching instruction. At this time, the clock switching instruction carries a new clock tag, for example, "2.2". The new clock tag corresponds to a higher clock frequency. In response to the new clock switching instruction, the HWC may determine a new target clock frequency corresponding to the new clock tag, and then the HWC may switch the clock frequency of the display processor 12 to the new target clock frequency through set_mod1 () or set_mod2 (), while updating the MIPI rate, transmission time, and other related parameters to match the target clock frequency to meet the display requirements of the display-intensive application.
For example, the HWC may determine the target clock frequency 0.5GHz corresponding to the new clock tag "2.2", and then the HWC may switch the clock frequency of the display processor 12 to the new target clock frequency 0.5GHz through set_mod1 () or set_mod2 (), while updating the MIPI rate, transmission time, etc. related parameters to match the target clock frequency 0.5 GHz.
In some embodiments, the electronic device 100 may detect the number of layers in a super power save scene or an AOD scene. The electronic device 100 may further fine tune the clock frequency of the display processor 12 based on the current number of layers.
Fig. 10 is a flowchart of another data transmission method according to an embodiment of the present application.
S501, detecting a target scene.
S502, determining the minimum clock frequency of the target scene, and setting the clock frequency of the display processor 12 to the minimum clock frequency.
Also taking the super power saving scenario and the software structure shown in fig. 7B as an example, after the super power saving application is started, the super power saving application may first issue a clock switching command carrying the clock tag "2.1". In response to the above instruction, the HWC may determine the target clock frequency of 0.33GHz for clock tag "2.1", i.e., the minimum clock frequency in super power saving scenarios (including target clock frequencies of 0.33GHz and 0.5 GHz), and then the HWC may switch the clock frequency of the display processor 12 to the target clock frequency of 0.33GHz through set_mod1 () or set_mod2 (), while updating the MIPI rate, transmission time, and other related parameters to match the target clock frequency.
S504, detecting that the number of the current layers exceeds a threshold value.
After the super power saving application is started, the super power saving application can acquire the current layer number, particularly the current changing layer number needing to be drawn and updated. The layer threshold M1 is preset in the super power saving application. When the current layer number or the changed layer number is greater than M1, the super power saving application may determine that the current layer number exceeds a preset value.
S505, determining a target clock frequency corresponding to the number of the current layers, and setting the clock frequency of the display processor 12 to the target clock frequency.
Taking the current number of images as an example, after the current number of images exceeds the threshold M1, the super power saving application may issue a new clock switching instruction. At this time, the clock switching instruction carries a new clock tag, for example, "2.2". The new clock tag corresponds to a higher clock frequency. In response to a new clock switch instruction, the HWC may determine a new target clock frequency to which the new clock tag corresponds, and then the HWC may instruct the display processor 12 to switch to the new target clock frequency. For example, the HWC may determine the target clock frequency 0.5GHz corresponding to the new clock tag "2.2", and then the HWC may switch the clock frequency of the display processor 12 to the new target clock frequency 0.5GHz through set_mod1 () or set_mod2 (), while updating the MIPI rate, transmission time, etc. related parameters to match the target clock frequency to meet the display requirements including more layers.
Illustratively, the layer threshold m1=5. When the number of the current layers or the number of the changed layers is within 1-5 (comprising boundary values of 1 and 5 and a first range), the target clock frequency is 0.33GHz, and when the number of the current layers or the number of the changed layers is greater than 5 (a second range), the target clock frequency is 0.5GHz.
Referring to table 4, in some embodiments, the super power save application may also set more number of intervals of layers, match more clock frequencies, and provide a finer dynamic clock adjustment strategy for the electronic device 100.
TABLE 4 Table 4
| Label (tag) | Number of layers interval | Clock frequency (clock frequency) |
| 2.1 | 1~5 | 0.33GHz |
| 2.3 | 6~10 | 0.4GHz |
| 2.2 | 10~15 | 0.5GHz |
| ...... | ...... | ...... |
The super power-saving application can issue clock switching instructions carrying different clock labels according to the number of layers interval where the current number of layers is located, so as to update the clock frequency of the display processor 12 according to the current number of layers.
Similarly, the AOD application may also detect the current layer number, determine a target clock frequency corresponding to the current layer number, and instruct the display processor 12 to use the new target clock frequency, which is not described herein.
In some embodiments, the electronic device 100 may also implement the data transmission methods shown in fig. 9 and 10. That is, the electronic device 100 may identify an application running in the super power saving scene, and when a display-intensive application is running, the electronic device 100 may increase the clock frequency of the display processor 12, and at the same time, the electronic device 100 may detect the number of layers in the super power saving scene or the AOD scene, and update the clock frequency of the display processor 12 according to the current number of layers.
As used in the specification of the present application and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include the plural forms as well, unless the context clearly indicates to the contrary. It should also be understood that the term "and/or" as used in this disclosure refers to and encompasses any or all possible combinations of one or more of the listed items. As used in the above embodiments, the term "when..is interpreted as meaning" if..or "after..or" in response to determining..or "in response to detecting..is" depending on the context. Similarly, the phrase "when determining..or" if (a stated condition or event) is detected "may be interpreted to mean" if determined.+ -. "or" in response to determining.+ -. "or" when (a stated condition or event) is detected "or" in response to (a stated condition or event) "depending on the context.
In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line), or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk), etc.
Those of ordinary skill in the art will appreciate that implementing all or part of the above-described method embodiments may be accomplished by a computer program to instruct related hardware, the program may be stored in a computer readable storage medium, and the program may include the above-described method embodiments when executed. The storage medium includes a ROM or a random access memory RAM, a magnetic disk or an optical disk, and other various media capable of storing program codes.