Disclosure of Invention
In view of the foregoing, embodiments of the present disclosure provide a semiconductor structure and an electronic device.
In a first aspect, embodiments of the present disclosure provide a semiconductor structure, comprising:
a plurality of sense amplifying circuits arranged along a first direction, wherein devices in the sense amplifying circuits are arranged on an active device layer;
a plurality of wire groups arranged along the first direction, wherein the wire groups are arranged on a first conductive layer above the active device layer, and one wire group is connected with a device in a corresponding sense amplifying circuit;
The sense amplifier circuit comprises a sense amplifier circuit, a first wire group, a second wire group, a first wire, a second wire, a first voltage source, a second voltage source, a first voltage source and a second voltage source, wherein the sense amplifier circuit comprises a first wire and a second wire;
the first direction and the second direction are two intersecting directions on a plane of the semiconductor structure.
In some embodiments, the semiconductor structure further includes memory arrays located on both sides of the plurality of sense amplifying circuits along the second direction;
The wire set comprises a sensing wire, a complementary sensing wire, a bit wire and a complementary bit wire, wherein the bit wire is from the memory array on the first side, the complementary bit wire is from the memory array on the second side, the sensing wire is used for transmitting data to the bit wire, and the complementary sensing wire is used for transmitting data to the complementary bit wire;
The first conductive line is one of the bit line, the complementary bit line, the sense line, or the complementary sense line, and the second conductive line is one of the sense line or the complementary sense line.
In some embodiments, the plurality of sense amplifying circuits is divided into a number of sense amplifying circuit groups, each of the sense amplifying circuit groups including two non-repeating of the sense amplifying circuits arranged along the first direction;
The wire sets corresponding to the two sense amplifying circuits in the same sense amplifying circuit set are a first wire set and a second wire set respectively;
The first part of the first wire set and the first part of the second wire set are mirror symmetrical along the second direction, and the second part of the first wire set coincides with the second part of the second wire set after being translated along the first direction;
Or alternatively
The first wire set is overlapped with the second wire set after being translated along the first direction;
Or alternatively
The first wire set and the second wire set are mirror symmetrical along the second direction.
In some embodiments, for the first wire set, the first end of the sense line is located on a side of the first end of the complementary bit line away from the second wire set; the first end of the sensing line is the end of the sensing line close to the complementary bit line, and the first end of the complementary bit line is the end of the complementary bit line far away from the sensing line;
The sensing lines in the second wire set are mirror symmetrical with the sensing lines in the first wire set.
In some embodiments, the first conductive layer is a single conductive layer, the first conductive line is a complementary bit line, and the second conductive line is a sense line.
In some embodiments, the sense line of the first conductor set includes a first subsection, a second subsection, and a third subsection, and the complementary bit line of the first conductor set includes a fourth subsection and a fifth subsection;
The first subsection, the fifth subsection and the third subsection are sequentially arranged along the second direction;
the fourth subsection, the second subsection and the complementary sensing lines of the first wire group are sequentially arranged along the second direction;
The third subsection and the complementary sensing lines of the first wire group are adjacently arranged along the first direction;
The first subsection is positioned at one side of the fourth subsection away from the second wire group;
the second wire set is mirror symmetrical to the first wire set.
In some embodiments, the complementary sense lines of the first wire set, the complementary bit lines of the third wire set, the complementary bit lines of the fourth wire set, and the complementary sense lines of the second wire set are arranged sequentially along the first direction;
The sense amplifying circuits corresponding to the third wire set and the sense amplifying circuits corresponding to the first wire set respectively belong to the sense amplifying circuit sets adjacent to each other along the second direction, and the sense amplifying circuits corresponding to the fourth wire set and the sense amplifying circuits corresponding to the second wire set respectively belong to the sense amplifying circuit sets adjacent to each other along the second direction.
In some embodiments, the first sub-segment and the second sub-segment are connected by a connection structure of the same conductive layer, and the second sub-segment and the third sub-segment are connected by a connection structure of the same conductive layer;
The fourth sub-segment and the fifth sub-segment are connected by a connection structure crossing different conductive layers or by a gate layer.
In some embodiments, the first conductive layer includes a first conductive sub-layer and a second conductive sub-layer stacked along a third direction;
the sensing line and the complementary sensing line of the same wire group are twisted, and the third direction is perpendicular to the plane of the semiconductor structure.
In some embodiments, the sense lines of the second conductor set are twisted with complementary bit lines of the second conductor set.
In some embodiments, at least a portion of the complementary bit lines, sense lines, complementary sense lines of the first conductor set and at least a portion of the complementary bit lines, sense lines, complementary sense lines of the second conductor set are all located in the first conductive sublayer;
the sensing line of the first wire group comprises a first subsection and a second subsection, the complementary sensing line of the first wire group comprises a third subsection and a fourth subsection, the sensing line of the second wire group comprises a fifth subsection, a sixth subsection and a seventh subsection, the complementary sensing line of the second wire group comprises an eighth subsection and a ninth subsection, and the complementary bit line of the second wire group comprises a tenth subsection and an eleventh subsection, and the first subsection to the eleventh subsection extend along the second direction;
the third sub-segment and the second sub-segment are aligned along the second direction;
the first subsection, the fourth subsection, and complementary bit lines of the first wire set are aligned along the second direction;
the eighth sub-segment, the sixth sub-segment, the tenth sub-segment being aligned along the second direction;
The fifth subsection, the ninth subsection the eleventh sub-segment and the seventh sub-segment are aligned along the second direction;
the third sub-segment, the first sub-segment, the eighth sub-segment and the fifth sub-segment are sequentially arranged along the first direction;
the second sub-segment, the fourth sub-segment, the sixth sub-segment, and the ninth sub-segment are sequentially arranged along the first direction.
In some embodiments, the complementary bit lines of the third wire set and the complementary bit lines of the fourth wire set are located in the second conductive sub-layer;
The projections of the complementary bit lines of the fourth wire group and the complementary bit lines of the second wire group along the third direction are at least partially overlapped;
The sense amplifying circuits corresponding to the third wire set and the sense amplifying circuits corresponding to the first wire set respectively belong to the sense amplifying circuit sets adjacent to each other along the second direction, and the sense amplifying circuits corresponding to the fourth wire set and the sense amplifying circuits corresponding to the second wire set respectively belong to the sense amplifying circuit sets adjacent to each other along the second direction.
In some embodiments, the first sub-segment and the second sub-segment are connected by a connection structure of the same conductive layer, and the fifth sub-segment and the sixth sub-segment are connected by a connection structure of the same conductive layer;
The third sub-segment and the fourth sub-segment are connected through a connection structure crossing different conductive layers or through a gate layer;
the eighth subsection and the ninth subsection are connected through a connection structure crossing different conductive layers or through the gate layer;
The tenth and eleventh sub-segments are connected by a connection structure across different conductive layers or by the gate layer.
In some embodiments, a projection of the first subsection in a third direction is located on an N-type amplifying tube of the sense amplifying circuit;
the projection of the fifth subsection in the third direction is located on a bias elimination transistor or a precharge transistor of the sense amplifying circuit.
In some embodiments, a projection of the seventh subsection in the third direction is located on an N-type amplifying tube of the sense amplifying circuit;
the projection of the eleventh subsection in the third direction is positioned on an isolation transistor or a precharge transistor of the sense amplifying circuit;
And the projections of the fourth subsection and the ninth subsection in the third direction are positioned on a P-type amplifying tube of the sensing amplifying circuit.
In a second aspect, embodiments of the present disclosure provide a semiconductor structure as in any one of the above embodiments.
The embodiment of the disclosure provides a semiconductor structure and electronic equipment, wherein the semiconductor structure comprises a plurality of sense amplifying circuits which are arranged along a first direction, devices in the sense amplifying circuits are arranged on an active device layer, a plurality of wire groups which are arranged along the first direction, a first conductive layer which is arranged above the active device layer and connected with the devices in a corresponding sense amplifying circuit, the wire groups comprise first wires and second wires, at least part of the first wires and the second wires in the same wire group which correspond to the sense amplifying circuits are twisted, at least part of the second wires are positioned between the first wires in different wire groups, and when the sense amplifying circuits are in an amplifying stage, the electric potential of the first wires and the electric potential of the second wires in the same wire group represent different data.
Here, since the first wire and the second wire both extend in the second direction and the first wire and the second wire inside the same wire group are twisted, at least part of the second wire is located between the first wires in different wire groups; further, when the sense amplifying circuit is in the amplifying stage, the voltage of the first wire of the other group can affect the voltages of the first wire and the second wire of the current wire group, that is, the voltages of the first wire and the second wire of the current wire group are simultaneously pulled up or pulled down, so that the voltage difference between the first wire and the second wire of the current wire group is reduced due to the fact that the voltage of the first wire (or the second wire) of the current wire group is only affected, and the sense amplifying circuit is guaranteed to be capable of effectively amplifying data.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, well-known functions and constructions are not described in detail to avoid obscuring the present disclosure, i.e., not all features of an actual embodiment are described herein.
In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present in the present disclosure.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Before describing embodiments of the present disclosure, three directions describing a three-dimensional structure that may be used in the following embodiments are defined, and may include a first (X-axis) direction, a second (Y-axis) direction, and a third (Z-axis) direction. The Z-axis direction may be a direction perpendicular to a plane in which the semiconductor structure is located, and the X-axis direction and the Y-axis direction are two directions perpendicular to each other on the plane in which the semiconductor structure is located, wherein the Y-axis direction may be a direction in which the first conductive line extends.
The disclosed embodiment provides a semiconductor structure 100, as shown in fig. 1 and 2, wherein the semiconductor structure 100 comprises a plurality of sense amplifying circuits SA (refer to fig. 2) arranged along an X-axis direction, devices in the sense amplifying circuits SA (SENSING AMPLIFIER Circuit) are arranged on an active device layer, a plurality of wire groups 110 (refer to fig. 1) arranged along the X-axis direction, the wire groups 110 are arranged on a first conductive layer above the active device layer, one wire group 110 is connected with the devices in the corresponding sense amplifying circuits SA, the wire groups 110 comprise a first wire 111 and a second wire 112, the first wire 111 and the second wire 112 extend along a Y-axis direction, the first wire 111 and the second wire 112 inside the same wire group 110 are twisted, at least part of the second wire 112 is positioned between the first wires 111 in different wire groups 110, and when the sense amplifying circuits are in an amplifying stage, the potential characteristics of the first wires 111 in the same wire group are different from the potential characteristics of the second wires 112.
Note that the devices in the sense amplifier circuit SA are not shown in fig. 1, and only the first wire 111 and the second wire 112 in one wire group 110 and the first wire 111 in an adjacent wire group 110 are shown.
In the embodiment of the disclosure, the active device layer is a core functional layer in the semiconductor structure 100, and the devices in the sense amplifying circuit SA include active elements such as transistors, for example, N-type amplifying tubes, P-type amplifying tubes, and the like. The first conductive layer may be a first Metal layer (Metal 1, M1) in the semiconductor structure 100, the first Metal layer being a Metal layer closest to the active device layer for transmitting signals and routing, and the ports (e.g., source, drain, and gate of a transistor) of different devices in the sense amplifier circuit SA may be connected to higher layer Metal wirings (e.g., second Metal layer Metal2, M2) through a set of wires 110 disposed in the first conductive layer, the second Metal layer being another Metal layer located above and closest to the first Metal layer.
In the embodiment of the disclosure, please continue to refer to fig. 1, in which the first conductive line 111 and the second conductive line 112 both extend along the Y-axis direction, it means that the main portions of the first conductive line 111 and the second conductive line 112 extend along the Y-axis direction, but not each portion extends along the Y-axis direction. That is, the first and second wires 111 and 112 may have portions extending in the X-axis direction or the Z-axis direction due to portions of routing, winding, or jumping. For example, inside the same wire group 110, the first wire 111 extends partially in the Y-axis direction, then extends in the X-axis direction, jumps to the track of the second wire 112, and then extends in the Y-axis direction.
In the embodiment of the disclosure, please continue to refer to fig. 1, in which the first conductive line 111 and the second conductive line 112 in the same conductive line set 110 are twisted, that is, the first conductive line 111 and the second conductive line 112 in the same conductive line set 110 are periodically exchanged in left and right positions or at least exchanged with each other in a line path (similar to a DNA duplex structure), for example, in the same conductive line set 110, the second conductive line 112 is jumped to the line path of the first conductive line 111 in the extending path, and at the same time, the first conductive line 111 is jumped to the line path of the second conductive line 112 in the extending path.
In addition, in the embodiment of the disclosure, please continue to refer to fig. 1, at least a portion of the second conductive lines 112 are located between the first conductive lines 111 in the different conductive line groups 110, which means that at least a portion of the second conductive lines 112 are located between the first conductive lines 111 in the conductive line group 110 where the second conductive lines 112 are located and the first conductive lines 111 in the other conductive line group.
It should be noted that, in the embodiment of the disclosure, the data of the different conductive lines 110 may be the same or different, and because the first conductive line 111 and the second conductive line 112 in the same conductive line 110 represent different data, the first conductive line 111 may be a bit line or an internal wiring connected to the bit line in the sense amplifying circuit SA, the second conductive line 112 may be a complementary bit line or an internal wiring connected to the complementary bit line in the sense amplifying circuit SA, and at this time, since at least part of the second conductive line 112 is located between the first conductive lines 111 in the different groups, the voltage of the first conductive line 111 in the other group may affect the voltages of the first conductive line 111 and the second conductive line 112 in the current conductive line group, that is, the voltages of the first conductive line 111 and the second conductive line 112 in the current conductive line group are pulled up or pulled down simultaneously, which is beneficial to avoid the voltage difference of the first conductive line 111 and the second conductive line 112 in the current conductive line group from being reduced due to affecting only the voltages of the first conductive line 111 (or the second conductive line 112) in the current conductive line group, thereby ensuring that the sense amplifying circuit can effectively amplify the data.
Next, please refer to fig. 2 to 12, a detailed description is given of the semiconductor structure 100.
In some embodiments, referring to FIGS. 2 and 3, the semiconductor structure 100 further comprises a memory array 120 located on both sides of the plurality of sense amplifier circuits SA along the Y-axis direction, the set of conductive lines 110 comprises a sense line SABL, a complementary sense line SABLB, a bit line BL and a complementary bit line BLB, the bit line BL is from the memory array 120 on the first side, the complementary bit line BLB is from the memory array 120 on the second side, the sense line SABL is used to transmit data to the bit line BL, the complementary sense line SABLB is used to transmit data to the complementary bit line BLB, the first conductive line 111 is one of the bit line BL, the complementary bit line BLB, the sense line SABL or the complementary sense line SABLB, and the second conductive line 112 is one of the sense line SABL or the complementary sense line SABLB. When the sense amplifying circuit SA is in the amplifying stage, the potential of the first conductive line 111 and the potential of the second conductive line 112 represent different data.
In the embodiment of the disclosure, the memory array 120 has n rows and m columns of memory cells, each memory cell is used for storing 1bit (bit) of data, that is, one memory array 120 can store n×mbit of data, after one word line is gated, a specific memory cell is selected through a switch unit corresponding to a gate column address, and the memory data in the memory cell is read out or written into the memory cell, where n and m are positive integers.
Note that, in fig. 2, only 2 memory arrays 120 are shown and arranged along the Y-axis direction, and a plurality of sense amplifying circuits SA (shown as 2 rows, each row being 4 as an example) are located between the 2 memory arrays 120, in practice, the semiconductor structure 100 may include a plurality of memory arrays 120 arranged along the Y-axis direction, and a plurality of sense amplifying circuits SA are located between adjacent memory arrays 120 (for example, two rows along the Y-axis direction, each row having 256 sense amplifying circuits SA). In addition, a word line WL connected to the memory array 120 is also schematically shown in fig. 2.
Further, referring to fig. 2, the sense amplifier circuit SA is coupled to the memory array 120 on the first side through the bit line BL, and coupled to the memory array 120 on the second side through the complementary bit line BLB, for sensing the voltage of the memory cell and outputting a logic 1 or 0 corresponding to the voltage.
In some embodiments, the devices in sense amp circuit SA include a sense amp module coupled to bit line BL through sense line SABL and to complementary bit line BLB through complementary sense line SABLB for sensing the voltage of a memory cell in the memory array and outputting a logic 1 or 0 corresponding to the voltage.
Specifically, please continue to refer to fig. 3, the sense amplifier module includes a first N-type amplifying tube M7, a second N-type amplifying tube M8, a first P-type amplifying tube M1 and a second P-type amplifying tube M2. The gate of the first N-type amplifying tube M7 is connected with the bit line BL, the drain of the first N-type amplifying tube M7 is connected with the complementary sensing line SABLB, the source of the first N-type amplifying tube is connected with the second signal end NCS, and when the sensing amplifying module is in an amplifying stage, the second signal end NCS is electrically connected with a voltage corresponding to logic 0. The gate of the second N-type amplifying tube M8 is connected with the complementary bit line BLB, the drain of the second N-type amplifying tube M8 is connected with the sensing line SABL, and the source of the second N-type amplifying tube M8 is connected with the second signal end NCS. The first N-type amplifying transistor M7 and the second N-type amplifying transistor M8 are NMOS (Negative channelMetalOxide Semiconductor, N-type metal oxide semiconductor) transistors. The grid electrode of the first P-type amplifying tube M1 is connected with the sensing line SABL, the drain electrode of the first P-type amplifying tube M1 is connected with the complementary sensing line SABLB, the source electrode of the first P-type amplifying tube M1 is connected with the first signal end PCS, and when the sensing amplifying module is in an amplifying stage, the first signal end PCS is electrically connected with a voltage corresponding to logic 1. The grid electrode of the second P-type amplifying tube M2 is connected with the complementary sensing line SABLB, the drain electrode of the second P-type amplifying tube M2 is connected with the sensing line SABL, and the source electrode of the second P-type amplifying tube M2 is connected with the first signal end PCS. The first P-type amplifying transistor M1 and the second P-type amplifying transistor M2 are PMOS (Positive channelMetalOxide Semiconductor, P-type metal oxide semiconductor) transistors.
In some embodiments, the device in sense amp circuit SA further includes an isolation module connected between sense line SABL and bit line BL and between complementary sense line SABLB and complementary bit line BLB for isolating or enabling a change in potential between bit line BL and sense line SABL and isolating or enabling a change in potential between complementary bit line BLB and complementary sense line SABLB according to isolation signal iso.
Specifically, please continue to refer to fig. 3, the isolation module includes a first isolation transistor M3 and a second isolation transistor M4, wherein a gate of the first isolation transistor M3 is configured to receive the isolation signal iso, a source of the first isolation transistor M3 is connected to the bit line BL, and a drain of the first isolation transistor M3 is connected to the sensing line SABL. The gate of the second isolation transistor M4 is for receiving the isolation signal iso, the source of the second isolation transistor M4 is connected to the complementary bit line BLB, and the drain of the second isolation transistor M4 is connected to the complementary sense line SABLB.
In some embodiments, the device in the sense amp circuit SA further includes a bias elimination module connected between the sense line SABL and the complementary bit line BLB and between the complementary sense line SABLB and the bit line BL for eliminating a threshold voltage deviation between the first N-type amplifier M7 and the second N-type amplifier M8 in the sense amp module according to the bias elimination signal Oc.
Specifically, please continue to refer to fig. 3, the bias eliminating module includes a first bias eliminating transistor M5 and a second bias eliminating transistor M6, wherein a gate of the first bias eliminating transistor M5 is configured to receive the bias eliminating signal Oc, a source of the first bias eliminating transistor M5 is connected to the bit line BL, and a drain of the first bias eliminating transistor M5 is connected to the complementary sensing line SABLB. The gate of the second bias eliminating transistor M6 is for receiving the bias eliminating signal Oc, the source of the second bias eliminating transistor M6 is connected to the complementary bit line BLB, and the drain of the second bias eliminating transistor M6 is connected to the sense line SABL.
In some embodiments, please continue to refer to fig. 3, the semiconductor structure further includes a first column selection transistor M10 and a second column selection transistor M11, wherein the first column selection transistor M10 is disposed between the local data line LIO and the bit line BL, a gate of the first column selection transistor M10 is configured to receive the selection signal CSL, a source of the first column selection transistor M10 is connected to the bit line BL, and a drain of the first column selection transistor M10 is connected to the local data line LIO. The second column selecting transistor M11 is arranged between the local complementary data line LION and the complementary bit line BLB, the grid electrode of the second column selecting transistor M11 is used for receiving the selecting signal CSL, the source electrode of the second column selecting transistor M11 is connected with the complementary bit line BLB, and the drain electrode of the second column selecting transistor M11 is connected with the local complementary data line LION.
In some embodiments, the devices in sense amp circuit SA further include a precharge transistor M9, wherein the drain of precharge transistor M9 is connected to sense line SABL and/or complementary sense line SABLB, the gate of precharge transistor M9 is configured to receive precharge signal PreEO, and when precharge signal PreEO is active (e.g., high), precharge transistor M9 is turned on to provide precharge voltage Vad2 to sense line SABL or complementary sense line SABLB.
In the embodiment of the disclosure, the first conductive line 111 is one of the bit line BL, the complementary bit line BLB, the sensing line SABL or the complementary sensing line SABLB, and the second conductive line 112 is one of the sensing line SABL or the complementary sensing line SABLB, and meanwhile, when the sense amplifying circuit SA is in the amplifying stage, the electric potential of the first conductive line 111 and the electric potential of the second conductive line 112 represent different data.
For example, when the first conductive line 111 is the complementary bit line BLB, the second conductive line 112 can be the sense line SABL, when the first conductive line 111 is the bit line BL, the second conductive line 112 can be the complementary sense line SABLB, for example, the first conductive line 111 can also be the sense line SABL, the second conductive line 112 can also be the complementary sense line SABLB, and so on. Therefore, the voltage of the first wire 111 of the other group can influence the voltages of the first wire 111 and the second wire 112 in the current wire group at the same time, namely, the voltages of the first wire 111 and the second wire 112 in the current wire group are simultaneously pulled up or pulled down, so that the voltage difference between the first wire 111 and the second wire 112 in the current wire group is reduced due to the fact that the voltage of the first wire 111 (or the second wire 112) in the current wire group is influenced only, and the sense amplifying circuit is guaranteed to be capable of effectively amplifying data.
In some embodiments, please continue to refer to fig. 2, the plurality of sense amplifying circuits SA is divided into a plurality of sense amplifying circuit sets 130, each sense amplifying circuit set 130 includes two non-repeated sense amplifying circuits SA arranged along the X-axis direction, and the wire sets 110 corresponding to the two sense amplifying circuits SA in the same sense amplifying circuit set 130 are the first wire set 110a and the second wire set 110b, respectively.
For example, referring to fig. 2, the sense amplifier circuits SA1 and SA2 may form a sense amplifier circuit set 130, and referring to fig. 4, the wire set 110 corresponding to the sense amplifier circuit SA1 is used as the first wire set 110a, and the wire set 110 corresponding to the sense amplifier circuit SA2 is used as the second wire set 110b.
In some embodiments, referring to fig. 4 or fig. 5, the first wire set 110a and the second wire set 110b are mirror symmetrical along the Y-axis direction.
For example, referring to fig. 4 or fig. 5, the first conductive line 111a and the second conductive line 112b in the first conductive line group 110a are mirror-symmetrical to the first conductive line 111b and the second conductive line 112b in the second conductive line group 110b along the Y-axis direction.
In some embodiments, referring to fig. 6 or fig. 7, the first wire set 110a is translated along the X-axis and then coincides with the second wire set 110 b.
For example, referring to fig. 6 or fig. 7, after the first conductive line 111a and the second conductive line 112b in the first conductive line group 110a are translated along the X-axis direction, they overlap with the first conductive line 111b and the second conductive line 112b in the second conductive line group 110 b.
In some embodiments, referring to fig. 8, the first portion of the first wire set 110a and the first portion of the second wire set 110b are mirror symmetrical along the Y-axis direction, and the second portion of the first wire set 110a coincides with the second portion of the second wire set 110b after being translated along the X-axis direction.
For example, referring to fig. 8, the first portion of the first wire set 110a and the first portion of the second wire set 110b are located in the region a, and in the region a, the first wire 111a and the second wire 112b in the first wire set 110a are mirror-symmetrical to the first wire 111b and the second wire 112b in the second wire set 110b along the Y-axis direction. The second portion of the first wire set 110a and the second portion of the second wire set 110B are located in the region B, and in the region B, the first wire 111a and the second wire 112B in the first wire set 110a are overlapped with the first wire 111B and the second wire 112B in the second wire set 110B after being shifted in the X-axis direction.
Note that, the first wire 111a and the second wire 112b in the first wire group 110a shown in fig. 8 refer to BLB1 and SABL1, respectively, and the first wire 111b and the second wire 112b in the second wire group 110b refer to BLB2 and SABL2, respectively. In some other embodiments, the first and second wires 111a and 112b in the first wire set 110a may be referred to as SABL1 and SABLB1, respectively, and the first and second wires 111b and 112b in the second wire set 110b may be referred to as SABL2 and SABLB, respectively.
In some embodiments, the first conductive layer is a single conductive layer (e.g., the M1 layer shown in fig. 4 or 6), the first conductive line 111 is a complementary bit line BLB, and the second conductive line 112 is a sense line SABL.
In some embodiments, please continue to refer to fig. 4 or fig. 6, for the first conductive line set 110a, the first end (shown as region C) of the sensing line SABL1 is located at a side of the first end (shown as region D) of the complementary bit line BLB1 away from the second conductive line set 110b, the first end of the sensing line SABL1 refers to an end of the sensing line SABL1 near the complementary bit line BLB1, and the first end of the complementary bit line BLB1 refers to an end of the complementary bit line BLB1 away from the sensing line SABL 1.
In some embodiments, referring to fig. 2, and fig. 4 or 6, the area between two memory arrays 120 is a BLSA area (bit line sensing area), LIOSA area (local data line sensing area), and a BLSA area in order, that is, the BLSA area is located between the memory arrays 120 and LIOSA area. The BLSA region is provided with a sense amplifier for amplifying a voltage difference between the bit line and the complementary bit line, and the LIOSA region is provided with a sense amplifier for amplifying a voltage difference between the local data line and the local complementary data line. The first end of the sense line SABL1 (shown as region C) is the end near the adjacent memory array 120, rather than the end near the local data line sensing region. The first end of the complementary bit line BLB1 (shown as region D) is the end near the adjacent memory array 120, rather than the end near the local data line sensing region.
In some embodiments, please continue with reference to fig. 4 or 6, a first end (shown as region C) and a second end (not shown) of the sensing line SABL1 are aligned in the Y-axis direction or in the same line parallel to the Y-axis, wherein the second end of the sensing line SABL1 is an end opposite to the first end of the sensing line SABL 1.
In some embodiments, referring to FIG. 4 or FIG. 6, the conductor sets further include complementary sense lines, for complementary sense line SABLB in first conductor set 110a, located between sense line SABL1 and sense line SABL2 (or complementary sense line SABLB) in the other conductor set 110 b. The tracks where the first end (as shown in the area C) and the second end of the sensing line SABL1 are located on a side of the complementary sensing line SABLB away from the second conductive line set 110 b.
It should be noted that, the lines mentioned in this disclosure refer to a linear space extending along the Y-axis direction, and different lines are arranged along the X-axis direction. In fig. 4 to 8 and 11, the traces within four tracks are described, while in fig. 9 and 10, the traces within six tracks are described.
In some embodiments, please continue to refer to fig. 4, the sensing line SABL1 in the first conductive line set 110a is mirror symmetric to the sensing line SABL2 in the second conductive line set 110 b. With continued reference to fig. 6, after the sensing line SABL1 in the first conductive line set 110a is shifted along the X-axis direction, it coincides with the sensing line SABL2 in the second conductive line set 110 b.
In some embodiments, the first conductive layer includes a first conductive sub-layer (e.g., M1-1 layer in FIG. 8) and a second conductive sub-layer (not shown) stacked in the Z-axis direction, the first conductive line 111 is a complementary bit line BLB, the second conductive line 112 is a sense line SABL, and at least a portion of the complementary bit line BLB and sense line SABL in the sense amplifier circuit SA are twisted (e.g., as shown by the second conductive line group 110b in FIG. 8). In addition, referring still to FIG. 8, when the conductor sets further include complementary sense lines, sense lines SABL and complementary sense lines SABLB in the same conductor set 110 can also be twisted with each other, e.g., sense line SABL1 and complementary sense line SABLB1 in first conductor set 110a are twisted with each other, and sense line SABL2 and complementary sense line SABLB2 in second conductor set 110b are twisted with each other.
In some embodiments, please continue to refer to fig. 5, 7 or 8, for the first conductive line set 110a, the first end of the sensing line SABL1 (as shown in the region C) is located at a side of the first end of the complementary bit line BLB1 (as shown in the region D) away from the second conductive line set 110b, the first end of the sensing line SABL1 refers to an end of the sensing line SABL1 close to the complementary bit line BLB1, and the first end of the complementary bit line BLB1 refers to an end of the complementary bit line BLB1 away from the sensing line SABL 1.
In some embodiments, referring to fig. 2, and fig. 5, 7, or 8, the area between two storage arrays 120 is a BLSA area, LIOSA area, and a BLSA area in order, that is, the BLSA area is located between the storage arrays 120 and LIOSA area. The first end of the sense line SABL1 (shown as region C) is the end near the adjacent memory array 120, rather than the end near the local data line sensing region. The first end of the complementary bit line BLB1 (shown as region D) is the end near the adjacent memory array 120, rather than the end near the local data line sensing region.
In some embodiments, please continue to refer to fig. 5, 7 or 8, the first end (as shown in region C) of the sensing line SABL1 is adjacent to the line where the second end (not shown) of the sensing line SABL1 is located, wherein the second end of the sensing line SABL1 is opposite to the first end of the sensing line SABL 1.
In some embodiments, referring to FIG. 5, FIG. 7 or FIG. 8, the conductive line set further includes a complementary sense line, for the complementary sense line SABLB a in the first conductive line set 110a, the first end of the sense line SABL1 is on the same lane, and the second end of the sense line SABL1 and the first end of the complementary bit line BLB1 are on the same lane.
In some embodiments, please continue to refer to fig. 5, the sensing line SABL1 in the first conductive line set 110a is mirror symmetric to the sensing line SABL2 in the second conductive line set 110 b. With continued reference to fig. 7, after the sensing line SABL1 in the first conductive line set 110a is shifted along the X-axis direction, it coincides with the sensing line SABL2 in the second conductive line set 110 b. Referring to fig. 8, in the area a, the sensing line SABL1 in the first conductive line set 110a is mirror symmetrical to the sensing line SABL2 in the second conductive line set 110B, and in the area B, the sensing line SABL1 in the first conductive line set 110a is shifted along the X-axis direction and then coincides with the sensing line SABL2 in the second conductive line set 110B.
It should be noted that, with continued reference to fig. 8, the first end (as shown in the area C) and the second end (not shown) of the sensing line SABL1 are adjacent to each other, and at the same time, the first end and the second end of the sensing line SABL2 are aligned in the Y-axis direction.
In the embodiment of the disclosure, the first conductive layer is a single conductive layer (M1 layer), and the layout of the plurality of conductive wire groups is described in detail on the basis of fig. 4. The first conductive line 111 is a complementary bit line BLB, and the second conductive line 112 is a sensing line SABL.
In the embodiment of the present disclosure, the sensing line SABL and the complementary sensing line SABLB of the same conductive line set 110 are twisted, for example, referring to fig. 9, the sensing line SABL1 of the first conductive line set 110a is twisted with the complementary bit line BLB1 of the first conductive line set 110 a.
In some embodiments, referring to fig. 9, the sensing line SABL1 of the first conductive line set 110a includes a first sub-segment 11, a second sub-segment 12 and a third sub-segment 13, the complementary bit line BLB1 of the first conductive line set 110a includes a fourth sub-segment 14 and a fifth sub-segment 15, the first sub-segment 11 to the fifth sub-segment 15 all extend along the Y-axis direction, the first sub-segment 11, the fifth sub-segment 15 and the third sub-segment 13 are sequentially arranged along the Y-axis direction, the complementary sensing lines SABLB1 of the fourth sub-segment 14, the second sub-segment 12 and the first conductive line set 110a are sequentially arranged along the Y-axis direction, the complementary sensing lines SABLB1 of the third sub-segment 12 and the first conductive line set 110a are adjacently arranged along the X-axis direction, the first sub-segment 11 is located at a side of the fourth sub-segment 14 away from the second conductive line set 110b, and the second conductive line set 110b and the first conductive line set 110a are mirror-symmetrical.
In the embodiment of the disclosure, referring to fig. 2 and 9, in order to clearly distinguish between the sense amplifier circuits SA and the corresponding wire sets 110 in the sense amplifier circuit sets 130 adjacent to each other along the Y-axis direction, in the following description, the wire set corresponding to the sense amplifier circuit SA3 is referred to as a third wire set 110c, and the wire set corresponding to the sense amplifier circuit SA4 is referred to as a fourth wire set 110d. That is, the sense amplifying circuit SA3 corresponding to the third wire group 110c and the sense amplifying circuit SA1 corresponding to the first wire group 110a respectively belong to the sense amplifying circuit groups 130 adjacent in the Y-axis direction, and the sense amplifying circuit SA4 corresponding to the fourth wire group 110d and the sense amplifying circuit SA2 corresponding to the second wire group 110b respectively belong to the sense amplifying circuit groups 130 adjacent in the Y-axis direction.
In some embodiments, please continue with reference to fig. 9, the complementary sense line SABLB of the first wire set 110a, the complementary bit line BLB3 of the third wire set 110c (i.e., the first wire 111 c), the complementary bit line BLB4 of the fourth wire set 110d (i.e., the first wire 111 d), and the complementary sense line SABLB2 of the second wire set 110b are sequentially arranged along the X-axis direction.
In some embodiments, please continue to refer to fig. 9, the first sub-section 11 and the second sub-section 12 are connected by a connection structure of the same conductive layer, the second sub-section 12 and the third sub-section 13 are connected by a connection structure of the same conductive layer, and the fourth sub-section 14 and the fifth sub-section 15 are connected by a connection structure crossing different conductive layers or by a gate layer. In the embodiment of the disclosure, please continue to refer to fig. 9, the fourth sub-segment 14 and the fifth sub-segment 15 are connected through a connection structure crossing different conductive layers or through a gate layer, specifically, the fourth sub-segment 14 and the fifth sub-segment 15 are located on the first conductive layer (M1 layer), and in order to avoid collision with the complementary bit line BLB1 and the sensing line SABL1 of the first wire group 110a, after the fourth sub-segment 14 is close to one end of the sensing line SABL1, the fourth sub-segment 14 is connected to a gate layer in the lower active device layer (i.e. connected to a gate of a device in the active device layer, such as a gate in the second P-type amplifying tube in fig. 12), and the fourth sub-segment 14 is connected to one end of the fifth sub-segment 15 close to the sensing line SABL1 in the X-axis direction through the gate of the device in the gate layer.
Accordingly, since the conductive layer of the fourth sub-segment 14 has been changed to the gate layer before the lane change is made, the fourth sub-segment 14 includes two portions on the first conductive layer and the gate layer, respectively, and the fifth sub-segment 15 also includes two portions on the first conductive layer and the gate layer, respectively. In the case of the jumper, the conductive layers of the subsections can be understood according to the description, and the description is omitted.
Like this, cross-layer is carried out through the grid for the wire can realize the lane change, not only can avoid connecting wire winding because of the overall arrangement restriction is longer, reduces resistance and delay, can also further reduce the quantity that the lane occupies, avoids the lane to block up. In addition, in some other embodiments, the fourth sub-segment 14 and the fifth sub-segment 15 may also be connected by a connection structure of the same conductive layer, while the first sub-segment 11 and the second sub-segment 12 are connected by a connection structure of different conductive layers or by a gate layer, and the present disclosure is not limited to the sub-segments connected by specific jumpers, and the subsequent embodiments may be understood herein.
In the embodiment shown in fig. 9, when the sense amplifying circuit SA is in the amplifying stage, the potential of the complementary bit line BLB is different from the potential of the sensing line SABL, meanwhile, since the sensing line SABL1 of the first wire set 110a is located between the complementary bit line BLB1 of the first wire set 110a and the complementary bit line BLB3 of the third wire set, that is, the second subsection 12 is located between the fifth subsection 15 and the complementary bit line BLB3 of the third wire set, the complementary bit line BLB3 can simultaneously generate a coupling effect on the complementary bit line BLB1 and the sensing line SABL1, and the potentials of the complementary bit line BLB1 and the sensing line SABL1 are pulled up or down at the same time, so as to ensure that the voltage difference between the complementary bit line BLB1 and the sensing line SABL1 meets the amplifying requirement.
In some embodiments, the first conductive layer includes a first conductive sub-layer (M1-1 layer) and a second conductive sub-layer (M1-2 layer) stacked along the Z-axis direction, and the heights of the first conductive sub-layer and the second conductive sub-layer are lower than the height of the upper electrode of the storage capacitor in the memory cell, and the layout of the plurality of wire groups will be described in detail based on fig. 8. The first conductive line 111 is a complementary bit line BLB, and the second conductive line 112 is a sensing line SABL.
In some embodiments, sense line SABL and complementary sense line SABLB of the same wire set 110 are twisted. For example, referring to fig. 10, the sensing line SABL2 of the second conductive line set 110b is twisted with the complementary bit line BLB2 of the second conductive line set 110 b.
In some embodiments, referring to FIG. 10, at least a portion of the complementary bit line BLB1, the sense line SABL1, the complementary sense line SABLB of the first conductive set 110a, and at least a portion of the complementary bit line BLB2, the sense line SABL2, and the complementary sense line SABLB2 of the second conductive set 110b are all located in the first conductive sub-layer (M1-1 layer).
Here, the complementary bit line BLB1, the sensing line SABL1, and at least a portion of the complementary sensing line SABLB of the first conductive line group 110a are all located in the first conductive sub-layer, meaning that at least a portion of the complementary bit line BLB1, at least a portion of the sensing line SABL1, and at least a portion of the complementary sensing line SABLB1 are all located in the first conductive sub-layer, and the second conductive line group 110b is similar.
It should be noted that at least a portion of the complementary sense line SABLB and at least a portion of the complementary sense line SABLB jumper to the second conductive layer (i.e., the second metal layer M2) or the gate layer.
In this disclosure embodiment, please continue to refer to fig. 10, the sensing line SABL1 of the first wire set 110a includes a first sub-segment 11 and a second sub-segment 12, the complementary sensing line SABLB of the first wire set 110a includes a third sub-segment 13 and a fourth sub-segment 14, the sensing line SABL2 of the second wire set 110b includes a fifth sub-segment 15, a sixth sub-segment 16 and a seventh sub-segment 17, the complementary sensing line SABLB2 of the second wire set 110b includes an eighth sub-segment 18 and a ninth sub-segment 19, the complementary bit line BLB2 of the second wire set 110b includes a tenth sub-segment 20 and an eleventh sub-segment 21, the first sub-segment 11 to the eleventh sub-segment 21 all extend along the Y axis direction, the third sub-segment 13 and the second sub-segment 12 are aligned along the Y axis direction, the first sub-segment 11, the fourth sub-segment 14, the complementary bit line SABL1 of the first wire set 110a is aligned along the Y axis direction, the eighth sub-segment 18, the sixth sub-segment 16, the tenth sub-segment 20, the eleventh sub-segment 21, the seventh sub-segment 19, the fifth sub-segment 11, the seventh sub-segment 19 and the seventh sub-segment 19 are aligned along the Y axis direction, the fifth sub-segment 11, the seventh sub-segment 19, the third sub-segment 11 and the third sub-segment 13.
In the embodiment of the disclosure, referring to fig. 2 and 10, for clarity of distinguishing between the sense amplifier circuits SA and the corresponding wire sets 110 in the sense amplifier circuit sets 130 adjacent to each other along the Y-axis direction, in the following description, the wire set corresponding to the sense amplifier circuit SA3 is referred to as the third wire set 110c, and the wire set corresponding to the sense amplifier circuit SA4 is referred to as the fourth wire set 110d. That is, the sense amplifying circuit SA3 corresponding to the third wire group 110c and the sense amplifying circuit SA1 corresponding to the first wire group 110a respectively belong to the sense amplifying circuit groups 130 adjacent in the Y-axis direction, and the sense amplifying circuit SA4 corresponding to the fourth wire group 110d and the sense amplifying circuit SA2 corresponding to the second wire group 110b respectively belong to the sense amplifying circuit groups 130 adjacent in the Y-axis direction.
It should be noted that, to clearly illustrate the positional relationship of the wires in the first conductive sub-layer (M1-1 layer) in fig. 10, the wires in the second conductive sub-layer (M1-2 layer) in fig. 10 are drawn outside the first wire group 110a and the second wire group 110b, and in fact, the positions of the wires in the second conductive sub-layer (M1-2 layer) are shown in fig. 11.
In some embodiments, referring to fig. 10 and 11, the complementary bit line BLB3 of the third conductive line group 110c and the complementary bit line BLB4 of the fourth conductive line group 110d are located in the second conductive sub-layer (M1-2 layer), projections of the complementary bit line BLB3 of the third conductive line group 110c and the complementary bit line BLB1 of the first conductive line group 110a along the Z-axis direction at least partially overlap, and projections of the complementary bit line BLB4 of the fourth conductive line group 110d and the complementary bit line BLB2 of the second conductive line group 110b along the Z-axis direction at least partially overlap.
In some embodiments, please refer to fig. 10, the first sub-section 11 and the second sub-section 12 are connected by a connection structure of the same conductive sub-layer, the fifth sub-section 15 and the sixth sub-section 16 are connected by a connection structure of the same conductive layer, the sixth sub-section 16 and the seventh sub-section 17 are connected by a connection structure of the same conductive layer, the third sub-section 13 and the fourth sub-section 14 are connected by a connection structure crossing different conductive layers or by a gate layer, the eighth sub-section 18 and the ninth sub-section 19 are connected by a connection structure crossing different conductive layers or by a gate layer, and the tenth sub-section 20 and the eleventh sub-section 21 are connected by a connection structure crossing different conductive layers or by a gate layer. In this way, by connecting across layers (e.g., through the gate layer or the second conductive layer), it is advantageous to avoid excessive connection routing due to layout limitations, thereby reducing resistance and delay.
In the embodiment shown in fig. 11, since a portion of the complementary bit line BLB2 (i.e., eleventh subsection 21) and a portion of the sense line SABL2 (i.e., seventh subsection) of the second conductive line group 110b are not located at an adjacent lower layer of the complementary bit line BLB4 in the fourth conductive line group 110d, it is advantageous to reduce the coupling between the complementary bit line BLB2 and the sense line SABL2 and the complementary bit line BLB 4.
In addition, the complementary sensing lines SABLB and the sensing lines SABL1 of the first wire set 110a extend side by side and are twisted (as shown in the first subsection 11 and the third subsection 13, and the second subsection 12 and the fourth subsection 14) with each other, so that the variation amplitude of noise in the sense amplifying circuit SA can be reduced, and the noise is relatively uniform, which is beneficial to improving the performance of the semiconductor structure.
It should be noted that, in the above embodiment, the first conductive line 111 is taken as the complementary bit line BLB, the second conductive line 112 is taken as the sensing line SABL as an example, and in other embodiments, the first conductive line 111 may be the bit line BL, the second conductive line 112 may be the complementary sensing line SABLB, and the layout is understood with reference to the above embodiment, but the disclosure is not limited thereto.
In some embodiments, referring to fig. 9 and 12, the projection of the first subsection 11 in the Z-axis direction is located on an N-type amplifying transistor of the sense amplifying circuit SA, and the projection of the fifth subsection 15 in the Z-axis direction is located on a bias eliminating transistor or a precharge transistor of the sense amplifying circuit SA.
In the embodiment of the present disclosure, fig. 12 shows a layout structure of each device in the sense amplifying circuit SA, wherein a dashed box in fig. 12 is a device in the sense amplifying circuit SA, and a specific connection relationship thereof may be understood with reference to fig. 2.
In some embodiments, please refer to fig. 9 and 12, taking the first end (as shown in the area C) of the first subsection 11 located above the first N-type amplifying transistor as an example, the first subsection 11 is connected to the source or drain of the first N-type amplifying transistor from the first isolation transistor in the direction of the first N-type amplifying transistor, the connection point is located in the middle of the first N-type amplifying transistor, and the projection of the fifth subsection 15 in the Z-axis direction is located on the first bias eliminating transistor or the first precharge transistor of the sense amplifying circuit SA.
In some embodiments, referring to fig. 10 and 12, the projection of the seventh subsection 17 in the Z-axis direction is located on the N-type amplifying tube of the sense amplifying circuit SA, the projection of the eleventh subsection 21 in the Z-axis direction is located on the isolation transistor of the sense amplifying circuit SA, and the projections of the fourth subsection and the ninth subsection in the Z-axis direction are located on the P-type amplifying tube of the sense amplifying circuit SA.
In the embodiment of the disclosure, taking an example that the seventh subsection 17 is located above the surface of the first N-type amplifying tube, the projection of the seventh subsection 17 in the Z-axis direction is located on the middle of the first N-type amplifying tube of the sense amplifying circuit SA, the projection of the eleventh subsection 21 in the Z-axis direction is located on the first isolation transistor or the first precharge transistor of the sense amplifying circuit SA, and the projections of the fourth subsection and the ninth subsection in the Z-axis direction are located on the middle of the first P-type amplifying tube of the sense amplifying circuit SA.
In addition, an electronic device is provided in an embodiment of the disclosure, and fig. 13 is a schematic structural diagram of an electronic device 200 provided in an embodiment of the disclosure, where, as shown in fig. 13, the electronic device 200 includes a processor 210 and any one of the semiconductor structures 100 in the embodiment, and a memory is coupled to the processor.
In some embodiments, the electronic device includes, but is not limited to, a cell phone, tablet, smart bracelet, wearable electronic device, virtual reality device, augmented reality device, vehicle device, server, workstation, etc.
In several embodiments provided by the present disclosure, it should be understood that the disclosed structures and methods may be implemented in a non-targeted manner. The structural embodiments described above are merely illustrative, e.g., the division of elements is merely a logical functional division, and there may be additional divisions in actual implementation, e.g., multiple elements or components may be combined or integrated into another system, or some features may be omitted, or not implemented. In addition, the components shown or discussed are coupled to each other or directly.
Features disclosed in the several method or structure embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or structure embodiments.
The above is merely some embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present disclosure, and should be covered in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.