Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
It should be appreciated that the terms "first," "second," and the like herein are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more of the described features. In the description of the present disclosure, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the description of the present disclosure, unless explicitly stated and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected, mechanically connected, electrically connected, or communicable with each other, directly connected, indirectly connected via an intermediary, or in communication between two elements, or in an interaction relationship between two elements. The specific meaning of the terms in this disclosure will be understood by those of ordinary skill in the art as the case may be.
Furthermore, it should be understood that the dimensions of the various elements shown in the figures are not necessarily drawn to actual scale, e.g., the thickness or width of some layers may be exaggerated relative to other layers for ease of description. Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but where applicable, should be considered part of the present specification.
Currently, the mainstream NOR memory devices in the market are implemented by floating gate (floating gate) technology, and the erase (erase) operation uses FN tunneling (Fowler-Nordheim tunneling) mechanism, and the program (program) (also referred to as "write" or "write") operation uses channel hot electron injection (Channel hot electron injection, CHE) mechanism. The channel length of such devices is limited by the need for a lateral accelerating electric field for channel hot electron injection. The present disclosure finds that it is very difficult to go down to the 45nm node in the current fabrication process of NOR-type memories based on floating gate technology.
In view of this, the present disclosure proposes a NOR-type memory array structure composed of memory transistors using a dielectric material instead of a floating gate as a charge storage layer, which is capable of adopting FN tunneling mechanism for both programming and erasing operations, so that the channel length is not limited, more advanced process nodes (i.e., smaller critical dimensions) can be adopted, and the size of individual memory transistors is further scaled.
Examples of the novel structure of the present disclosure and examples of its corresponding operation will be described in more detail below with reference to the accompanying drawings.
Fig. 1 illustrates, in cross-section, an exemplary structure of a memory transistor according to one embodiment of the present disclosure.
In some embodiments, as shown in fig. 1, a well 102 may be formed in a substrate 101, a source region 103, a drain region 104, and a channel region therebetween of a memory transistor are formed in the well 102, and a gate structure, i.e., a tunneling layer 105, a charge storage layer 106, a blocking layer 107, and a gate electrode layer 108, is formed over the channel region.
The charge storage layer 106 of the present disclosure is a dielectric material rather than a conductive material that acts as a floating gate, enabling programming and erasing operations to the memory transistor using FN tunneling mechanisms. For example, by applying a positive or negative voltage differential between gate electrode layer 108 and drain region 104, electrons can be tunneled through tunneling layer 105 into or out of charge storage layer 106, respectively, to effect a program or erase operation. The blocking layer 107 serves to block the flow of charge between the charge storage layer 106 and the gate electrode layer 108.
In some embodiments, the gate structure of the memory transistor of the present disclosure may adopt an ONO (Oxide-Nitride-Oxide) -based structure, that is, where the tunneling layer 105 is an Oxide layer (in this implementation, the tunneling layer 105 may also be referred to as the tunneling Oxide layer 105), the charge storage layer 106 is a Nitride layer, and the blocking layer 107 is an Oxide layer (in this implementation, the blocking layer 107 may also be referred to as the blocking Oxide layer 107). In this case, it can also be considered that a tunnel oxide layer 105, a charge storage layer 106 which is a nitride layer, a block oxide layer 107, and a gate electrode layer 108 are formed over a channel region of the memory transistor in this order from bottom to top. In some examples, tunnel oxide layer 105 may be various oxide layers, such as silicon oxide, that may be, for example, 15-30 angstroms thick, and/or charge storage layer 106 may be various dielectric material layers, such as silicon nitride, that may be, for example, 40-70 angstroms thick, and/or blocking oxide layer 107 may be various oxide layers, such as silicon oxide, that may be, for example, 40-70 angstroms thick. Various suitable processes such as oxidation, deposition, etc. may be employed to form tunnel oxide layer 105, charge storage layer 106 as a nitride layer, and blocking oxide layer 107.
It should be understood that while different fill patterns are used to distinguish between different components (e.g., tunneling layer and barrier layer) in the various figures of the present disclosure, in some possible embodiments, these components may comprise or be composed of the same material, e.g., tunneling layer and barrier layer may comprise or be composed of the same insulating material (e.g., silicon oxide, etc.), which may be substantially the same material layer, but may be formed in different manufacturing process steps or function differently.
In some embodiments, the gate electrode layer 108 may be a polysilicon layer, or may also be a metal layer. In the case of forming the gate electrode layer 108 from a metal material (e.g., tungsten), the fabrication process of the memory array may be better integrated with the logic process of advanced nodes, and thus more advanced process nodes may be more conveniently employed to fabricate the memory array of the present disclosure, reducing the size of the memory array.
In some embodiments, the substrate 101 may be a silicon substrate, such as a silicon wafer (wafer). It will be appreciated by those skilled in the art that the present disclosure is not limited in any way to a substrate, and the substrate 101 may also be other various substrates, such as an SOC substrate, etc. The well 102 may be doped in the substrate 101. It should be understood that fig. 1 shows only a portion of a substrate and well by way of example, and that in practice many memory transistors and possibly other devices may be fabricated in the substrate and well as desired. In addition, it should be understood that the substrate 101 and well 102 in fig. 1 are merely exemplary and not required, e.g., memory transistors may be fabricated in semiconductor layers formed over the substrate in some cases, and the substrate may be removed after fabrication is complete.
Although not shown in fig. 1, in some embodiments, the well 102, the source region 103, the drain region 104, and/or the gate electrode layer 108 may be connected to respective metal lines in various ways in order to apply respective voltages to these components. The source region 103 and the drain region 104 may have the same structure, but are distinguished by their respective connected metal lines or voltages applied thereto.
In some embodiments, the structure shown in fig. 1 may be applied to a plurality of memory transistors, respectively, which are arranged in a determinant as a NOR-type memory array.
Fig. 2A exemplarily illustrates a schematic plan layout of a NOR-type memory array according to an embodiment of the present disclosure, fig. 2B illustrates a schematic sectional view taken along a dotted line A-A in fig. 2A, and fig. 2C illustrates a schematic sectional view taken along a dotted line B-B in fig. 2A.
Fig. 2A shows a layout (layout) of a plurality of memory transistors arranged in 5 rows by 5 columns in a NOR-type memory array, wherein the specific configuration of each memory transistor may employ the structure described in the embodiment shown in fig. 1, although the present disclosure is not limited thereto. The planar position of each memory transistor in fig. 2A may be approximately determined by where the laterally extending gate electrode layers 203 intersect the longitudinally extending bit line metal lines 205, wherein the gate electrode layers 203 respectively act as gate electrode layers of the memory transistors of the rows and are connected to the word lines WLn-2, WLn-1, WLn, wln+1, wln+2 of the rows, the metal lines 205 respectively act as bit lines of the columns (thus the metal lines 205 are identified as BLn in fig. 2B) and are respectively connected to the drain regions 201 of the memory transistors of the columns by contact holes 206, and the source regions 202 of the memory transistors of the rows are connected to each other and to the common source line CSL via conductive strips 204 doped in the substrate as indicated by dashed lines. Wherein the bit lines BL include BLn-2, BLn-1, BLn, BLn+1, BLn+2. It should be understood that the metal lines that are the word lines are omitted from the drawings of the present disclosure for clarity, and the gate electrode layers to which they are connected are indicated by the reference numerals of the word lines, respectively.
It should be further appreciated that although not shown in the plan view of fig. 2A for clarity, isolation features (e.g., shallow trench isolation 215 shown in later cross-section fig. 2C) may also be present between the active regions of adjacent columns to isolate the active regions of adjacent columns from each other to prevent mutual interference.
The numbering of rows and columns in the figures of this disclosure with "n-2", "n-1", "n", "n+1", "n+2" is intended to indicate consecutive 5 rows and 5 columns in a memory array and is not limiting as to which specific rows and columns in the array. The illustrated memory array may also have other rows and columns not shown, which may have the same or different construction than that shown.
In addition, it will be appreciated by those skilled in the art that the rows and columns illustrated in this disclosure are exemplary only, and that virtually any h m array can be made as desired, where h and m are natural numbers greater than 1. Those skilled in the art will appreciate that the h×m layout is only one of ways to implement the technical solutions of the embodiments of the present disclosure, and the embodiments of the present disclosure are not limited thereto. Meanwhile, the "h rows" and "m columns" in all embodiments of the present disclosure merely mean that a plurality of memory transistors are arranged in an array, and do not limit that the memory transistors must be arranged in a completely regular array as shown in the drawings. The rows and columns in the array are not determined by the locations of the memory transistors, but rather by the connection of these memory transistors (e.g., with word lines, bit lines/source lines, etc.), etc. That is, the term "column" throughout the various embodiments of the present disclosure may be a completely virtual concept, which may be memory transistors laid out approximately in a horizontal direction or a vertical direction on a horizontal plane, or even memory transistors laid out in an arc or curve shape extension, and may be based on artificial arrangement/division. Similarly, the term "row" throughout the various embodiments of the present disclosure may be a fully virtual concept that may be memory transistors laid out approximately horizontally or vertically in a horizontal plane, or even memory transistors laid out in an arc or curve-like extension, and may be based on artificial setup/division. The memory array described throughout the various embodiments of the present disclosure includes an h×m array of memory transistors, and is not limited to the same number of memory transistors in each row or to the same number of memory transistors in each column.
The structure shown in fig. 2A includes 5 rows of memory transistors, and the number of memory transistors included in each row is equal, i.e., 5 memory transistors are included in each row, but this is merely illustrative and not a limitation of the protection scope of the technical solution of the present disclosure, and it will be understood by those skilled in the art that the number of memory transistors included in each row may be the same or different. Similarly, the structure shown in fig. 2A includes 5 columns of memory transistors, and the number of memory transistors included in each column is equal, i.e. 5 memory transistors are included in each column, which is merely illustrative and not a limitation of the protection scope of the technical solution of the present disclosure, and it will be understood by those skilled in the art that the number of memory transistors included in each column may be the same or different.
FIG. 2B shows a cross-sectional A-A view of the 5 memory transistors of the nth column of FIG. 2A. As shown in the cross-sectional view of fig. 2B, each memory transistor may employ the structure described in the embodiment shown in fig. 1 previously, although the present disclosure is not limited thereto.
As shown in fig. 2B, the active regions (including source, drain and channel regions) of the memory transistors of the column may be formed in wells 214 in a substrate 213, wherein adjacent rows of memory transistors share one source region 202/drain region 201, each drain region 201 being connected to a bit line BLn of the column via a contact hole (contact) 206, each source region 202 being connected to a source line of each row (in this example a common source line CSL, as will be described in more detail in fig. 2C) via a respective row of conductive strips 204. While fig. 2B illustrates a cross-sectional structure of only the nth column, it should be understood that other columns in the memory array (e.g., the n+2, n+1, n-1, n-2 columns illustrated in fig. 2A) may have the same cross-sectional structure as illustrated in fig. 2B, or other columns in the memory array may have completely or partially different cross-sectional structures than illustrated in fig. 2B, which is not a limitation of the present disclosure. In addition, as shown in fig. 2B, a tunneling layer 210, a charge storage layer 211, a blocking layer 212, and gate electrode layers WL of respective rows may be formed over the channel regions of the respective memory transistors of the column similarly to fig. 1.
Fig. 2C shows a cross-sectional B-B view of the 5 memory transistors of row n-2 of fig. 2A, which mainly illustrates the structure of the conductive strips 204 of row n-2 and their connected common source lines CSL, and shallow trench isolation 215 between source regions 202 of adjacent columns.
As shown in fig. 2C, a continuous conductive strip 204 may be formed in the well 214 or in the substrate 213 at a suitable location by a suitable process, such as an ion implantation (Ion Implantation, IMP) process, etc., the conductive strip 204 at least partially overlapping the source regions 202 of the individual memory transistors of the row, thereby electrically connecting the source regions 202 of the row to one another. The conductive strip 204 may also at least partially overlap one active region 207 below the common source line CSL, thereby electrically connecting to the active region 207 and to the common source line CSL via a contact hole 206 above the active region 207. In addition, as shown in fig. 2C, the conductive strip 204 may sink down at the location of the shallow trench isolation 215 due to the existence of the shallow trench isolation 215, i.e., form a continuous conductive strip around the lower portion of the shallow trench isolation 215.
In some examples, the heavily doped regions may be formed as conductive strips 204 in the substrate at a depth at least partially coincident with the source regions 202 by controlling parameters of the ion implantation process, thereby connecting the individual source regions 202 of the same row. It should be appreciated that the examples of fig. 2A-2C are not intended to limit the manner in which rows of conductive strips 204 or source regions 202 are brought out to connect to source lines, and that the present disclosure may also be implemented in a variety of other suitable ways. In one possible implementation, the conductive strips 204 may be formed by doping in the wells 214 or in the substrate 213 at appropriate locations.
The source regions of the memory transistors in the same row are connected by forming conductive strips in the well or in the substrate, which makes the manufacturing process simple and does not occupy additional area, which is more beneficial to reducing the size of the memory array.
It should be appreciated that while fig. 2C illustrates each bit line and source line in the same metal layer, the present disclosure is not limited thereto, and each bit line and source line may be arbitrarily distributed in one or more metal layers in some embodiments. The word lines of each row omitted in the drawings may be arbitrarily distributed in one or more metal layers, which may be the same as or different from the metal layer to which each bit line or source line belongs.
In some embodiments, any of the word lines, bit lines, source lines, and the like, and corresponding contact holes used in the foregoing and later described embodiments of the present disclosure may be made of a material containing tungsten, or any of the word lines, bit lines, source lines, and the like, and corresponding contact holes may be made of tungsten.
Although the conductive members of the gate electrode layer, the contact hole, the bit line, the source line, the metal line, etc. are shown differently in the foregoing and later described figures of the present disclosure, in some possible embodiments, some or all of these conductive members may comprise or consist of the same conductive material (e.g., tungsten), which may be substantially the same material layer, but which may be functionally different or may be formed in different manufacturing process steps.
It will be appreciated that, for clarity and emphasis on the drawings, there may be blank areas between some of the components in the cross-sectional views of the disclosure described above and below, which are not limited to these being necessarily blank. In some implementations, these full or partial empty areas may be filled with an electrically insulating material to isolate and support the components in an actual device.
Fig. 3A-3C and fig. 4A-4C illustrate another two NOR-type memory array structures according to the present disclosure, which differ from the structures shown in fig. 2A-2C described above mainly in the manner in which the sources of the memory transistors of the same row are connected.
Specifically, fig. 3A exemplarily illustrates a schematic plan layout of a NOR-type memory array according to another embodiment of the present disclosure, fig. 3B illustrates a schematic sectional view taken along a dotted line A2-A2 in fig. 3A, and fig. 3C illustrates a schematic sectional view taken along a dotted line B2-B2 in fig. 3A.
The exemplary memory array shown in fig. 3A to 3C is mainly different from the exemplary memory array shown in fig. 2A to 2C in the manner of connecting the sources of the memory transistors of the same row. As shown in fig. 3A to 3C, the source regions 302 of the respective memory transistors of the same row may be connected to the same source line 304 via respective contact holes 306, whereas the source lines 304 of the respective rows are each connected to a common source line CSL as shown in fig. 3C.
It should be understood that, in addition to the source connection manner discussed above, the specific configuration of the memory array shown in fig. 3A to 3C of the present disclosure may refer to the drawings and the related discussion of other embodiments of the present disclosure, for example, refer to the contents of the embodiments shown in fig. 2A to 2C, which are not repeated herein. Those skilled in the art will appreciate that the present disclosure is not limited to the aforementioned NOR-type memory array configuration, and that any other suitable configuration may be employed.
In a possible implementation, the part structures in fig. 3A to 3C may be similar to the part structures shown in fig. 2A to 2C, and the similar parts will not be repeated. As shown in fig. 3A to 3C, the active regions (including source, drain and channel regions) of the memory transistors of the column may be formed in a well 314 in a substrate 313, wherein adjacent rows of memory transistors share one source/drain region 302/301, each drain region 301 being connected to a bit line BL of the column via a contact hole (contact) 306, wherein the bit line BL comprises bln+2, bln+1, BLn-1, BLn-2. In one possible implementation, a tunneling layer 310, a charge storage layer 311, a blocking layer 312, and respective rows of gate electrode layers 303 may be formed over the channel regions of the respective memory transistors of the column, as shown in fig. 3B, similar to fig. 1, 2A-2C. The planar position of each memory transistor in fig. 3A may be generally determined by where the laterally extending gate electrode layers 303 intersect the longitudinally extending bit line metal lines 305, wherein the gate electrode layers 303 respectively act as gate electrode layers of the memory transistors of the rows and are connected to the word lines WL of the rows, wherein the word lines WL comprise wln+2, wln+1, WLn-1, WLn-2. Each metal line 305 serves as a bit line for each column (hence metal line 305 is identified as BLn in fig. 3B) and is connected to the drain region 301 of the memory transistor for each column, respectively, through each contact hole 306, and the source region 302 of the memory transistor for each row is connected to the common source line CSL via the source line 304 shown in fig. 3A. The metal line 305 is therefore identified as BLn in fig. 3B. The source line 304 may also at least partially overlap one active region 307 below the common source line CSL, thereby electrically connecting to the active region 307 and to the common source line CSL via a contact hole 306 above the active region 307. In addition, as shown in fig. 3C, there is a shallow trench isolation 315 between the active regions of adjacent columns to isolate the active regions of adjacent columns from each other and prevent mutual interference.
It should be appreciated that while the cross-sectional views of fig. 3B and 3C illustrate each bit line and each source line being located in different two metal layers, respectively, the present disclosure is not limited thereto and, in some embodiments, each bit line and each source line may be arbitrarily distributed in one or more metal layers. The word lines of each row omitted in the drawings may be arbitrarily distributed in one or more metal layers, which may be the same as or different from the metal layer to which each bit line or each source line belongs.
Fig. 4A exemplarily illustrates a schematic plan layout of a NOR-type memory array according to still another embodiment of the present disclosure, fig. 4B illustrates a schematic sectional view taken along a dotted line A3-A3 in fig. 4A, and fig. 4C illustrates a schematic sectional view taken along a dotted line B3-B3 in fig. 4A.
The exemplary memory array shown in fig. 4A to 4C is mainly different from the exemplary memory array shown in fig. 2A to 2C in the manner of connecting the sources of the memory transistors of the same row. As shown in fig. 4A to 4C, the source regions 402 of the memory transistors in the same row may be connected to each other via a metal line 404 formed on the surface of a well 414 or a substrate 413, i.e., may be considered to be connected to the same source line, and the source lines in each row may be connected to a common source line CSL via a contact hole 406 disposed at the end of the metal line 404. In some examples, metal line 404 may be a tungsten line, which may be formed by a process of slotting in an insulating layer (not shown) overlying the surface of well 414 or substrate 413 and filling tungsten. Compared with the mode of leading out connection through a contact hole, the tungsten groove (Wslot) process is used for connecting the source regions in the same row, so that smaller area can be occupied, and the size of the memory array is reduced.
It should be understood that, in addition to the source connection manner discussed above, the specific configuration of the memory array shown in fig. 4A to 4C of the present disclosure may refer to the drawings and the related discussion of other embodiments of the present disclosure, for example, refer to the contents of the embodiments shown in fig. 2A to 2C, which are not repeated herein. Those skilled in the art will appreciate that the present disclosure is not limited to the aforementioned NOR-type memory array configuration, and that any other suitable configuration may be employed.
In a possible implementation manner, the part structures in fig. 4A to 4C may be similar to the part structures shown in fig. 2A to 2C or fig. 3A to 3C, and the similar parts will not be repeated. As shown in fig. 4A to 4C, the active regions (including source, drain and channel regions) of the memory transistors of the column may be formed in a well 414 in a substrate 413, wherein adjacent rows of memory transistors share one source region 402/drain region 401, each drain region 401 being connected to a bit line BL of the column via a contact hole (contact) 406, wherein the bit line BL comprises bln+2, bln+1, BLn-1, BLn-2. In one possible implementation, a tunneling layer 410, a charge storage layer 411, a blocking layer 412, and a gate electrode layer 403 of each row may be formed over the channel regions of each memory transistor of the column, as shown in fig. 4B, similar to fig. 1, 2A-2C, 3A-3C. The planar position of each memory transistor in fig. 4A may be generally determined by where the laterally extending gate electrode layers 403 intersect the longitudinally extending bit line metal lines 405, with the gate electrode layers 403 acting as gate electrode layers for the memory transistors of the rows, respectively, and being connected to the word lines WL of the rows, wherein the word lines WL include wln+2, wln+1, WLn-1, WLn-2. Each metal line 405 serves as a bit line for each column (thus the metal line 405 is identified as BLn in fig. 4B) and is connected to the drain region 401 of the memory transistor for each column, respectively, through each contact hole 406, and the source region 402 of the memory transistor for each row is connected to the common source line CSL via the source line 404 shown in fig. 4A. The source line 404 may also at least partially overlap one active region 407 below the common source line CSL, thereby electrically connecting to the active region 407, and to the common source line CSL via a contact hole 406 above the active region 407. In addition, as shown in fig. 4C, shallow trench isolation portions 415 are also present between the active regions of adjacent columns to isolate the active regions of adjacent columns from each other and prevent mutual interference.
It should be appreciated that while the cross-sectional view of fig. 4C illustrates each bit line in the same metal layer as the common source line, the present disclosure is not so limited and, in some embodiments, each bit line and common source line may be arbitrarily distributed in one or more metal layers. The word lines of each row omitted in the drawings may be arbitrarily distributed in one or more metal layers, which may be the same as or different from the metal layer to which each bit line or source line belongs.
Although the foregoing examples of fig. 2A to 2C, 3A to 3C, and 4A to 4C all show that the source regions of the memory transistors of the same row are connected to the same source line and the source lines of the rows are all commonly connected to the common source line, the present disclosure is not limited thereto, and for example, the source regions of the memory transistors of the same column may be connected to the same source line, and for example, the source lines of the rows or columns may not be connected to the common source line and voltages may be applied to the source lines of the rows or columns, respectively, as needed. As shown in fig. 2A to 2C, 3A to 3C, and 4A to 4C, the gates of the memory transistors in the same row are all connected to the same word line, the drains of the memory transistors in the same column are all connected to the same bit line, and the sources of the memory transistors in the same row or column are all connected to the same source line. It will be appreciated by those skilled in the art that any one or more of the structures may occur where portions of the gates of the individual memory transistors of the same row are connected to the same word line, or where portions of the drains of the individual memory transistors of the same column are connected to the same bit line, or where portions of the sources of the individual memory transistors of the same row or column are connected to the same source line, for any reason. Any one or more of the foregoing structures, although not specifically illustrated and described herein, are contemplated as falling within the scope of the present application, as the design concepts are similar to those illustrated in the foregoing embodiments.
The circuit structure of the memory array and its corresponding write, read and erase operations as shown in fig. 2A-2C, 3A-3C, or 4A-4C above are described in detail below in conjunction with fig. 5-8. Fig. 5-8 are all illustrated as 5 x 5 arrays, but it should be understood that the present disclosure is not limited thereto.
Fig. 5 shows a schematic diagram of a memory array circuit 500 according to one embodiment of the present disclosure.
As shown in fig. 5, the gates of the memory transistors of the same row are all connected to the same word line WLn-2, WLn-1, WLn, wln+1 or wln+2, the drains of the memory transistors of the same column are all connected to the same bit line BLn-2, BLn-1, BLn, bln+1 or bln+2, the sources of the memory transistors of the same row are all connected to the same source line and the source lines of the rows are all connected to the common source line CSL.
Thus, according to the memory array structure of the present disclosure, it is possible to uniquely determine the operation of one memory transistor in the memory array only by the control of the word line and the bit line without additional control (e.g., without additional control devices such as selection transistors). That is, one memory cell in the NOR-type memory array of the present disclosure includes only one memory transistor, and compared to the conventional SONOS memory array of a 2T (2 transistors including one select transistor and one memory transistor) structure, the present disclosure removes a separate MOS transistor as a select transistor, which can greatly reduce the size of a single memory cell, thereby reducing the size of the memory array. In addition, the memory array is simple in structure, corresponding circuit design and layout are also simple, design difficulty is greatly reduced, manufacturability is improved, compactness of the memory array layout is facilitated, and the size of the memory array is reduced.
FIG. 6 illustrates one example of a NOR type memory writing to the memory array shown in FIG. 5, according to one embodiment of the present disclosure. FIG. 7 illustrates one example of a NOR type memory performing a read operation of the memory array shown in FIG. 5 according to one embodiment of the present disclosure. Fig. 8 illustrates one example of an erase operation of the memory array illustrated in fig. 5 by a NOR-type memory according to one embodiment of the present disclosure. Of course, the circuit configuration shown in fig. 5 is merely illustrative, and the write operation of fig. 6, the read operation of fig. 7, and the erase operation of fig. 8 are not limited in the embodiments of the present disclosure and can be applied only to the circuit configuration shown in fig. 5.
As shown in fig. 6 to 8, the NOR type memory may further include a read/write/erase operation part 610, 710 or 810 for applying respective voltages to respective word lines, bit lines and/or source lines of the memory array so as to implement a read/write/erase operation, in addition to the NOR type memory array shown in fig. 5. In this context, in some embodiments, a memory array in a NOR-type memory is typically fabricated in one chip, and peripheral circuits for reading/writing/erasing the memory array, such as the read/write/erase operation portion 610, 710 or 810, may be fabricated in the same chip as the memory array or in a different chip.
Note that in all embodiments of the present disclosure, the structure of the read/write/erase operation portion 610, 710, or 810 may be the same or different. While it is referred to as a read/write/erase operation section, it may be used only for performing any one of a read operation, a write operation, and an erase operation, or may also be used for performing any two or all of a read operation, a write operation, and an erase operation.
Of course, the embodiment of the write operation shown in fig. 6, the embodiment of the read operation shown in fig. 7, and the embodiment of the erase operation shown in fig. 8 may be implemented alone, or may be implemented in combination with each other or all of them, or may be implemented in combination with other one or more embodiments of the present disclosure, which are not limited in this regard. In the following exemplary description, the exemplary description is made in combination of the implementation of the write operation of fig. 6, the implementation of the read operation of fig. 7, and the implementation of the erase operation of fig. 8, but it will be understood by those skilled in the art that the exemplary description is not a limitation of the embodiments of the present disclosure, and the read/write/erase operation portion 610, 710, or 810 may be a write-only operation to implement the scheme shown in fig. 6, a read-only operation to implement the scheme shown in fig. 7, or an erase-only operation to implement the scheme shown in fig. 8.
The writing operation, the reading operation, and the erasing operation to the memory array circuit shown in fig. 5 are exemplarily described below with one read/write/erase operation section 610, 710, or 810. Although fig. 6, 7 and 8 illustrate that the read/write/erase operation is performed by the same operation part 610, 710 or 810, the present disclosure is not limited thereto, and the read operation, the write operation and the erase operation may be performed by separate read operation parts, write operation parts and erase operation parts, respectively, in some embodiments. In addition, those skilled in the art will appreciate that there are various circuit ways to implement the read/write/erase operations that will be described in detail later.
It should be appreciated that in this disclosure, the memory transistor is erased before being written. Since electrons tunnel into the charge storage layer and are held therein at the time of writing, the threshold voltage of the written memory transistor is raised, i.e., higher than that of the erased memory transistor (may also be referred to as an erase threshold voltage), compared to the erased memory transistor. Therefore, when a memory transistor is read, a gate-source voltage difference (Vgs) thereof may be set to a value between the two threshold voltages, whereby the memory transistor is judged to be erased according to an on state of the memory transistor and to be written according to an off state of the memory transistor, whereby the erased memory transistor may be regarded as storing data "1" and the written memory transistor may be regarded as storing data "0".
Fig. 6 illustrates an exemplary write operation 600 for writing to memory transistors located in the nth row and nth column (as indicated by the dashed box in the figure).
As shown in fig. 6, the memory transistors to be written are located in the nth row and the nth column, with their gates connected to the word line WLn of the row, their drains connected to the bit line BLn of the column, and their sources connected to the common source line CSL. The read/write/erase operation part 610 may apply a first gate voltage Vg1 to a word line WLn (also may be referred to as a selected word line) connected to a gate of a memory transistor to be written and a second gate voltage Vg2 to the remaining word lines (also may be referred to as non-selected word lines), wherein the second gate voltage Vg2 is lower than the first gate voltage Vg1, apply a first drain voltage Vd1 to a bit line BLn (also may be referred to as a selected bit line) connected to a drain of the memory transistor to be written and a second drain voltage Vd2 to the remaining bit lines (also may be referred to as non-selected bit lines), wherein the second drain voltage Vd2 is higher than the first drain voltage Vd1, and the common source line CSL is floating (floating). It should be understood that in this disclosure, by "floating" is meant that no voltage is connected, including not grounded, which may be, for example, an open circuit. Thus, in the memory array, the voltage difference (=v1-Vd 1) between the gate and the drain of the (selected) memory transistor to be written is higher than the voltage difference (=v1-Vd 2 or=v2-Vd 1 or=v2-Vd 2) between the gate and the drain of the remaining non-selected memory transistors, and it can be ensured that only the (selected) memory transistor to be written achieves a desired writing effect (i.e., a desired electron tunneling effect).
In some embodiments, the values of the first gate voltage Vg1, the second gate voltage Vg2, the first drain voltage Vd1, and the second drain voltage Vd2 may be set appropriately according to factors such as the thickness of the tunneling layer, so that the gate-drain voltage difference (=vg 1-Vd 1) of only the selected memory transistor is greater than the voltage required for electron tunneling, the gate-drain voltage differences of the remaining memory transistors are insufficient to satisfy the condition of electron tunneling, or the amount of tunneling electrons generated is far smaller than the amount of tunneling electrons in the selected memory transistor (e.g., by at least one order of magnitude).
In some examples, the difference (=v2-Vd 1) between the second gate voltage Vg2 and the first drain voltage Vd1 may be about half of the difference (=v1-Vd 1) between the first gate voltage Vg1 and the first drain voltage Vd1, whereby an electron tunneling effect (i.e., a writing effect) of the memory transistors in the non-selected row on the selected column (nth column) may be avoided. For example, the difference between the first gate voltage Vg1 and the first drain voltage Vd1 may be 6v to 10v, and/or the difference between the second gate voltage Vg2 and the first drain voltage Vd1 may be 2v to 6v.
In some examples, the value of the second drain voltage Vd2 may be approximately equal to the value of the second gate voltage Vg2, whereby there is substantially no potential difference between the gates and drains of the memory transistors in the unselected columns and the unselected rows, better avoiding the electron tunneling effect (i.e., writing effect) of these unselected memory transistors.
In some examples, the difference (=v1-Vd 2) between the first gate voltage Vg1 and the second drain voltage Vd2 may be approximately equal to the value of the second drain voltage Vd2, whereby the electron tunneling effect (i.e., the writing effect) of the memory transistors in the non-selected columns on the selected row (n-th row) may be better suppressed. This is because, in the memory transistors in the non-selected columns on the selected row, the channel is inverted, its potential approaches its drain voltage Vd2, and the voltage between the gate and the channel is partially cancelled, suppressing the electron tunneling effect of the memory transistors in the non-selected columns on the selected row.
In some examples, the difference between the second drain voltage Vd2 and the first drain voltage Vd1 may be 2v to 6v.
For example, the first drain voltage Vd1 may be 0 volt. It should be understood that in the present disclosure, applying 0 volts also includes the case of grounding, in other words, when a certain conductive line is grounded, it can be regarded as being applied with 0 volts. At this time, the first gate voltage Vg1 may be 6-10V (e.g., about 10V), the second gate voltage Vg2 may be 2-6V (e.g., about 5V), and the second drain voltage Vd2 may be 2-6V (e.g., about 5V).
In addition, in some examples, although not shown in the drawings, when the memory transistor is formed in the well as shown in fig. 1, a voltage of 0 volt may also be applied to the well. Alternatively, when the memory transistor is directly formed in the substrate, a voltage of 0v may be applied to the substrate.
Thus, in the various embodiments of the present disclosure as described above, it is possible to achieve a write operation of a selected memory transistor by appropriately setting voltages applied to word lines of respective rows and bit lines of respective columns, and to avoid crosstalk to the remaining non-selected memory transistors.
Fig. 7 illustrates an exemplary read operation 700 for reading memory transistors located in the nth row and nth column (as indicated by the dashed box in the figure).
As shown in fig. 7, the memory transistors to be read are located in the nth row and the nth column, with their gates connected to the word line WLn of the row, their drains connected to the bit line BLn of the column, and their sources connected to the common source line CSL. The read/write/erase operation part 710 may apply a third gate voltage Vg3 to a word line WLn (also may be referred to as a selected word line) connected to a gate of a memory transistor to be read and a fourth gate voltage Vg4 to the remaining word lines (also may be referred to as non-selected word lines), wherein the fourth gate voltage Vg4 is lower than the third gate voltage Vg3, apply a third drain voltage Vd3 to a bit line BLn (also may be referred to as a selected bit line) connected to a drain of the memory transistor to be read and a fourth drain voltage Vd4 to the remaining bit lines (also may be referred to as non-selected bit lines), and apply a first source voltage Vs1 to the common source line CSL, wherein a difference between the fourth gate voltage Vg4 and the first source voltage Vs1 is smaller than an erase threshold voltage of each memory transistor, and the fourth drain voltage Vd4 is equal to the first source voltage Vs1. As previously described, in the present disclosure, "erase threshold voltage" means a threshold voltage that a memory transistor has after being erased. Thus, in the memory array, the gate-source voltage difference (=v4—vs 1) of the memory transistors in the non-selected rows is smaller than the erase threshold voltage thereof, ensuring that the memory transistors are all in an off state, preventing the disturbance of the reading of the memory transistors in the selected rows, and the drain-source voltage difference (=v4—vs 1) of the memory transistors in the non-selected columns in the selected rows is 0, thereby avoiding the current flow on the bit lines of the non-selected columns.
In some embodiments, as previously described, the voltage difference (=vg 3-Vs 1) between the gate and source of the (selected) memory transistor to be read may be set to a value between the erase threshold voltage and the written threshold voltage, and the voltage on the selected bit line (third drain voltage Vd 3) is made greater than the first source voltage Vs1, thereby determining that the selected memory transistor is on, i.e., erased (memory data "1"), when there is current flow on the selected bit line, and determining that the selected memory transistor is off, i.e., written (memory data "0"), when there is no current flow on the selected bit line.
In some embodiments, the values of the third gate voltage Vg3, the fourth gate voltage Vg4, the third drain voltage Vd3, the fourth drain voltage Vd4, the first source voltage Vs1 described above may be appropriately set according to, for example, the values of the erase threshold voltage, the written threshold voltage, etc. of each memory transistor as described above, to avoid the non-selected memory transistor from interfering with the read operation of the selected memory transistor.
In some examples, the difference between the third drain voltage Vd3 and the first source voltage Vs1 may be 0.5V to 2V, and/or the difference between the third gate voltage Vg3 and the first source voltage Vs1 may be 0V to 1V, and/or the difference between the fourth gate voltage Vg4 and the first source voltage Vs1 may be-1V to-5V.
In some examples, the difference between the fourth gate voltage Vg4 and the first source voltage Vs1 may be 0.5 v-1 v lower than the erase threshold voltage of each memory transistor to ensure that the memory transistors of the non-selected row are all in the off state.
In some examples, the first source voltage Vs1 may be 0V, the third gate voltage Vg3 may be 0V to 1V, the fourth gate voltage Vg4 may be-1V to-5V, the third drain voltage Vd3 may be 0.5V to 2V, and the fourth drain voltage Vd4 may be 0V.
In addition, in some examples, although not shown in the drawings, when the memory transistor is formed in the well as shown in fig. 1, a voltage of 0 volt may also be applied to the well. Alternatively, when the memory transistor is directly formed in the substrate, a voltage of 0v may be applied to the substrate.
Thus, in the various embodiments of the present disclosure as described above, the read operation of the selected memory transistor can be achieved by appropriately setting the voltages applied to the word lines of the rows, the bit lines of the columns, and the common source line, and the crosstalk of the remaining non-selected memory transistors to their read operation is avoided.
Fig. 8 illustrates an exemplary erase operation 800 for erasing memory transistors of an nth row (as indicated by the dashed box in the figure).
Although fig. 8 shows that the memory transistors of one row are subjected to the erase process, it is to be understood that the read/write/erase operation section 810 may generally perform the erase process in units of rows or blocks (composed of a plurality of rows), in other words, may simultaneously perform the erase process for the memory transistors of at least one row (one row or more rows), and may perform the same operation as the row to be erased shown in fig. 8 for all the rows to be erased.
As shown in fig. 8, to be erased is the memory transistor of the n-th row. The read/write/erase operation part 810 may apply a fifth gate voltage Vg5 to a word line WLn (which may also be referred to as a selected word line) of a row to be erased and a sixth gate voltage Vg6 to the remaining word lines (which may also be referred to as non-selected word lines), wherein the sixth gate voltage Vg6 is higher than the fifth gate voltage Vg5, and apply a fifth drain voltage Vd5 to each bit line, wherein a common source line CSL connecting sources of the storage transistors may be floating or applied with a second source voltage Vs2. Thus, in the memory array, the voltage difference (=vg 5-Vd 5) between the gate and the drain of the memory transistor in the (selected) row to be erased is smaller than the voltage difference (=vg 6-Vd 5) between the gate and the drain of the memory transistor in the remaining non-selected row, but since electrons are to be moved from the charge storage layer in the gate structure to the active region in the erase operation, the above-mentioned gate-drain voltage difference is to be negative, the smaller the value thereof means that the potential difference therebetween is larger, and thus it can be ensured that only the memory transistor in the (selected) row to be erased achieves a desired erase effect (i.e., a desired effect of electron tunneling out of the charge storage layer).
In some embodiments, the values of the fifth gate voltage Vg5, sixth gate voltage Vg6, fifth drain voltage Vd5, and second source voltage Vs2 described above may be appropriately set according to factors such as the thickness of the tunneling layer, such that the absolute value of the gate-drain voltage difference (=vg 5-Vd 5) of the memory transistors in only the selected row is greater than the voltage required for electrons to tunnel from the charge storage layer to the active region, the absolute value of the gate-drain voltage difference (=vg 6-Vd 5) of the memory transistors in the non-selected row is insufficient to satisfy the condition for electrons to tunnel from the charge storage layer to the active region, or the amount of tunneling electrons generated is much smaller than the amount of tunneling electrons in the memory transistors in the selected row (e.g., differs by at least one order of magnitude).
In some examples, the value of the second source voltage Vs2 may be equal to the value of the fifth drain voltage Vd5, whereby electron tunneling may occur across both the source and drain of the memory transistors in the selected row, increasing the speed of erase.
In some examples, the difference between the fifth gate voltage Vg5 and the fifth drain voltage Vd5 may be-10V to-6V.
For example, the fifth drain voltage Vd5 may be 0V, the fifth gate voltage Vg5 may be-10V to-6V, the sixth gate voltage Vg6 may be 0V, the second source voltage Vs2 may be 0V or the common source line CSL may be floating.
In addition, in some examples, although not shown in the drawings, when the memory transistor is formed in the well as shown in fig. 1, a voltage of 0 volt may also be applied to the well. Alternatively, when the memory transistor is directly formed in the substrate, a voltage of 0v may be applied to the substrate.
Thus, in the various embodiments of the present disclosure as described above, the erase operation of the memory transistors of the selected row can be achieved by appropriately setting voltages applied to the word lines of the rows, the bit lines of the columns, and the common source line, and crosstalk is prevented from being generated to the memory transistors of the remaining non-selected rows.
With the write operation 600, read operation 700, and/or erase operation 800 illustrated in fig. 6,7, and/or 8 as described above, writing, reading, and/or erasing of a memory array in embodiments of the present disclosure may be accomplished simply, conveniently, and quickly, and avoiding cross-talk of non-selected memory transistors.
Fig. 5-8 described above illustrate the circuit structure of the memory array and its corresponding write, read and erase operations as described above in fig. 2A-2C, 3A-3C, or 4A-4C. It will be appreciated by those skilled in the art that the memory array of figures 2A-2C, 3A-3C, or 4A-4C may exhibit any one or more of a configuration in which portions of the gates of the respective memory transistors of the same row are connected to the same word line, or portions of the drains of the respective memory transistors of the same column are connected to the same bit line, or portions of the sources of the respective memory transistors of the same row or column are connected to the same source line, for any reason. Any one or more of the foregoing structures, although not illustrated and described in the embodiments shown in fig. 5-8, are contemplated as falling within the scope of the present application, as the design concepts are similar to those illustrated in the embodiments described above.
In addition, the NOR-type memory array and the corresponding NOR-type memory according to the present disclosure as described above may be applied to various electronic devices having storage requirements, for example, computers, smart phones and peripheral electronic devices thereof (such as bluetooth headphones and wearable devices), electronic devices applying the internet of things, vehicle-mounted electronic devices, and the like.
Those skilled in the art will appreciate that various circuit configurations of the present disclosure described above may be suitably modified as desired, and such modifications are within the scope of the present disclosure.
The foregoing description of the embodiments of the present disclosure has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the improvement of technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.