Disclosure of Invention
Based on the technical problems in the background art, the invention provides a quantum bit waveform real-time calibration system based on a pre-calculation pipeline mixed architecture, which is used for solving the waveform distortion compensation problem in high-speed and high-fidelity quantum gate operation and meeting the requirements of a superconducting quantum computing system on waveform precision, speed and flexibility.
The invention provides a quantum bit waveform real-time calibration system based on a pre-calculation pipeline mixed architecture, which comprises the following components:
The multiphase envelope distributor is used for receiving and analyzing external predefined envelope data and dynamically converting the external envelope data into parallel output;
The differential module is used for carrying out differential operation on the output of the multiphase envelope distributor to obtain M paths of differential signals, wherein M is an integer;
The coefficient generator is used for latching the coefficients transmitted by the upper computer and generating the coefficients required by the filter according to the latched coefficients;
The filter is used for filtering the multipath differential signals based on the M paths of differential signals and the filter coefficients generated by the coefficient generator as inputs and outputting calibrated waveforms in a multipath parallel mode;
And a digital adder for adding the output of the polyphase envelope distributor and the output of the filter to generate a final calibration waveform, the calibration waveform being output by the digital-to-analog converter, acting on the qubits after passing through the qubit control line, for controlling the qubits.
Further, the filter adopts an IIR filter, and the filtering process of the multipath differential signals is as follows:
introducing a pre-computation stage and a pipeline computation stage in an IIR filter and providing coefficients to said pre-computation stage and said pipeline computation stage by a coefficient generator;
the pre-calculation stage performs pre-calculation on the M paths of differential signals through M+1 times of multiplication operation and M times of addition and addition operation;
The pipeline computing stage utilizes a classical first-order IIR filter to compute based on the computing result of the pre-computing stage, a first stage in the pipeline computing stage takes the computing result of the pre-computing stage after the differential signal output by the corresponding branch of the differential module is delayed as an input signal, and the computing result of the other stages takes the computing result of the differential signal corresponding to the branch of the differential module after the differential signal is delayed and the computing result of the previous stage as an input signal.
Further, in the pipeline compute stage, splitting the M-1 stage pipeline to complete in at least M-1 clock cycles, each stage pipeline processes at most only two multiplications and one addition.
Further, the pre-calculation stage calculates the output signals of all the moments of the corresponding branches completely independently, and each stage in the pipeline completes calculation in two clock cycles.
Further, the coefficient generator issues coefficient data based on the upper computer and latches the coefficient data, and the remaining coefficients are dynamically calculated and latched by using the complex multiplier.
Further, the complex multipliers used in the coefficient generator and the filter are both divide-and-conquer operation models, which are specifically:
The complex multiplication is decomposed into the combination of three times of real multiplication and five times of real addition, so that one multiplier is saved.
Further, set upAre all real numbers, and the real numbers are all the same,Is calculated by using a divide-and-conquer operation model as imaginary number unitAnd outputs real and imaginary parts, the specific structure is as follows:
Will be realInput into a real adder I to carry out realInputting the real number into a real number adder II;
Taking the output of the adder I and the output of the adder II as the input of a real multiplier I;
Will be realInput to a real multiplier II to carry out realInputting to a real multiplier III;
taking the inverse number of the output of the real multiplier I and the output of the real multiplier II as the input of a real adder III;
taking the inverse number of the output of the real multiplier II and the output of the real multiplier III as the input of a real adder IV to output an imaginary part;
The output of the real adder three and the inverse of the output of the multiplier three are taken as the input of the real adder five to output the real part.
Further, the calibration waveform is output through a digital-to-analog converter, and acts on the qubit after passing through the qubit control line, specifically:
outputting a calibration waveform to a qubit control line through a digital-to-analog converter and a low noise amplifier;
The correction waveform is applied to the qubit through the qubit control line.
Further, the classical first-order IIR filter is as follows:
;
Wherein, theRespectively representing the discrete-time index(s),Respectively represent time of dayIs used to determine the value of the output signal of (a),Indicating time of dayIs used to determine the value of the input signal,As the weight coefficient of the input path,Representing the weight coefficients of the feedback path.
Further, the saidAndThe calculation formula of (2) is as follows:
Wherein, theAndAs a function of the line parameters,,For the sampling rate, T is the sampling period.
The quantum bit waveform real-time calibration system based on the pre-calculation pipeline hybrid architecture has the advantages that an extensible hardware implementation scheme based on real-time calibration on an IIR filter sheet of pre-calculation and pipeline interleaving is provided, a complex domain calibration scheme can be supported, intermediate results are calculated in advance through pre-calculation, data correlation is reduced, effective data points are multiplexed out through pipeline calculation, output data rate is improved, a large number of coefficients are needed for filtering calculation in the IIR filter architecture, higher delay is generated through upper computer configuration, coefficients are generated on the sheet in real time through a coefficient generator, a large number of storage resources are not needed, low delay and high real-time performance can be ensured, a divide-and-treat operation model of a complex multiplier is constructed, one complex multiplication is divided into an optimal combination of three real multiplications and five real additions, hardware overhead is saved, compatibility with the complex calibration scheme is facilitated, a pipeline structure is easy to expand, a key path is not lengthened, each sampling point is updated by one value, all sampling points are effective values, filter coefficients can be dynamically configured, and requirements of a superconducting quantum computing system on waveform precision, speed and flexibility are met.
Detailed Description
In the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The invention may be embodied in many other forms than described herein and similarly modified by those skilled in the art without departing from the spirit or scope of the invention, which is therefore not limited to the specific embodiments disclosed below.
As shown in fig. 1 to 14, the quantum bit waveform real-time calibration system based on the pre-calculation pipeline hybrid architecture provided by the invention comprises:
The multiphase envelope distributor is used for receiving and analyzing external predefined envelope data and dynamically converting the external envelope data into parallel output;
The differentiating module is used for differentiating the output of the multiphase envelope distributor;
The coefficient generator is used for latching the coefficients transmitted by the upper computer and generating the coefficients required by the filter in the scheme according to the latched coefficients;
The filter is used for filtering the multipath differential signals based on the multipath differential signals output by the differential module and the coefficients generated by the coefficient generator as inputs;
a digital adder for adding the output of the polyphase envelope distributor and the output of the filter to generate a final calibration waveform, which is output by a digital-to-analog converter (DAC), passes through a qubit control line and acts on the qubits for controlling the qubits.
In the embodiment, the quantum bit control waveform calibration with high speed, high precision and high real-time performance is realized by a pre-calculation pipeline interleaving method, the on-chip calculation of the coefficient generator is performed in real time, a large amount of storage resources are not needed, and the low delay and the high real-time performance are ensured. Therefore, the embodiment carries out waveform calibration on the quantum bit waveform through the coefficient generator and the filter, is used for solving the problem of waveform distortion compensation in high-speed and high-fidelity quantum gate operation, and meets the requirements of a superconducting quantum computing system on waveform precision, speed and flexibility.
In other words, aiming at the waveform distortion compensation requirement in the superconducting quantum measurement and control system, a pre-calculation pipeline interweaved filter architecture is provided, and a calibration circuit capable of supporting complex domain modeling characteristics is provided. The intermediate result is calculated in advance by the pre-calculation stage, the data correlation is reduced, and the output data rate is improved by the pipeline stage. By setting the coefficient generator, the filter coefficients are externally configured, and the required coefficients are generated on-chip in real time. By the method, the output precision and the output data rate are improved, each sampling point is updated once, all sampling points are effective values, the coefficients of the filter can be dynamically configured, and the high performance requirement of the superconducting quantum computing system can be met.
In one embodiment, the multiphase envelope distribution apparatus is primarily for receiving externally pre-stored envelope data, multiphase output according to clock frequency, to match the subsequent multipath parallel filtering structure.
In one embodiment, the filter is configured with filter coefficients by a coefficient generator, and high-speed and high-precision filtering is realized on multiple paths of differential signals output by the differential module.
The conventional Infinite Impulse Response (IIR) filter has a time sequence constraint problem in hardware implementation due to a recursion structure, and is particularly characterized in that a clock frequency is limited due to an overlong critical path, so that the data rate and the calibration accuracy of a system are affected. In order to solve the problem, the present embodiment optimally designs the existing IIR filter, as shown in fig. 7, and proposes a high-speed IIR filter based on pre-calculation pipeline interleaving, wherein the values of sampling points are updated once in each clock period, and all the sampling points are valid data points, so that the performance requirements of a high-speed digital-to-analog converter (DAC) can be adapted, and the data rate and the output precision of the system are significantly improved.
Specifically, as shown in fig. 3, the direct one-type representation method of the conventional classical first-order IIR filter is as follows: , wherein,Respectively representing the discrete-time index(s),Indicating time of dayIs used to determine the value of the output signal of (a),Indicating time of dayIs used to determine the value of the input signal,For the moment of timeIs used to determine the value of the output signal of (a),For the weight coefficient of the input path, the current input signal value is directly controlledFor the current output signal valueIs used for the degree of contribution of (a),Mainly affects the overall gain and high frequency response of the filter; The weight coefficient representing the feedback path directly controls the output signal value of the previous momentFor the output signal value at the current timeIn a qubit waveform calibration circuit,,WhereinObtained through experiments of quantum bit correlation, represents the relevant parameters of the line,,For the sampling rate, T is the sampling period, the structure of which is shown in fig. 2, the recursive structure of which makes the current output depend on the past output and the current input, and the feedback mechanism makes the critical path too long, which limits the maximum clock frequency of the system in hardware implementation, the rate of the first-order IIR filter in FPGA implementation does not exceed 100MHz, and the rate of the first-order IIR filter in chip implementation does not exceed 500MHz. The existing implementation scheme matches the rate of the DAC by averaging a plurality of points, not all calibration waveforms are effective data points, errors exist in partial points in the process of calculating the calibration waveforms in real time, the measurement and control requirements of superconducting quantum calculation cannot be effectively supported along with further improvement of the sampling rate, and larger errors exist for short pulses, wherein the DAC (Digital to Analog Converter, digital-to-analog converter) is a device for converting digital signals into analog signals.
The filter can output the multi-point effective calibration waveform in parallel in the same clock period in the slow clock domain, and the first-order filtering is repeatedly iterated to obtain the following steps:
wherein M represents the number of pre-calculated stages,For the index of the number of levels,As the weight coefficient of the input path,Representing the weight coefficients of the feedback path.
At this moment in timeOutput signal value of (2)Only with time of dayOutput signal value of (2)In relation, the critical path may be optimized such that the rate of a single IIR filter is increased but insufficient to support the 3G sampling rate. In ASIC implementation, a single IIR filter can work to 375M, and the complete calibration waveform can be obtained by splitting the input envelope data through a difference module and calibrating the split envelope data respectively;
Wherein, theFor the pre-computed number of stages, equal to the number of paths output in parallel,Is an index of the output path.
Although the method of implementing iterative computation through full parallelism as shown in fig. 4 meets the requirement of data rate, M multiplications and M-1 additions are additionally introduced for each computation, and M paths are needed, and the resource overhead is as followsThe magnitude of (a) increases, so this embodiment introduces an increased block filtering structure, as shown in FIG. 5, i.e., forThe data at the moment adopts full parallel computation, and the following M-1 data still adopts a recursion structure to compute, namely:
;
;
Wherein, theIs the firstThe differential signal is provided in a path,As a result of the feedback signal,Is the firstThe output signal of the way is provided,Is the firstDifferential signals of the paths.
The cost is 2M times of that of a classical filter, but an M-1 level carry chain is introduced when the recursive structure is calculated, the logic structure of the recursive structure is M-1 times more complex than that of the classical IIR filter, and the highest main frequency capable of working is greatly reduced. By inserting registers into the recursive computation structure, the pipeline structure is formed, the length of a critical path is reduced, and the working frequency is improved.
In the embodiment, a precalculation stage and a pipeline stage based on a classical IIR filter are introduced, the precalculation stage comprises M+1 multipliers and M adders, precalculation is performed based on M paths of differential signals and M+1 coefficients, the hierarchical pipeline utilizes a classical first-order IIR filter structure to respectively calculate differential signals of the remaining paths, the first stage takes the precalculation results of the corresponding differential input and precalculation stage as input signals, and the other stages take the differential input and the calculation results of the previous stage as input signals.
The pre-calculation stage calculates the signals at all moments completely independentlyFurther, the pipeline computing stage may calculate the signal independently of the 3~M stages. The calculation result of the previous stage can be utilizedCalculating the current timeThe method comprises the following steps:
;
This does not affect any timeThe rest of the stages are the same. To this end, the M-1 stage carry chain has been broken into an M-1 stage pipeline structure, with the M-1 stage combinational logic split to complete in M-1 or more clock cycles, with each stage pipeline handling at most only two multiplications and one addition.
For the description of m=8, each stage of pipeline is implemented using two clock cycles, and the structure is shown in fig. 7, and the algorithm of the structure can be specifically developed as follows:
。
The embodiment provides an IIR filter architecture with pipeline interleaving, and a calibration circuit capable of supporting complex domain modeling characteristics. And through a pipeline architecture, intermediate results are calculated in advance, so that the data correlation is reduced, and the output data rate is improved. The classical structure has the advantages that the critical path is overlong due to the feedback calculation of the IIR filter, the critical path can be run to 375M through time sequence constraint in ASIC (application specific integrated circuit) realization, linear interpolation or near interpolation is needed for matching a high-speed DAC (digital-to-analog converter), and a large error exists in the process of short pulse calibration. While the full parallel architecture needs to consume a large number of multipliers, and occupies more resources. The increment block structure optimizes resources on the basis of the full parallel structure, but introduces a carry chain, so that a critical path is overlong. The design breaks through a carry chain to form a pipeline structure, shortens a key path on the premise of guaranteeing the data effectiveness, improves expansibility and effective data throughput, and can provide powerful support for quantum regulation waveform calibration in a large scale at high speed and high precision.
In one embodiment, as shown in FIG. 6, the coefficient generator is used for latching the coefficients transmitted by the upper computer and generating the coefficients required by the IIR filter according to the latched coefficients;
the classical first-order IIR filter only needsAndTwo filter coefficients are configured by an upper computer, and the implementation of the full-parallel IIR filter (taking M=8 as an example) is as follows;
Wherein, theAs the weight coefficient of the input path,The weight coefficients representing the feedback path are represented,Are all coefficients configured by the upper computer.
In this embodiment, more coefficients are needed, taking m=8 as an example, nine coefficients are needed for one filter, and only two coefficients are needed for a classical IIR filter. The specific coefficients are shown in the fully parallel structure of fig. 4. If all the coefficients are configured by the upper computer, a large amount of time is required, the real-time performance is poor, and the coefficients to be configured are too many, so the upper computer is adopted in the embodimentTwo filter coefficients are calculated in real time on-chip using two complex multipliers.
In order to support modeling of the complex characteristics of qubits, complex multipliers are used during calibration, and conventional IIR filters do not need to use real multipliers, and in this embodiment, complex multipliers are used in both the coefficient generator and the IIR filter for optimizing complex multiplication units to save area and power consumption.
All the complex multipliers used by the coefficient generator and the IIR filter in the embodiment are divide-and-conquer operation models, specifically, one complex multiplication is decomposed into a combination of three real multiplications and five real additions, one multiplier is saved, and resources required in hardware implementation can be saved.
A complex multiplier as shown in fig. 8, whereinAre all real numbers and have the function of completing operationAnd outputs real and imaginary parts thereof. Direct computation requires four multipliers, i.e. complex operationsThen 4 real multipliers are required.
The embodiment will be realInput into a real adder I to carry out realInput to a real adder II, taking the output of the adder I and the output of the adder II as the input of a real multiplier I, taking the real numbersInput to a real multiplier II to carry out realThe method comprises the steps of inputting the output of a real number multiplier I and the inverse number of the output of a real number multiplier II into a real number multiplier III, taking the inverse number of the output of the real number multiplier II and the output of the real number multiplier III as the input of a real number adder IV to output an imaginary number, and taking the output of the real number adder III and the output of the multiplier III as the input of a real number adder V to output a real number.
Namely, the present embodiment sorts the complex operations:
;
Only three multipliers are needed in this embodiment. In the embodiment, by constructing the divide-and-conquer operation model of the complex multiplier, one complex multiplication is decomposed into the optimal combination of three real multiplications and five real additions, and one multiplier is saved.
In this embodiment, in order to avoid overflow during multiplication and addition, an extended bit width and truncation compensation logic is used to reduce quantization errors in the operation process and optimize resource utilization, fig. 7 is an error analysis result, and compares errors of PC pre-storing and on-chip real-time generation of a calculated code value, which is shown as a normalized error.
The ideal calibration waveforms in fig. 9 and 11 are identical, comparing fig. 9 and 11, the rising and falling edges of which have seen a significant gap, the rising and falling edges of fig. 9 being closer to the ideal calibration waveforms, comparing fig. 10 and 12, normalizing the errors, and the waveform real-time correction using the present embodiment can be seen, and the final error can be controlled to be on the order of ten thousandths.
Fig. 13 shows a comparison graph of the effect of the scheme among the embodiment, the ideal calibration waveform and the linear interpolation scheme, when the pulse time is short, as the effective data points are fewer, when the linear interpolation scheme is adopted, a larger error can be obviously seen at the rising edge and the falling edge.
Fig. 14 compares normalized error analysis of different types of regulated waveforms calibrated in different line parameters, including average value and standard deviation of normalized error in corresponding time after falling edge, four lines corresponding to four different sets of line parameters, each line including seven points corresponding to waveforms of different lengths and different types. Compared with the hardware implementation of the linear interpolation scheme, the method can reduce the average value of errors by at least one order of magnitude for different line parameters within 20ns-40ns after the falling edge, optimize standard deviation and have smaller fluctuation of different lines and different envelopes. Most of the indexes 1us-1.1us after the falling edge are optimized without obvious degradation.
Therefore, the key path is shortened by inserting the latch based on the pre-calculation stage, the time sequence is optimized, the pipeline stage calculates the rest output results based on the result of the pre-calculation stage, the data is not required to be compressed, and one sampling point can be updated under each high-frequency clock period, so that all the data are effective data, and the equivalent sampling rate and the accuracy are greatly improved.
As an example;
1) A multiphase envelope distributor;
receiving four paths of external parallel inputs, converting the four paths of analyzed parallel inputs into eight paths of parallel outputs according to the needs, and transmitting the eight paths of parallel data outputs to the differential module. In addition, the external input can be adjusted as required.
2) A differential module;
And carrying out differential operation on the eight paths of parallel data, and transmitting the eight paths of differential signals which are output in a differential mode to the IIR filter module.
3) A coefficient generator; for real-time generation of on-chip coefficients;
The method comprises the steps of outputting coefficient data based on a lookup table, latching required filter coefficients, generating other filter coefficients according to the latching coefficients, and adjusting the other filter coefficients according to target frequency when the coefficient generator calculates the other filter coefficients according to the latching coefficients.
4) An IIR filter;
Correlation coefficients required by the IIR filter are configured in real time by a coefficient generator, and multiple paths of differential signals from the differential module are filtered.
5) A digital adder;
the output of the multiphase envelope distributor is added with the multipath parallel output signals of the IIR filter to generate a final correction waveform, the correction waveform is output to a quantum bit control line through a high-speed DAC and a low-noise amplifier by an analog output module, and the correction waveform acts on quantum bits by the quantum bit control line.
The embodiment realizes high-precision waveform generation and synchronous control through multipath interleaving, combines the advantages of a digital circuit and an analog circuit, and fully plays the flexibility of the digital circuit and the high-precision characteristic of the analog circuit. The embodiment has the characteristics of high precision, high real-time performance, high flexibility, high synchronism and high stability, and is suitable for a superconducting quantum computing measurement and control system.
In this embodiment, a quantum bit waveform calibration system of an IIR filter with pre-calculation pipeline interleaving is further provided, including a multiphase envelope distributor, a difference module, a coefficient generator, an IIR filter, and a digital adder;
The multiphase envelope distributor is used for receiving and analyzing external predefined envelope data and dynamically converting the external envelope data into parallel output;
The differentiating module is used for differentiating the output of the multiphase envelope distributor;
the coefficient generator is used for latching the coefficients transmitted by the upper computer and generating other coefficients according to the latched coefficients;
The IIR filter is used for filtering the multipath differential signals based on the multipath differential signals output by the differential module and the coefficients generated by the coefficient generator as inputs;
And a digital adder for adding the output of the polyphase envelope distributor and the output of the IIR filter to generate a final calibration waveform, which acts on the qubits after passing through the qubit control line, for controlling the qubits.
In this embodiment, a computer-readable storage medium is also provided, on which a plurality of classification programs for being called by a processor and performing the waveform calibration method as described above are stored.
It will be appreciated by those of ordinary skill in the art that implementing all or part of the steps of the above method embodiments may be accomplished by hardware associated with program instructions, and that the above program may be stored in a computer readable storage medium which, when executed, performs the steps comprising the above method embodiments, where the above storage medium includes various media that may store program code, such as ROM, RAM, magnetic or optical disks.
The foregoing is only a preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art, who is within the scope of the present invention, should make equivalent substitutions or modifications according to the technical scheme of the present invention and the inventive concept thereof, and should be covered by the scope of the present invention.