Detailed Description
In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
In describing positional relationships, when an element such as a layer, film or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present unless otherwise indicated. Further, when a layer is referred to as being "under" another layer, it can be directly under, or one or more intervening elements may also be present. It will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening elements may also be present.
Where the terms "comprising," "having," and "including" are used herein, another component may also be added unless explicitly defined terms such as "only," "consisting of," etc., are used. Unless mentioned to the contrary, singular terms may include plural and are not to be construed as being one in number.
It will be understood that, although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present application.
It will be further understood that when interpreting an element, although not explicitly described, the element is intended to include the range of errors which should be within the acceptable limits of deviation from the particular values identified by those skilled in the art. For example, "about," "approximately," or "substantially" may mean within one or more standard deviations, and is not limited herein.
Further, in the specification, the phrase "planar distribution diagram" refers to the drawing when the target portion is viewed from above, and the phrase "cross-sectional diagram" refers to the drawing when the cross section taken by vertically cutting the target portion is viewed from the side.
Moreover, the figures are not drawn to a 1:1 scale, and the relative sizes of elements are drawn in the figures by way of example only and are not necessarily drawn to true scale.
As described in the background art section, in the related art, there is a problem that the display effect of the display screen of the display panel is not ideal. The inventor researches and discovers that the reason why the phenomenon occurs is that in the bias reset process of the driving transistor in the pixel circuit, a voltage difference exists between a bias reset signal and a data signal to be displayed currently, so that the driving current input to the light emitting device is inaccurate, the light emitting brightness of the light emitting device is affected, the display uniformity is poor finally, and the display effect is not ideal.
Specifically, taking the pixel circuit shown in fig. 1 as an example, the Data signal Data1 is written into the gate of the driving transistor M2 through the transistor M1, and is stored in the capacitor C1. The driving transistor M2 generates a driving current to drive the light emitting device D1 to emit light according to the Data signal Data 1. However, since the potential of the node a cannot be stably maintained (such as leakage current, etc.), and the voltage of the node B is the power supply voltage to be connected, a voltage difference between the gate and the source of the driving transistor M2 is forward biased. The characteristic of the driving transistor M2 is changed by being in the forward bias state for a long time, so that a problem of unreliable display easily occurs.
In order to adjust such a bias state, in the related art, a bias reset signal is generally introduced to the node B by the transistor M1 to perform bias adjustment, and the characteristics of the driving transistor M2 are improved. However, in practical applications, the bias reset signal is often a data signal (e.g., dataN) to be displayed by an nth row (e.g., 7 th row, 8 th row, etc.) pixel circuit below the current pixel circuit. When DataN has a voltage difference from the Data signal Data1 of the current pixel circuit, the voltage DataN affects the driving current transmitted to the light emitting device D1 through the node C, and thus affects the light emitting brightness of the light emitting device D1.
Taking fig. 2 as an example, a gray picture (e.g., gray 32) is displayed in a region 1 of the display panel, a black picture block (e.g., gray 0) is displayed in a region 2, at this time, an abnormal brightness phenomenon occurs in an R-angle (Radius corner) region below the panel, and an abnormal brightness transition region 11 occurs between the region 1 and the region 2, which affects display uniformity. The inventors have found that this is because, in the pixel circuit corresponding to the transition region 11, the data signal of gray32 is written to the gate of the driving transistor M2, but the bias reset signal introduced into the node B is the data signal of gray 0. Since the data signal voltage of gray0 is higher than the voltage of the data signal of gray32, the signal will pull up the voltages of node B and node C simultaneously. The rise of the voltage of the node C causes the anode voltage of the light emitting device D1 to increase, thereby increasing the driving current input to the light emitting device D1, resulting in the luminance of the light emitting device D1 being higher than expected, and thus the picture of the transition region 11 is abnormally lighted, exhibiting a bright band phenomenon. However, the R-angle region is generally subjected to a "black insertion" process to improve the R-angle display effect, and thus, similarly to the transition region 11, the R-angle region under the panel may be abnormally lighted. Especially, under low brightness, the abnormal brightness phenomenon is more obvious, and the display effect is seriously affected.
Based on the above technical problems, the inventors further studied and found that by adopting the same data signal as the writing gate of the driving transistor to perform bias reset on the driving transistor, the problem of abnormal brightness of the R angle and the transition region can be improved, and the display effect can be improved. Based on this, the inventors have studied the technical solution of the embodiments of the present application. The display panel comprises a pixel circuit, a data line, a first fixed potential signal line, a first scanning line, a second scanning line and a light-emitting element, wherein the pixel circuit comprises a driving transistor, a data writing transistor, a first switching tube, a second switching tube and a first capacitor, a first electrode of the data writing transistor is electrically connected with the data line and a first electrode of the first switching tube, a second electrode of the data writing transistor is electrically connected with the first electrode or the second electrode of the driving transistor, a second electrode of the first switching tube is electrically connected with the first electrode of the first capacitor and the first electrode of the second switching tube, a second electrode of the second switching tube is electrically connected with the first electrode or the second electrode of the driving transistor, a gate of the data writing transistor and a gate of the first switching tube are electrically connected with the first scanning line, a gate of the second switching tube is electrically connected with the second scanning line, the first electrode of the driving transistor is electrically connected with the first fixed potential signal line, and the second electrode of the second switching tube is electrically connected with the first electrode of the first switching tube and the second switching tube, and the first electrode of the second switching tube and the second switching tube is electrically connected with the first electrode of the second switching tube and the first switching tube and the second switching tube, and the second switching tube is electrically connected with the first electrode of the second switching tube and the first switching tube and the second switching tube. By adopting the technical scheme, the data signals written into the driving transistor are used for biasing and resetting the driving transistor, so that the voltage of the driving transistor is not influenced by the data signals of other rows of pixel circuits, the driving current input to the light-emitting element is more stable, the display uniformity of the display panel is higher, and the display effect is better.
The foregoing is the core idea of the present application, and the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without making any inventive effort are intended to fall within the scope of the present application.
Fig. 3 is a schematic circuit diagram of a display panel according to an embodiment of the present application, and fig. 4 is a schematic circuit diagram of another display panel according to an embodiment of the present application. Referring to fig. 3 to fig. 4, the display panel provided in the embodiment of the application includes a pixel circuit 100, a data line for accessing a data signal Vdata, a first fixed potential signal line for accessing a first fixed potential signal PVDD, a first scan line for accessing a first scan signal S1P, a second scan line for accessing a second scan signal S2P, and a light emitting element D.
The pixel circuit 100 includes a driving transistor T1, a data writing transistor T2, a first switching transistor T3, a second switching transistor T4, and a first capacitor Cst1.
The transistors may be thin film transistors (Thin Film Transistor, TFT), such as low temperature polysilicon transistors (Low Temperature Poly-Silicon, LTPS) or low temperature poly oxide transistors (Low Temperature Polycrystalline Oxide, LTPO). The first and second poles of each transistor need to be determined according to the specific type of TFT transistor, and illustratively, the source of each transistor is the first pole and the drain is the second pole.
The first pole of the data writing transistor T2 is electrically connected to the data line and the first pole of the first switching tube T3, and the second pole of the first switching tube T3 is electrically connected to the first pole of the first capacitor Cst1 and the first pole of the second switching tube T4. The second pole of the first capacitor Cst1 is electrically connected to a first fixed potential signal line. The gate of the data writing transistor T2 and the gate of the first switching transistor T3 are electrically connected with the first scanning line, the gate of the second switching transistor T4 is electrically connected with the second scanning line, the first pole of the driving transistor T1 is electrically connected with the first fixed potential signal line, and the second pole of the driving transistor T1 is electrically connected with the light emitting element D.
In the embodiment of the present application, the connection modes of the second pole of the second switching transistor T4 and the second pole of the data writing transistor T2 and the driving transistor T1 are flexible. As an example, referring to fig. 3, the second pole of the second switching transistor T4 and the second pole of the data writing transistor T2 are electrically connected to the first pole of the driving transistor T1.
In the same display stage, the enable level period of the second scan signal S2P accessed by the second scan line is located after the enable level period of the first scan signal S1P accessed by the first scan line.
The enable level period refers to a time interval in which the enable level exists. During this period, the transistor being controlled is continuously in an on state, allowing current to pass.
In practical implementation, each signal including the first scan signal S1P and the second scan signal S2P has a high level state and a low level state, wherein one level state is an enable level, and the other level state is a disable level, which is specifically determined according to the type of the controlled transistor (such as N-type or P-type). As an example, the data writing transistor T2, the first switching transistor T3, and the second switching transistor T4 are P-type transistors, and the enable level of the first scan signal S1P and the second scan signal S2P is low. When the first scan signal S1P is at an enable level, the data writing transistor T2 and the first switching transistor T3 are in a conductive state, thereby allowing a current to flow between the first pole and the second pole. When the first scan signal S1P is at a disable level, the data writing transistor T2 and the first switching transistor T3 transition to an off state. When the second scan signal S2P is at the enable level, the second switch T4 is in the on state. When the second scan signal S2P is at the disable level, the second switching tube T4 is in the off state. For convenience of explanation, the data writing transistor T2, the first switching transistor T3, and the second switching transistor T4 are P-type transistors.
The driving period of the display panel includes a refresh frame for updating data of pixels on the display panel and a hold frame for maintaining a display state of the pixels between the two refreshes, so that an image can be stably presented.
The same display stage refers to a refresh frame in the same driving period or a hold frame in the same driving period. The refresh frame may include a data writing phase, a bias reset phase, and a light emitting phase, among others. As shown in fig. 5, in the data writing stage t2, the first scan signal S1P is at an enable level. At this stage, the data signal Vdata transferred from the data line is transferred to the first electrode of the driving transistor T1 through the data writing transistor T2 on the one hand, so that the data signal Vdata transferred from the data writing transistor T2 is written to the gate electrode. On the other hand, the data signal Vdata transmitted by the data line is written into the first capacitor Cst1 through the first switching tube T3, and the first capacitor Cst1 stores a voltage value corresponding to the data signal Vdata.
In the offset reset phase t4, the second scan signal S2P is at an enable level. The data signal Vdata stored in the first capacitor Cst1 is biased and reset to the first pole of the driving transistor T1 through the second switching transistor T4, so that the driving transistor T1 is in an On-bias (OBS) state, and forward bias between the source and gate potentials of the driving transistor T1 is improved, so as to improve the characteristics of the driving transistor T1.
In the light emitting stage, the driving transistor T1 generates a driving current according to the data signal Vdata to drive the light emitting element D to emit light. The light emitting element D may be a light emitting Diode, for example, an Organic LIGHT EMITTING Diode (OLED). The second electrode of the driving transistor T1 is connected to the anode of the light emitting element D, and the cathode of the light emitting element D is connected to a second fixed potential signal line for connecting to the second fixed potential signal PVEE.
In summary, in the display panel provided by the embodiment of the application, during the refresh frame period, when the first scan signal S1P is in the enable level period, the data signal Vdata transmitted by the data line is written into the driving transistor T1 through the data writing transistor T2 on the one hand, and is written into the first capacitor Cst1 through the first switching transistor T3 on the other hand, and the voltage value corresponding to the data signal Vdata is stored in the first capacitor Cst 1. When the second scan signal S2P is in the enable level period, the data signal Vdata stored in the first capacitor Cst1 is biased and reset to the driving transistor T1 through the second switch T9, so that the bias state of the driving transistor T1 can be adjusted, and the characteristics of the driving transistor T1 are improved. The data signal Vdata for bias reset is the same as the data signal Vdata written into the driving transistor T1, so that the voltage of the driving transistor T1 is not affected by the data signals of the pixel circuits of other rows, and the potential of the anode of the light emitting device D is more stable, and the driving current transmitted to the light emitting element D is more stable. Thus, the display uniformity of the display panel can be improved, and the display effect is improved.
It should be noted that, in the related art, the first electrode of the driving transistor T1 is electrically connected to the fixed voltage signal line, so as to introduce the fixed voltage signal to bias and reset the driving transistor T1. However, this way of introducing a fixed voltage through the fixed voltage signal line increases the load of the display panel, thus increasing power consumption. According to the embodiment of the application, the data signal Vdata written into the driving transistor T1 is saved, and the driving transistor T1 is biased and reset by utilizing the data signal Vdata, so that a fixed voltage signal is not required to be consumed, and the power consumption of the display panel can be reduced.
Specifically, when the first scan signal S1P accessed by the first scan line is in the enable level period, the first switch tube T3 is turned on, the second switch tube T4 is turned off, and the data signal Vdata accessed by the data line is written into the first capacitor Cst1. When the second scan signal S2P accessed by the second scan line is in the enabling level period, the first switch tube T3 is turned off, the second switch tube T4 is turned on, and the data signal Vdata stored by the first capacitor performs bias reset on the driving transistor T1.
As shown in fig. 5, the bias reset phase t4 of the same display phase is located after the data write phase t 2. In the data writing stage T2, the first scan signal S1P is at an enabling level, the first switch tube T3 is turned on, and the second switch tube T4 is turned off due to the second scan signal S2P being at a non-enabling level, so that the data signal Vdata accessed by the data line can be stored in the first capacitor Cst1. After the enabling level period of the first scan signal S1P is ended, the first switching tube T3 is turned off, and the signal transmission path between the data line and the first capacitor Cst1 is cut off.
In the bias reset stage T4, the second scan signal S2P is converted into an enable level, the second switch tube T4 is turned on, the data signal Vdata stored in the first capacitor Cst1 is transmitted to the first pole of the driving transistor T1 through the second switch tube T4, and bias reset is performed on the driving transistor T1.
In the embodiment, the data signal Vdata is written into the first capacitor Cst1 in the data writing stage t2, and is stored in the first capacitor Cst 1. In the bias reset phase, the data signal Vdata stored in the first capacitor Cst1 biases and resets the driving transistor T1. Thus, the voltage of the anode of the light emitting element D can be stabilized by the driving transistor T1, and the driving current flowing into the light emitting device D can be stabilized, so that the display uniformity can be improved, and the display effect of the panel can be improved.
It can be appreciated that the connection manner of the second pole of the second switching transistor T4 and the second pole of the data writing transistor T2 with the driving transistor T1 is flexible, and can be specifically determined according to the type of the driving transistor T1.
In some embodiments, referring to fig. 4, an example of the driving transistor T1 is an N-type transistor, and the second pole of the data writing transistor T2 and the second pole of the second switching transistor T4 are electrically connected to the second pole of the driving transistor T1.
In the present embodiment, in the data writing stage, the data signal Vdata is transmitted to the second pole of the driving transistor T1, and then transmitted to the gate of the driving transistor T1. In the bias reset stage T4, the data signal Vdata stored in the first capacitor Cst1 can be transmitted to the second pole of the driving transistor T1, so as to effectively adjust the bias state of the driving transistor T1, and improve the performance of the driving transistor T1. Meanwhile, the voltage of the node N3 can be stabilized, so that the driving current flowing into the light emitting device D is stabilized, and the light emitting luminance of the light emitting device D is stabilized.
In some embodiments, as shown in fig. 3, the driving transistor T1 is a P-type transistor, and the second pole of the data writing transistor T2 and the second pole of the second switching transistor T4 are electrically connected to the first pole of the driving transistor T1.
In the present embodiment, in the data writing stage, the data signal Vdata can be transmitted from the data writing transistor T2 to the first pole of the driving transistor T1, and transmitted to the gate through the second pole of the driving transistor T1. In the bias reset stage T4, the data signal Vdata stored in the first capacitor Cst1 can be effectively transmitted to the first pole of the driving transistor T1 through the second switching transistor T4, so as to realize accurate adjustment of the bias state of the driving transistor T1, and further enable the voltage of the node N3 to be more stable. For convenience of explanation, the driving transistor T1 is exemplified as a P-type transistor.
In some embodiments, in the refresh frame, the first scan signal S1P is a single pulse signal, and the second scan signal S2P is a single pulse signal.
In the related art, in the same display stage, a scan signal of a transistor for controlling writing of data is generally set to a signal including two pulses, the first pulse for writing a data signal to a driving transistor and the second pulse for bias resetting the driving transistor. Still taking fig. 1-2 as an example, the pixel circuit shown in fig. 1 is a pixel circuit corresponding to the transition region 11. Referring to fig. 6, in the same display stage, the scan signal SP for controlling the transistor M1 includes two active pulses, and the transistor M1 is turned on to write the data signal of the gray32 into the driving transistor M2 under the action of the first active pulse. Under the action of the second active pulse, the transistor M1 is turned on to write the data signal of gray0 to the first pole of the driving transistor M2, so as to perform bias reset on the driving transistor M2. Although this two-pulse timing control scheme can realize offset reset, it also causes problems of abnormal lighting of the R angle and bright lines.
In this embodiment, taking the data signal of gray32 as an example, in the refresh frame, the first scan signal S1P is a single pulse signal, and when the first scan signal S1P is at the enable level, the data signal of gray32 is written into the driving transistor T1 through the data writing transistor T2 and is written into the first capacitor Cst1 through the first switching transistor T3. When the second scan signal S2P is at the enable level, the first scan signal S1P is at the disable level, and the first switch T3 is turned off, so that the data signal of the gray0 cannot be written, and the node N2 or the node N3 writes the voltage of the node N5, i.e. Vdata（gray32）. Thus, the potential of the anode of the light emitting element D is not affected by the data signals of the other row pixel circuits, the driving current writing of the light emitting element D is stabilized, and abnormal increase of the driving current does not occur. As shown in fig. 7, by adopting the scheme of the embodiment of the application, the abnormal brightness and abnormal bright line condition of the R-angle area of the display panel can be obviously improved, and the display uniformity is high.
In some embodiments, the pixel circuit further includes a second capacitance Cst2. The first pole of the second capacitor Cst2 is electrically connected to the gate of the driving transistor T1, and the second pole of the second capacitor Cst2 is electrically connected to the first fixed potential signal line. The second capacitor Cst2 plays a role of storing the data signal Vdata of the gate of the driving transistor T1, so that the gate voltage of the driving transistor T1 is more stable, and the driving current generated in the light emitting stage is stable, so as to improve the display uniformity.
In some embodiments, the display panel further includes a third scan line for accessing a third scan signal S2N, and the pixel circuit 100 further includes a threshold compensation transistor T5. The first pole of the threshold compensation transistor T5 is electrically connected to the second pole of the driving transistor T1, the second pole of the threshold compensation transistor T5 is electrically connected to the gate of the driving transistor T1, and the gate of the threshold compensation transistor T5 is electrically connected to the third scan line.
In the refresh frame, the enable level period of the third scan signal S2N accessed by the third scan line overlaps the enable level period of the first scan signal S1P, and does not overlap the enable level period of the second scan signal S2P.
It will be appreciated that the refresh frame also includes a threshold compensation phase t3, the threshold compensation phase t3 being located before the bias reset phase t4 and overlapping the data write phase t2 in time sequence. Thus, in the data writing stage T2, when the first scan signal S1P is at the enabling level, the data writing transistor T2 is turned on, the data signal Vdata is written to the first pole (P-type transistor) or the second pole (N-type transistor) of the driving transistor T1, the third scan signal S2N is also at the enabling level, the threshold compensation transistor T5 is turned on, and the data signal Vdata is transmitted to the gate of the driving transistor T1 through the threshold compensation transistor T5, so as to implement data writing and threshold compensation.
By setting the threshold compensation transistor T5, the threshold voltage of the driving transistor T1 can be compensated in the threshold compensation stage T3, so that the problem of uneven display brightness caused by the threshold voltage drift of the driving transistor T1 can be solved, and the display quality of the display panel can be improved.
In this embodiment, by overlapping the enable level period of the third scan signal S2N with the enable level period of the first scan signal S1P, so that the threshold compensation stage T3 and the data writing stage T2 overlap in time sequence, the on periods of the threshold compensation transistor T5 and the data writing transistor T2 can overlap, the processes of threshold compensation and data writing are accelerated, the total duration of the refresh frame is reduced, and the display refresh efficiency is improved.
By the fact that the enabling level period of the third scanning signal S2N and the enabling level period of the second scanning signal S2P are not overlapped, threshold compensation and bias reset can be independent, expected functions can be accurately completed in each process, and reliability and stability of operation of the pixel circuit are improved.
In some embodiments, the start time of the enable level period of the third scan signal S2N is earlier than the start time of the enable level period of the first scan signal S1P, and the end time is later than the end time of the enable level period of the first scan signal S1P. Therefore, the data writing stage T2 is in the threshold compensation stage T3, so that the threshold compensation transistor T5 is in a conducting state in the data writing stage T2, and the data signal Vdata can be stably transmitted to the gate of the driving transistor T1. And the compensation of the threshold voltage can be completed in enough time, so that the threshold compensation effect is improved.
In some embodiments, as shown in fig. 5, the third scan signal S2N remains at the disable level during the hold frame.
The third scan signal S2N maintains the disable level, which can keep the threshold compensation transistor T5 in an off state, prevent charge leakage, and stabilize the gate potential of the driving transistor T1. Further, the stable gate voltage can improve the uniformity of the driving current generated by the driving transistor T1, and can improve the stability of the frame display.
In the hold frame, the enable level period of the second scan signal S2P is located after the enable level period of the first scan signal S1P.
In the enable level period of the first scan signal S1P, the data signal transmitted by the data line is transmitted to the first pole of the driving transistor T1 through the data writing transistor T2, and the bias reset of the driving transistor T1 is started. Meanwhile, the data signal transmitted by the data line is transmitted to the first capacitor Cst1 through the first switching tube T3, and is stored by the first capacitor Cst 1. In the enable level period of the second scan signal S2P, the second switching transistor T4 is turned on, and the data signal stored in the first capacitor Cst1 performs bias adjustment on the driving transistor T1. Thus, it is possible to have enough time to perform bias adjustment on the driving transistor T1 during the holding frame, and the characteristics of the driving transistor T1 can be effectively improved.
In some embodiments, the voltage of the data signal to which the data line is connected is a constant voltage at the hold frame. By adjusting the bias state of the driving transistor T1 by applying a constant voltage, the problem that the driving transistor T1 is unstable in display due to the forward bias state can be improved, and the display states of the holding frame and the refresh frame are made to coincide.
Further, the voltage of the data signal connected to the hold frame data line is greater than the voltage of the data signal connected to the refresh frame data line.
The bias state of the driving transistor T1 can be further adjusted by increasing the voltage of the signal for bias reset in the hold frame, contributing to the improvement of the display effect.
In some embodiments, the refresh frame and the sustain frame each include a non-light emitting period and a light emitting period, and the enable level period of the first scan signal and the enable level period of the second scan signal overlap with the non-light emitting period.
Specifically, the refresh frame includes a non-light-emitting period and a light-emitting period, in which both the enable level period of the first scan signal S1P and the enable level period of the second scan signal S2P overlap the non-light-emitting period and do not overlap the light-emitting period.
In this embodiment, by separating the light-emitting phase from the non-light-emitting phase, the data writing and bias adjustment process can not interfere with normal light-emitting display, and brightness fluctuation or picture flickering caused by operation overlapping can be avoided. Further, the bias adjustment is performed in the non-light-emitting period, and the driving transistor T1 can be kept in a good driving state in the light-emitting period.
It will be appreciated that the display panel further includes a light emission control signal line connected to the light emission control signal EM, and the pixel circuit 100 further includes a first light emission control transistor T6 and a second light emission control transistor T7, wherein a first electrode of the first light emission control transistor T6 is electrically connected to the first fixed potential signal line, and a second electrode of the first light emission control transistor T6 is electrically connected to a first electrode of the driving transistor T1. The first electrode of the second light-emitting control transistor T7 is electrically connected with the second electrode of the driving transistor T1, the second electrode of the second light-emitting control transistor T7 is electrically connected with the anode of the light-emitting element D, and the cathode of the light-emitting element D is electrically connected with the second fixed potential signal line. The gate of the first light emission control transistor T6 and the gate of the second light emission control transistor T7 are both electrically connected to a light emission control signal line.
The end time of the enable level period of the second scan signal S2P is earlier than the start time of the enable level period of the emission control signal EM to which the emission control signal line is connected in the refresh frame and the sustain frame.
In the present embodiment, the first light emission control transistor T6 and the second light emission control transistor T7 are synchronously controlled by the light emission control signal EM for controlling the light emitting element D to be turned on. In timing, the enable level period of the second scan signal S2P of the refresh frame and the sustain frame is earlier than the enable level period of the light emission control signal EM, and the bias reset operation may be continued until the light emission period starts.
In the refresh frame, the first OBS stage T6 in which the driving transistor T1 is in the OBS state includes a bias reset stage T4 and a reset sustain stage T5, and the reset sustain stage T5 is a time interval between the end time of the enable level of the second scan signal S2P and the start time of the enable level of the emission control signal EM. In the hold frame, the second OBS period T7 in which the driving transistor T1 is in the OBS state is a time period between the start timing of the enable level of the first scan signal S1P and the start timing of the enable level of the emission control signal EM. Therefore, the offset adjustment effect can be improved, so that abnormal bright lines and abnormal bright phenomena of R angles can be better improved, and the display effect is improved.
In some embodiments, the display panel further includes a first initialization signal line for accessing the first initialization signal REF1, and a fourth scan line for accessing the fourth scan signal S1N. The pixel circuit 100 further includes a first initialization transistor T8, a first pole of the first initialization transistor T8 is electrically connected to the first initialization signal line, a second pole of the first initialization transistor T8 is electrically connected to a gate of the driving transistor T1, and a gate of the first initialization transistor T8 is electrically connected to the fourth scan line.
In the refresh frame, the enable level period of the fourth scan signal S1N introduced by the fourth scan line is located before the enable level period of the second scan signal S2P, the enable level period of the first scan signal S1P, and the enable level period of the third scan signal S2N.
The non-light emitting phase of the refresh frame further includes an initialization phase t1, the initialization phase t1 being located before the threshold compensation phase t3, the data writing phase t2, and the offset reset phase t 4. In the initialization stage T1, the fourth scan signal S1N is an enable level, the first initialization transistor T8 is turned on, the first initialization voltage signal Vrefn1 is provided to the gate of the driving transistor T1, the second end of the storage capacitor Cst, and the second pole of the threshold compensation transistor T5, and the gate of the driving transistor T1, the second pole of the threshold compensation transistor T5, and the second capacitor Cst2 are reset, so that the influence of the previous frame on the next frame is avoided, and the light emitting accuracy of the light emitting element D is further improved.
The type of the first initializing transistor T8 may be set according to the specific case. As an example, the first initializing transistor T8 is an N-type transistor, so as to reduce the leakage of the second capacitor Cst2, which is beneficial to maintaining the stable gate potential of the driving transistor T1 and improving the accuracy of the driving current generated by the driving transistor T1. Further, the threshold compensation transistor T5 may be an N-type transistor, so that the gate potential of the driving transistor T1 is more stable.
In some embodiments, the display panel further includes a second initialization signal line for accessing the second initialization signal REF 2. The pixel circuit 100 further includes a second initializing transistor T9, a first electrode of the second initializing transistor T9 is electrically connected to the second initializing signal line, a second electrode of the second initializing transistor T9 is electrically connected to an anode of the light emitting element D, and a gate of the second initializing transistor T9 is electrically connected to the first scanning line.
In this embodiment, the second initializing transistor T9 is turned on under the action of the first scanning signal S1P, so that the anode potential of the anode D of the light emitting device can be reset to the level of the second initializing signal REF2 before the light emitting stage starts, so as to effectively eliminate the residual charge of the previous frame and improve the display residual image problem.
For a better understanding of the above embodiments, the following detailed explanation is made in connection with an alternative embodiment. Referring to fig. 3, the display panel includes a pixel circuit 100, a data line for accessing a data signal Vdata, a first fixed potential signal line for accessing a first fixed potential signal PVDD, a second fixed potential signal line for accessing a second fixed potential signal PVEE, a first scan line for accessing a first scan signal S1P, a second scan line for accessing a second scan signal S2P, a third scan line for accessing a third scan signal S2N, a fourth scan line for accessing a fourth scan signal S1N, a light emission control signal line for accessing a light emission control signal EM, a first initialization signal line for accessing a first initialization signal REF1, a second initialization signal line REF for accessing a second initialization signal 2, and a light emitting element D.
The pixel circuit 100 includes a driving transistor T1, a data writing transistor T2, a first switching transistor T3, a second switching transistor T4, a threshold compensating transistor T5, a first light emitting control transistor T6, a second light emitting control transistor T7, a first initializing transistor T8, a second initializing transistor T9, a first capacitor Cst1, and a second capacitor Cst2. The driving transistor T1, the data writing transistor T2, the first switching transistor T3, the second switching transistor T4, the first light emitting control transistor T6, the second light emitting control transistor T7, and the second initializing transistor T9 are P-type transistors, and the threshold compensating transistor T5 and the first initializing transistor T8 are N-type transistors. Each transistor may be a TFT, and the source of each transistor is a first pole and the drain is a second pole.
Fig. 5 is a timing chart of the pixel circuit 100 in the present embodiment, and the working procedure of the pixel circuit 100 in the present embodiment is described below with reference to fig. 3 and 5:
In the non-light emitting period of the refresh frame, the light emission control signal EM is at a non-enable level, and the first light emission control transistor T6 and the second light emission control transistor T7 are turned off.
In the initialization stage T1, the fourth scan signal S1N is at an enable level, the first initialization transistor T8 is turned on, the first initialization signal REF1 is transmitted to the node N1, and the gate of the driving transistor T1, the second pole of the threshold compensation transistor T5, and the second capacitor Cst2 are reset.
In the data writing stage T2 and the threshold compensation stage T3, the third scan signal S2N is at an enable level, and the threshold compensation transistor T5 is turned on to connect the node N3 and the node N1.
After the first scan signal S1P is converted from the disable level to the enable level, the data writing transistor T2 and the first switching transistor T3 are turned on, and the data signal Vdata to be displayed transmitted by the data line is transmitted to the node N2 through the data writing transistor T2, is transmitted to the node N1 through the second diode of the driving transistor T1 and the threshold compensation transistor T5, and is stored by the second capacitor Cst 2. On the other hand, the data signal Vdata transmitted by the data line is written into the node N5 through the first switching tube T3, and the voltage value corresponding to the data signal Vdata is stored by the first capacitor Cst 1. In the enable level period of the first scan signal S1P, the second initialization transistor T9 is turned on, and the anode potential of the light emitting element anode D is reset according to the second initialization signal REF 2.
After the first scan signal S1P is converted from the enable level to the disable level, the threshold compensation transistor T5 is turned on continuously, so that there is enough time for threshold compensation. After the threshold compensation is finished, the third scan signal S2N is converted into a disable level.
In the bias reset phase T4, the second scan signal S2P is at an enable level, and the data signal Vdata stored in the first capacitor Cst1 biases and resets the first electrode of the driving transistor T1 through the second switching transistor T4.
In the reset maintaining period T5, the first electrode of the driving transistor T1 is kept at the potential of the data signal Vdata and is kept in the OBS state.
In the light emitting stage, that is, after the light emission control signal EM is converted from the disable level to the enable level, the first light emission control transistor T6 and the second light emission control transistor T7 are turned on, the driving transistor T1 generates a driving current and transmits the driving current to the light emitting element D, and the light emitting element D emits light according to the driving current.
In the hold frame, the second OBS period T7 in which the driving transistor T1 is in the OBS state is a time period between the start timing of the enable level of the first scan signal S1P and the start timing of the enable level of the emission control signal EM. In the hold frame, the third scan signal S2N and the fourth scan signal S1N are at a non-enable level, and no data refreshing is required, and no reset is performed on the node N1. By increasing the voltage of the data signal accessed by the data line, the offset adjustment effect can be improved, and the display effect of the holding frame can be improved.
The display panel can adjust the bias state of the driving transistor T1 and improve the characteristics of the driving transistor T1. The data signal Vdata for bias reset is the same as the data signal Vdata written into the driving transistor T1, so that the voltage of the driving transistor T1 is not affected by the data signals of the pixel circuits of other rows, and the potential of the anode of the light emitting element D is more stable, and the driving current transmitted to the light emitting element D is more stable. Thus, the display uniformity of the display panel can be improved, and the display effect is improved.
Based on the same application conception, the embodiment of the application also provides a display device. Fig. 8 is a schematic structural diagram of a display device 20 according to an embodiment of the present application, and as shown in fig. 8, the display device 20 includes a display panel 10, and the display panel 10 may be disposed with reference to the display panel in any of the above embodiments. Illustratively, as shown in fig. 8, the display device 20 includes a display panel 10. Therefore, the display device 20 also has the advantages of the display panel in the above embodiment, and the same points can be understood by referring to the explanation of the display panel 10, which is not described in detail below.
The display device 20 provided in the embodiment of the present application may be a mobile phone, or any electronic product with a display function, including but not limited to a television, a notebook computer, a desktop display, a tablet computer, a digital camera, a smart bracelet, smart glasses, a vehicle-mounted display, an industrial control device, a medical display screen, a touch interaction terminal, etc., which is not particularly limited in the embodiment of the present application.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.