Disclosure of Invention
The invention discloses an MIM capacitor, a manufacturing method thereof and a semiconductor device, which are used for solving the problem of high manufacturing cost of the MIM capacitor.
The invention discloses a manufacturing method of an MIM capacitor, which comprises the steps of providing a substrate, sequentially forming a first electrode layer, a first insulating layer, a second electrode layer and a second insulating layer on the substrate, etching the first electrode layer, the first insulating layer, the second electrode layer and the second insulating layer by taking a mask layer with a first electrode pattern as a mask, enabling the first electrode layer to form a first electrode, enabling the patterns of the first insulating layer, the second electrode layer and the second insulating layer to be identical with those of the first electrode, carrying out back etching on the second insulating layer to remove the edge part of the second insulating layer, enabling the second insulating layer to expose the edge part of the second electrode layer, and carrying out etching on the second electrode layer by taking the back etched second insulating layer as a mask, so as to remove the edge part of the second electrode layer, and enabling the second electrode layer to form a second electrode.
In some embodiments of the present invention, the first insulating layer and the second insulating layer are made of the same material, and the etching back the second insulating layer includes etching back the first insulating layer and the second insulating layer by a wet etching process to remove an edge portion of the second insulating layer and an edge portion of the first insulating layer.
In some embodiments of the invention, the material of the first insulating layer and the second insulating layer comprises silicon nitride.
In some embodiments of the present invention, the first insulating layer and the second insulating layer are different in material, and the etching the second electrode layer includes etching the second electrode layer and the first insulating layer by a dry etching process to remove an edge portion of the second electrode layer and an edge portion of the first insulating layer. In some embodiments of the invention, the second insulating layer has a thickness in a range of greater than or equal to 1500 angstroms. In some embodiments of the present invention, the first electrode layer and the second electrode layer are the same material, and the material of the first electrode layer and the second electrode layer comprises titanium nitride.
In some embodiments of the present invention, the materials of the first electrode layer and the second electrode layer are different, and the materials of the first electrode layer and the second electrode layer are different metals or metal compounds.
In some embodiments of the invention, the base includes a semiconductor substrate, a circuit layer on the semiconductor substrate, and a third insulating layer including a silicon carbonitride layer.
In a second aspect, the invention discloses a MIM capacitor fabricated by a fabrication method as described in any of the preceding claims.
In a third aspect, the present invention discloses a semiconductor device comprising a MIM capacitor as described above.
The invention discloses an MIM capacitor and a manufacturing method thereof and a semiconductor device, comprising the steps of providing a substrate, sequentially forming a first electrode layer, a first insulating layer, a second electrode layer and a second insulating layer on the substrate, taking a mask layer with a first electrode pattern as a mask, etching the first electrode layer, the first insulating layer, the second electrode layer and the second insulating layer to enable the first electrode layer to form a first electrode, enabling the patterns of the first insulating layer, the second electrode layer and the second insulating layer to be identical with those of the first electrode, then carrying out back etching on the second insulating layer to remove the edge part of the second insulating layer, enabling the second insulating layer to expose the edge part of the second electrode layer, then carrying out etching on the second electrode layer to remove the edge part of the second electrode layer, and enabling the second electrode layer to form a second electrode, thereby only needing to use a photomask to form the mask layer with the first electrode pattern, further reducing the manufacturing cost of the capacitor and improving the manufacturing efficiency of the capacitor.
Detailed Description
The technical solutions in the embodiments of the present invention will be described below with reference to the accompanying drawings in the embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
As shown in fig. 1, the conventional MIM capacitor is fabricated by sequentially forming a first electrode layer 11, a first insulating layer 12, a second electrode layer 13 and a second insulating layer 14 on a substrate 10, then forming a first mask 15 having a second electrode pattern on the second insulating layer 14, as shown in fig. 2, then etching the second electrode layer 13 to form a second electrode, as shown in fig. 3, then forming a protective layer 16 on the second electrode, as shown in fig. 4, then forming a second mask 17 having a first electrode pattern on the protective layer 16, as shown in fig. 5, and then etching the first electrode layer 11 and the first insulating layer 12 to form a first electrode and an insulating layer, as shown in fig. 6, but two different photomasks are required to form the first mask 15 having the second electrode pattern and the second mask 17 having the first electrode pattern, respectively, resulting in a high fabrication cost of the MIM capacitor.
Based on this, the invention discloses a manufacturing scheme of MIM capacitor, firstly, a mask layer with a first electrode pattern is used as a mask, the first electrode layer, the first insulation layer, the second electrode layer and the second insulation layer are etched to form the first electrode on the first electrode layer, then the second insulation layer is etched to expose the peripheral area of the second electrode layer, then the second insulation layer is used as a mask, and the second electrode layer is etched to form the second electrode, so that the MIM capacitor can be manufactured by using only one photomask, and further the manufacturing cost of the MIM capacitor can be reduced.
As an optional implementation of the present disclosure, an embodiment of the present invention discloses a method for manufacturing an MIM capacitor, as shown in fig. 7, where the method includes:
S101, providing a substrate, and sequentially forming a first electrode layer, a first insulating layer, a second electrode layer and a second insulating layer on the substrate.
In some embodiments of the present invention, as shown in fig. 8, a base 10 is provided, the base 10 includes a semiconductor substrate 101, a circuit layer 102 and a third insulating layer 103 on the semiconductor substrate 101, and a first electrode layer 11, a first insulating layer 12, a second electrode layer 13 and a second insulating layer 14 are sequentially formed on the base 10. The deposition method of the first electrode layer 11, the first insulating layer 12, the second electrode layer 13 and the second insulating layer 14 may be a chemical vapor deposition method, a physical vapor deposition method, an atomic layer deposition method or the like. Of course, the present invention is not limited thereto, and in other embodiments, the base 10 may include only the semiconductor substrate 101, that is, the first electrode layer 11, the first insulating layer 12, the second electrode layer 13, and the second insulating layer 14 may be sequentially formed on the semiconductor substrate 101.
The semiconductor substrate 101 includes at least one of a Si substrate, a Ge substrate, a SiGe substrate, a SiC substrate, a SiGeC substrate, an InAs substrate, a GaAs substrate, an InP substrate, an InGaAs substrate, and the like. The semiconductor substrate 101 may have a single-layer structure formed over the above substrate, or may have a multi-layer structure formed over the above substrate. The circuit layer 102 includes a plurality of metal layers and a dielectric layer between any two metal layers, each metal layer including a trace or conductive plane, etc., the traces or conductive planes between different metal layers being electrically connected by vias that extend through the dielectric layer between the two, wherein the metal layers include a copper layer. The third insulating layer 103 includes a silicon carbonitride layer, a silicon oxide layer, or the like.
And S102, etching the first electrode layer, the first insulating layer, the second electrode layer and the second insulating layer by taking the mask layer with the first electrode pattern as a mask, so that the first electrode layer forms a first electrode, and the patterns of the first insulating layer, the second electrode layer and the second insulating layer are identical to those of the first electrode.
In the embodiment of the present invention, a mask layer may be formed on the second insulating layer 14, the mask layer is a photoresist layer, then a photomask having a first electrode pattern is used to expose and develop the photoresist layer, so as to transfer the first electrode pattern onto the photoresist layer, that is, the mask layer, and then, as shown in fig. 9, the mask layer 20 having the first electrode pattern is used as a mask, to etch the first electrode layer 11, the first insulating layer 12, the second electrode layer 13 and the second insulating layer 14, and the etched first electrode layer 11, first insulating layer 12, second electrode layer 13 and second insulating layer 14 are as shown in fig. 10, where the first electrode layer 11 forms a first electrode, and the patterns of the first insulating layer 12, second electrode layer 13 and second insulating layer 14 are the same as those of the first electrode.
It should be noted that, in some embodiments of the present invention, the first electrode layer 11, the first insulating layer 12, the second electrode layer 13, and the second insulating layer 14 may be etched by a wet etching process, and of course, the present invention is not limited thereto, and in other embodiments, the first electrode layer 11, the first insulating layer 12, the second electrode layer 13, and the second insulating layer 14 may be etched by a dry etching process.
And S103, back etching the second insulating layer to remove the edge part of the second insulating layer, so that the edge part of the second electrode layer is exposed by the second insulating layer.
In some embodiments of the present invention, a wet etching process may be used to etch back the second insulating layer 14, as shown in fig. 11, where the etched back second insulating layer 14 exposes an edge portion of the second electrode layer 13. Based on this, in some embodiments of the present invention, the materials of the first insulating layer 12 and the second insulating layer 14 may be the same, for example, the materials of the first insulating layer 12 and the second insulating layer 14 are silicon nitride or silicon dioxide, and the first insulating layer 12 is etched back in the process of etching the second insulating layer 14 by wet etching. As shown in fig. 11, the etched back first insulating layer 12 also exposes the edge portion of the second electrode layer 13. Of course, the present invention is not limited thereto, and in other embodiments, the second insulating layer 14 may be etched using a dry etching process.
It should be noted that, because the wet etching process is isotropic etching, the second insulating layer 14 needs to have a certain thickness so as not to etch the second insulating layer 14 completely. In some embodiments of the present invention, the thickness of the second insulating layer 14 ranges from greater than or equal to 1500 angstroms. Of course, the present invention is not limited to this, and in other embodiments, the thickness of the second insulating layer 14 may be set according to actual requirements, which is not described herein.
And S104, etching the second electrode layer by taking the etched second insulating layer as a mask so as to remove the edge part of the second electrode layer, and forming a second electrode on the second electrode layer.
In the embodiment of the present invention, the second insulating layer 14 exposing the edge portion of the second electrode layer 13 may be used as a mask to etch the second electrode layer 13 to remove the edge portion of the second electrode layer 13, so that the second electrode layer 13 forms the second electrode shown in fig. 12, where the length of the second electrode in the direction parallel to the substrate 10 is smaller than the length of the first electrode in the direction parallel to the substrate 10.
Note that, in the process of dry etching the second electrode layer 13, the second insulating layer 14 is also etched, so that after dry etching the second electrode layer 13, the second insulating layer 14 is etched away or a small portion of the film layer remains as shown in fig. 12.
In the embodiment of the invention, by etching the first electrode and then etching the second electrode from bottom to top, two photomasks are not needed to form the masks of the first electrode and the second electrode, and only one photomask is needed to form the mask of the first electrode, so that the manufacturing cost of the MIM capacitor can be reduced. In addition, the manufacturing method of the MIM capacitor in the embodiment of the invention has the advantages of simpler flow and higher manufacturing efficiency of the MIM capacitor.
In other embodiments of the present invention, the materials of the first insulating layer 12 and the second insulating layer 14 may be different, for example, the materials of the first insulating layer 12 and the second insulating layer 14 are silicon nitride, silicon dioxide, and the like, respectively. On this basis, as shown in fig. 13, the second insulating layer 14 may be etched back by a wet etching process or a dry etching process, and the edge portion of the second insulating layer 14 may be removed, so that the edge portion of the second electrode layer 13 is exposed by the second insulating layer 14, and then the second electrode layer 13 and the first insulating layer 12 may be etched synchronously by using the etched back second insulating layer 14 as a mask and by using the dry etching process, so as to remove the edge portion of the second electrode layer 13 and the edge portion of the first insulating layer 12, so as to form the second electrode as shown in fig. 12.
Of course, the present invention is not limited thereto, and in other embodiments, the etched second insulating layer 14 shown in fig. 13 may be used as a mask, the second electrode layer 13 may be etched by a wet etching process or a dry etching process, the edge portion of the second electrode layer 13 may be removed, the second electrode shown in fig. 14 may be formed, the first insulating layer 12 may be etched by a wet etching process or a dry etching process, and the edge portion of the first insulating layer 12 may be removed, so as to form the structure shown in fig. 12.
In some embodiments of the present invention, the materials of the first electrode layer 11 and the second electrode layer 13 are the same, for example, the materials of the first electrode layer 11 and the second electrode layer 13 are both titanium nitride, so in order to avoid etching the second electrode layer 13 during etching the first electrode layer 11, a dry etching process is preferred to etch the second electrode layer 13. Of course, the present invention is not limited thereto, and in other embodiments, the materials of the first electrode layer 11 and the second electrode layer 13 may be different, for example, the materials of the first electrode layer 11 and the second electrode layer 13 are respectively different metals or metal compounds such as copper, silver, and aluminum.
Note that, as shown in fig. 15, since the conductive layer 30 on top of the MIM capacitor needs to be electrically connected to the first electrode and the second electrode through the plurality of vias 301, and the via 301 electrically connected to the first electrode cannot be electrically connected to the second electrode, the length of the second electrode in the direction parallel to the substrate 10 is smaller than the length of the first electrode in the direction parallel to the substrate 10.
It should be noted that, as shown in fig. 15, after etching the second electrode layer 13 to form the MIM capacitor, the protection layer 16, the planarization layer 50, and the like may be formed on the side of the MIM capacitor facing away from the substrate 10, which is not described herein.
As an alternative implementation of the disclosure, an embodiment of the present invention discloses a MIM capacitor fabricated by using the method for fabricating a MIM capacitor as disclosed in any one of the above embodiments.
As an alternative implementation of the present disclosure, an embodiment of the present disclosure discloses a semiconductor device including a MIM capacitor as disclosed in any one of the embodiments above. The semiconductor device may include a radio frequency power supply or a filter, etc.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples only represent a few embodiments of the present specification, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the present description, which is within the scope of the present description. Accordingly, the protection scope of the patent should be determined by the appended claims.