Detailed Description
The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings.
As shown in fig. 1, the present invention provides a vehicle-mounted multi-communication protocol test motherboard, which includes:
The CANFD communication module is used for sending a test frame to equipment to be tested under the condition of receiving a CANFD test instruction;
The vehicle-mounted Ethernet communication module is used for converting a standard Ethernet test signal into a vehicle-mounted Ethernet test signal, and transmitting the vehicle-mounted Ethernet test signal to the equipment to be tested;
the processor module is used for generating a CANFD test instruction and a standard Ethernet test signal, and generating a device test report of the device to be tested according to the response frame and the standard Ethernet response signal;
the test frame comprises a data frame, a control instruction frame, a fault frame and an error frame, and the vehicle-mounted Ethernet test signal comprises a data packet, a control signal, a fault signal and an error signal.
Specifically, a processor module, a memory module, a CANFD communication module, a vehicle-mounted ethernet communication module, a PCIe bus, a power conversion module and a clock module are arranged on the main board. The CANFD communication module and the vehicle-mounted Ethernet communication module are respectively communicated with the processor module through PCIe buses, the power supply conversion module is connected with an external power supply through a power interface and is used for adaptively supplying power to the processor module, the CANFD communication module and the vehicle-mounted Ethernet communication module, the CANFD communication module is connected with external equipment to be tested through a CAN interface, the vehicle-mounted Ethernet module is connected to the external equipment to be tested through a common Ethernet interface and a vehicle-mounted Ethernet interface, and the processor module is respectively connected with external display equipment and external storage equipment through an HDMI interface and an NVME interface. The processor module can adopt an Intel i7 series processor, and the memory module can adopt a DDR4 SODIMM dual in-line memory module.
And the CANFD communication module is used for generating and actively transmitting test frames comprising specified contents to the equipment to be tested according to a preset protocol format under the condition that the CANFD test instruction transmitted by the processor module is received, wherein the types of the test frames comprise, but are not limited to, data frames, control instruction frames, fault frames and error frames, and each frame can be configured with a specific identifier, a specific data load length and a specific bit filling strategy. In addition, the CANFD communication module is further provided with a response detection and frame filtering mechanism for monitoring the CAN bus in real time after sending the test frame and capturing a response frame which is returned by the equipment to be tested and corresponds to the test frame one by one, and after receiving the response frame, judging the validity of the response frame through a checking mechanism comprising CRC check, bit filling identification and frame interval analysis, and uploading the analyzed valid frame data to the processor module for subsequent communication performance evaluation, protocol consistency detection and functional response analysis. The in-vehicle Ethernet communication module is configured to implement bi-directional protocol and electrical layer conversion between a standard Ethernet and an in-vehicle Ethernet conforming to IEEE 802.3bw (100 BASE-T1) or IEEE 802.3bp (1000 BASE-T1) specifications. Specifically, when the vehicle-mounted Ethernet communication module receives a standard Ethernet test signal generated by the processor module, frame structure reconstruction, data rate adjustment, clock synchronization and modulation coding adaptation processing are performed on the test signal through the protocol conversion unit to generate a test data frame which meets the vehicle-mounted Ethernet communication requirement, namely a vehicle-mounted Ethernet test signal, and then the test data frame is sent to a corresponding Ethernet port of the device to be tested through the physical layer interface circuit. In addition, the vehicle-mounted Ethernet communication module is further provided with a high-speed interception and frame identification mechanism, and is used for receiving the vehicle-mounted Ethernet response signal corresponding to the test signal returned by the equipment to be tested in real time, and the response signal is converted into a standard Ethernet response signal through reverse protocol conversion processes after being received, including frame format reduction, differential signal decoding, signal integrity judgment and the like, and is uploaded to the processor module. By the aid of the vehicle-mounted Ethernet communication module, seamless bridging between different Ethernet protocols of test signals and response signals can be realized, function and stability tests of the vehicle-mounted Ethernet equipment in a physical layer, a link layer and a part of transmission layers are effectively supported, and compatibility and coverage capacity of the whole test system are improved. the processor module is used for coordinating and controlling a multi-communication protocol test flow of the whole test main board, internally supporting a CANFD protocol and an Ethernet protocol stack, integrating a test task scheduling engine, generating a specific CANFD test instruction set and a standard Ethernet test signal sequence according to a preset test template or user-defined parameters, wherein the CANFD test instruction and the standard Ethernet test signal sequence can comprise contents such as a function verification command, a bandwidth pressure packet, a boundary condition trigger frame, abnormal simulation data and the like, and ensuring test coverage rate. During testing, the processor module is also configured with a response frame parsing unit and data consistency analysis logic. The processor module receives the response frame from the CANFD communication module, analyzes the content, identifies the frame head, extracts the time stamp and detects the abnormality, receives the standard Ethernet response signal converted by the vehicle-mounted Ethernet communication module, and executes the operations of protocol level verification, data integrity analysis, response delay calculation and the like. After data acquisition and analysis are completed, the processor module comprehensively evaluates the test results according to multiple dimensions, such as communication delay, response accuracy, protocol consistency, frame loss rate, error type, frequency and the like, and automatically generates a structured equipment test report. The device test report is presented in a chart and data parallel form, supporting export into multiple formats for subsequent archiving, comparison, or quality analysis. In addition, the processor module also supports uploading the report result to a remote server or a cloud platform through an external interface, such as USB, wiFi or a vehicle-mounted diagnosis port, so that centralized management and statistical analysis of large-scale equipment test data are facilitated.
Test frames are constructed based on the CANFD protocol, including data frames, control instruction frames, fault frames, and error frames. The data frame is used for simulating the transmission of normal service data in an actual vehicle-mounted communication environment and comprises a payload field, a frame identifier, a data length code and a cyclic redundancy check field, wherein the payload field, the frame identifier, the data length code and the cyclic redundancy check field are used for testing the data receiving and transmitting capacity of equipment, the control instruction frame is used for triggering the equipment to be tested to execute specific control logic or state switching, such as a start/stop command, a mode switching instruction and the like, the fault frame is used for simulating standard fault conditions such as frame loss, interruption, arbitration loss and the like in a bus and verifying the fault-tolerant mechanism of the equipment in an abnormal bus state, and the error frame is used for injecting an illegal format frame or a CRC error frame so as to test the identification and response capacity of the equipment to protocol errors, including whether an error processing flow or an error counter is triggered or not. The in-vehicle Ethernet test signal is constructed according to an in-vehicle Ethernet protocol, such as BroadR-Reach/100BASE-T1, and comprises a data packet, a control signal, a fault signal and an error signal. The data packet carries effective data of a service layer or an application layer, the data throughput capacity and the protocol analysis capacity of the device are tested, the control signal comprises an instruction packet based on an Ethernet control protocol and is used for simulating network management instructions, a flow control mechanism and QoS triggering, the fault signal simulates conditions of network anomalies such as packet loss, retransmission, link flashover and the like, the device is tested for sensing and recovering the physical layer anomalies and the link layer anomalies, and the error signal is used for injecting illegal Ethernet frames so as to evaluate the protocol fault tolerance, the error detection precision and the defense mechanism of the device. By flexibly combining the multi-type test frames and the test signals in the test flow, a vehicle-mounted communication simulation scene which is highly complex and approximates to the actual use environment is constructed, so that the protocol support integrity, the exception handling capability and the stability robustness of the equipment to be tested are comprehensively evaluated.
Preferably, referring to fig. 2, the CANFD communication module includes:
The FPGA chip is used for generating a test frame under the condition of receiving the CANFD test instruction;
and the CAN transceivers are used for sending the test frames to the equipment to be tested, receiving CAN response frames which are sent by the equipment to be tested and correspond to the test frames, and converting the CAN response frames into response frames compatible with a PCIe bus.
Specifically, the CANFD communication module comprises an FPGA chip, an SPI Flash chip, a reset and clock, a power supply, and a 4-way CAN transceiver, wherein the 4-way CAN transceiver is connected with a 4-way CAN bus. The FPGA chip, i.e., field-Programmable gate array (fieldprogrammable GATE ARRAY), is configured to generate test frames conforming to the CANFD protocol specification based on its reconfigurable logic resources upon receipt of CANFD test instructions issued from the processor module. And a CANFD frame construction logic unit is pre-deployed in the FPGA chip and dynamically assembles a test frame field according to the instruction content, wherein the test frame field comprises a frame start bit, an arbitration field, a control field, a data field, a CRC check segment and a frame end flag bit. The FPGA chip can generate various frame structures according to test requirements, including data frames, control frames, fault simulation frames, error injection frames and the like in standard formats and extended formats. In addition, the FPGA chip is also integrated with a frame scheduling controller and a time stamp management unit, supports the periodic transmission, event triggering transmission and frame interval accurate control of test frames, and can meet the requirements of high-bandwidth and high-real-time communication test. By means of the hardware-level parallel processing capability, the FPGA chip greatly improves the speed and flexibility of test frame generation, and is a key frame generation execution unit in the whole CANFD test flow. And the CAN transceivers respectively correspond to the CANFD channels, and each transceiver comprises a differential signal driving unit, a receiving filter, a bit level electric protection module and interface buffer control logic and is used for realizing bidirectional data communication between a vehicle-mounted CAN bus physical layer and a main control system logic layer. After receiving a test frame generated by an FPGA chip, the CAN transceiver carries out level conversion and differential drive output on the frame, and sends the test frame to the equipment to be tested through a standard CAN bus topological structure. In the receiving direction, the CAN transceiver CAN monitor the bus state in real time and identify the CAN response frame corresponding to the test frame returned by the equipment to be tested. The CAN response frame is further transmitted to a later PCIe protocol adaptation unit after differential signal restoration and logic level conversion are completed through the transceiver. In this process, the CAN response frame is encapsulated into a data frame format compatible with the PCIe bus protocol according to predefined frame packing rules, and is transmitted to the processor module or the master control system through the high bandwidth PCIe channel for subsequent data parsing and test analysis. In order to improve the concurrency processing capability and the multi-channel data consistency of the system, the CAN transceiver CAN correspond to a plurality of independent CAN channels, support the parallel test and data return of a plurality of devices to be tested or a plurality of CAN nodes, each transceiver is configured with an error detection and frame verification mechanism, CAN report the real-time alarm and status report to the conditions of abnormal frame formats, electrical layer faults and the like, and ensure the stability and traceability of the whole communication test process.
The CANFD communication module is connected with the outside through a CAN interface, the CAN interface adopts a DB9 external interface form, and signal pins of each path of CAN interface are configured according to CAN standard 2.0A/B and FD standard. The pin 2 is a can_l pin, and is used for transmitting a low-level signal of the CAN bus, and the low-level signal is used as a part of differential signals to participate in the transmission of a data frame. The pin 7 is a CAN_H pin, which is used for transmitting a high-level signal of the CAN bus and forms a differential signal together with the CAN_L, so that the reliability and the anti-interference capability of data transmission are ensured. The CAN interface accords with CAN standard 2.0A/B, supports traditional standard frame format and extended frame format, has the highest supported transmission rate of 1 Mbit/s, and is suitable for traditional vehicle bus communication and equipment test. The CAN interface further supports the CAN FD protocol, allowing the use of extended data fields, the effective data length of each data frame CAN be extended to 64 bytes, with a significant performance improvement over CAN 2.0. The CAN FD maximum supported transmission rate is 12 Mbit/s, and is suitable for test scenes requiring high-speed data exchange, in particular for the requirement of large-data-volume transmission in modern vehicle-mounted electronic equipment. The electrical design of the interface meets the CAN communication anti-interference requirement while adopting the differential signal transmission mode, so that the data loss or error code caused by electromagnetic interference or long-line transmission CAN be effectively avoided, and the communication stability in the complex electromagnetic environment of the vehicle-mounted system is ensured. The DB9 interface form is used as an industrial standard which is widely applied, has wide compatibility and supports convenient connection with other devices conforming to the DB9 standard. Meanwhile, the main board CAN realize parallel test through multiple paths of CAN interfaces, so that the test efficiency is improved. Each CAN interface supports the functions of real-time monitoring and fault diagnosis, and the system CAN capture the conditions of error frames, bus conflicts, bit errors and the like in transmission and provide detailed error codes so as to help developers to quickly locate communication faults. Through the CAN interface in the DB9 form, the vehicle-mounted multi-communication protocol test main board CAN efficiently and reliably test the CAN protocol, meets the requirements of the traditional vehicle-mounted communication and the modern vehicle-mounted system on high-speed data exchange, and provides powerful technical support for development and verification of the automobile electronic system.
The peripheral circuit of the FPGA chip also comprises a clock module and a reset control circuit, and the clock module and the reset control circuit are used for ensuring that the FPGA chip has stable and reliable time sequence reference and reset control capability during power-on initialization, logic configuration and normal operation. The clock module comprises a high-precision crystal oscillator, a clock driving chip and an optional clock buffer or clock divider, and is used for providing a stable system main clock signal for the FPGA chip. The clock signal is used as a time sequence reference for the operation of the logic block in the FPGA, supports various frequency configuration schemes, and can dynamically switch high-frequency or low-frequency clock sources according to different application scenes. The clock module is also cooperated with the unified clock management system of the main board to realize clock synchronization and unified timestamp distribution of the cross-module. The reset control circuit comprises a power-on reset circuit, an external reset input interface, a soft reset control logic and a reset trigger mechanism linked with the processor, so that the FPGA can realize deterministic initialization behavior in key states such as power-on, abnormal recovery or configuration update. The reset circuit also supports a multi-stage reset strategy, including global reset, local logic block reset and configuration logic reset, and improves the stability and fault recovery capability of the system. Through the cooperation of peripheral circuits, the FPGA chip is ensured to have stable working time sequence and controllable state recovery mechanism in the configuration, operation and cooperative communication processes of the mainboard system, and a reliable hardware basis is provided for the following CANFD test frame generation, ethernet protocol conversion, data processing and other functional modules.
Preferably, referring to fig. 2, the CANFD communication module further includes:
the SPI Flash chip is used for storing the starting firmware configuration information and the communication logic configuration information of the FPGA chip;
The FPGA chip is also used for performing starting configuration according to the starting firmware configuration information and the communication logic configuration information.
Specifically, the SPI Flash chip is used as a nonvolatile storage device and is connected with the FPGA chip through a standard SPI bus interface to store firmware configuration data and communication logic configuration files which are required to be loaded in the power-on starting process of the FPGA. The starting firmware preset in the SPI Flash chip comprises bit stream information of the FPGA and is used for defining initialization configuration of FPGA logic resources, such as a test frame generation module, a frame scheduling controller, a time stamp unit, interface control logic and the like. The SPI Flash chip also stores communication logic configuration information which can be dynamically updated by the processor, including a CANFD frame format template and injection rules, frame scheduling parameters under different test scenes, multi-channel configuration parameters, test state machine configuration and event response logic and the like. When the system is powered on, the FPGA chip actively accesses the Flash chip through the SPI main equipment interface, the configuration data are loaded in sequence, and the logic reconstruction is completed, so that the FPGA is ensured to have complete test task execution capacity. By carrying the SPI Flash chip, maintainability and flexibility of the system are improved, and a user is allowed to remotely update or reconfigure the SPI Flash on line through a processor module or an external debugging interface, so that evolution requirements of different test application scenes or protocol versions are rapidly met. The FPGA chip is further used for executing a system start configuration flow according to the start firmware configuration information and the communication logic configuration information stored in the SPI Flash chip in a power-on initialization stage. After detecting a system power-on or reset signal, the FPGA chip firstly loads a corresponding bit stream file from the SPI Flash to complete the basic configuration of a programmable logic unit, an I/O resource, a clock distribution network and an interface control module of the FPGA chip, and realize the dynamic construction of a logic architecture. After the basic starting is completed, the FPGA chip further analyzes and applies the communication logic configuration information to complete the fine configuration of the communication sub-modules. The configuration parameters can be dynamically updated according to specific test scenes, including frame type definition, injection timing, priority setting, response judgment rules and the like, so that the FPGA is ensured to have highly flexible communication test logic in the operation period. Through the mechanism, the FPGA chip not only bears hardware-level test frame generation and protocol execution tasks, but also serves as a self-defined reconfigurable core controller of the whole system, and the adaptability, expandability and maintenance efficiency of the test main board under multi-protocol and complex scenes are remarkably improved.
Preferably, referring to fig. 3, the on-board ethernet communication module includes:
The vehicle-mounted Ethernet transceiver is used for converting the standard Ethernet test signal into a vehicle-mounted Ethernet test signal and transmitting the vehicle-mounted Ethernet test signal to the equipment to be tested;
and the common Ethernet transceiver is used for receiving the vehicle-mounted Ethernet response signal which is sent by the equipment to be tested and corresponds to the vehicle-mounted Ethernet test signal, and converting the vehicle-mounted Ethernet response signal into a standard Ethernet response signal.
Specifically, the vehicle-mounted Ethernet communication module comprises a vehicle-mounted Ethernet transceiver, a common Ethernet transceiver, a power supply, a dial switch and an LED indicator lamp. The vehicle-mounted Ethernet transceiver is used for realizing conversion of electrical signals and coding mechanisms between the standard Ethernet and the vehicle-mounted Ethernet in a physical layer, and is one of core devices in the vehicle-mounted Ethernet communication module. The vehicle-mounted Ethernet transceiver is compatible with various mainstream vehicle-mounted Ethernet standards including but not limited to 100BASE-T1 and 1000BASE-T1, supports single-pair unshielded twisted pair transmission, can effectively reduce wiring complexity and improve anti-interference capability, and is suitable for the requirements of vehicle-mounted complex electromagnetic environments. On the transmission path, the vehicle-mounted Ethernet transceiver receives the standard Ethernet test signal output by the protocol conversion module and converts the standard Ethernet test signal into a signal format conforming to the standard of the vehicle-mounted Ethernet physical layer, and the operations of differential signal modulation, level conversion, cable equalization, synchronous coding, CRC check bit insertion and the like are specifically included. After the signal conversion is completed, a corresponding test signal is sent to the equipment to be tested through the vehicle-mounted Ethernet physical channel. The vehicle-mounted Ethernet transceiver has the characteristics of low delay, wide-temperature operation, high jitter tolerance and the like, supports PHY Loopback, self-diagnosis, link detection and error injection functions, and can be matched with a test main control module to execute link stability test, response time measurement and signal integrity verification. In addition, an ESD protection mechanism, an EMC inhibition mechanism and a cable short-circuit protection mechanism are arranged in the system, so that the safety and the reliability of the whole system are improved, and the electrical damage to the equipment to be tested is avoided in the test process. The common ethernet transceiver is also called an ethernet PHY chip, and is used for completing the physical layer conversion from the vehicle-mounted ethernet response signal returned by the device to be tested to the standard ethernet response signal. The common ethernet transceiver is mainly disposed in a receiving path of the ethernet communication module, an input interface of the common ethernet transceiver is connected with a physical output layer of the vehicle-mounted ethernet transceiver, and an output interface is in butt joint with a MAC control unit of the processor module, and is generally based on MII, RMII, RGMII or SGMII and other standard interface formats. The common Ethernet transceiver has physical layer decoding capability, can demodulate a coding mechanism in the vehicle-mounted Ethernet response signal, completes operations such as signal level restoration, error correction, link alignment, clock recovery and the like, and outputs a response signal compatible with a standard MAC layer after being restored to a standard Ethernet data format. In order to ensure the communication stability under the high-interference and high-speed scene, the common Ethernet transceiver is also integrated with a low-jitter clock management unit, an automatic equalizer, a crosstalk suppressor and a link quality monitoring module, so that the communication quality can be monitored while the data integrity is maintained, and a diagnosis prompt can be sent out for serious signal attenuation, intersymbol interference or cable faults. After the response signal is converted by the module, the response signal can be analyzed by the processor module or a later diagnosis system for generating a corresponding test report or further fault analysis. By introducing the vehicle-mounted Ethernet communication module, the seamless butt joint between the vehicle-mounted Ethernet and the standard Ethernet in a physical layer is realized, and the adaptation capability and the expandability of the test main board in different network protocol environments are enhanced.
Preferably, referring to fig. 3, the on-board ethernet communication module further includes:
The vehicle-mounted Ethernet communication module is used for setting the vehicle-mounted Ethernet communication module as a master node when the vehicle-mounted Ethernet communication module is in a first switch state, and setting the vehicle-mounted Ethernet communication module as a slave node when the vehicle-mounted Ethernet communication module is in a second switch state.
Specifically, the vehicle-mounted Ethernet communication module further comprises a dial switch device, which is used for realizing physical layer configuration and rapid switching of the node roles of the communication module. The dial switch is a multi-position mechanical switch or a two-position double-throw dial component, can switch the internal working mode of the module through a physical toggle state, and is used for collecting and identifying the state by the FPGA or the processor module when the system is powered on or reset. When the dial switch is in the first switch state, the vehicle-mounted Ethernet communication module is set to be in a master node mode, the module actively transmits a synchronous signal, a frame start signal or a link establishment request and controls time sequence and handshake logic in a communication initialization flow in the mode, and when the dial switch is in the second switch state, the communication module is set to be in a slave node mode, and in the mode, the module is in a monitoring state, and waits for the master node to initiate communication handshake and respond to a synchronous command and a test frame signal sent by the master node. The physical state of the dial switch can be read by the node identification logic unit in the system initialization stage in real time, and relevant control marks are set through the internal register, so that the Ethernet PHY chip, the MAC layer protocol state machine and the link management controller are driven to enter corresponding master/slave working states. The configuration result of the dial switch can also be fed back to the processor module for automatically matching node roles when a test data frame or a response frame is generated, so that consistency of communication topology and protocol time sequence in the test process is ensured. By introducing a hardware-level master-slave node configuration mechanism, the adaptability of the system to different vehicle-mounted Ethernet communication topologies is improved, the operation complexity of a user in actual test deployment is simplified, the repeated programming or debugging process is avoided, and the test efficiency and reliability are improved.
Preferably, referring to fig. 3, the on-board ethernet communication module further includes:
the signal indicator lamp is used for being extinguished under the condition that the vehicle-mounted Ethernet transceiver is powered off, being lightened under the condition that the vehicle-mounted Ethernet transceiver is powered on, and flashing at preset frequency under the condition that the vehicle-mounted Ethernet transceiver works.
Specifically, the vehicle-mounted Ethernet communication module further comprises a signal indicator lamp unit, namely an LED indicator lamp, and the signal indicator lamp is used for carrying out visual feedback and real-time indication on the power state and the running state of the vehicle-mounted Ethernet transceiver. The signal indicator lamp is preferably a low-power consumption high-brightness LED component, is connected with the transceiver power supply control channel and the running state monitoring module, and can show different indicating behaviors under different working states, so that an intuitive module running state identification means is provided for testers. When the vehicle-mounted Ethernet transceiver is in a power-off state, the signal indicator lamp is in a power-off state, the prompting module does not work or has a power supply fault, when the transceiver is in a power-on state but does not activate a communication link, the indicator lamp is in a normally-on state, which indicates that the transceiver has communication preparation capability, and when the transceiver is in a normal working state, i.e. a physical link is established and is participating in the receiving and transmitting of a communication frame, the indicator lamp periodically flashes according to a preset frequency, and the preset frequency can be set to be related to the data packet transmission frequency or the link heartbeat frequency so as to reflect real-time communication activity. In order to improve the reliability of the system, the signal indicator lamp control unit is also integrated with an overvoltage protection, abnormal state latching and state feedback interface, and can interact with the main control processor, and when abnormal power failure, short circuit or communication failure of the transceiver is detected, alarm prompt is carried out in an abnormal mode flashing mode, such as flash, slow flashing and double flashing. In addition, the signal indicator lamp unit is arranged at a remarkable position of the test main board, man-machine interaction friendliness can be enhanced by matching with modes such as silk-screen printing labels and color distinction, and field debugging efficiency and fault investigation accuracy are improved.
The vehicle-mounted Ethernet communication module is connected with external equipment to be tested through a vehicle-mounted Ethernet interface, the vehicle-mounted Ethernet interface adopts an HMTD or MATEnet external interface form, each path of vehicle-mounted Ethernet interface provides reliable network communication through standardized physical connection, and data transmission and protocol testing in the vehicle-mounted Ethernet system are supported. The HMTD adopts a high-performance HMTD connector, is specially designed for high-speed data transmission, and has excellent anti-interference capability and stability. Through the optimized contact design and high temperature resistance and corrosion resistance, the HMTD interface is suitable for extreme working conditions in a vehicle-mounted environment. The MATEnet interface adopts MATEnet standardized connection mode, and is suitable for various configuration requirements of the vehicle-mounted Ethernet. The MATEnet connector has high bandwidth capability, supports an auto-negotiation function, can intelligently switch transmission rate according to transmission requirements, and is compatible with various vehicle-mounted Ethernet devices.
Preferably, referring to fig. 1, the vehicle-mounted multi-communication protocol test motherboard further includes:
The vehicle-mounted multi-communication protocol test main board comprises a power supply conversion module, a power supply conversion module and a power supply control module, wherein the power supply conversion module is used for converting external first voltage into second voltage based on the pressing state of a starting button under the condition that the vehicle-mounted multi-communication protocol test main board is configured to be in a first starting mode, and supplying power to the vehicle-mounted multi-communication protocol test main board by using the second voltage.
Specifically, the vehicle-mounted multi-communication protocol test main board further comprises a power supply conversion module, wherein the power supply conversion module is used for realizing voltage self-adaptive conversion and modularized power supply control according to different starting modes, and ensuring that the test main board can be stably started and enters a normal working state under various power supply scenes. When the test motherboard is configured in a first starting mode, such as a local debugging or independent power-on mode, the power conversion module receives a first voltage, preferably a 12V or 24V direct current input voltage, from an external power input interface, and converts the first voltage into a second voltage required by the system, such as a 5V, 3.3V or 1.8V multi-path voltage stabilizing output, through the voltage conversion circuit, such as a buck DC-DC converter or an LDO voltage stabilizing module, under the condition that the pressing of a starting button is detected, so as to provide stable power for all core functional units including the processor module, the FPGA chip and the communication module. When the test main board is configured into a second starting mode, such as a vehicle-mounted access or remote wake-up mode, the power supply conversion module does not depend on manual button triggering, but automatically judges the system starting condition by detecting an external power supply state signal, such as a vehicle-mounted ignition voltage IG or an ACC line voltage, and after detecting that a preset power supply threshold is reached, the external first voltage is also converted into a second voltage required by the system operation, so that the automatic power-on starting of the main board is realized. In the mode, the power supply module can also work cooperatively with the management controller of the main board to realize closed-loop control of power supply time sequence, soft start curve and voltage rising rate so as to ensure that each module is powered on in sequence according to the preset time sequence and avoid communication interference and equipment damage caused by unstable system or abrupt voltage change. The power conversion module is preferably integrated with a reverse connection protection circuit, a short circuit detection circuit, an overvoltage and overcurrent protection circuit, has a power supply state indication function and a fault diagnosis output interface, can be linked with the main processor to perform real-time state monitoring and protection strategy adjustment, and remarkably improves the safety and adaptability of the whole test platform in a multi-power supply environment.
The power interface of the vehicle-mounted multi-communication protocol test main board adopts a 2PIN locking terminal connector design, and the connector is specially customized for a high-reliability and high-stability power supply system, so that the normal power supply and safe connection of the main board in a vehicle-mounted environment can be effectively ensured. The connector has the locking function, namely, when the connector is connected, the terminal and the socket form stable connection through the mechanical locking structure, so that the contact looseness caused by vibration, external force or long-term use is avoided. The design is particularly suitable for high-vibration and high-noise environments in vehicle-mounted systems, and ensures stable and error-free power supply transmission. The plug and the socket of the connector are prevented from being connected in error through the special polarity design, correct pairing of the anode and the cathode is ensured, and the problems of power short circuit, main board damage or circuit fault initiation and the like caused by incorrect connection are effectively avoided. The 2PIN terminal connector is made of high-conductivity materials and through a precise manufacturing process, has excellent contact performance and corrosion resistance, can bear large current load common in a vehicle-mounted system, and ensures high efficiency and low temperature rise of a main board power interface in a long-time use process. The compact design of the 2PIN terminal connector is highly compatible with the miniaturization requirements of vehicle-mounted electronic devices, and can provide a highly reliable power connection solution in a limited space, and is convenient to integrate into vehicle-mounted test mainboards and other electronic modules. The connector has IPXX protection levels, has the characteristics of water resistance, dust resistance and the like, and is suitable for various severe conditions in a complex vehicle-mounted environment. Through adopting 2PIN lock to attach the terminal connector, the stability and the security of power input can be ensured to the mainboard, avoids on-vehicle system to appear the risk such as power contact failure, short circuit or power failure in high dynamic environment, provides firm electric power guarantee for whole car or on-vehicle equipment's test work.
Preferably, referring to fig. 1, the vehicle-mounted multi-communication protocol test motherboard further includes:
The HDMI display interface is used for converting the equipment test digital image data into high-speed serial differential signals and sending the high-speed serial differential signals to the display;
The processor module is also configured to convert the device test report into device test digital image data.
Specifically, the vehicle-mounted multi-communication protocol test main board further comprises an HDMI display interface module, wherein the HDMI display interface module is used for encoding the equipment test digital image data generated by the processor module, converting the equipment test digital image data into a high-speed serial differential signal conforming to the HDMI standard, and transmitting the image signal to external display equipment through a standard HDMI physical interface to realize graphical real-time presentation of the test data. The HDMI display interface module comprises a group of video coding units, a time sequence control unit and a signal driver, wherein the video coding units receive original test image data output by the processor module, RGB data coding, row-column time sequence generation, synchronous signal insertion and differential driving are carried out according to HDMI protocol standards, and the output TMDS coded data stream is sent to a connected display in a high-speed serial mode through a differential circuit, so that low-delay, high-resolution and high-refresh-rate image display is realized. The processor module is further configured with a graphics-generating engine capable of converting internally generated device test reports, including communication protocol interaction processes, response frame parsing results, error frame statistics, test decision results, etc., into standard format image data frames, preferably bitmap, vector diagram or frame buffer formats, and superimposing visualization elements, such as color labels, chart curves, status icons, etc., to enhance the intuitiveness and readability of the test information. Through the configuration, the test main board provided by the invention not only has the automatic multi-protocol test capability, but also has the functions of imaging and displaying test results, is convenient for a tester to observe in real time, compare results and trace faults, improves the overall test efficiency and operability, and is particularly suitable for application scenes such as research and development and debugging sites, vehicle-mounted terminal maintenance and batch equipment screening.
Preferably, referring to fig. 1, the vehicle-mounted multi-communication protocol test motherboard further includes:
The NVME interface is used for receiving configuration information sent by the external storage device and sending the device test report to the external storage device;
The processor is also used for configuring the vehicle-mounted multi-communication protocol test mainboard according to the configuration information.
Specifically, the vehicle-mounted multi-communication protocol test main board further comprises an NVMe high-speed interface module, which is used for establishing data communication connection with external high-speed nonvolatile storage equipment, so as to realize high-speed read-write and dynamic interaction management of test data. The NVME interface is realized by adopting a physical protocol stack which accords with the NVMe protocol standard, supports PCIe Gen3 and above versions, has the storage access capability of high bandwidth, low delay and low power consumption, and is suitable for real-time access of a large amount of data in the test process. In the system initialization or test task switching stage, the NVMe interface can read pre-stored configuration information such as a communication protocol configuration file, a test instruction template, a test item parameter set and the like from an external storage device, and load the configuration information to a processor module or an FPGA module in a main board in a DMA mode to realize quick configuration and automatic deployment of a test system, after equipment testing is completed, an equipment test report generated by the processor module can be written into the external NVMe storage device in a high-speed mode through the NVMe interface, so that classification management according to dimensions such as test tasks, equipment numbers, time stamps and the like is supported, and subsequent offline analysis, batch backtracking or quality evaluation is facilitated. The NVMe interface module is also integrated with a multi-queue data access control unit, a power-down protection mechanism and a storage integrity check logic, so that concurrency capability and system stability during large-scale data interaction can be effectively improved, and key data loss caused by power supply fluctuation or test interruption is avoided. Through the configuration, the test main board has the multi-communication protocol test capability, and simultaneously provides high-speed, high-capacity and structured data interaction and management capability, so that the test main board is suitable for batch equipment test scenes and industrial-level automatic test platforms with severe requirements on storage performance. The processor module is also configured to automatically configure and load parameters for each functional module of the vehicle-mounted multi-communication protocol test main board according to configuration information in an initialization stage after the vehicle-mounted multi-communication protocol test main board is powered on or restarted. The processor can read configuration information such as communication protocol parameters, a test instruction set, a signal mapping rule, a module enabling state, an interface working mode, a power management strategy and the like from external storage equipment, SPI Flash or a configuration file obtained through a remote communication port, and accordingly, the FPGA chip, the CANFD communication module, the vehicle-mounted Ethernet communication module, the clock module, the power conversion module, the HDMI display interface module and the like of the main board are configured one by one, so that the self-adaptive starting and the function initialization of the system are realized. The processor also supports dynamic configuration and runtime thermal updating functions, and in the execution process of the test task, the working parameters of the specific module are dynamically modified or the running mode of the specific module is switched according to user instructions or external trigger events so as to adapt to diversified test requirements and complex application scenes, and the flexibility and expansibility of the test platform are improved.
Preferably, referring to fig. 1, the vehicle-mounted multi-communication protocol test motherboard further includes:
a clock module for generating a clock signal;
The processor is further configured to generate a uniform timestamp for the response frame and the standard ethernet response signal based on the clock signal.
Specifically, the vehicle-mounted multi-communication protocol test main board also comprises a clock module, which is used for providing stable and configurable system clock signals for each functional module of the main board and ensuring the time sequence consistency, the data synchronism and the communication precision of the whole test system under the multi-protocol concurrent working condition. The clock module comprises a high precision crystal oscillator unit, a clock synthesis circuit, a clock buffer distributor and an optional programmable oscillator or a PLL phase-locked loop component. The clock module generates a reference frequency signal through a crystal oscillator to serve as a source of the whole test main board system frequency, and the reference frequency is changed up or divided into different target frequencies through the PLL, DPLL and other equivalent synthesis technologies, and the different target frequencies are respectively provided for each module such as an FPGA chip, a CANFD communication module, an Ethernet transceiver, a PCIe/NVMe interface and the like. The clock module supports a master-slave node clock synchronization mechanism in a multi-protocol communication scene, can realize phase locking and edge alignment according to a master node or an external clock signal when CANFD or vehicle-mounted Ethernet communication test is carried out, ensures accurate time sequence of communication test, supports a double-crystal oscillator hot backup structure, automatically switches to a standby crystal oscillator when a master crystal oscillator fails or frequency drift exceeds standard, and realizes on-line diagnosis and alarm through the clock health monitoring module. The clock module is also integrated with a jitter remover and a filter device, so that jitter and EMI interference of a high-frequency clock signal in a high-speed differential transmission process are reduced, and the signal integrity of a high-speed interface is ensured. The processor module is further configured to perform unified time-stamping processing on communication response data received in the testing process based on the high-precision clock signal provided by the clock module, generate unified format timestamps conforming to a system time base for response frames from the CANFD communication module and standard ethernet response signals obtained through conversion of the common ethernet transceiver, wherein the generated timestamps are preferably incremental count values based on nanosecond or microsecond precision, and have monotonicity, global uniqueness and resolvability. The introduction of the unified time stamp enables the processor module to realize time sequence alignment and synchronous analysis on response data returned under different communication protocols, so that the combined analysis on a time axis is carried out on a CANFD response frame and a vehicle-mounted Ethernet response signal in the same test task to realize time sequence matching of a cross-protocol event, the appearance time, communication delay and jitter characteristics of the CANFD response frame and the vehicle-mounted Ethernet response signal can be rapidly evaluated through statistics calculation on time stamp information of a specific error frame or a packet loss frame, and the test response data is sequenced, screened and replayed based on the time stamp sequence to provide data support for subsequent time sequence diagram/graph presentation on an HDMI image display interface. In order to improve the precision and consistency of the time stamp generation, the processor can also cooperate with the clock module, and the time stamp binding is completed at the moment of data receiving by adopting a hardware trigger sampling mechanism or an FPGA cooperative processing mode, so that the time offset caused by software delay is avoided.
In some embodiments, the processor module and the memory module in the vehicle-mounted multi-communication protocol test main board adopt a modularized design architecture to support integral plug replacement, so that a user can conveniently and rapidly upgrade or customize and deploy the calculation power or the storage capacity of the CPU according to different test application requirements, calculation power load intensity or system function expansion requirements. The modularized interface is preferably a standard high-speed interconnection interface, has the advantages of hot plug capability, strong compatibility, high signal integrity and the like, and can remarkably improve the flexible deployment capability and the later maintainability of the test platform. The motherboard system software adopts a layered decoupling architecture, and an application layer program and a communication protocol stack interact through a set of standardized and abstract interface protocols, so that protocol processing logic and upper test service logic are mutually independent and are not mutually coupled. The main board supports loading or replacing different protocol stacks according to external configuration files, test environments or FPGA logic changes without modifying upper application logic, the software bottom layer driver and the hardware abstraction layer have high universality, can be quickly transplanted to different processing platforms or embedded operating systems, and various peripheral interfaces of the main board, such as PCIe, SPI, UART, I C, realize resource sharing and dynamic scheduling through unified interface management middleware, and improve the utilization efficiency of the IO resources of the whole system. Through the combination of the modularized hardware design and the decoupling software architecture, the test main board provided by the invention has high expansibility, high adaptability and high life cycle management capability, and is suitable for complex vehicle-mounted electronic system test tasks of multi-vehicle type, multi-provider and multi-protocol combination.
The vehicle-mounted multi-communication protocol test main board is further matched with a set of system-level application test software architecture platform, the platform is deeply integrated with a main board hardware structure, and a full stack type software support system from a bottom layer drive to application layer test logic is constructed. The platform is pre-integrated and automatically loads the driving programs of various functional modules on the vehicle-mounted main board, and supports running under the dual operating system environment of Windows and Linux so as to meet the use preference of different developers and integrators. In the protocol support layer, the platform encapsulates and abstracts the communication protocol at the kernel level of the operating system, realizes complete analysis and management functions of CAN and CANFD protocols and TCP, UDP and IP protocols based on Ethernet in the communication protocol stack, supports multi-protocol parallel operation, data multiplexing and protocol level fault detection, and provides a unified call entry and middleware scheduling mechanism. The software platform also builds a multi-language application program interface layer facing the developer, supports programming interface call of mainstream development languages including but not limited to C/C++, python, java, rust and the like, and can quickly build a customized test flow, a simulation tool or an analysis application based on the platform, thereby greatly improving the programmability and the integration convenience of the system. In the aspects of test task organization and execution, the platform supports the creation of self-defined test items, flexible test case management and case library maintenance mechanisms, wherein the test cases have independent description languages or metadata structures, and loose coupling design with hardware interfaces and test frames is realized. The test platform supports rapid deployment and automatic execution of test cases to any functional module and has the functional modules of task queue scheduling, error retry, log acquisition, result report generation and the like, so that the complexity of test script development and system integration is remarkably reduced. Through the software and hardware collaborative platform design, the system not only realizes unified test interfaces of multiple communication protocols, cross-platform operation environment support, dynamic use case deployment and automatic execution, but also has good expandability, maintainability and engineering landing capability, and is suitable for various scenes such as production test, function verification and regression test of a vehicle-mounted electronic system.
The USB module is integrated on the vehicle-mounted multi-communication protocol test main board, and the USB3.0 module comprises a main control chip conforming to the USB 3.1 Gen1 standard, an ultra-high speed differential signal driving circuit and a data interaction bus between the ultra-high speed differential signal driving circuit and the processor module or the FPGA module, so that the data transmission rate of up to 5Gbps can be provided, and the USB3.0 module is used for realizing high-speed and low-delay external equipment access and data exchange. Program development of each communication protocol interface of the vehicle-mounted multi-communication protocol test main board is realized based on Windows or Linux operating system environment. The operating system is used as a basic platform for running the mainboard software, has unified management and scheduling capability for various hardware resources on the mainboard, provides stable kernel support and hardware abstraction interfaces, and ensures stable running and resource isolation of various functional modules in a multi-task parallel scene. The USB interface is used for connecting and communicating the vehicle-mounted multi-communication protocol test main board with external equipment, and can be connected with equipment such as a mouse, a keyboard, a USB flash disk and the like.
The vehicle-mounted multi-communication protocol test main board integrates an 8-way CAN interface and a 2-way gigabit vehicle-mounted Ethernet interface, and provides an efficient and flexible solution for testing, monitoring and data transmission in a complex vehicle network environment. The test main board can be widely applied to a plurality of fields such as automobile research and development, intelligent transportation, vehicle detection and the like, and plays a vital role in the test and verification of a domain controller. In the testing process of the domain controller, the domain controller and the testing main board perform signal interaction through a vehicle-mounted bus system, and the bidirectional data transmission of CAN signals and 1000Base-T1 vehicle-mounted Ethernet signals is involved. The specific test program runs in the test main board, so that the vehicle-mounted communication protocol, the data integrity and the real-time performance can be comprehensively verified. The test main board CAN simulate data exchange between the domain controller and other vehicle-mounted Electronic Control Units (ECU) through an 8-way CAN interface and a 2-way gigabit vehicle-mounted Ethernet interface according to the complexity of the actual vehicle network environment. Through the flexibly configured interface, the test main board can restore various communication scenes in the vehicle-mounted network and simulate interaction and data flow under different communication protocols. The test main board CAN verify the communication protocol between the domain controller and other ECUs through the dual support of the CAN and the vehicle-mounted Ethernet protocol, and check the correctness, the integrity and the instantaneity of the data packet. Particularly, when the CAN FD protocol is used, the main board CAN verify the high efficiency and large data volume support of data frame transmission, and ensure the stability of the domain controller when processing various vehicle-mounted communication protocols. The test main board can simulate normal communication and also simulate fault conditions, such as different faults of communication interruption, data loss or error frames, and the like, and test the reaction capability and error handling mechanism of the domain controller. In addition, the mainboard can perform performance test under high load, simulate the stability and response time of the vehicle-mounted system in a pressure environment, and verify the reliability of the domain controller under extreme working conditions. In the test process, the mainboard supports an automatic test flow, a user can customize test cases, and the mainboard automatically executes the test and generates a detailed report. In the testing process, the main board can record all data exchange and events in real time so as to facilitate subsequent analysis and problem tracking. These data include the content of the data packets transmitted in each round of testing, error frames, response times, etc., ensuring that the developer can clearly analyze the performance of the domain controller in various scenarios. In the testing process, the testing main board carries out double communication of CANFD and the vehicle-mounted Ethernet through simulating the vehicle-mounted bus, and data transmission is carried out between the domain controller and other ECUs, so that compatibility and interaction stability of different protocols are ensured. The main board executes the transmission accuracy verification of the data packet through a special test program, checks the integrity, the instantaneity and the transmission reliability of the data, and ensures that no packet loss, delay or disorder occurs. By simulating multiple fault conditions, the response time and fault recovery capability of the domain controller under different abnormal conditions are tested, such as the processing mechanism of vehicle-mounted network faults, communication interruption or error frames. Under high load conditions, the performance of the test domain controller in handling large amounts of data, multiple signal channels, and high frequency interactions, including response time, bandwidth utilization, and stability under extreme loads. All data in the test process are recorded in real time, including the content of the data packet, the time stamp, the test result and the like, and can be used for analyzing the performance bottleneck of the domain controller later and providing detailed fault checking data for developers. Through the test functions, the vehicle-mounted multi-communication protocol test main board can not only efficiently and accurately verify the communication capability and stability of the domain controller in the vehicle-mounted network, but also provide detailed performance data and fault reports for developers, thereby helping to optimize the design of the vehicle-mounted system and improve the reliability of the system.