Array substrate, manufacturing method thereof and display deviceTechnical FieldThe disclosure relates to the technical field of display, and in particular relates to an array substrate, a manufacturing method thereof and a display device.
BackgroundLiquid crystal displays are currently common flat panel displays, in which a thin film transistor liquid crystal display (Thin Film Transistor Liquid CRYSTAL DISPLAY, abbreviated as TFT-LCD) is the mainstream product in liquid crystal displays.
With the progress of technology, consumers put higher demands on the display effect of mobile products, and the display effect of a common TN (TWISTED NEMATIC ) liquid crystal display cannot meet the market demand. Currently, various wide viewing angle technologies with better display effect are gradually applied to mobile products by various manufacturers, such as IPS (In-PLANE SWITCHING ), VA (VERTICAL ALIGNMENT, vertical alignment), AD-SDS (Advanced-Super Dimensional Switching, advanced super-dimensional field switch, abbreviated as ADs) and the like. In the ADS mode, the electric field generated by the edges of the slit electrode in the same plane and the electric field generated between the slit electrode layer and the plate electrode layer form a multidimensional electric field, so that all oriented liquid crystal molecules in the liquid crystal box between the slit electrode and right above the electrode can rotate, thereby improving the working efficiency of the liquid crystal and increasing the light transmission efficiency. Therefore, the ADS technology can improve the picture quality of the TFT-LCD, and has the advantages of high transmittance, wide viewing angle, high aperture ratio, low chromatic aberration, low response time, no extrusion water ripple (Push Mura) and the like.
Disclosure of Invention
The embodiment of the disclosure provides an array substrate, a manufacturing method thereof and a display device, and the specific scheme is as follows:
an array substrate provided in an embodiment of the present disclosure includes:
a substrate having a display region and a non-display region surrounding the display region;
A plurality of gate lines and a plurality of data lines, which are positioned on the substrate and in the display area, wherein the gate lines and the data lines are insulated and crossed to define a plurality of sub-pixels; the plurality of data lines comprise a plurality of display data lines and a plurality of dummy data lines which are alternately arranged along the row direction, and the adjacent dummy data lines and the display data lines are respectively arranged between different sub-pixels;
the common electrode layer is positioned at one side of the plurality of gate lines and the plurality of data lines, which is away from the substrate base plate, and is at least positioned in the display area;
And the pixel electrodes are positioned on one side of the common electrode layer, which is away from the substrate base plate, and each pixel electrode is arranged in each corresponding sub-pixel, wherein each pixel electrode is a slit electrode with a plurality of slits.
In one possible implementation manner, the array substrate provided in the embodiment of the disclosure further includes a first insulating layer located between the gate line, the data line and the common electrode layer, a second insulating layer located between the common electrode layer and the pixel electrode, and a thin film transistor located between the substrate and the first insulating layer and disposed at each sub-pixel,
The thin film transistor comprises a grid electrode, a grid insulating layer, an active layer, a source electrode and a drain electrode which are sequentially stacked between the substrate base plate and the first insulating layer, wherein the grid electrode is close to the substrate base plate;
The pixel electrode is electrically connected to the drain electrode through a first via hole penetrating the second insulating layer and the first insulating layer.
In a possible implementation manner, in the above array substrate provided by the embodiment of the present disclosure, the common electrode layer is a planar electrode that is disposed on the whole surface, the common electrode layer has a plurality of second vias, the second vias are disposed in one-to-one correspondence with the first vias, and orthographic projection of the first vias on the substrate is located in an orthographic projection range of the second vias on the substrate.
In a possible implementation manner, in the array substrate provided by the embodiment of the present disclosure, the first insulating layer and the second insulating layer are both inorganic insulating layers.
In one possible implementation manner, in the array substrate provided by the embodiment of the disclosure, the non-display area includes a common electrode ring disposed along a periphery of the display area in a same layer as the data line, and a lap joint portion disposed in a same layer as the pixel electrode,
One end of the lap joint part is electrically connected with the common electrode ring through a third via hole penetrating through the second insulating layer and the first insulating layer, and the other end of the lap joint part is electrically connected with a part of the common electrode layer extending to the non-display area through a fourth via hole penetrating through the second insulating layer.
In a possible implementation manner, in the array substrate provided by the embodiment of the present disclosure, the first insulating layer is an organic insulating layer, and the second insulating layer is an inorganic insulating layer.
In one possible implementation manner, in the array substrate provided by the embodiment of the disclosure, the non-display area includes a common electrode ring disposed along a periphery of the display area in a same layer as the data line, and a lap joint portion disposed in a same layer as the pixel electrode,
The overlap joint portion is electrically connected with a portion of the common electrode layer extending to the non-display area through a fourth via hole penetrating through the second insulating layer, and a portion of the common electrode layer extending to the non-display area is electrically connected with the common electrode ring through a fifth via hole penetrating through the first insulating layer.
In a possible implementation manner, in the array substrate provided in the embodiment of the present disclosure, the dummy data line extends to the non-display area and is electrically connected to the common electrode ring.
In a possible implementation manner, in the above array substrate provided by the embodiment of the present disclosure, the plurality of sub-pixels are arranged in a plurality of rows and a plurality of columns, and sources of two columns of the thin film transistors on two sides of each display data line are electrically connected to the display data line;
two grid lines are arranged on two sides of each row of the sub-pixels along the column direction, and grid electrodes of the thin film transistors of each row of the sub-pixels are alternately and electrically connected with the two grid lines.
In a possible implementation manner, in the array substrate provided in the embodiment of the present disclosure, each of the sub-pixels in the same column has the same light emission color, and each of the sub-pixels in the same row includes a first sub-pixel, a second sub-pixel, and a third sub-pixel that are sequentially and circularly arranged along the row direction, where the light emission color of the first sub-pixel, the light emission color of the second sub-pixel, and the light emission color of the third sub-pixel are different from each other.
In a possible implementation manner, in the array substrate provided by the embodiment of the present disclosure, a material of the common electrode layer and a material of the pixel electrode are both transparent conductive materials.
Correspondingly, the embodiment of the disclosure also provides a display device, which comprises a display panel, wherein the display panel comprises an array substrate, an opposite substrate and a liquid crystal layer, wherein the array substrate and the opposite substrate are oppositely arranged, the liquid crystal layer is arranged between the array substrate and the opposite substrate, and the array substrate is any one of the array substrates provided by the embodiment of the disclosure.
Correspondingly, the embodiment of the disclosure also provides a manufacturing method of the array substrate, which comprises the following steps:
Providing a substrate, wherein the substrate is provided with a display area and a non-display area surrounding the display area;
Forming a plurality of gate lines and a plurality of data lines in a display area of the substrate, wherein the gate lines and the data lines are insulated and crossed to define a plurality of sub-pixels;
Forming a common electrode layer at least in the display region on one side of the gate lines and the data lines away from the substrate;
and forming a pixel electrode arranged in each sub-pixel on one side of the common electrode layer, which is away from the substrate base plate, wherein the pixel electrode is a slit electrode with a plurality of slits.
In one possible implementation manner, in the above manufacturing method provided by the embodiment of the present disclosure, a plurality of gate lines and a plurality of data lines are formed in a display area of the substrate, specifically, a plurality of gate lines are formed on the substrate, and a plurality of data lines are formed on a side of the plurality of gate lines facing away from the substrate;
forming a source electrode and a drain electrode in each sub-pixel and forming a common electrode ring in the non-display area simultaneously with forming the plurality of data lines;
After the plurality of data lines are formed and before the common electrode layer is formed, depositing a first insulating layer on one side of the plurality of data lines away from the substrate base plate, wherein the first insulating layer is an inorganic insulating layer;
depositing a first transparent conducting layer on one side of the first insulating layer, which is away from the substrate, and patterning the first transparent conducting layer to form the public electrode layer with a plurality of second through holes, wherein the second through holes are arranged corresponding to the drain electrodes;
After the common electrode layer is formed and before the pixel electrode is formed, a second insulating layer is deposited on one side, which is away from the substrate, of the common electrode layer, wherein the second insulating layer is an inorganic insulating layer, and a primary composition process is adopted to composition the first insulating layer and the second insulating layer, so that a plurality of first through holes which are arranged in one-to-one correspondence with the drain electrodes, third through holes which are arranged in correspondence with the common electrode rings and fourth through holes which are arranged in correspondence with the parts, extending to the non-display area, of the common electrode layer are respectively formed;
The forming of the pixel electrode specifically comprises the steps of depositing a second transparent conducting layer on one side, away from the substrate, of the second insulating layer, patterning the second transparent conducting layer to form the pixel electrode and forming a lap joint part located in the non-display area, wherein one end of the lap joint part is electrically connected with the public electrode ring through the third via hole, and the other end of the lap joint part is electrically connected with a part, extending to the non-display area, of the public electrode layer through the fourth via hole.
In one possible implementation manner, in the above manufacturing method provided by the embodiment of the present disclosure, a plurality of gate lines and a plurality of data lines are formed in a display area of the substrate, specifically, a plurality of gate lines are formed on the substrate, and a plurality of data lines are formed on a side of the plurality of gate lines facing away from the substrate;
forming a source electrode and a drain electrode in each sub-pixel and forming a common electrode ring in the non-display area simultaneously with forming the plurality of data lines;
after the plurality of data lines are formed and before the common electrode layer is formed, a first insulating layer is formed on one side, away from the substrate base plate, of the plurality of data lines by adopting a one-time composition process, wherein the first insulating layer is an organic insulating layer and is provided with first sub-through holes which are arranged in one-to-one correspondence with the drain electrodes and fifth through holes which are arranged in correspondence with the common electrode ring;
The forming of the common electrode layer specifically comprises the steps of depositing a first transparent conducting layer on one side, away from the substrate, of the first insulating layer, patterning the first transparent conducting layer to form the common electrode layer with a plurality of second through holes, wherein the second through holes are arranged corresponding to the drain electrodes;
After the common electrode layer is formed and before the pixel electrode is formed, a second insulating layer is formed on one side, away from the substrate, of the common electrode layer by adopting a one-time composition process, wherein the second insulating layer is an inorganic insulating layer and is provided with a plurality of second sub-vias which are arranged in one-to-one correspondence with the first sub-vias and fourth vias which are arranged in correspondence with the parts, extending to the non-display area, of the common electrode layer, the second sub-vias and the first sub-vias form first vias, and orthographic projection of the first vias on the substrate is positioned in orthographic projection range of the second vias on the substrate;
The forming of the pixel electrode specifically comprises the steps of depositing a second transparent conducting layer on one side, away from the substrate, of the second insulating layer, patterning the second transparent conducting layer to form the pixel electrode, and forming a lap joint part located in the non-display area, wherein the lap joint part is electrically connected with a part, extending to the non-display area, of the public electrode layer through the fourth via hole.
DrawingsFig. 1 is a layout diagram of an array substrate in a conventional ADS mode liquid crystal display panel;
FIG.2 is a schematic layout diagram corresponding to one sub-pixel in FIG. 1;
FIG.3 is a schematic cross-sectional view corresponding to FIG. 2;
Fig.4 is a schematic plan view of an array substrate according to an embodiment of the disclosure;
FIG. 5 is a layout diagram corresponding to the display area in FIG. 4;
FIG.6 is a layout diagram corresponding to one sub-pixel in FIG. 5;
FIG. 7 is a schematic cross-sectional view corresponding to FIG. 6;
FIG. 8 is a schematic cross-sectional view corresponding to FIG. 6;
FIG. 9 is a schematic plan view of the common electrode layer of FIG. 5;
FIG.10 is a schematic diagram of a manufacturing process flow corresponding to the array substrate shown in FIG. 7;
FIG. 11 is a layout diagram within the dashed box E of FIG. 4;
FIG. 12 is a schematic cross-sectional view of the broken line box F in FIG. 11;
FIG.13 is a schematic view of a process flow for fabricating the array substrate shown in FIG. 8;
FIG.14 is a schematic view of yet another layout within the dashed box E of FIG. 4;
FIG. 15 is a schematic cross-sectional view of the broken line box F in FIG. 14;
Fig. 16 is a schematic flow chart of a manufacturing method of an array substrate according to an embodiment of the disclosure;
fig.17 is a schematic structural diagram of a display device according to an embodiment of the disclosure.
Detailed DescriptionFor the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. And embodiments of the disclosure and features of embodiments may be combined with each other without conflict. All other embodiments, which can be made by one of ordinary skill in the art without the need for inventive faculty, are within the scope of the present disclosure, based on the described embodiments of the present disclosure.
Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of the terms "comprising" or "includes" and the like in this disclosure is intended to cover an element or article listed after that term and equivalents thereof without precluding other elements or articles. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "inner", "outer", "upper", "lower", etc. are used merely to denote relative positional relationships, which may also change accordingly when the absolute position of the object to be described changes.
It should be noted that the dimensions and shapes of the various figures in the drawings do not reflect true proportions, and are intended to illustrate the present disclosure only. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.
As shown in fig. 1 to 3, fig. 1 is a layout diagram of an array substrate in a conventional ADS mode liquid crystal display panel, fig. 2 is a layout diagram of one sub-pixel in fig. 1, fig. 3 is a cross-sectional diagram of fig. 2, the array substrate includes a substrate 1, and a gate layer 2, a gate insulating layer 3, an active layer 4, a pixel electrode layer 5, a source drain electrode layer 6, a first insulating layer 7, and a common electrode layer 8 sequentially stacked on the substrate 1, wherein the gate layer 2 includes a gate electrode 21, a gate line (G1, G2..) a source drain electrode layer 6 includes a source electrode 61, a drain electrode 62, a data line (S1 ', S2), a gate line (G1, G2..) a gate electrode layer (S1', S2.) an insulating layer crossing the gate electrode layer 4, a plurality of gate electrode layers 21, a gate electrode layer 62, a thin film layer 62, and a gate electrode layer 51, a thin film layer 62, and a common electrode 51, each of which is disposed in the same plane as the gate electrode layer, and a slit-shaped electrode layer, are disposed in the same plane as the gate electrode layer, and connected to the source electrode 51 in the pixel electrode layer, and the common electrode layer is disposed in the pixel layer, and the thin film layer is in the same plane as the pixel layer 51, and the common electrode is connected to the gate electrode 51, and the common electrode layer is connected to the gate electrode 51. Since the pixel electrode 51 and the drain electrode 62 are located on the same plane, so that a larger coupling capacitance exists between the pixel electrode 51 and the data lines on both sides thereof, in order to reduce the coupling capacitance in the related art, both sides of the pixel electrode 51 need to be designed to be far away from the data lines, so that the size of the pixel electrode 51 is relatively reduced, the number of slits 81 on the common electrode layer 8 corresponding to the pixel electrode 51 is also reduced, and thus, the electric field intensity generated at the edges of the slits 81 in the same plane and the electric field intensity generated between the pixel electrode 51 and the common electrode layer 8 are both reduced, so that the deflection degree of liquid crystal molecules is reduced, and the light transmission efficiency of the liquid crystal display panel is reduced.
In view of the above, in order to improve the transmittance of the lcd panel, an embodiment of the disclosure provides an array substrate, as shown in fig. 4-8, fig. 4 is a schematic plan view of the array substrate, fig. 5 is a schematic layout view corresponding to the display area in fig. 4, fig. 6 is a schematic layout view corresponding to one sub-pixel in fig. 5, fig. 7 is a schematic cross-sectional view corresponding to fig. 6, and fig. 8 is a schematic cross-sectional view corresponding to fig. 6, where the array substrate includes:
a base substrate 1 having a display area AA and a non-display area BB surrounding the display area AA;
A plurality of gate lines (G1, G2...g 2N) and a plurality of data lines (S1 ', S1, S2', S2...sn ', SN), is positioned on the substrate 1 and in the display area AA, the plurality of gate lines (G1, G2...g 2N) and the plurality of data lines (S1', S1, S2', S2..sn', SN) define a plurality of sub-pixels P in insulated intersections; wherein the plurality of data lines (S1 ', S1, S2', S2..once again, SN ', including a plurality of display data lines (S1, S2..once again, SN) alternately arranged in the row direction, and a plurality of dummy data lines (S1', S2..once again, SN '), and adjacent dummy data lines (e.g. S1') and display data lines (e.g. S1) are respectively arranged between different sub-pixels P;
A common electrode layer 8 which is provided on the substrate, are arranged between a plurality of gate lines (G1, G2... Sub.G 2N) and a plurality of data lines (S1 '; S1, S2', S2.....once again SN ', SN) facing away from the substrate base plate 1, the common electrode layer 8 is at least located in the display area AA;
A plurality of pixel electrodes 51 located at a side of the common electrode layer 8 facing away from the substrate 1, each pixel electrode 51 being disposed within a corresponding sub-pixel P, wherein the pixel electrode 51 is a slit electrode having a plurality of slits 511.
According to the array substrate provided by the embodiment of the disclosure, the pixel electrode is arranged on one side of the common electrode layer, which is away from the substrate, so that the coupling between the pixel electrode and the data line is reduced, the side edge of the pixel electrode, which is close to the data line, is not required to be far away from the data line, so that the pixel electrode with larger size can be designed in each sub-pixel as far as possible. And, the data lines in the present disclosure include a display data line for supplying a data signal to the pixel electrode, and a dummy data line for defining a sub-pixel together with the display data line and the gate line on the one hand, and the dummy data line may be connected to the common electrode layer on the other hand to reduce the resistance of the common signal.
Alternatively, the pixel electrode provided in the embodiment of the present disclosure may be a comb-shaped electrode, a stripe-shaped electrode, or the like, which is of course any electrode structure provided with a slit. Specifically, slits are provided in the pixel electrode, so that a horizontal electric field for driving the liquid crystal to rotate can be generated at the edges of the slit electrode.
In a specific implementation, in the above array substrate provided in the embodiment of the present disclosure, as shown in fig. 5 to 8, the method further includes: a first insulating layer 7 between the gate lines (G1, G2...g. G2N), the data lines (S1 ', S1, S2', S2..sn ', SN) and the common electrode layer 8, a second insulating layer 9 between the common electrode layer 8 and the pixel electrode 51, and a thin film transistor T between the substrate 1 and the first insulating layer 7 and provided at each sub-pixel P; specifically, since the first insulating layer 7 and the second insulating layer 9 exist between the pixel electrode 51 and the data line, the coupling between the pixel electrode 51 and the data line is small, and thus the present disclosure can make the size of the pixel electrode 51 larger than that of the pixel electrode 51 in the related art when manufacturing the pixel electrode 51, thereby improving transmittance.
In particular, in the array substrate provided in the embodiment of the present disclosure, as shown in fig. 5 to 8, the thin film transistor T includes a gate electrode 21, a gate insulating layer 3, an active layer 4, a source electrode 61, and a drain electrode 62 sequentially stacked between the substrate 1 and the first insulating layer 7, the gate electrode 21 is close to the substrate 1, the gate line (G1, G2...g2n) is disposed on the same layer as the gate electrode 21 and electrically connected thereto, and the data line (S1 ', S1, S2', S2..sn ') is disposed on the same layer as the source electrode 61 and the drain electrode 62 and electrically connected to the source electrode 61, wherein the gate line and the gate electrode 21 are disposed on the gate layer 2, and the source electrode 61 and the drain electrode 62 and the data line are disposed on the source-drain electrode layer 6;
The pixel electrode 51 is electrically connected to the drain electrode 62 through a first via hole V1 penetrating the second insulating layer 9 and the first insulating layer 7.
Alternatively, the embodiment of the disclosure takes the thin film transistor T as the bottom gate structure as an example, and may also be a top gate structure.
In a specific implementation, in the array substrate provided in the embodiment of the present disclosure, as shown in fig. 5 to fig. 9, fig. 9 is a schematic plan view of a common electrode layer 8 in fig. 5, where the common electrode layer 8 may be a planar electrode disposed on the whole surface, the common electrode layer 8 has a plurality of second vias V2, the second vias V2 are disposed in one-to-one correspondence with the first vias V1, and the orthographic projection of the first vias V1 on the substrate 1 is located in the orthographic projection range of the second vias V2 on the substrate 1. The pixel electrode 51 may thus be electrically connected to the drain electrode 62 through the first and second via holes V1 and V2.
In particular, in order to further improve the transmittance, in the array substrate provided in the embodiment of the disclosure, the material of the common electrode layer and the material of the pixel electrode may be transparent conductive materials, such as ITO, which is not limited thereto.
In a specific implementation, in the array substrate provided in the embodiment of the present disclosure, as shown in fig. 7, the first insulating layer 7 and the second insulating layer 9 may be inorganic insulating layers (for example, PVX). The manufacturing process flow is shown in fig. 10, and the specific process steps comprise (1) manufacturing a grid layer (G) on a substrate 2 by adopting a first mask, (2) depositing a grid insulating layer (GI) on the whole surface of the grid layer, (3) manufacturing an active layer (Act) on the grid insulating layer by adopting a second mask, (4) manufacturing a source drain electrode layer (SD) on the active layer by adopting a third mask, (5) manufacturing a common electrode layer (1 ITO) on the whole surface of the source drain electrode layer by adopting a fourth mask, (6) manufacturing a common electrode layer (1 ITO) on the first insulating layer, (7) manufacturing a first via hole V1 by adopting a fifth mask to simultaneously open the first insulating layer and the second insulating layer, and (8) manufacturing a pixel electrode (2 ITO) on the second insulating layer by adopting a sixth mask. The fabrication process shown in fig. 7 increases the deposition of the second insulating layer and changes the process sequence of 1ITO compared to the fabrication process shown in fig. 3 in the related art, and thus the present disclosure does not increase the fabrication cost.
In particular, in the array substrate provided in the embodiment of the present disclosure, as shown in fig. 4, 11 and 12, fig. 11 is a layout view in a dashed line frame E in fig. 4, and fig. 12 is a cross-sectional view in a dashed line frame F in fig. 11, the non-display area BB includes a common electrode ring 10 disposed along a layer surrounding the display area AA with the data lines (S1 ', S1, S2', S2..sn) and a lap joint portion 11 disposed along a layer with the pixel electrode 51,
Since the first insulating layer 7 and the second insulating layer 9 in the present disclosure use one mask, in order not to increase the mask, the common electrode ring 10 cannot be directly connected to the common electrode layer 8 through the via hole penetrating the first insulating layer 7, so that two kinds of via holes are needed to be connected in a jumping manner, that is, one end of the lap portion 11 is electrically connected to the common electrode ring 10 through the third via hole V3 penetrating the second insulating layer 9 and the first insulating layer 7, and the other end of the lap portion 11 is electrically connected to the portion of the common electrode layer 8 extending to the non-display area BB through the fourth via hole V4 penetrating the second insulating layer 9, so that the first insulating layer 7 and the second insulating layer 9 can be simultaneously perforated by one mask to form the first via hole V1 in the display area AA and the third via hole V3 and the fourth via hole V4 in the non-display area BB.
In a specific implementation, in the array substrate provided in the embodiment of the present disclosure, as shown in fig. 8, the first insulating layer 7 may be an organic insulating layer (e.g., resin material, resin), and the second insulating layer 9 may be an inorganic insulating layer (PVX). In particular, since the thickness of the organic insulating layer is generally thicker than that of the inorganic insulating layer, for example, the thickness of the organic insulating layer isAbout, the thickness of the inorganic insulating layer is smaller thanTherefore, the first insulating layer 7 of the present disclosure is made of an organic material, and parasitic capacitances such as Cgs, cgc (parasitic capacitance between the gate electrode and the common electrode ring), cdc (parasitic capacitance between the drain electrode and the common electrode ring) and the like can be further reduced, thereby enhancing the overall optical reliability of the liquid crystal display panel. The process flow of manufacturing the array substrate shown in fig. 8 is shown in fig.13, and the specific process steps include (1) manufacturing a gate layer (G) on a substrate 2 by using a first mask, (2) depositing a gate insulating layer (GI) on the whole surface of the gate layer, (3) manufacturing an active layer (Act) on the gate insulating layer by using a second mask, (4) manufacturing a source and drain electrode layer (SD) on the active layer by using a third mask, (5) manufacturing a first insulating layer (Res) on the source and drain electrode layer by using a fourth mask, (6) manufacturing a common electrode layer (1 ITO) on the first insulating layer by using a fifth mask, (7) manufacturing a second insulating layer (PVX 2) on the common electrode layer by using a sixth mask, and (8) manufacturing a pixel electrode (2 ITO) on the second insulating layer by using a seventh mask.
In particular, in the array substrate provided in the embodiment of the present disclosure, as shown in fig. 14 and 15, fig. 14 is a schematic view of another layout in a dashed line frame E in fig. 4, and fig. 15 is a schematic view of a cross section in a dashed line frame F in fig. 14, wherein the non-display area BB includes a common electrode ring 10 arranged along a layer around the display area AA with the data lines (S1 ', S1, S2', S2..once.. SN.. Once again, and a lap portion 10 arranged along a layer with the pixel electrode 51; wherein,
The overlap portion 10 is electrically connected to a portion of the common electrode layer 8 extending to the non-display region BB through a fourth via hole V4 penetrating the second insulating layer 9, and a portion of the common electrode layer 8 extending to the non-display region BB is electrically connected to the common electrode ring 10 through a fifth via hole V5 penetrating the first insulating layer 7. Specifically, since the bonding area pad of the non-display area BB is generally bonded with 2ITO, FPC, etc., the present disclosure can simultaneously manufacture the lap joint portion 10 when manufacturing the bonding area pad, so that the resistance can be reduced, and the signal transmission effect can be improved.
In particular, in order to reduce the resistance of the common electrode signal, in the above-described array substrate provided in the embodiment of the present disclosure, as shown in fig. 5, 10 and 13, the dummy data lines (S1 ', S2'. Once.
With the increasing market competition for consumer products, the cost reduction and performance are both sought after, with the transmittance (Tr.) being one of the important indicators for product performance evaluation. In the current market, PPI (pixel resolution) of liquid crystal display panels of wearable, scanning pen, industrial control and other types is concentrated between 200-330, and in order to realize low cost and border maximization, driver ICs (driver chips) with smaller volumes and supporting Dual Gate (Dual Gate, each row of pixel units is driven by two rows of scanning lines) driving architecture are basically adopted, therefore, in the above-mentioned array substrate provided in the embodiment of the present disclosure, as shown in fig. 5, a plurality of sub-pixels P are arranged in a multi-row multi-column array, and the source electrodes 61 of the two thin film transistors T on both sides of each display data line (S1, S2..sn) are electrically connected to the display data line (S1, S2..sn);
Two gate lines are disposed on both sides of each row of the sub-pixels P in the column direction, for example, gate lines G1 and G2 are disposed on both sides of the first row of the sub-pixels P in the column direction, gate lines G3 and G4 are disposed on both sides of the second row of the sub-pixels P in the column direction, gate lines G5 and G6. are disposed on both sides of the third row of the sub-pixels P in the column direction, the gate electrodes 21 of the thin film transistors T of each row of the sub-pixels P are alternately electrically connected to the two gate lines, for example, the gate electrodes 21 of the thin film transistors T of the first row of the sub-pixels P are alternately electrically connected to the gate lines G1 and G2, the gate electrodes 21 of the thin film transistors T of the second row of the sub-pixels P are alternately electrically connected to the gate lines G3 and G4, and the gate electrodes 21 of the thin film transistors T of the third row of the sub-pixels P are alternately electrically connected to the gate lines G5 and G6. Specifically, although the space for wiring in the extending direction of the lower frame data line and the number of driving ICs can be reduced by adopting the above-described dual gate driving architecture, the dual gate driving architecture sacrifices the Aperture Ratio (AR) of the pixel, but the transmittance can be improved by adopting the pixel structure in which the pixel electrode 51 is above the common electrode layer 8. Therefore, compared with the dual gate driving architecture in the related art, the embodiment of the disclosure can realize the reduction of the number of driving ICs and meet the requirement of transmittance.
Optionally, the array substrate provided in the embodiments of the present disclosure may further be a single gate (SINGLE GATE) driving architecture or a tri-gate (TRIPLE GATE) driving architecture.
In a specific implementation, in the above array substrate provided in the embodiment of the present disclosure, as shown in fig. 5, the emission colors of the sub-pixels P in the same column are the same, and each sub-pixel P in the same row includes a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3 that are sequentially and circularly arranged along the row direction, where the emission colors of the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are different from each other. Alternatively, the light emission color of the first subpixel P1 is red (R), the light emission color of the second subpixel P2 is green (G), and the light emission color of the third subpixel P3 is blue (B).
For the current lcd products, in order to prevent polarization of the liquid crystal during normal operation of the lcd panel, the polarity of the pixel voltage periodically changes with positive polarity and negative polarity centered on the common voltage. However, when the gate voltage is switched from the on-state high level VGH to the off-state low level VGL, the data line voltage finally applied to the pixel is shifted from the initial voltage, i.e., the Feed voltage (Feed-Through) Δvp, due to the parasitic capacitance. Because of the existence of the delta Vp, the pixel voltages with positive and negative polarities are wholly deviated to a certain direction, so that the difference value between the pixel voltages with the positive and negative polarities and the common voltage is asymmetric, the liquid crystal display panel has a serious Flicker (Flicker) problem, the product quality is reduced, and the phenomena of visual fatigue and dizziness of human eyes are caused.
As shown in fig. 2,3, and 6 to 8, for example, the sizes of the display products corresponding to the related art and the present disclosure are 1.3inch, respectively, and the sub-pixel P sizes of the two are the same, but the size of the pixel electrode 51 in the related art is smaller than that of the pixel electrode 51 in the present disclosure due to the coupling effect between the pixel electrode 51 and the data line in the related art, and when the widths of the slits in the two are the same and the widths of the branch electrodes between the adjacent slits are the same, the number of the branch electrodes and the number of the slits 81 of the common electrode layer 8 are, for example, 3 and 4, respectively, for the pixel structure design in the present disclosure shown in fig. 2 and 3, and the number of the branch electrodes and the number of the slits 511 of the pixel electrode 51 may be, for example, 4 and 5, respectively, for the pixel structure design in the present disclosure shown in fig. 6 to 8, due to the larger size of the pixel electrode 51. Wherein the pixel electrode 51 and the common electrode layer 8 form a storage capacitance Cst, according to a storage capacitance formulaIn the related art, only the area S of the pixel electrode 51 is different from that of the two pixel designs in the present disclosure, and as the number of the branch electrodes can be known, the area S of the pixel electrode 51 corresponding to the pixel structure design in the present disclosure is larger, so that the storage capacitance Cst in the present disclosure is larger than that in the related art. And (V)Wherein VGH is the high level signal of the grid, VGL is the low level signal of the grid, clc is the liquid crystal capacitance, cst is the pixel storage capacitance, cgs is the coupling capacitance formed by overlapping the grid and the source, the degree of Flicker is positively correlated with the DeltaVp process, and the smaller DeltaVp is, the lower the Flicker risk is. For the pixel structure designs shown in fig.2 and 6, the Clc values are the same because of the same subpixel size and LC model, and the pixel structure design shown in fig.2 corresponds to cgs=5ff (dielectric layer thickness)) In the thin film transistor design shown in fig. 6, compared with fig. 2, since the pixel electrode 51 is connected to the drain electrode 62 through the first via hole V1, the overlap capacitance of the pixel electrode 51 and the gate electrode 21 is increased in fig. 6 (thickness of medium layer in between)) Cgs=6ff corresponding to the pixel structure design shown in fig. 6 was calculated. Because the increment of Cgs is far lower than that of Cst, the Flicker risk corresponding to the pixel structure provided by the present disclosure is lower than that of the related art.
For product design, besides the avoidance of Flicker, the avoidance of cross talk (crosstalk) may be evaluated according to the formula: Where Cpd is the total coupling capacitance between the pixel electrode and the data line, cpd1 is the coupling capacitance between the pixel electrode and the nearest neighboring data line, cpd2 is the coupling capacitance between the pixel electrode and the nearest neighboring data line, vd 1-Vd 1 is the difference between the data voltages of the nearest neighboring data line to the pixel electrode in two adjacent frames, vd 2-Vd 2 is the difference between the data voltages of the nearest neighboring data line to the pixel electrode in two adjacent frames, Δv is the pulling of the visual pixel signal by the adjacent pixel, Δv is smaller, and the degree of cross talk is smaller, so as shown in the formula Δv, increasing Cst and decreasing Cpd in design is beneficial to reducing the degree of cross talk, since the storage capacitance Cst in the present disclosure is greater than the storage capacitance Cst in the related art, and as shown in fig. 3 and 7, the pixel electrode 51 and the data line in fig. 3 are located in the same plane (i.e. belong to the same layer), and the pixel electrode 51 and the data line in fig. 6 belong to different layers, and the degree of cross talk is smaller, so that the image structure of Cpd is formed by the pixel structure shown in fig. 6. In summary, the prevention of cross talk of the pixel structure design provided by the present disclosure is superior to the pixel structure design in the related art.
It should be noted that the pixel structure design of the array substrate provided by the present disclosure is applicable to SINGLE GATE, dual Gate, TRIPLE GATE pixel architecture products, but is not limited to the size, shape (circle & R angle & square) and product type (wear, industrial control, furniture medical treatment, etc.).
In summary, compared with the conventional pixel (the structure shown in fig. 3), the array substrate provided in the embodiment of the disclosure has the same Aperture Ratio (AR), but the number of slits of the pixel electrode of the disclosure is increased (for example, by 1), and through optical simulation, the transmittance of the liquid crystal display panel in which the array substrate of the disclosure is located may be increased from 4.2% to 5.1% in the related art under the same conditions of color gamut, pixel resolution, and the like. In addition, the pixel scheme of the present disclosure not only does not increase the number of masks, but also optimizes the flicker and cross talk reliability capabilities of the liquid crystal display product as compared to conventional pixels (the structure shown in fig. 3).
In specific implementation, the array substrate provided in the embodiments of the present disclosure may further include other functional structures well known to those skilled in the art, which are not described in detail herein.
Based on the same inventive concept, the embodiment of the present disclosure further provides a method for manufacturing an array substrate, as shown in fig. 16, including:
S1601, providing a substrate, wherein the substrate is provided with a display area and a non-display area surrounding the display area;
S1602, forming a plurality of grid lines and a plurality of data lines in a display area of a substrate, wherein the grid lines and the data lines are insulated and crossed to define a plurality of sub-pixels;
S1603, forming a common electrode layer at least in the display area on one side of the plurality of gate lines and the plurality of data lines away from the substrate;
s1604, forming a pixel electrode arranged in each sub-pixel on one side of the common electrode layer away from the substrate, wherein the pixel electrode is a slit electrode with a plurality of slits.
According to the manufacturing method of the array substrate, the pixel electrode is manufactured on the side, away from the substrate, of the common electrode layer, so that the pixel electrode and the data line are not in the same plane, coupling between the pixel electrode and the data line is reduced, the side, close to the data line, of the pixel electrode is not required to be far away from the data line, the pixel electrode with the larger size can be designed in each sub-pixel as far as possible, compared with the sub-pixels with the same size in the related art, the size of the pixel electrode in each sub-pixel is larger, the number of slits corresponding to each sub-pixel in the present disclosure can be more under the condition that the slit widths are consistent, and therefore, both the electric field intensity generated by the edge of the slit in the same plane and the electric field intensity generated between the pixel electrode and the common electrode layer are increased, so that the deflection degree of liquid crystal molecules is increased, and the transmittance of the liquid crystal display panel can be improved.
In a specific implementation, in the above manufacturing method provided by the embodiment of the present disclosure, when forming the array substrate shown in fig. 7, a plurality of gate lines and a plurality of data lines are formed in a display area of the substrate, specifically, a plurality of gate lines are formed on the substrate, and a plurality of data lines are formed on a side of the plurality of gate lines facing away from the substrate;
forming a plurality of data lines and forming a common electrode ring in a non-display area, wherein the source electrode and the drain electrode are formed in each sub-pixel;
after forming the plurality of data lines and before forming the common electrode layer, depositing a first insulating layer on one side of the plurality of data lines away from the substrate, wherein the first insulating layer is an inorganic insulating layer;
Depositing a first transparent conducting layer on one side of a first insulating layer, which is away from a substrate, and patterning the first transparent conducting layer to form a common electrode layer with a plurality of second through holes, wherein the second through holes are arranged corresponding to the drain electrodes;
After forming the common electrode layer and before forming the pixel electrode, depositing a second insulating layer which is an inorganic insulating layer on one side of the common electrode layer away from the substrate, and patterning the first insulating layer and the second insulating layer by adopting a one-time patterning process to respectively form a plurality of first through holes which are arranged in one-to-one correspondence with the drain electrodes, third through holes which are arranged in correspondence with the common electrode rings and fourth through holes which are arranged in correspondence with the parts of the common electrode layer extending to the non-display area, wherein the orthographic projection of the first through holes on the substrate is positioned in the orthographic projection range of the second through holes on the substrate;
the pixel electrode forming method specifically comprises the steps of depositing a second transparent conducting layer on one side, away from a substrate, of a second insulating layer, patterning the second transparent conducting layer to form a pixel electrode and forming a lap joint part located in a non-display area, wherein one end of the lap joint part is electrically connected with a common electrode ring through a third via hole, and the other end of the lap joint part is electrically connected with a part, extending to the non-display area, of the common electrode layer through a fourth via hole.
Specifically, the manufacturing process flow for forming the array substrate shown in fig. 7 may refer to fig. 10, which is not described in detail herein.
In a specific implementation, in the above manufacturing method provided by the embodiment of the present disclosure, when forming the array substrate shown in fig. 8, a plurality of gate lines and a plurality of data lines are formed in a display area of the substrate, specifically, a plurality of gate lines are formed on the substrate, and a plurality of data lines are formed on a side of the plurality of gate lines facing away from the substrate;
forming a plurality of data lines and forming a common electrode ring in a non-display area, wherein the source electrode and the drain electrode are formed in each sub-pixel;
After forming a plurality of data lines and before forming a common electrode layer, forming a first insulating layer on one side of the plurality of data lines away from the substrate by adopting a one-time composition process, wherein the first insulating layer is an organic insulating layer and is provided with first sub-through holes which are arranged in one-to-one correspondence with drain electrodes and fifth through holes which are arranged in correspondence with the common electrode ring;
The method specifically comprises the steps of depositing a first transparent conducting layer on one side, away from a substrate, of a first insulating layer, patterning the first transparent conducting layer to form a common electrode layer with a plurality of second through holes, wherein the second through holes are correspondingly arranged with a drain electrode;
The method comprises the steps of forming a common electrode layer, forming a first insulating layer on one side of the common electrode layer, which is away from a substrate, by adopting a one-time composition process, wherein the first insulating layer is an inorganic insulating layer, and the first insulating layer is provided with a plurality of first sub-vias, a plurality of second sub-vias and a plurality of fourth vias, wherein the first sub-vias are arranged in one-to-one correspondence with the first sub-vias, and the fourth vias are arranged in correspondence with the parts, extending to a non-display area, of the common electrode layer;
The pixel electrode forming method specifically comprises the steps of depositing a second transparent conducting layer on one side, away from a substrate, of a second insulating layer, patterning the second transparent conducting layer to form a pixel electrode and forming a lap joint part located in a non-display area, wherein the lap joint part is electrically connected with a part, extending to the non-display area, of a public electrode layer through a fourth via hole.
Specifically, the manufacturing process flow for forming the array substrate shown in fig. 8 may refer to fig. 13, which is not described in detail herein.
It should be noted that, in the method for manufacturing an array substrate provided in the embodiment of the present disclosure, the manufacturing process may include only a photolithography process, or may include a photolithography process and an etching step, and may also include other processes for forming a predetermined pattern, such as printing, ink-jet, etc., where the photolithography process refers to a process for forming a pattern using photoresist, a mask plate, an exposure machine, etc., including a process of film formation, exposure, development, etc. In particular implementations, the corresponding patterning process may be selected in accordance with the structures formed in the present invention.
Based on the same inventive concept, the embodiments of the present disclosure further provide a display device, including a display panel, where the display panel includes an array substrate and an opposite substrate that are disposed opposite to each other, and a liquid crystal layer interposed between the array substrate and the opposite substrate, and the array substrate is the above-mentioned array substrate provided by the embodiments of the present disclosure. The principle of the display device for solving the problems is similar to that of the array substrate, so that the implementation of the display device can be referred to the implementation of the array substrate, and the repetition is omitted herein.
In practice, the opposite substrate is a Color Filter substrate (CF) having a Color Filter and a black matrix.
In a specific implementation, the display device provided in the embodiment of the disclosure further includes other functional structures such as a backlight module.
In specific implementation, the display device provided in the embodiments of the present disclosure may be a full-screen display device, or may also be a flexible display device, which is not limited herein.
In a specific implementation, the display device provided in the embodiment of the present disclosure may be a full-screen mobile phone as shown in fig. 17. Of course, the display device provided in the embodiment of the present disclosure may be any product or component having a display function, such as a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator. Other essential components of the display device are those of ordinary skill in the art and will not be described in detail herein, nor should they be considered as limiting the present disclosure.
The embodiment of the disclosure provides an array substrate, a manufacturing method thereof and a display device, wherein a pixel electrode is arranged on one side of a common electrode layer, which is away from a substrate, so that the pixel electrode and a data line are not in the same plane, and the coupling between the pixel electrode and the data line is reduced, so that the side edge of the pixel electrode, which is close to the data line, is not required to be far away from the data line, and a pixel electrode with a larger size can be designed in each sub-pixel as far as possible.
While the preferred embodiments of the present disclosure have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the disclosure.
It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the spirit and scope of the disclosed embodiments. Thus, given that such modifications and variations of the disclosed embodiments fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to encompass such modifications and variations.