Detailed Description
To facilitate understanding of the present invention, examples are set forth below. It will be apparent to those skilled in the art that the examples are merely to aid in understanding the invention and are not to be construed as a specific limitation thereof.
It is to be understood that in the description of the present invention, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", etc. may explicitly or implicitly include one or more such feature. In the description of the present invention, unless otherwise indicated, the meaning of "a plurality" is two or more.
It should be noted that, in the description of the present invention, unless explicitly specified and limited otherwise, the terms "disposed," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, integrally connected, mechanically connected, electrically connected, directly connected, indirectly connected through an intermediate medium, or communicating between the two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art in a specific case.
In order to solve the problems of high equipment cost, reduced cutting efficiency and high fragmentation risk existing in the prior art that thick copper with the thickness of 10-50 mu m is plated on the back surface of a wafer sheet with the thickness of 20-100 mu m, the positioning points on the front surface and the back surface of the wafer are associated by adopting a positioning hole mode, the problem of thick copper cutting is avoided by adopting a photoetching mode, the whole process flow is short, the fragmentation rate is low, and the application prospect is wide.
The following is a detailed description of specific embodiments.
As a specific embodiment of the present invention, there is provided a method for electroplating metal on the back of a wafer, the specific flow is shown in fig. 1, and the method includes the following steps:
s1, forming at least two positioning holes at the edge of the wafer, wherein the positioning holes at least penetrate through the thickness direction of the wafer.
It is worth to say that the process difficulty of arranging the locating hole is completely different from the process difficulty of punching in other process production, firstly, the invention aims at the wafer production process, on one hand, the wafer is small and thin, the brittleness is high, cracks and breakage are easy to occur, stress is necessarily generated in the punching process, how to ensure that the wafer is not damaged during punching is very critical, on the other hand, the whole process belongs to micron-sized manufacturing, the unknown accuracy requirement is extremely high, the position accuracy of punching is required, the deviation of the aperture is small, and meanwhile, the performance of the following wafer can be influenced by the rough hole wall condition after punching and the like. In order to solve the problems, the invention adopts a laser etching and punching process, improves punching precision by controlling light spots below 10 mu m formed in laser etching, and reduces stress concentration and debris risk by preferably adopting a femtosecond laser.
In some embodiments of the present invention, the diameter of the positioning hole may be 10 μm or less, for example, 10 μm, 9.8 μm, 9.5 μm, 9 μm, 8.5 μm, 8 μm, 7.5 μm, 7 μm, 6.5 μm, 6 μm, 5.5 μm, 5 μm, 4.5 μm, 4 μm, or 3.5 μm, etc., but not limited to the recited values, and other non-recited values within the range are equally applicable.
The invention preferably controls the diameter of the positioning hole to be less than or equal to 10 mu m, can better improve the positioning accuracy and reduce the wafer fragment risk.
The method provided by the invention does not need to etch the carrier disc, thereby greatly reducing the production cost and the debris risk.
In some embodiments of the present invention, the method of forming at least two pilot holes includes forming pilot holes using laser etching. The spot of 10 μm or less may be formed by, for example, 10 μm, 9.8 μm, 9.5 μm, 9 μm, 8.5 μm, 8 μm, 7.5 μm, 7 μm, 6.5 μm, 6 μm, 5.5 μm, 5 μm, 4.5 μm, 4 μm or 3.5 μm during the laser etching, but the present invention is not limited to the above-mentioned values, and other values not mentioned in the above range are equally applicable.
In some embodiments of the present invention, the power of the laser etching is 1 to 10W, for example, 1W, 2W, 3W, 4W, 5W, 6W, 7W, 8W, 9W, or 10W, but not limited to the recited values, and other non-recited values within the range are equally applicable. The wavelength of the laser etching is 320 to 380nm, and may be, for example, 320nm, 330nm, 340nm, 350nm, 352nm, 353nm, 354nm, 355nm, 356nm, 357nm, 358nm, 359nm, 360nm, 370nm, 380nm, or the like, but is not limited to the values recited, and other values not recited in the range are equally applicable. The 355 laser is generally adopted in the invention, and the actual emitted wavelength range fluctuates within 320-380 nm due to the different manufacturing process and use environments of the chip. Typically, the wavelength of the laser etching is ultraviolet 355nm. The absorption rate of the silicon to 355nm ultraviolet light is up to more than 80%, the silicon can be efficiently converted into ablation energy, the thermal diffusion is reduced, the ultraviolet wavelength is shorter, smaller light spots (approaching the diffraction limit) can be focused, and the aperture requirement of 10 mu m is met.
The pulse frequency of the laser etching is 100 to 500kHz, for example, 100kHz, 145kHz, 189kHz, 234kHz, 278kHz, 323kHz, 367kHz, 412kHz, 456kHz or 500kHz, etc., but the present invention is not limited to the values listed, and other values not listed in the range are equally applicable. The single pulse energy of the laser etching may be 0.1 to 1. Mu.J, for example, 0.1. Mu.J, 0.2. Mu.J, 0.3. Mu.J, 0.4. Mu.J, 0.5. Mu.J, 0.6. Mu.J, 0.7. Mu.J, 0.8. Mu.J, 0.9. Mu.J, or 1. Mu.J, etc., but the present invention is not limited to the above-mentioned values, and other values not mentioned in the above range are applicable.
In the invention, when the wafer bonding sheet is subjected to laser drilling, the configuration of the laser needs to comprehensively consider the factors such as material characteristics, processing quality (aperture, precision, heat affected zone), efficiency, cost and the like.
The pulse type adopted by the invention is femtosecond laser (fs level, 100-500 fs), and the heat affected zone is almost zero, so that silicon melting or microcracking is avoided, and the smooth hole wall and no residual stress are ensured. If the budget is limited, picosecond lasers (ps-scale) may be selected, but the repetition rate needs to be reduced appropriately to reduce heat build-up.
The single pulse energy of the laser etching is 0.1-1 mu J, the single pulse energy is required to be matched with the aperture and the thickness of the silicon wafer, and the average power is 1-10W.
The repetition frequency of the invention is 100-500 kHz, the processing speed can be improved when the high repetition frequency is adopted, the high-speed vibrating mirror and the motion platform are matched, the experiment optimization is needed, and the edge roughness caused by heat accumulation is avoided.
The optical system configuration in the laser etching process comprises a light spot control and focusing system, wherein the light spot control adopts DOE (diffraction optical element) or SLM (spatial light modulator) to form light spots below 10 μm, and the processing precision is improved. The NA value of the objective lens in the focusing system is more than or equal to 0.4, wherein the high numerical aperture reduces the light spot, for example, the diameter of the light spot with the aperture of 10 mu m is approximately equal to 5 mu m, and the galvanometer scanning system is matched with an F-theta lens, so that the light spot consistency under high-speed scanning is ensured, and the position accuracy is ensured to be +/-1 mu m.
Illustratively, the processing environment for laser etching in the present invention is a clean room (ISO 5 grade) and a nitrogen purge is employed during etching, wherein the scanning speed of the galvanometer system is 500mm/s.
In certain embodiments of the present invention, prior to forming the at least two locating holes, the method further comprises:
And bonding the front surface of the wafer with the glass substrate to obtain the bonded assembly.
And thinning the back surface of the wafer of the bonded assembly to obtain the thinned assembly.
The invention preferably carries out the bonding and thinning treatment steps firstly, wherein the glass substrate is a transparent substrate, the front surface pattern of the wafer can be identified in the process of laser hole etching, and the problem of hole blockage in the process of hole punching, bonding and thinning treatment can be avoided.
In certain embodiments of the invention, the front side of the wafer is bonded to the glass substrate by an adhesive layer.
In the present invention, the adhesive layer may be made of a transparent material or an opaque material, and is not particularly limited, and since the front surface pattern of the wafer has a certain thickness, even if the opaque material is used, the adhesive layer formed on the front surface of the wafer has the same bump pattern as the front surface pattern, and does not affect the punching process.
In some embodiments of the present invention, the positioning hole penetrates the bonding layer while penetrating the thickness direction of the wafer, or the positioning hole penetrates the bonding layer and the glass substrate while penetrating the thickness direction of the wafer.
Generally, if bonding is performed before punching is performed, the positioning hole penetrates through the bonding layer and the glass substrate while penetrating through the thickness direction of the wafer.
In some embodiments of the present invention, the thickness of the thinned wafer is 20 to 100 μm, for example, 20 μm, 29 μm, 38 μm, 47 μm, 56 μm, 65 μm, 74 μm, 83 μm, 92 μm or 100 μm, etc., but the thickness is not limited to the recited values, and other non-recited values within the range are equally applicable.
It is worth noting that the thinner the wafer, the higher the risk of chipping in each process during the production process, and the wafer with the current thickness of 20-100 μm is more difficult to manufacture if the back of the wafer is electroplated with thick copper with the thickness of up to 10-50 μm.
The material of the wafer is not particularly required, and the material can be wafer materials well known to those skilled in the art, for example, silicon, germanium, gallium arsenide, indium phosphide, gallium nitride, silicon carbide, sapphire, quartz or aluminum nitride, etc.
S2, forming a seed layer on the back surface of the wafer to obtain a seed layer-containing component.
In certain embodiments of the present invention, the seed layer comprises a first sub-layer and a second sub-layer disposed sequentially stacked along the wafer.
The seed layer is arranged, so that the adhesion between the copper plating layer and the wafer substrate can be obviously improved, the copper layer is prevented from falling off or layering in the subsequent process, the seed layer is used as a conducting layer, the contact resistance between the copper plating layer and the wafer substrate can be effectively reduced, the current transmission efficiency is improved, the energy loss is reduced, and the quality of the copper layer of the subsequent electroplated copper layer, namely the uniformity of the electroplated metal layer, can be improved.
The first sub-layer is a titanium layer, and the second sub-layer is a copper layer.
It is worth mentioning that the process for manufacturing the seed layer comprises four steps of pretreatment, titanium seed layer sputtering, copper seed layer sputtering, post-treatment and detection:
Pretreatment, namely removing organic residues and metal pollutants by using RCA standard cleaning (SC 1 +SC2), and performing Ar plasma bombardment (RF power 50-100W for 5 minutes) in a sputtering cavity by adopting a plasma cleaning mode to activate the silicon surface.
The RCA standard clean is a critical wet chemical cleaning process in the semiconductor manufacturing process, which aims to remove particulate, organic and inorganic contaminants from the silicon wafer surface and provide a clean surface for the subsequent semiconductor manufacturing process. The process was developed by the American Radio Company (RCA), and Sc1+Sc2 refers to SC-1 cleaning solution and SC-2 cleaning solution, wherein the ratio of specific substances is not particularly limited, and the composition known to those skilled in the art is adopted.
Sputtering the titanium seed layer, namely preparing a high-purity titanium target (more than or equal to 99.995 percent), removing a surface oxide layer by pre-sputtering, and depositing the titanium seed layer in a low-pressure argon environment.
Sputtering copper (Cu) seed layer, namely switching the target material into a high-purity copper target (more than or equal to 99.999 percent), pre-sputtering to clean the target surface, depositing a conductive copper layer on the titanium layer, and ensuring continuity and low resistivity.
And (3) post-treatment and detection, namely selecting vacuum alloy according to the product property, and low-temperature annealing to optimize the conductivity of the copper layer. And after coating, testing the film thickness, the resistivity, the adhesive force and the uniformity of the quality detection film.
For the sputtering process of the seed layer, the following parameter description is given by taking an 8-inch silicon-based wafer as an example, and the following parameter description needs to be adjusted in combination with the wafer dimension characteristics (such as uniformity and thermal management requirements) and the subsequent electroplating process requirements:
In some embodiments of the present invention, the thickness of the first sub-layer is 50 to 80nm, for example, 50nm, 55nm, 60nm, 62nm, 65nm, 70nm, 75nm, 78nm, 80nm, or the like. The 8-inch wafer has larger surface area, and uniformity and adhesion of the titanium layer are ensured, so that the barrier layer failure caused by over-thinness (< 50 nm) or the introduction of stress caused by over-thickness (> 100 nm) is avoided.
In some embodiments of the present invention, the thickness of the second sub-layer is 200 to 400nm, for example, 200nm, 210nm, 220nm, 250nm, 280nm, 300nm, 310nm, 320nm, 350nm, 370nm, 380nm, 400nm, or the like. The 8-inch power device needs to support subsequent 10-50 mu m thick copper electroplating, and the seed layer needs to be continuous and free of holes, and meanwhile, the conductivity and the cost are balanced.
The seed layer is thinner, and can be cut directly later without chemical etching.
In certain embodiments of the invention, the processing of the first and second sub-layers each independently comprises vapor plating and/or sputter plating.
The specific process parameters of the first and second sub-layers during processing are not particularly limited, and may be performed using process parameters well known to those skilled in the art. Only the process parameters of sputter plating are described herein.
Preferably, the sputtering power of the first sub-layer is 300 to 500W, for example, 300W, 320W, 340W, 350W, 380W, 400W, 420W, 450W, 480W, 500W, or the like.
Preferably, the sputtering power of the second sub-layer is 200 to 350W, for example, 200W, 210W, 220W, 250W, 280W, 300W, 320W, or 350W may be used. Copper has a relatively low melting point, and therefore contamination of the droplets due to overheating of the target is to be avoided.
Preferably, the vacuum degree in the sputtering plating of the first sub-layer and the second sub-layer is the same, the basic vacuum is less than or equal to 5×10-7 Torr, for example, 5×10-7Torr、4.9×10-7Torr、4.8×10-7Torr、4.7×10-7Torr、4.5×10-7Torr、4.3×10-7Torr、4.2×10-7Torr、4.0×10-7Torr、3.9×10-7Torr、3.8×10-7Torr or 3.5×10-7 Torr, so as to obtain higher cleanliness requirements, reduce impurity pollution, the working air pressure is 3-5 Torr, for example, 3mTorr, 3.2mTorr, 3.4mTorr, 3.5mTorr, 3.8mTorr, 4.0mTorr, 4.2mTorr, 4.5mTorr or 5mTorr, etc., scattering is reduced at a low air pressure, and the film uniformity is improved, the pre-sputtering time is 10-15 minutes, for example, 10 minutes, 11 minutes, 12 minutes, 13 minutes, 14 minutes or 15 minutes, etc., so as to ensure the pre-sputtering time to thoroughly remove the oxide on the surface of the titanium target, and ensure the sputtering stability.
Preferably, the deposition rate in the sputter plating of the first sub-layer is 0.2 to 0.4nm/s, for example, 0.2nm/s, 0.23nm/s, 0.25nm/s, 0.27nm/s, 0.29nm/s, 0.32nm/s, 0.34nm/s, 0.36nm/s, 0.38nm/s or 0.4nm/s, etc., but not limited to the recited values, other non-recited values in the range are equally applicable, and the film compactness can be improved by adopting a low speed.
Preferably, the deposition rate in the sputter plating of the second sub-layer is 1.0 to 1.8nm/s, for example, 1.0nm/s, 1.09nm/s, 1.18nm/s, 1.27nm/s, 1.36nm/s, 1.45nm/s, 1.54nm/s, 1.63nm/s, 1.72nm/s or 1.8nm/s, etc., but not limited to the recited values, other non-recited values in the range are equally applicable, and the high rate is used to increase the productivity in the sputter plating of the second sub-layer, but the gas pressure is required to be matched for optimization.
S3, positioning is carried out through the positioning holes, and a glue layer containing patterns is formed on the surface of one side, far away from the wafer, of the seed layer containing component, so that the glue layer containing component is obtained.
The seed layer is covered by the pattern-containing adhesive layer, and the pattern formed by the area covered by the pattern-containing adhesive layer on the seed layer is marked as a back pattern.
The front surface of the wafer is provided with cutting channels, and the pattern formed by the cutting channels is marked as a front surface pattern.
The back pattern and the front pattern are provided with at least two locating points which are arranged in a matching mode, and the locating points are arranged corresponding to the locating holes.
The specific material of the photoresist in the photoresist layer containing the pattern in the present invention is not particularly limited, and may be a photoresist known to those skilled in the art, for example, a negative photoresist or a positive photoresist.
Preferably, the forming process of the pattern-containing glue layer is a photolithography process.
In certain embodiments of the present invention, the steps of the lithographic process include sequential gumming, lithography and development.
Specifically, the photolithography process includes:
S301, gluing, namely forming a first glue layer on the surface of the seed layer.
And S302, photoetching, namely setting a mask plate matched with the required back surface pattern on the surface of the first adhesive layer, and exposing and drying.
And S303, developing, namely removing the first adhesive layer of the unnecessary part to obtain the adhesive layer containing the pattern.
In some embodiments of the present invention, the thickness of the patterned photoresist layer is denoted as H1, the thickness of the electroplated metal layer is denoted as H2, and the ratio of H1 to H2 is 1.20:1 or more, for example 1.20:1、1.21:1、1.22:1、1.23:1、1.24:1、1.25:1、1.26:1、1.27:1、1.28:1、1.29:1、1.30:1、1.32:1、1.35:1、1.40:1、1.45:1、1.50:1 or 1.5:1, etc., but not limited to the values listed, other values not listed in the range are equally applicable, and preferably (1.20 to 2.0): 1.
The method for electroplating metal on the back of the wafer preferably controls the ratio of H1 to H2 to be more than 1.20:1, can avoid adhesion caused by overflow of metal to the upper surface of the adhesive layer containing the pattern in the copper electroplating process, and further preferably controls the ratio of H1 to H2 to be (1.20-2.0): 1, so that the thickness of adhesive coating and the use amount of developing agents can be further reduced, and the production cost is lower.
Preferably, the back pattern and the front pattern are the same.
The back pattern and the front pattern are the same, the photoetching position is calibrated in a laser drilling mode, the electroplated thick copper layer with the back pattern consistent with the front pattern can be accurately obtained, double-sided photoetching (expensive equipment) is avoided, and a carrying disc is not needed to be etched (the process is complex and difficult).
In some embodiments of the present invention, the thickness of the patterned adhesive layer is 12 to 65 μm, for example, 12 μm, 15 μm, 20 μm, 22 μm, 25 μm, 28 μm, 30 μm, 32 μm, 35 μm, 40 μm, 42 μm, 45 μm, 50 μm, 55 μm, 60 μm or 65 μm, etc., but not limited to the recited values, and other non-recited values within this range are equally applicable.
S4, forming an electroplated metal layer on the surface of the seed layer in the area which is not covered by the pattern-containing adhesive layer, and removing the pattern-containing adhesive layer to obtain the assembly with the back pattern.
In some embodiments of the present invention, the thickness of the electroplated metal layer is 10 to 50 μm, for example, 10 μm, 15 μm, 19 μm, 24 μm, 28 μm, 33 μm, 37 μm, 42 μm, 46 μm, or 50 μm, etc., but not limited to the recited values, and other non-recited values within the range are equally applicable.
In certain embodiments of the present invention, the process of forming the electroplated metal layer is horizontal electroplating.
In some embodiments of the present invention, the process parameters and plating solution composition during the plating of the metal layer are not particularly limited and may be performed using process parameters well known to those skilled in the art. For example, the current density in the electroplated metal layer is 2-5A/dm 2, wherein the low current density is 2-3A/dm 2, the method is suitable for high-precision plating layers such as 10-20 mu m, edge effect is reduced, and the high current density is 4-5A/dm 2, and the method is used for rapidly depositing thick copper layers such as 30-50 mu m, and needs to be matched with strong stirring to maintain uniformity. The components of the electroplating solution in the electroplated metal layer are 70-220g/L copper sulfate (copper sulfate pentahydrate), 150-250g/L sulfuric acid, 30-90ppm chloride ions, 60-90ppm additives (such as thiourea derivatives), 10-30ppm leveling agents (such as polyethylene glycol), 20-40ppm inhibitors (such as tetrabutylammonium bromide), 120-480ppm carrier agents (complex containing chloride ions and alum ions) and the like.
In some embodiments of the present invention, the electroplated metal layer comprises copper, copper alloy, and the like.
Preferably, after the removal of the pattern-containing glue layer, the method further comprises the steps of debonding the assembly with the back pattern and dicing the debonded wafer composite directly against the dicing film.
The invention can use the E-chuck to perform de-bonding.
The seed layer formed by the process method is thinner, the dicing film can be directly pasted for cutting after the subsequent debonding, the etching process is not needed, and the success rate of the flaking is high.
Specific examples are set forth below in detail.
Example 1
The embodiment provides a method for electroplating copper on the back surface of a wafer, which comprises the following steps:
S101, completing the front side process of the wafer 1 to obtain a first component, as shown in FIG. 2.
And S102, bonding the front surface of the wafer 1 with the glass substrate 3 through the bonding layer 2 to obtain a bonded assembly, as shown in fig. 3.
S103, thinning the back surface of the wafer 1 of the bonded assembly until the thickness of the wafer 1 is 50 μm, so as to obtain a thinned assembly, as shown in FIG. 4.
S104, as shown in fig. 5, 3 positioning holes 4 are formed on the edge of the wafer 1 by laser etching, the positioning holes 4 penetrate through the bonding layer 2 and the glass substrate 3 while penetrating through the thickness direction of the wafer 1, and the 3 positioning holes 4 are not on the same line so as to better form a positioning effect.
The laser etching device comprises a laser etching device, a laser beam system and a galvanometer system, wherein the laser etching device adopts a pulse type of 300fs femtosecond laser, the power is 5W, the wavelength of the laser etching device is 355nm, the pulse frequency of the laser etching device is 200kHz, the single pulse energy of the laser etching device is 0.5 mu J, a DOE (diffraction optical element) is adopted, the NA value of an objective lens in the focusing system is 0.4, so that light spots with the size of 5 mu m are formed, the light spot consistency under high-speed scanning is ensured, the position accuracy is +/-1 mu m, and the scanning speed of the galvanometer system is 500mm/s.
And S2, forming a seed layer 5 on the back surface of the wafer 1 to obtain a seed layer-containing component, as shown in fig. 6.
The seed layer 5 includes a first sub-layer and a second sub-layer which are sequentially stacked along the wafer 1. The first sub-layer is a titanium layer, and the second sub-layer is a copper layer. The thickness of the first sub-layer is 60nm. The thickness of the second sub-layer is 300nm.
The sputtering power of the first sub-layer is 400W, the deposition rate is 0.3nm/s, the sputtering power of the second sub-layer is 250W, the deposition rate is 1.5nm/s, the vacuum degree in the sputtering plating of the first sub-layer and the second sub-layer is the same, the basic vacuum is 4 multiplied by 10-7 Torr, and the working pressure is 4mTorr.
And S3, positioning by using the positioning holes 4, and forming a pattern-containing adhesive layer 6 on the surface of one side, far away from the wafer 1, of the seed layer 5 of the seed layer-containing assembly to obtain an adhesive layer-containing assembly, as shown in fig. 7.
Wherein the pattern-containing glue layer 6 partially covers the seed layer 5, and the pattern formed on the seed layer 5 by the area covered by the pattern-containing glue layer 6 is denoted as a back pattern. The front surface of the wafer 1 is provided with cutting channels, and the pattern formed by the cutting channels is marked as a front surface pattern. The back surface pattern and the front surface pattern are provided with at least two locating points which are arranged in a matching way, the locating points are arranged corresponding to the locating holes 4, and the back surface pattern and the front surface pattern are identical.
Specifically, the forming process of the pattern-containing adhesive layer 6 is a photolithography process, and the photolithography process includes:
s301, gluing, namely forming a first glue layer on the surface of the seed layer 5.
And S302, photoetching, namely setting a mask plate matched with the required back surface pattern on the surface of the first adhesive layer, and exposing and drying.
S303, developing, namely removing the first adhesive layer of the unnecessary part to obtain the adhesive layer 6 containing the pattern, wherein the thickness of the adhesive layer 6 containing the pattern is recorded as H1, the thickness of the electroplated copper layer 7 is recorded as H2, the ratio of H1 to H2 is 1.20:1, and the thickness of the adhesive layer 6 containing the pattern is 60 mu m.
S4, carrying out horizontal electroplating on the surface of the seed layer 5 which is not covered by the pattern-containing adhesive layer 6 to form an electroplated copper layer 7 with the thickness of 50 mu m, as shown in fig. 8, and removing the pattern-containing adhesive layer 6 to expose a back cutting area 8, so as to obtain the assembly with the back pattern, as shown in fig. 9.
S5, the assembly with the back pattern is subjected to debonding, and the wafer 1 composite piece after debonding is directly pasted with the scribing film for cutting.
The method for electroplating copper on the back of the wafer is simple in steps, greatly shortens the production flow of electroplating copper on the back, does not need to adopt a double-sided photoetching machine, and can realize copying of front cutting channel patterns to the back by directly punching holes on the edge of the wafer from the front, so that the problem that wafer fragments or production cost is high due to the cutting process of electroplating thick copper is avoided, and the application prospect is wide.
Example 2
The embodiment provides a method for electroplating copper on the back surface of a wafer, which comprises the following steps:
S101, completing the front-side process of the wafer to obtain a first component.
And S102, bonding the front surface of the wafer with the glass substrate through an adhesive layer to obtain a bonded assembly.
S103, thinning the back surface of the wafer of the bonded assembly until the thickness of the wafer is 20 mu m, and obtaining the thinned assembly.
S104, forming 3 positioning holes at the edge of the wafer by laser etching, wherein the positioning holes penetrate through the bonding layer and the glass substrate while penetrating through the thickness direction of the wafer, and the 3 positioning holes are not in the same straight line so as to better form a positioning effect.
The laser etching device comprises a laser etching device, a laser system, a focusing system, a laser beam forming device and a galvanometer system, wherein the laser etching device adopts a pulse type of femtosecond laser, the power is 10W, the wavelength of the laser etching device is 355nm, the pulse frequency of the laser etching device is 100kHz, the single pulse energy of the laser etching device is 1 mu J, a DOE (diffraction optical element) is adopted, the NA value of an objective lens in the focusing system is 0.5, so that light spots with the size of 4 mu m are formed, the light spot consistency under high-speed scanning is ensured, the position accuracy is +/-1 mu m, and the scanning speed of the galvanometer system is 400mm/s.
S2, forming a seed layer on the back surface of the wafer to obtain a seed layer-containing component.
The seed layer comprises a first sub-layer and a second sub-layer which are sequentially stacked along the wafer. The first sub-layer is a titanium layer, and the second sub-layer is a copper layer. The thickness of the first sub-layer is 80nm. The thickness of the second sub-layer is 400nm.
The sputtering power of the first sub-layer is 500W, the deposition rate is 0.4nm/s, the sputtering power of the second sub-layer is 350W, the deposition rate is 1.0nm/s, the vacuum degree in the sputtering plating of the first sub-layer and the second sub-layer is the same, the basic vacuum is 5 multiplied by 10-7 Torr, and the working pressure is 5mTorr.
S3, positioning is carried out through the positioning holes, and a glue layer containing patterns is formed on the surface of one side, far away from the wafer, of the seed layer containing component, so that the glue layer containing component is obtained.
The seed layer is covered by the pattern-containing adhesive layer, and the pattern formed by the area covered by the pattern-containing adhesive layer on the seed layer is marked as a back pattern. The front surface of the wafer is provided with cutting channels, and the pattern formed by the cutting channels is marked as a front surface pattern. The back pattern and the front pattern are provided with at least two locating points which are arranged in a matching way, the locating points are arranged corresponding to the locating holes, and the back pattern and the front pattern are identical.
Specifically, the forming process of the pattern-containing adhesive layer is a photolithography process, and the photolithography process comprises:
S301, gluing, namely forming a first glue layer on the surface of the seed layer.
And S302, photoetching, namely setting a mask plate matched with the required back surface pattern on the surface of the first adhesive layer, and exposing and drying.
S303, developing, namely removing the first adhesive layer of the unnecessary part to obtain a pattern-containing adhesive layer, wherein the thickness of the pattern-containing adhesive layer is recorded as H1, the thickness of the electroplated copper layer is recorded as H2, the ratio of H1 to H2 is 1.25:1, and the thickness of the pattern-containing adhesive layer is particularly 50 mu m.
S4, carrying out horizontal electroplating on the surface of the seed layer in the area which is not covered by the pattern-containing adhesive layer to form an electroplated copper layer with the thickness of 40 mu m, and removing the pattern-containing adhesive layer to obtain the assembly with the back pattern.
And S5, debonding the assembly with the back pattern, and cutting the wafer composite piece after debonding by directly sticking the dicing film.
The method for electroplating copper on the back of the wafer is simple in steps, greatly shortens the production flow of electroplating copper on the back, does not need to adopt a double-sided photoetching machine, and can realize copying of front cutting channel patterns to the back by directly punching holes on the edge of the wafer from the front, so that the problem that wafer fragments or production cost is high due to the cutting process of electroplating thick copper is avoided, and the application prospect is wide.
Example 3
The embodiment provides a method for electroplating copper on the back surface of a wafer, which comprises the following steps:
S101, completing the front-side process of the wafer to obtain a first component.
And S102, bonding the front surface of the wafer with the glass substrate through an adhesive layer to obtain a bonded assembly.
S103, thinning the back surface of the wafer of the bonded assembly until the thickness of the wafer is 100 mu m, and obtaining the thinned assembly.
And S104, forming 2 positioning holes at the edge of the wafer by adopting laser etching, wherein the positioning holes penetrate through the bonding layer and the glass substrate while penetrating through the thickness direction of the wafer.
The laser etching device comprises a laser etching device, a laser system and a galvanometer system, wherein the laser etching device adopts a pulse type of femtosecond laser, the power is 1W, the wavelength of the laser etching device is 355nm, the pulse frequency of the laser etching device is 500kHz, the single pulse energy of the laser etching device is 0.1 mu J, a DOE (diffraction optical element) is adopted, the NA value of an objective lens in the focusing system is 0.4, so that a light spot of 5 mu m is formed, the light spot consistency under high-speed scanning is ensured by matching with an F-theta lens, the position accuracy is +/-1 mu m, and the scanning speed of the galvanometer system is 550mm/s. S2, forming a seed layer on the back surface of the wafer to obtain a seed layer-containing component.
The seed layer comprises a first sub-layer and a second sub-layer which are sequentially stacked along the wafer. The first sub-layer is a titanium layer, and the second sub-layer is a copper layer. The thickness of the first sub-layer is 50nm. The thickness of the second sub-layer is 200nm.
The sputtering power of the first sub-layer is 300W, the deposition rate is 0.2nm/s, the sputtering power of the second sub-layer is 200W, the deposition rate is 1.8nm/s, the vacuum degree in the sputtering plating of the first sub-layer and the second sub-layer is the same, the basic vacuum is 4.5 multiplied by 10-7 Torr, and the working pressure is 3mTorr.
S3, positioning is carried out through the positioning holes, and a glue layer containing patterns is formed on the surface of one side, far away from the wafer, of the seed layer containing component, so that the glue layer containing component is obtained.
The seed layer is covered by the pattern-containing adhesive layer, and the pattern formed by the area covered by the pattern-containing adhesive layer on the seed layer is marked as a back pattern. The front surface of the wafer is provided with cutting channels, and the pattern formed by the cutting channels is marked as a front surface pattern. The back pattern and the front pattern are provided with at least two locating points which are arranged in a matching way, the locating points are arranged corresponding to the locating holes, and the back pattern and the front pattern are identical.
Specifically, the forming process of the pattern-containing adhesive layer is a photolithography process, and the photolithography process comprises:
S301, gluing, namely forming a first glue layer on the surface of the seed layer.
And S302, photoetching, namely setting a mask plate matched with the required back surface pattern on the surface of the first adhesive layer, and exposing and drying.
S303, developing, namely removing the first adhesive layer of the unnecessary part to obtain a pattern-containing adhesive layer, wherein the thickness of the pattern-containing adhesive layer is recorded as H1, the thickness of the electroplated copper layer is recorded as H2, the ratio of H1 to H2 is 1.2:1, and the thickness of the pattern-containing adhesive layer is specifically 12 mu m.
S4, carrying out horizontal electroplating on the surface of the seed layer in the area which is not covered by the pattern-containing adhesive layer to form an electroplated copper layer with the thickness of 10 mu m, and removing the pattern-containing adhesive layer to obtain the assembly with the back pattern.
And S5, debonding the assembly with the back pattern, and cutting the wafer composite piece after debonding by directly sticking the dicing film.
The method for electroplating copper on the back of the wafer is simple in steps, greatly shortens the production flow of electroplating copper on the back, does not need to adopt a double-sided photoetching machine, and can realize copying of front cutting channel patterns to the back by directly punching holes on the edge of the wafer from the front, so that the problem that wafer fragments or production cost is high due to the cutting process of electroplating thick copper is avoided, and the application prospect is wide.
Example 4
The embodiment provides a method for electroplating copper on the back surface of a wafer, which is the same as that of embodiment 1 except that the thickness of the patterned photoresist layer in step S303 is 55 μm, i.e. the ratio of H1 to H2 is controlled to be 1.1:1, and will not be described herein.
Compared with example 4, example 1 can better ensure that the copper layer in the copper electroplating process does not grow to the upper surface of the patterned glue layer, thereby avoiding the situation that the subsequent glue layer is difficult to remove or the copper layer still needs to be cut.
Example 5
The embodiment provides a method for electroplating copper on the back surface of a wafer, which is the same as embodiment 1 except that a laser etching is used to form a light spot with a diameter of 12 μm, and will not be described again.
In this embodiment, due to the large diameter of the formed light spot, the diameter of the punched positioning hole is as high as 20 μm, so that it is difficult to more accurately position the mask on the back surface, after thick copper is electroplated, on one hand, a part of thick copper needs to be cut when cutting is performed, on the other hand, a part of area on the back surface of the wafer is not electroplated with thick copper, and the production process failure easily occurs.
Example 6
The embodiment provides a method for electroplating copper on the back surface of a wafer, which is the same as that of embodiment 1 except that the pulse type used in the laser etching is 100ps laser, and will not be described herein.
In this example, since picosecond laser is used, the wafer is likely to be molten or microcracked, and residual stress may occur, the wafer breakage rate is increased as compared with that in example 1.
Example 7
The embodiment provides a method for electroplating copper on the back surface of a wafer, which is the same as embodiment 1 except that step S104 is performed first and step S103 is performed again, and will not be described again.
In example 1, compared with example 7, in example 1, the positioning holes were first thinned and then laser etched, so that there is no risk of blocking the positioning holes, while in example 7, the positioning holes were first laser etched and then thinned, and then the positioning holes were blocked in the thinning process, so that it was difficult to accurately position the back mask plate through the positioning holes, and the process could not be continued.
Comparative example 1
This comparative example provides a fenestrated double-sided thick copper film plating process using the method provided in the embodiments of CN111710647 a.
The comparative example can simultaneously plate Cu on the front and back crystal faces by forming a glass carrier window at the front contact point of the wafer, however, the process needs a double-sided photoetching machine, the cost of which is obviously increased compared with that of a single-sided photoetching machine and the operation precision of equipment is high, and the comparative example needs etching to remove the double-sided seed layer after removing the photoresist layer, so that the whole process is quite complex, and the fragmentation risk is obviously increased when one step is added, thereby obviously increasing the fragmentation rate of the whole process compared with the invention.
The present invention is described in detail by the above embodiments, but the present invention is not limited to the above detailed features, that is, it does not mean that the present invention must be implemented depending on the above detailed features. It should be apparent to those skilled in the art that any modifications, equivalent substitutions for selected features of the present invention, addition of auxiliary features, selection of specific modes, etc. fall within the scope of the invention and the disclosure.