FCBGA package stacking and packaging structure and preparation method thereofTechnical Field
The invention relates to the technical field of advanced packaging products, in particular to a FCBGA packaging body stacking packaging structure and a preparation method thereof.
Background
In the technical field of semiconductor packaging, the demands of ultra-low signal loss factors, ultra-high density, ultra-high speed, ultra-low delay and ultra-multiple interconnection chips of equipment chips in high frequency fields such as communication, high-speed calculation and AI ultra-calculation are increased. 3D packaging is therefore a focus of current industry attention. In contrast to 2.5D packages, the principle of 3D packages is to make transistor structures on the chip and use vias to connect the electrical signals of different chips up and down to directly stack the memory or other chips vertically above. The 3D package area is smaller, the power consumption is lower, is used for super-large bandwidth. But how to solve the insulation problem under ultra-high density wiring, the heat accumulation problem of ultra-high density chips and realize ultra-multi-chip packaging becomes an important challenge.
On the one hand, the existing 3D packaging structure has the advantages that chips are vertically stacked, the chips located in the middle are limited by the packaging structure, heat can be conducted only through the chips, the heat dissipation efficiency is low, heat accumulation in the chips is serious, and the working efficiency of the chips is affected. In addition, the traditional heat dissipation mode only contacts with the top of the chip, and only the top contacts with the chip, so that the heat dissipation can be effectively achieved.
On the other hand, the existing silicon intermediate layer circuit signal transmission has the insulation problem, has larger signal attenuation, loss and larger incident signal loss, is high in cost due to the complicated process of the silicon-based intermediate layer, cannot be ultrathin in thickness and larger in size due to the fact that warpage is large, and influences the packaging capability of oversized chips and oversized chips.
Furthermore, the conventional embedded package is mainly embedded in the substrate and the PCB, and is limited by the process capability of the substrate and the PCB, which results in low interconnection density, long transmission path, low transmission rate, large signal delay, and large package volume, and cannot meet the high-density, high-speed and low-delay interconnection requirements of high-frequency and high-speed electronic devices.
Therefore, a new 3D package structure is needed to solve the above-mentioned problems.
Disclosure of Invention
In order to solve the problems, the invention provides a FCBGA package stacking and packaging structure and a preparation method thereof, wherein 3D vertical interconnection of chips is realized through a glass-based through hole technology and an embedded packaging technology, face-to-face 3D vertical interconnection of chips can be realized at lower cost, an ultra-short transmission path between the chips is realized, 3D vertical interconnection density and transmission rate are improved, signal delay is reduced, packaging volume is reduced, high-density, high-speed and low-delay interconnection requirements of high-frequency and high-speed electronic equipment are met, and meanwhile, a novel liquid cooling micro-channel auxiliary heat dissipation cover is adopted for heat dissipation, so that a good heat dissipation effect is realized.
In a first aspect, the invention provides an FCBGA package, which comprises an HBM chip and an SOC chip stacked on a glass substrate in a vertical direction, wherein one side of the HBM chip and one side of the SOC chip are respectively provided with a micro-channel, the glass substrate is provided with a substrate micro-channel through which cooling liquid flows, and the substrate micro-channel is communicated with the micro-channels of the HBM chip and the SOC chip.
Preferably, the FCBGA package specifically includes:
the first glass-based medium layer is embedded with an SOC chip, the front side and the back side of the SOC chip are respectively provided with a rewiring layer, the rewiring layers are interconnected, the rewiring layers are provided with micro-bumps, and a first micro-channel is arranged between the back side of the SOC chip and the rewiring layers;
the second glass-based medium layer is embedded with an HBM chip, the front surface of the HBM chip is provided with a passivation layer and a micro-bump, and the back surface of the HBM chip is provided with a second micro-channel;
The glass substrate is provided with a circuit layer, a substrate micro-channel and a substrate conductive through hole, wherein the substrate micro-channel comprises a first substrate micro-channel and a second substrate micro-channel, the first substrate micro-channel forms a first inlet on the front surface of the glass substrate and a second inlet on the back surface of the glass substrate;
Wherein,
The second glass-based medium layer is inversely arranged on one side of the front side of the SOC chip of the first glass-based medium layer, then is inversely arranged on the front side of the glass substrate, a capacitor is attached to the front side of the glass substrate, and balls are planted on the back side of the glass substrate to form an FCBGA package;
In the FCBGA package, an inlet of the second micro-channel is communicated with an inlet of the first micro-channel and a first inlet of the substrate micro-channel, and an outlet of the second micro-channel is communicated with an outlet of the first micro-channel and a first outlet of the substrate micro-channel to form a cooling channel.
Preferably, the heat dissipation cover is arranged on the front surface of the glass substrate, and covers the first glass-based medium layer, the second glass-based medium layer, the capacitor and the front surface of the glass substrate.
In a second aspect, the invention further provides a stacked package structure, which is formed by welding the FCBGA package body on a PCB, wherein the PCB is provided with a cooling liquid inlet and a cooling liquid outlet, the cooling liquid inlet is communicated with a second inlet on the back surface of the glass substrate, and the cooling liquid outlet is communicated with a second outlet on the back surface of the glass substrate.
In a third aspect, the present invention also discloses a method for preparing the stacked package structure, which includes the following steps:
S1, forming a first micro-channel, a first chip preset cavity and a first conductive through hole in a first glass-based intermediate layer, embedding an SOC chip in the first chip preset cavity, respectively arranging a rewiring layer on the front surface and the back surface of the SOC chip, realizing interconnection between the rewiring layers through the first conductive through hole, arranging micro-bumps on the rewiring layers, and arranging the first micro-channel between the back surface of the SOC chip and the rewiring layers;
s2, forming a second micro-channel and a second chip preset cavity in the second glass-based medium layer, embedding a forward-mounted HBM chip in the second chip preset cavity, wherein a passivation layer and micro-bumps are arranged on the front surface of the HBM chip, and the back surface of the HBM chip is close to the second micro-channel;
S3, forming a circuit layer, a substrate micro-channel and a substrate conductive through hole in the glass substrate, wherein the substrate micro-channel comprises a first substrate micro-channel and a second substrate micro-channel, the first substrate micro-channel forms a first inlet on the front surface of the glass substrate and a second inlet on the back surface of the glass substrate;
s4, reversely mounting the second glass-based interposer in S2 on one side of the front side of the SOC chip of the first glass-based interposer in S1, reversely mounting the whole on the front side of the glass substrate, attaching a capacitor on the front side of the glass substrate, and implanting balls on the back side of the glass substrate to form an FCBGA package;
In the FCBGA package, an inlet of the second micro-channel is communicated with an inlet of the first micro-channel and a first inlet of the substrate micro-channel, and an outlet of the second micro-channel is communicated with an outlet of the first micro-channel and a first outlet of the substrate micro-channel to form a cooling channel;
S5, welding the FCBGA package body in the step S4 on a PCB, wherein the PCB is provided with a cooling liquid inlet and a cooling liquid outlet, the cooling liquid inlet is communicated with a second inlet on the back surface of the glass substrate, and the cooling liquid outlet is communicated with a second outlet on the back surface of the glass substrate.
Compared with the prior art, the invention has the beneficial effects that:
The invention realizes 3D vertical interconnection of chips by a glass-based through hole technology and an embedded packaging technology, can realize face-to-face 3D vertical interconnection of chips with lower cost, realize ultra-short transmission paths among chips, improve 3D vertical interconnection density and transmission rate, reduce signal delay, reduce packaging volume and meet the high-density, high-speed and low-delay interconnection requirements of high-frequency and high-speed electronic equipment.
According to the invention, the micro-flow channel is manufactured in the first glass-based medium layer, the second glass-based medium layer and the glass substrate, is subjected to whole 3D packaging and communicated, is in direct contact with the back surface of each chip, directly dissipates heat of the chip at the middle position of the 3D packaging through liquid cooling heat dissipation, and improves the heat-relieving capability of the packaging, so that the chip performance is improved, the chip design and packaging requirements of ultrahigh-density and high-heat-emitting high-speed electronic equipment are met, and the working performance of the high-performance chip is improved.
According to the invention, the glass insulator is used as the intermediate layer of the 3D package and the base material of the substrate, compared with the silicon-based material, the glass-based intermediate layer is used, compared with the silicon-based intermediate layer, the glass is easy to obtain due to the large-size ultrathin panel glass, the deposition of the insulating layer is not needed, the manufacturing cost of the glass adapter plate is about 1/8 of that of the silicon-based intermediate layer, the ultrathin adapter plate does not need a thinning process, the packaging process flow is simple, and the 3D packaging cost can be effectively reduced. The substrate loss and parasitic effect of the glass substrate are greatly reduced, the integrity of transmission signals is ensured, the signal loss factor is reduced, higher-density wiring interconnection is realized based on the advantages, the optical fiber glass has excellent electrical, thermal and mechanical properties, good mechanical stability is realized, even when the thickness of the adapter plate is smaller than 100 mu m, the warping performance is good, the advantage of low warping is realized, and ultra-large-area packaging with ultra-large size and ultra-thin packaging thickness can be realized, so that ultra-multi-chip packaging is realized.
Drawings
FIG. 1 is a schematic diagram of the FCBGA package in accordance with embodiment 1 of the present invention;
FIG. 2 is a schematic diagram of a first glass-based interposer according to embodiment 1 of the present invention;
FIG. 3 is a schematic diagram of the structure of an embedded SOC chip in embodiment 1 of the present invention;
FIG. 4 is a schematic diagram of a second glass-based interposer according to example 1 of the present invention;
FIG. 5 is a schematic view showing the structure of a glass substrate in example 1 of the present invention;
FIG. 6 is a schematic diagram of the structure of a second glass-based interposer inverted over the first glass-based interposer according to example 1 of the present invention;
FIG. 7 is a schematic view of the structure of the molded package of FIG. 6;
FIG. 8 is a schematic diagram of a structure in which the wafer in FIG. 7 is diced into individual chips and then flip-chip mounted on a glass substrate;
Fig. 9 is a schematic diagram of a structure of soldering an FCBGA package on a PCB board in embodiment 2 of the present invention;
Fig. 10 is a schematic diagram of a stacked package structure in embodiment 2 of the present invention.
The reference numerals illustrate a glass substrate 1, a first glass-based interposer 2, a second glass-based interposer 3, an soc chip 4, a redistribution layer 5, a microbump 6, a first microchannel 7, an hbm chip 8, a passivation layer 9, a second microchannel 10, a substrate microchannel 11, a wiring layer 12, a molding layer 13, a capacitor 14, a heat dissipating cover 15, a pcb board 16, a first base glass layer 201, a first top glass layer 202, a first conductive via 203, a first chip pre-cavity 401, an inlet 701 of the first microchannel, a second base glass layer 301, a second top glass layer 302, an inlet 1001, an outlet 1002, a second chip pre-cavity 801, a first base microchannel 1101, a second base microchannel 1102, a first inlet 1103, a second inlet 1104, a first outlet 1106, a third base glass layer 101, a third top glass layer 102, a substrate conductive via 103, a cooling liquid inlet 1601, a cooling liquid outlet 1602, a first facing opening 1603, a cooling liquid inlet and a second facing opening 1604.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the invention, the first glass-based medium layer, the second glass-based medium layer and the glass substrate are all made of glass, the glass insulator is adopted as the medium layer of the 3D package and the base material of the substrate, compared with the silicon-based material, the glass-based medium layer is adopted, compared with the silicon-based medium layer, the glass is beneficial to the acquisition of large-size ultrathin panel glass, and the glass adapter plate does not need to deposit an insulating layer, the manufacturing cost of the glass adapter plate is about 1/8 of that of the silicon-based medium layer, the ultrathin adapter plate does not need a thinning process, the packaging process flow is simple, and the 3D packaging cost can be effectively reduced.
EXAMPLE 1 FCBGA Package and method of preparing the same
The present embodiment provides an FCBGA package, whose structural schematic diagram is shown in fig. 1, specifically includes an HBM chip 8 and an SOC chip 4 stacked on a glass substrate 1 in a vertical direction, where one sides of the HBM chip 8 and the SOC chip 4 are respectively provided with a micro-channel, the glass substrate 1 is provided with a substrate micro-channel 11 through which a cooling liquid flows, and the substrate micro-channel 11 is communicated with the micro-channels of the HBM chip 8 and the SOC chip 4.
In order to realize the structure, the FCBGA package specifically comprises a first glass-based interposer 2, a second glass-based interposer 3 and a glass substrate 1.
As shown in fig. 2-3, the first glass-based interposer 2 is embedded with the SOC chip 4, the front and back sides of the SOC chip 4 are respectively provided with a redistribution layer 5, the redistribution layers 5 are interconnected, the redistribution layers 5 are provided with micro bumps 6, and a first micro channel 7 is provided between the back side of the SOC chip 4 and the redistribution layer 5.
In the specific preparation of the first glass-based interposer 2, the flow chart is shown in fig. 2, and the first glass-based interposer 2 is divided into a bonded first base glass layer 201 and a first top glass layer 202, and the structures shown in fig. 2a are all made of glass materials. As shown in fig. 2b, before bonding, the first micro flow channel 7 is formed on the first base glass layer 201 by drilling or etching technology, the first chip pre-cavity 401 is formed on the first top glass layer 202 by drilling or etching technology, and then the first base glass layer 201 and the first top glass layer 202 are bonded. A plurality of through holes are formed in the same positions of the bonded first base glass layer 201 and first top glass layer 202 by drilling or etching techniques, and conductive layers are formed in the through holes by a deposition process to form first conductive through holes 203. Finally, inlets and outlets are prepared at two ends of the first micro-channel 7 through drilling or etching technology, and the inlets 701 of the first micro-channel and the outlets 702 of the first micro-channel penetrate through the first glass-based interposer 2.
Then, as shown in 3a-3c of fig. 3, the SOC chip 4 is embedded in the first chip preset cavity 401, the front and back sides of the SOC chip 4 are respectively provided with a redistribution layer 5, interconnection between the redistribution layers 5 is realized through the first conductive through holes 203, the redistribution layers 5 are provided with micro bumps 6, and the first micro channels 7 are located between the back side of the SOC chip 4 and the redistribution layers 5.
As shown in fig. 4, the second glass-based interposer 3 is embedded with an HBM chip 8, the front surface of the HBM chip 8 is provided with a passivation layer 9 and a microbump 6, and the back surface of the HBM chip 8 is provided with a second micro flow channel 10.
In the specific preparation of the second glass-based interposer 3, the flow chart is shown in fig. 4a-4d, where the second glass-based interposer 3 is also divided into a bonded second base glass layer 301 and a second top glass layer 302. Before bonding, the second micro flow channel 10 is formed on the second base glass layer 301 by drilling or etching technology, the second chip preset cavity 801 is formed on the second top glass layer 302 by drilling or etching technology, and then the second base glass layer 301 and the second top glass layer 302 are bonded. Finally, inlets 1001 and outlets 1002 are prepared at both ends of the second micro flow channel 10 by drilling or etching technology, and the inlets and outlets of the second micro flow channel 10 penetrate only the second top glass layer 302.
And then a positive HBM chip 8 is embedded in the second chip preset cavity 801, a passivation layer 9 and a micro-bump 6 are arranged on the front surface of the HBM chip 8, and the back surface of the HBM chip 8 is close to the second micro-channel 10. Both ends of the second micro flow channel 10 are plated to make extended inlet 1001 and outlet 1002.
As shown in fig. 5, the glass substrate 1 is provided with a circuit layer 12, a substrate micro flow channel 11 and a substrate conductive through hole 103, wherein the substrate micro flow channel 11 comprises a first substrate micro flow channel 1101 and a second substrate micro flow channel 1102, the first substrate micro flow channel 1101 forms a first inlet 1103 on the front surface of the glass substrate 1 and a second inlet 1104 on the back surface of the glass substrate 1, the second substrate micro flow channel 1102 forms a first outlet 1105 on the front surface of the glass substrate 1 and a second outlet 1106 on the back surface of the glass substrate 1.
In the specific preparation of the glass substrate 1, as shown in fig. 5a, the glass substrate 1 is also divided into a bonded third base glass layer 101 and a third top glass layer 102. Before bonding, a substrate micro flow channel 11 is formed on the third base glass layer 101 by drilling or etching technology, the substrate micro flow channel 11 includes a first substrate micro flow channel 1101 and a second substrate micro flow channel 1102 which are symmetrically disposed left and right, and then the third base glass layer 101 and the third top glass layer 102 are bonded, as shown in fig. 5 b. A plurality of through holes are formed in the same positions of the bonded third base glass layer 101 and third top glass layer 102 by drilling or etching technique, and a conductive layer is formed in the through holes by a deposition process, forming substrate conductive through holes 103, as shown in fig. 5 c. A wiring layer 12 is formed within the bonded third base glass layer 101 and third top glass layer 102. The first substrate micro flow channel 1101 forms a first inlet 1103 on the front surface of the glass substrate 1 and a second inlet 1104 on the back surface of the glass substrate 1 by drilling or etching, the second substrate micro flow channel 1102 forms a first outlet 1105 on the front surface of the glass substrate 1 and a second outlet 1106 on the back surface of the glass substrate 1, as shown in fig. 5 d.
Thereafter, as shown in fig. 6a and 6b, the second glass-based interposer 3 is mounted upside down on the front side of the SOC chip 4 of the first glass-based interposer 2, the inlet 1001 of the second micro flow channel 10 communicates with the inlet 701 of the first micro flow channel 7, and the outlet of the second micro flow channel 10 communicates with the outlet of the first micro flow channel 7.
After connection, as shown in fig. 7, the micro bump 6 area on the front surface of the HBM chip 8 is filled with an insulating material, a plastic layer 13 is formed around the second glass-based interposer 3 and the upper surface of the second glass-based interposer is exposed, the plastic layer 13 is made of an epoxy resin plastic material to form a plastic-sealed wafer, and then the whole wafer is thinned by a lapping process until the surface of the second base glass layer 301 is exposed, so that the combined whole wafer is formed.
Finally, as shown in fig. 8, the whole wafer is cut into single chips and then flip-chip mounted on the front surface of the glass substrate 1 one by one according to a pattern. The inlet of the first micro flow channel 7 is made to communicate with the first inlet 1103 of the first substrate micro flow channel 1101 in the substrate micro flow channel 11, and the outlet of the first micro flow channel 7 is made to communicate with the first outlet 1105 of the second substrate micro flow channel 1102 and in the substrate micro flow channel 11.
And then filling insulating materials in the rewiring layer 5 and the micro-bump 6 area on the back of the SOC chip 4, mounting a capacitor 14 on the front of the glass substrate 1 through an SMT process, then mounting a heat dissipation cover 15, covering the front of the first glass-based interposer 2, the second glass-based interposer 3, the capacitor 14 and the glass substrate 1 by the heat dissipation cover 15, and finally implanting balls on the back of the glass substrate 1 to form the FCBGA package structure shown in figure 1.
In the FCBGA package manufacturing process, the inlet of the second micro flow channel 10 is communicated with the inlet of the first micro flow channel 7 and the first inlet 1103 of the substrate micro flow channel 11, and the outlet of the second micro flow channel 10 is communicated with the outlet of the first micro flow channel 7 and the first outlet 1105 of the substrate micro flow channel 11 to form a cooling channel, and the cooling channel is used for cooling liquid to pass through.
In the specific implementation process, the position of the first micro-channel 7 is arranged at the center of the SOC chip 4, and the position of the second micro-channel 10 is arranged at the center of the HBM chip 8, so that the cooling liquid in the first micro-channel 7 and the second micro-channel 10 can directly take away internal heat when the packaging body works, and quick and effective heat dissipation is realized. The substrate micro flow channel 11 is also provided at the middle position, and a plurality of micro flow channels can be provided to assist heat dissipation according to actual needs.
In this embodiment, the arrangement of the first micro flow channel 7, the second micro flow channel 10 and the substrate micro flow channel 11 directly and maximally helps the HBM chip 8 and the SOC chip 4 to dissipate heat in operation, so that the heat dissipation effect of the package is improved, and the working performance of the high-performance chip is improved.
In this embodiment, through the technology of arranging the through holes on the glass substrate, the 3D vertical interconnection of the chips is realized, the face-to-face 3D vertical interconnection of the chips can be realized at lower cost, the ultra-short transmission path between the chips is realized, the 3D vertical interconnection density and transmission rate are improved, the signal delay is reduced, the packaging volume is reduced, and the high-density, high-speed and low-delay interconnection requirements of high-frequency and high-speed electronic equipment are satisfied.
Example 2 stacked Package Structure with FCBGA Package
The stacked package structure disclosed in this embodiment is a structure in which the FCBGA package of embodiment 1 is soldered to the PCB board 16. As shown in fig. 9, the PCB 16 in this embodiment is provided with a coolant inlet 1601 and a coolant outlet 1602. After the FCBGA package is mounted, the cooling liquid inlet 1601 communicates with the second inlet 1104 on the back surface of the glass substrate 1 of the FCBGA package, and the cooling liquid outlet 1602 communicates with the second outlet 1106 on the back surface of the glass substrate 1.
Specifically, as shown in fig. 10, a cooling liquid inlet 1601 and a cooling liquid outlet 1602 are disposed on the left and right sides of the PCB board 16, the cooling liquid inlet 1601 is connected to a first opposite opening 1603 along the through hole, the cooling liquid inlet 1601 is connected to an external circulation pump body (not shown in the figure), the first opposite opening 1603 is connected to a second inlet 1104 on the back surface of the glass substrate 1, the cooling liquid outlet 1602 is connected to a second opposite opening 1604 along the through hole, the cooling liquid outlet 1602 is connected to the external circulation pump body, and the second opposite opening 1604 is connected to a second outlet 1106 on the back surface of the glass substrate 1.
In the stacked package structure, the external circulation pump body makes the cooling liquid introduced into the second inlet 1104 on the back side of the glass substrate 1 from the cooling liquid inlet 1601, flow into the cooling channel in the FCBGA package, finally flow out to the second outlet 1106 on the back side of the glass substrate 1, and flow out from the cooling liquid outlet 1602, and the flowing channel of the cooling liquid is shown as a red line trend schematic diagram with an arrow in fig. 9.
According to the embodiment, the micro flow channels are formed in the first glass-based interposer 2, the second glass-based interposer 3 and the glass substrate 1, the micro flow channels are communicated and are in direct contact with the back surfaces of all chips through the whole 3D package, the chips at the middle positions of the 3D package are directly subjected to heat dissipation through liquid cooling heat dissipation, and the heat dissipation capacity of the package is improved, so that the chip performance is improved, the chip design and package requirements of high-frequency and high-speed electronic equipment, which are ultrahigh in density and high in heat generation, are met, and the working performance of the high-performance chip is improved.
While only certain embodiments of the present invention have been described, it will be apparent to those skilled in the art that other modifications and improvements can be made without departing from the inventive concept of the present invention.