Disclosure of Invention
The present invention aims to solve at least one of the technical problems in the related art to some extent.
Therefore, a first object of the present invention is to provide a clock generating circuit of an intermediate frequency chip, which is a circuit designed in the intermediate frequency chip, and can directly provide a sampling clock signal and/or a reference clock signal to a baseband chip, so that a plurality of clock generating chips are not required to provide clock signals to an on-chip processor of the baseband chip, thereby reducing the cost and complexity of a clock scheme and improving the performance of an intermediate frequency module.
A second object of the present invention is to provide an intermediate frequency chip.
A third object of the present invention is to provide an intermediate frequency module.
A fourth object of the present invention is to propose a broadband terminal.
To achieve the above object, an embodiment of a first aspect of the present invention provides a clock generation circuit of an intermediate frequency chip, which includes a phase-locked loop configured to generate a first clock signal based on a received reference clock signal, wherein the first clock signal is used for characterizing a clock signal sampled by an analog-to-digital converter of the intermediate frequency chip during a process of converting the analog signal into a digital signal, a first frequency divider is used for dividing the first clock signal to generate a second clock signal, wherein the second clock signal is used for characterizing a sampling clock signal provided by the intermediate frequency chip to a baseband chip, and a multiplexer is used for outputting a target clock signal based on the received reference clock signal and the second clock signal, wherein the target clock signal is at least one of the reference clock signal and the second clock signal.
The clock generation circuit of the intermediate frequency chip comprises a phase-locked loop, a first frequency divider and a multiplexer, wherein the phase-locked loop is used for generating a first clock signal based on a received reference clock signal, the first clock signal is used for representing a clock signal sampled by an analog-to-digital converter controlled by the analog-to-digital converter in the process of converting the analog signal into a digital signal, the first frequency divider is used for dividing the first clock signal to generate a second clock signal, the second clock signal is used for representing a sampling clock signal provided by the intermediate frequency chip to a baseband chip, and the multiplexer is used for outputting a target clock signal based on the received reference clock signal and the second clock signal, and the target clock signal is at least one of the reference clock signal and the second clock signal. Therefore, the clock generating circuit is a circuit designed in the intermediate frequency chip, and can directly provide sampling clock signals and/or reference clock signals for the baseband chip, so that a plurality of clock generating chips are not needed to provide clock signals for an on-chip processor of the baseband chip, and the cost and the complexity of a clock scheme are reduced.
In addition, the clock generating circuit of the intermediate frequency chip provided by the embodiment of the first aspect of the present invention may further have the following additional technical features:
according to one embodiment of the invention, the phase-locked loop comprises a phase detector, a charge pump, a loop filter, a voltage controlled oscillator, a second frequency divider and a third frequency divider which are connected in sequence,
The first clock signal is a clock signal generated by dividing an output signal of the voltage controlled oscillator by the second frequency divider.
According to one embodiment of the present invention, in response to the communication interface of the baseband chip requiring a synchronous clock signal, the clock generation circuit of the intermediate frequency chip further includes:
And the fourth frequency divider is used for dividing the output signal of the voltage control oscillator to generate a third clock signal, wherein the third clock signal is used for representing a synchronous clock signal required by a communication interface of the baseband chip.
According to an embodiment of the invention, the phase locked loop further comprises:
and the buffer is used for buffering the output signal of the voltage control oscillator.
According to one embodiment of the invention, the frequency division ratio of the first frequency divider is an oversampling ratio or decimation multiple of the analog-to-digital converter.
According to one embodiment of the invention, the frequency of the second clock signal is in a multiple relationship with a common divisor of the receive data rate and the transmit data rate in response to the receive data rate and the transmit data rate of the intermediate frequency chip being different.
In order to achieve the above object, a second aspect of the present invention provides an intermediate frequency chip, which includes a clock generating circuit of the intermediate frequency chip.
According to the intermediate frequency chip provided by the embodiment of the invention, the clock generation circuit of the intermediate frequency chip is included, and the clock generation circuit can directly provide sampling clock signals and/or reference clock signals for the baseband chip, so that a plurality of clock generation chips are not needed to provide clock signals for an on-chip processor of the baseband chip, the cost and complexity of a clock scheme are reduced, and the performance of an intermediate frequency module is improved.
In order to achieve the above object, an embodiment of a third aspect of the present invention provides an intermediate frequency module, which includes an oscillator, a power divider, a baseband chip, and the intermediate frequency chip, wherein,
The power divider is used for dividing a clock signal output by the oscillator into a reference clock signal and a working clock signal;
The intermediate frequency chip is used for generating the target clock signal based on the reference clock signal;
The baseband chip is used for receiving the working clock signal and the target clock signal.
The intermediate frequency module comprises an oscillator, a power divider, a baseband chip and the intermediate frequency chip, wherein the power divider is used for dividing a clock signal output by the oscillator into a reference clock signal and a working clock signal, the intermediate frequency chip is used for generating a target clock signal based on the reference clock signal, and the baseband chip is used for receiving the working clock signal and the target clock signal. The clock generating circuit is designed in the intermediate frequency chip, and can directly provide sampling clock signals and/or reference clock signals for the baseband chip, so that a plurality of clock generating chips are not needed to provide clock signals for an on-chip processor of the baseband chip, the cost and the complexity of a clock scheme are reduced, and the performance of an intermediate frequency module is improved.
In addition, the intermediate frequency module provided by the embodiment of the third aspect of the present invention may further have the following additional technical features:
According to one embodiment of the present invention, the working clock signal and the target clock signal are not in an integer ratio and the baseband chip is not provided with a phase-locked loop, and the intermediate frequency module further includes:
And the clock generation chip is used for generating the working clock signal required by the baseband chip based on the working clock signal output by the power divider.
In order to achieve the above object, a fourth aspect of the present invention provides a broadband terminal, which includes an intermediate frequency module as described above.
According to the broadband terminal provided by the embodiment of the invention, through the use of the intermediate frequency module, the clock generating circuit on the clock chip can directly provide the sampling clock signal and/or the reference clock signal for the baseband chip, so that a plurality of clock generating chips are not needed to provide clock signals for an on-chip processor of the baseband chip, the cost and the complexity of a clock scheme are reduced, and the performance of the intermediate frequency module is improved.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative and intended to explain the present invention and should not be construed as limiting the invention.
An intermediate frequency chip, a clock generation circuit thereof, an intermediate frequency module and a broadband terminal according to an embodiment of the present invention are described below with reference to the accompanying drawings.
Before describing the clock generation circuit of the intermediate frequency chip in the embodiment of the invention, a clock scheme between the intermediate frequency chip and the baseband chip in the related art is described.
In the related art, an intermediate frequency module of a satellite internet broadband terminal mainly includes an intermediate frequency chip and a baseband chip, wherein the baseband chip often needs a plurality of clock generating chips, such as a clock generating chip 1 and a clock generating chip 2, to provide clock signals required by an on-chip processor. As shown in fig. 1, in the related art, an OCXO (Oven-controlled Crystal Oscillator, constant temperature crystal oscillator) with excellent phase noise performance is used to output a reference clock signal, and after passing through a power divider, one path is sent to a clock generating chip 1 to generate an operating clock signal CLK required by a processor on a baseband chip, and the other path is sent to a clock generating and distributing chip 2 to generate clock signals related to interface waveforms, such as a sampling clock signal SAMPLING RATE and a synchronizing clock signal SYSREF.
The clock scheme in the related art needs additional clock generation chips, and is complex, and has the defects that firstly, the clock generation chips with insufficient integration level and excellent phase noise performance are high in price, so that the cost of a broadband terminal is difficult to reduce, secondly, the number of the clock generation chips is large, stray is easily introduced into the broadband terminal to influence the quality of an analog signal, thirdly, if the broadband terminal adopts baseband chips with different types, the working frequency is different, other clock schemes are needed, and the difficulty of system debugging and system type is increased.
Therefore, the invention provides a clock generating circuit of an intermediate frequency chip, which is a circuit designed in the intermediate frequency chip, and can directly provide sampling clock signals and/or reference clock signals for a baseband chip, so that a plurality of clock generating chips are not needed to provide clock signals for an on-chip processor of the baseband chip, and the cost and complexity of a clock scheme are reduced.
Fig. 2 is a schematic diagram of a clock generation circuit of an intermediate frequency chip according to an embodiment of the invention.
As shown in fig. 2, the clock generation circuit of the intermediate frequency chip according to the embodiment of the invention comprises a phase-locked loop PLL, a first frequency divider/N3 and a multiplexer MUX.
The phase-locked loop PLL is configured to generate a first clock signal fs_ad based on the received reference clock signal fref, where the first clock signal fs_ad is used to characterize a clock signal of the analog-to-digital converter in the intermediate frequency chip, and the clock signal controls sampling of the analog-to-digital converter in the process of converting the analog signal into the digital signal. The first frequency divider/N3 is configured to divide the first clock signal fs_ad to generate a second clock signal, where the second clock signal is configured to characterize a sampling clock signal provided by the intermediate frequency chip to the baseband chip. The multiplexer MUX is configured to output a target clock signal Data CLK based on the received reference clock signal fref and the second clock signal, wherein the target clock signal Data CLK is at least one of the reference clock signal fref and the second clock signal.
Wherein the frequency division ratio of the first frequency divider (/ N3) is the oversampling ratio or decimation multiple of the analog-to-digital converter. If the intermediate frequency chip is applied to the satellite internet, the receiving data rate and the transmitting data rate of the intermediate frequency chip are different, and the frequency of the second clock signal is in a multiple relationship with the common divisor of the receiving data rate and the transmitting data rate.
In the present invention, the multiplexer MUX may selectively output the reference clock signal fref and/or the second clock signal according to the need. For example, the multiplexer MUX may be arranged to select the output reference clock signal and/or the sampling clock signal in dependence on the control signal, wherein the control signal may be arranged to select the reference clock signal fref as output when the reference clock signal fref is required, the control signal may be arranged to select the sampling clock signal as output when the sampling clock signal is required, and wherein a multiplexer having a plurality of inputs and a plurality of outputs may be used when the reference clock signal fref and a replica sampling clock signal are required to be output simultaneously, wherein the reference clock signal fref and the replica sampling clock signal are simultaneously connected to the inputs of the multiplexer, and wherein the control signal is arranged to simultaneously select the two input signals as output.
It should be noted that the selection of the multiplexer MUX depends on the specific application and system architecture, and various factors, such as the frequency, stability, synchronization, etc., of the clock signal need to be considered when designing and constructing the analog signal processing system, and the multiplexer MUX suitable for the system needs to be selected.
Therefore, the clock generating circuit is a circuit designed in the intermediate frequency chip, and can directly provide sampling clock signals and/or reference clock signals for the baseband chip, so that a plurality of clock generating chips are not needed to provide clock signals for an on-chip processor of the baseband chip, and the cost and the complexity of a clock scheme are reduced.
The clock generation circuit of the intermediate frequency chip of the present invention will be described in detail with reference to fig. 3.
As shown in fig. 3, the PLL according to the embodiment of the present invention includes a phase detector PDF, a charge pump CP, a loop filter LPF, a voltage controlled oscillator VCO, a second frequency divider/N1, and a third frequency divider/N2, which are sequentially connected, where the first clock signal is a clock signal generated by dividing an output signal fvco of the voltage controlled oscillator VCO by the second frequency divider.
The first input end and the second input end of the frequency discriminator PDF are input with the reference clock signal fref and the clock signal generated after being distributed by the third frequency divider/N2, the frequency discriminator PDF outputs a group of phase difference signals to be transmitted to the charge pump CP, then the charge pump CP outputs charging or discharging current to the loop filter LPF, a control voltage is generated through the low-pass filtering action of the loop filter LPF, and finally the control voltage modulates the output frequency of the voltage-controlled oscillator VCO to generate a final output signal fvco.
As shown in fig. 3, when the communication interface of the baseband chip, such as the high-speed interface, needs a synchronous clock signal (the synchronous clock signal is used for establishing a chain and measuring delay of the communication interface), the clock generating circuit of the intermediate frequency chip further comprises a fourth frequency divider/N4 for dividing the output signal fvco of the voltage control oscillator VCO to generate a third clock signal SYSREF, wherein the third clock signal SYSREF is used for characterizing a synchronous clock signal SYSREF needed by the communication interface of the baseband chip, and the synchronous clock signal SYSREF can be a periodic pulse signal, a single pulse signal or a multi-pulse signal.
It should be noted that, the output frequency of the first frequency divider/N3 is the data rate of the intermediate frequency signal, and the output frequency of the fourth frequency divider/N4 is the parallel computing processing frequency of the intermediate frequency chip, and the two are also usually in an integer multiple relationship.
As shown in fig. 3, the phase locked loop PLL further comprises a Buffer for buffering the output signal of the voltage controlled oscillator VCO.
In the embodiment of the invention, corresponding clock generating circuits are added on an analog circuit and a digital circuit in an intermediate frequency chip, wherein a phase-locked loop (integer phase-locked loop) is formed by a phase discriminator PDF, a charge pump CP, a loop filter LPF, a voltage control oscillator VCO, a Buffer, a second frequency divider/N1 and a third frequency divider/N2, a first clock signal Fs_AD is a sampling clock signal of an analog-to-digital converter, is one of loop clocks of the phase-locked loop and is in phase synchronization with a reference clock signal fref. The VCO output frequency fvco can generate the sampling clock signal required by the baseband chip after passing through the second divider/N1 and the first divider/N3, where N3 is the oversampling rate of the analog-to-digital converter and is also equal to the decimation multiple of the analog-to-digital converter. The first frequency divider/N3 and the reference clock signal fref can select the output sampling clock signal or the reference clock signal fref through the multiplexer MUX to adapt to different baseband chips. The other way, the VCO output frequency fvco of the voltage controlled oscillator generates the clock required by the interface only by the fourth frequency divider/N4, the clock frequency is the processing frequency of the parallel clock of the intermediate frequency chip signal, which is generally named pclk, the interface rate can be generated through 40 times of frequency multiplication, the clock frequency is supplied to the JESD204B PCS protocol layer to generate a multi-frame clock signal, which is generally an integer multiple of the synchronous clock signal SYSREF, and the clock frequency is only generated after the synchronization of the high-speed serial port, so that the clock generation module of the synchronous clock signal SYSREF needs to have two characteristics that the clock frequency is divided to obtain proper frequency and can be matched with a baseband chip, and the clock generation module also has the capabilities of multifunction, output after being started, optional non-output, one or more pulse output, periodic output, triggering output by other control signals and the like.
Fig. 4 is a schematic diagram of a clocking scheme between an intermediate frequency chip and a baseband chip according to one embodiment of the invention.
As shown in fig. 4, the intermediate frequency module of the present invention includes an oscillator OCXO, a power divider, a baseband chip and the intermediate frequency chip, wherein the power divider is configured to divide a clock signal output by the oscillator OCXO into a reference clock signal fref and a working clock signal CLK, the intermediate frequency chip is configured to generate a target clock signal Data CLK based on the reference clock signal fref, and the baseband chip is configured to receive the working clock signal CLK and the target clock signal Data CLK.
Assuming that the intermediate frequency chip is applied to the satellite internet, the synchronous clock signal required by the baseband chip of the satellite internet is used for the communication interface to build a chain and measure delay, the clock generating circuit of the intermediate frequency chip also generates the third clock signal SYSREF, so that the clock signals which can be received by the baseband chip at this time include a working clock signal CLK, a target clock signal Data CLK and the third clock signal SYSREF.
In one embodiment of the present invention, as shown in fig. 5, if the working clock signal CLK and the target clock signal Data CLK are not in an integer ratio and the baseband chip is not provided with a phase locked loop, the intermediate frequency module further includes a clock generating chip for generating the working clock signal CLK required by the baseband chip based on the working clock signal output from the power divider.
Therefore, the clock scheme between the intermediate frequency chip and the baseband chip can save at least one clock generation chip, the system integration level is improved, the design is more convenient, and the system reduces the clock sources possibly introducing strays, so that the dynamic performance of a receiving and transmitting link is improved.
The clock generation circuit of the intermediate frequency chip comprises a phase-locked loop, a first frequency divider and a multiplexer, wherein the phase-locked loop is used for generating a first clock signal based on a received reference clock signal, the first clock signal is used for representing a clock signal sampled by an analog-to-digital converter controlled by the analog-to-digital converter in the process of converting the analog signal into a digital signal, the first frequency divider is used for dividing the first clock signal to generate a second clock signal, the second clock signal is used for representing a sampling clock signal provided by the intermediate frequency chip to a baseband chip, and the multiplexer is used for outputting a target clock signal based on the received reference clock signal and the second clock signal, and the target clock signal is at least one of the reference clock signal and the second clock signal. Therefore, the clock generating circuit is a circuit designed in the intermediate frequency chip, and can directly provide sampling clock signals and/or reference clock signals for the baseband chip, so that a plurality of clock generating chips are not needed to provide clock signals for an on-chip processor of the baseband chip, the cost and the complexity of a clock scheme are reduced, and the performance of an intermediate frequency module is improved.
Based on the embodiment, the invention also provides an intermediate frequency chip.
The intermediate frequency chip comprises the clock generating circuit of the intermediate frequency chip.
According to the intermediate frequency chip provided by the embodiment of the invention, the clock generation circuit of the intermediate frequency chip is included, and the clock generation circuit can directly provide sampling clock signals and/or reference clock signals for the baseband chip, so that a plurality of clock generation chips are not needed to provide clock signals for an on-chip processor of the baseband chip, the cost and complexity of a clock scheme are reduced, and the performance of an intermediate frequency module is improved.
Based on the above embodiment, the invention further provides an intermediate frequency module.
As shown in fig. 4, the intermediate frequency module of the embodiment of the invention comprises an oscillator OCXO, a power divider, a baseband chip and the intermediate frequency chip, wherein,
The power divider is used for dividing a clock signal output by the oscillator OCXO into a reference clock signal and a working clock signal;
the intermediate frequency chip is used for generating a target clock signal based on the reference clock signal;
the baseband chip is used for receiving the working clock signal and the target clock signal.
According to one embodiment of the present invention, if the working clock signal and the target clock signal are not in an integer ratio and the baseband chip is not provided with a phase-locked loop, the intermediate frequency module further includes, as shown in fig. 5:
And the clock generation chip is used for generating the working clock signal required by the baseband chip based on the working clock signal output by the power divider.
It should be noted that, for details not disclosed in the intermediate frequency module in the embodiment of the present invention, please refer to details disclosed in the clock generation circuit of the intermediate frequency chip in the embodiment of the present invention, and detailed descriptions thereof are omitted herein.
The intermediate frequency module comprises an oscillator, a power divider, a baseband chip and the intermediate frequency chip, wherein the power divider is used for dividing a clock signal output by the oscillator into a reference clock signal and a working clock signal, the intermediate frequency chip is used for generating a target clock signal based on the reference clock signal, and the baseband chip is used for receiving the working clock signal and the target clock signal. The clock generating circuit is designed in the intermediate frequency chip, and can directly provide sampling clock signals and/or reference clock signals for the baseband chip, so that a plurality of clock generating chips are not needed to provide clock signals for an on-chip processor of the baseband chip, the cost and the complexity of a clock scheme are reduced, and the performance of an intermediate frequency module is improved.
Based on the above embodiment, the invention also provides a broadband terminal.
The broadband terminal provided by the embodiment of the invention comprises the intermediate frequency module.
According to the broadband terminal provided by the embodiment of the invention, through the use of the intermediate frequency module, the clock generating circuit on the clock chip can directly provide the sampling clock signal and/or the reference clock signal for the baseband chip, so that a plurality of clock generating chips are not needed to provide clock signals for an on-chip processor of the baseband chip, the cost and the complexity of a clock scheme are reduced, and the performance of the intermediate frequency module is improved.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
In addition, the terms "first," "second," are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
In addition, each functional unit in the embodiments of the present invention may be integrated in one processing module, or each unit may exist alone physically, or two or more units may be integrated in one module. The integrated modules may be implemented in hardware or in software functional modules. The integrated modules may also be stored in a computer readable storage medium if implemented as software functional modules and sold or used as a stand-alone product.