Disclosure of Invention
The invention aims to solve the problem of the prior MCU power management unit realization technology, and provides a power management unit realized by an asynchronous circuit so as to effectively reduce the power consumption and the area cost and shorten the response time of waking up from a low power consumption mode.
The invention provides the following technical scheme:
The invention provides a low-power consumption MCU power management unit realized by using an asynchronous circuit, which is called PMU for short, wherein the MCU comprises LDO, HSI, ISO, VCORE domains and HSION registers;
the PMU comprises an isolation control module, a power-on control module and a delay wake-up module;
the isolation control module outputs an Iso_on to the ISO as an enabling signal of the ISO;
The isolation control module is configured to:
When the Por_ rstn _dly is in a power-on reset state or the Iso_clamp is in an active state, the Iso_on is in an active state, wherein the Por_ rstn _dly is a Por_ rstn which is released in a delayed manner, the Por_ rstn is a power-on reset signal, the Iso_clamp is a signal obtained by delaying a standby_en through a delay chain, and the standby_en is a low-power-consumption mode switching enabling signal;
When the first condition is changed from the unsatisfied state to the satisfied state, after the delay chain is delayed, the Iso_on is set to be in an invalid state, the content of the first condition is that Port_ rstn _dly is in a reset release state and standby_ rstn is in an invalid state, wherein standby_ rstn is a VCORE domain reset signal, and when standby_ rstn is valid, the VCORE domain is reset;
the power-on control module outputs Ldo _on to the LDO as an enabling signal of the LDO;
The power-on control module is configured to:
when the Porj rstn _dly is in a power-on reset state or a wake-up condition is met, ldo _on is set to be in an active state, wherein the wake-up condition comprises that a wake-up flag signal Stdby_ wkup _src is in an active state, and Ldo _on_dly is Ldo _on after delay by a delay chain;
When the Iso_on_dly is changed from invalid to valid, ldo _on is set to an invalid state, wherein the Iso_on_dly is the Iso_on after being delayed by a delay chain;
The delay wake-up module outputs standby_ rstn;
The delayed wakeup module is configured to:
When Port_ rstn _dly is in a power-on reset state, standby_ rstn is set to an invalid state;
When the wake-up condition is changed from unsatisfied to satisfied, standby_ rstn is set to an active state, and when a preset wake-up time is delayed, standby_ rstn is set to an inactive state.
According to the scheme, the core circuit of the invention completes all time sequence control by using a plurality of delay chains, is independent of a clock, reduces the dynamic power consumption of the PMU, and has simpler structure compared with the PMU circuit realized by a state machine. Compared with the PMU realized by a state machine, which needs to wait for the clock to be stable and then start to work, the invention starts to work after the wake-up mark is valid, thereby effectively shortening the wake-up response time of the chip.
Further, when the enabling signals sent to the HSI by the LDO and HSION registers are valid, the HSI is started, otherwise, the HSI is closed;
The external wiring of the PMU is configured to:
When the port_ rstn _dly is in a power-on reset state or the standby_ rstn is in an active state, the VCORE domain is reset, and the HSION register is reset, so that an enable signal sent to the HSI by the HSION register is set to be active.
The scheme indirectly controls the HSI clock source to enable by controlling the LDO to enable and the standby_ rstn, so that the HSI can be controlled by hardware, and the control of software on the HSI is not influenced.
Further, when the time delay wake-up module delays a preset wake-up time, the clock signal Hsi_clk generated by the HSI is used for timing.
The scheme uses the clock signal Hsi_clk to clock, thereby ensuring that the VCORE domain reset is released after the HSI clock is stable.
Further, the wake-up condition further includes Ldo _on_dly being in an inactive state.
The scheme shields the wake-up mark signal before the end of the power-off flow (Ldo _on_dly is not changed into an invalid state), and avoids the circuit from being awakened by mistake.
Further, the isolation control module comprises a DFF trigger ISO_ON and a delay chain;
The data input end D of the ISO_ON is constant to be 1, and the positive output end Q is connected with the Iso_ON;
Delaying the standby_en by using a delay chain to obtain an Iso_clamp, performing logical OR operation ON the Iso_clamp and the inverted Por_ rstn _dly, and then accessing the Iso_clamp and the inverted Por_ rstn _dly to an ISO_ON high-level effective reset input end;
After carrying out logical AND operation ON Por_ rstn _dly and standby_ rstn, accessing a rising edge trigger clock input end of ISO_ON after a delay chain delays an operation result;
the iso_on and standby_ rstn are low-level active, standby_en is high-level active, the Por_ rstn _dly power-ON reset state is low-level, and the reset release state is high-level;
further, the power-ON control module comprises a DFF trigger LDO_ON and a delay chain;
The data input end D of LDO_ON is constant at 1, and the inverting output end QN is connected with Ldo _on;
The falling edge of the LDO_ON is connected to the clock input end after the delay chain is used for delaying the Iso_on;
After carrying out time delay ON Ldo _on by using a time delay chain, obtaining Ldo _on_dly, carrying out logical AND operation ON the inverted Ldo _on_dly and Stdby_ wkup _src to obtain Ldo _on_set, carrying out logical AND operation ON the inverted Ldo _on_set and Por_ rstn _dly, and accessing the low-level effective reset input end of LDO_ON;
The reset control circuit comprises a reset control circuit, a reset control circuit and a reset control circuit, wherein Ldo _on and Stdby_ wkup _src are high-level effective, iso_on is low-level effective, por_ rstn _dly is powered ON and reset, and a reset release state is high-level;
further, the delay wake-up module comprises a DFF trigger LDO_HSI_ON, a counter standby_ rstn _cnt, a comparator and a delay chain;
The data input end D of LDO_HSI_ON is constant at 1, the positive output end Q is connected with Ldo _hsi_on, and the reverse output end QN is connected with standby_ rstn; the method comprises the steps of using a result of Ldo _on_dly inverted and Stdby_ wkup _src to carry out logic AND operation, accessing a rising edge trigger input end of LDO_HSI_ON, wherein Ldo _on_dly is Ldo _on after delay of a delay chain, ldo _hsi_on is enabled input end of a standby_ rstn _cnt after synchronization, using a clock signal Hsi_clk generated by HSI to access the rising edge trigger clock input end of standby_ rstn _cnt, using a count value Hsi_cnt generated by standby_ rstn _cnt to connect the input end of a comparator, and using an output end of the comparator to connect Hsi_cnt signal, when Hsi_cnt is equal to a set threshold value n, hsi_stat is set 1, otherwise, hsi_stat is set 0;
the standby_ rstn is active low, ldo _hsi_on, ldo_on and Stdby_ wkup _src are active high, the Por_ rstn _dly power-ON reset state is active low, the reset release state is active high, and when the LDO_HSI_ON is reset, ldo _hsi_on is set to 0 and standby_rstn is set to 1.
The invention realizes isolation unit control, regulated power supply control, HSI clock control and VCORE domain reset control asynchronously through the trigger and a series of delay chains. Compared with a PMU realized based on a state machine, the PMU is designed in a fully asynchronous mode, a clock is not needed during operation, the dynamic power consumption of the PMU is reduced, and the power consumption required for maintaining the clock to run in a low power consumption mode is saved. Compared with the PMU realized by a state machine, which needs to wait for the clock to be stable and then start to work, the invention starts to work after the wake-up mark is valid, thereby effectively shortening the wake-up response time of the chip. From a circuit scale, the core circuit of the invention only uses 3 triggers, 1 counter and a plurality of delay chains to complete all time sequence control, and compared with a PMU circuit structure realized by a state machine, the PMU circuit structure is simpler. The invention can reset and release the VCORE domain during wake-up, and automatically reset the internal counter after wake-up without software reset. The invention indirectly controls the HSI clock source to enable by controlling the LDO to enable and the standby_ rstn, thereby realizing the control of the HSI through hardware and not affecting the control of the HSI by software. Finally, the invention can shield the wake-up sign signal before the end of the power-off process, thereby avoiding the circuit from being awakened by mistake.
Detailed Description
In order to make the objects, features and advantages of the present invention more obvious and understandable, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is apparent that the embodiments described below are only some embodiments of the present invention, not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
A low-power consumption MCU power management unit realized by an asynchronous circuit is abbreviated as PMU, wherein the MCU comprises an LDO (linear stabilized power supply), an HSI (high-speed internal oscillator), an ISO (isolation unit), a VCORE domain and a HSION register, wherein an output signal of the VCORE domain is output to other modules after passing through the ISO;
the PMU comprises an isolation control module, a power-on control module and a delay wake-up module;
the isolation control module outputs an Iso_on to the ISO as an enabling signal of the ISO;
The isolation control module is configured to:
When the Por_ rstn _dly is in a power-on reset state or the Iso_clamp is in an active state, the Iso_on is in an active state, wherein the Por_ rstn _dly is a Por_ rstn which is released in a delayed manner, the Por_ rstn is a power-on reset signal, the Iso_clamp is a signal obtained by delaying a standby_en through a delay chain, and the standby_en is a low-power-consumption mode switching enabling signal;
When the first condition is changed from the unsatisfied state to the satisfied state, after the delay chain is delayed, the Iso_on is set to be in an invalid state, the content of the first condition is that Port_ rstn _dly is in a reset release state and standby_ rstn is in an invalid state, wherein standby_ rstn is a VCORE domain reset signal, and when standby_ rstn is valid, the VCORE domain is reset;
the power-on control module outputs Ldo _on to the LDO as an enabling signal of the LDO;
The power-on control module is configured to:
when the Porj rstn _dly is in a power-on reset state or a wake-up condition is met, ldo _on is set to be in an active state, wherein the wake-up condition comprises a wake-up flag signal Stdby_ wkup _src being in an active state and Ldo _on_dly being in an inactive state, and Ldo _on_dly being Ldo _on after delay by a delay chain;
When the Iso_on_dly is changed from invalid to valid, ldo _on is set to an invalid state, wherein the Iso_on_dly is the Iso_on after being delayed by a delay chain;
The delay wake-up module outputs standby_ rstn;
The delayed wakeup module is configured to:
When Port_ rstn _dly is in a power-on reset state, standby_ rstn is set to an invalid state;
When the wake-up condition is changed from unsatisfied to satisfied, setting standby_ rstn to be in an effective state, and setting standby_ rstn to be in an ineffective state when delaying a preset wake-up time;
The external wiring of the PMU is configured to:
When the port_ rstn _dly is in a power-on reset state or the standby_ rstn is in an active state, the VCORE domain is reset, and the HSION register is reset, so that an enable signal sent to the HSI by the HSION register is set to be active.
More specific embodiments are described below:
The PMU is located in a 3.3V digital normally-open power domain of the MCU, the power domain is powered by a chip power pin, and power is kept when the MCU enters a low-power mode.
The VCORE domain is located in a 1.1V digital power-down domain, comprises an MCU core, a bus and various 1.1V digital peripherals, and is powered off when the chip enters a low-power consumption mode.
The circuit architecture of the PMU is shown in FIG. 1, and consists of 3 DFF triggers (ISO_ON, LDO_ON, LDO_HSI_ON), 1 counter (standby_ rstn _cnt), 1 digital Comparator (COMP), 5 groups of delay chains, a plurality of logic gates and a synchronizer. The PMU completes asynchronous power-on and power-off time sequence control through 5 groups of delay chains, and a clock is not needed. The counter counts with clock signal hsi_clk to release VCORE domain reset after Hsi clock has stabilized.
The PMU controls the enabling signals Iso_on and Ldo _on of the ISO and LDO to be set to 0 when the chip enters the low power mode, controls Ldo _on to be set to 1 when the chip exits the low power mode, controls the VCORE domain reset signal standby_ rstn to be set to 0 and to be set to 1 after a period of time, and finally controls the Iso_on to be set to 1 to remove isolation from the VCORE domain.
The Iso_on is an active low ISO enable signal, isolates output signals of all VCORE domains when Iso_on is 0, and de-isolates the VCORE domains when Iso_on is 1.
The Ldo _on is an active high LDO enable signal, which enables the LDO to resume power to the VCORE domain when Ldo _on is 1, and disables the LDO to power down the VCORE domain when Ldo _on is 0.
The standby_ rstn is an active-low VCORE domain reset signal, resets the VCORE domain when standby_ rstn is 0, and releases the VCORE domain reset when standby_ rstn is 1.
The circuit connection relationship of the PMU is shown in FIG. 1, and Por_ rstn _dly and standby_ rstn are connected to the rising edge trigger clock input end of the ISO_ON trigger after the Iso_Release_in is obtained and is delayed by a group of delay chains. The standby_en signal is delayed by a set of delay chains to obtain an iso_clamp, an iso_clamp and an inverted port_ rstn _dly or to obtain an iso_on_rst, which is connected to the high-level active reset input of the iso_on flip-flop. The data input terminal D of the ISO_ON trigger is constant to be 1, and the positive output terminal Q is connected with Iso_on. Iso_on is obtained after a group of delay chains and is input to the falling edge trigger clock input end of the LDO_ON trigger. The data input end D of LDO_ON is constant at 1, and the inverted output end QN is connected with Ldo _on to control the enabling of the 1.1V regulated power supply. Ldo _on goes through a set of delay chains to obtain Ldo _on_dly, ldo _on_dly, inverted and wake-up flag signal stdby_ wkup _src and Ldo _on_set. Ldo _on_set is inverted and summed with por_ rstn _dly to obtain an active low reset input signal Ldo _on_ rstn for the LDO_ON flip-flop. Ldo _on_set is simultaneously connected with the rising edge trigger clock input end of the LDO_HSI_ON trigger, and the data input end D of the LDO_HSI_ON trigger is constant to be 1. The positive output end Q of the LDO_HSI_ON trigger is connected with Ldo _Hsi_on and Ldo _Hsi_on, the positive output end Q of the LDO_HSI_ON trigger is synchronized to an HSI clock through a two-stage synchronizer and then is used as an enabling signal of a standby_ rstn _cnt counter, the inverted output end QN of the LDO_HSI_ON trigger is connected with a standby_ rstn signal, and the VCORE domain is reset when the signal is 0. The rising edge of the standby_ rstn _cnt counter triggers the clock input to connect to hsi_clk, and when the enable signal EN of the standby_ rstn _cnt counter is 1, the hsi_clk starts to be counted up. The count value Hsi_cnt output by the standby_ rstn _cnt is connected with the input end of the comparator, and the output end of the comparator is connected with the Hsi_stable signal. When Hsi_cnt is equal to the set threshold value n, hsi_stable is set to 1, otherwise Hsi_stable is set to 0.Hsi_stable is delayed by a group of delay chains to obtain Hsi_stable_dly, after the Hsi_stable_dly is inverted, and Por_ rstn _dly and obtain a low-level effective reset input end of Ldo _hsi_on_ rstn, ldo _hsi_on_ rstn input LDO_HSI_ON trigger and a low-level effective reset input end of Ldo _hsi_on_ rstn input standby_ rstn _cnt.
The peripheral circuitry of the PMU is shown in FIG. 2, port_ rstn _dly and standby_ rstn and the active low reset input connected to the HSION register and the VCORE domain, the output of the HSION register being Hsi_on, the reset value being 1, i.e., active. HSION registers are configurable by software. Ldo _on is connected to the enabling end of the LDO of the regulated power supply, when the output voltage of the LDO reaches a threshold value of 10us, an enabling signal VCORE_OK_HV sent by the LDO to the HSI is set to be 1, namely, the active state is achieved, and the VCORE_OK_HV and Hsi_on are obtained after being phase-separated, and then En_hsi is input to the enabling end of the HSI clock source. HSI starts to operate when en_hsi is 1, and outputs clock hsi_clk, otherwise clock output is disabled. The standby_en signal output by the VCORE domain when 1 indicates that the PMU is enabled to enter a low power mode. The output signal of the VCORE domain is output to other modules after passing through the ISO isolation unit, and the isolation unit is effective when the Iso_on is in a low level. The APB bus of the VCORE domain output is connected to HSION registers after ISO for configuration HSION registers.
As shown in fig. 3, the control flow of the PMU in this embodiment is described as follows:
1) Port_ rstn _dly is Port_ rstn that is released with a delay through Hsi_clk clock counting. Port_ rstn is a power-on reset signal. The Por_ rstn _dly power-on reset state defaults to low and resets all flip-flops, counters of the PMU, where Iso_on and Hsi_cnt reset to 0, ldo_on and standby_ rstn reset to 1, enabling LDO output and isolating the VCORE domain.
2) After the output voltage of the LDO reaches a threshold of 10us, VCORE_OK_HV is set to 1, enabling the HSI oscillator to generate a clock.
The and state of the port_ rstn _dly and the standby_ rstn is taken as the iso_release_in, and the reset release state of the port_ rstn _dly is high, so that the iso_release_in is set to 1.
3) Iso_Release_in generates Iso_Release through a delay chain, and the rising edge of Iso_Release triggers Iso_on to set 1, and ISO is changed from the enable just powering on to not enable.
4) When the low power consumption mode is entered, a low power consumption mode switching enabling signal standby_en is set to 1, after delay of a delay chain, an Iso_clamp is set to 1, an Iso_clamp high level triggers Iso_on to set to 0, and ISO is enabled to clamp standby_en to 0.
Meanwhile, since the PMU does not depend on a clock signal, the HSI is turned off by passing through the APB bus through the ISO configuration HSION register before the VCORE domain issues the standby_en.
5) After the Iso_on passes through the delay chain, the Iso_on_dly is set to 0, the falling edge of the Iso_on_dly triggers the LDO_ON output Ldo _on to set to 0, and the LDO is turned off, so that the whole power-down process is completed.
6) When the low power mode is exited, the input wake-up flag signal stdby_ wkup _src is set to 1.Ldo _on_dly is Ldo _on generated by a delay chain, and the wake-up condition is met when Ldo _on is 0. Ldo _on_set is set to 1 when Ldo _on_dly is 0 and stdby_ wkup _src is 1.
7) After Ldo _on_set is set to 1, the LDO_ON trigger is reset, ldo _on is set to 1, and the LDO is turned ON. After the LDO output is active, VCORE_OK_HV is set to 1.
Meanwhile, the Ldo _on_set rising edge triggers Ldo _Hsi_on to set 1, an enable counter counts Hsi_clk, the Ldo _on_set rising edge triggers LDO_HSI_ON inverted output end standby_ rstn to set 0, a VCORE domain register is reset, and meanwhile a HSION register is reset, so that Hsi_on is set 1, and an HSI oscillator generates a clock.
8) When the hsi_cnt count value reaches the comparator threshold, hsi_stable is set to 1, and the ldo_hsi_on flip-flop and counter are reset.
9) The ldo_hsi_on trigger reset enables Ldo _hsi_on to stop counting at 0, while standby_ rstn to 1 releases the VCORE domain reset.
10 Iso_release_in will vary with standby_ rstn, and a rising edge will be generated when standby_ rstn is released.
11 After the rising edge of the Iso_Release_in is delayed, the rising edge of the Iso_Release is generated, the Iso_on is triggered to be set to 1, and the whole low-power consumption wake-up process is completed.
The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.