Processing device and related low-power consumption standby control methodTechnical FieldThe present invention relates to the field of chip technologies, and in particular, to a processing apparatus and a related low power consumption standby control method.
BackgroundUnder the condition of limited battery capacity, when terminal equipment such as a smart phone or a smart watch is in a standby state, namely, the terminal equipment is in a state of being started up but does not perform any substantial work (namely, does not operate files and programs), in order to obtain longer standby time, the required standby power consumption is also lower and lower.
In the standby state of the existing terminal device, because the time for recovering the terminal device from the standby state to the normal working state is not suitable to be too long, at least one low-voltage normally open (AO) power domain and high-voltage interface power domain need to be reserved for a System On Chip (SoC) of the terminal device, so as to ensure that part of data or configuration is reserved in the standby state, thereby reducing the power-On recovery time. In this scenario, the standby power consumption of the terminal device mainly includes SoC standby power consumption, and may further include other power consumption such as a memory, a power management unit, and a board level. However, in the practical application process, it is found that after the terminal device enters the standby state, the SoC standby power consumption is higher, and the maximum duty ratio of the SoC standby power consumption can reach more than half of the total power consumption, which greatly shortens the standby time of the terminal device.
Therefore, how to provide a processing apparatus and a related low-power standby control method to reduce standby power consumption, increase standby duration, and improve user experience is a problem to be solved.
Disclosure of Invention
The embodiment of the invention provides a processing device and a related low-power consumption standby control method, which are used for reducing standby power consumption, increasing standby time and improving user experience.
In a first aspect, an embodiment of the present invention provides a processing apparatus, which is characterized in that the processing apparatus includes a power management unit, a system on chip SoC, and an internal memory, where the SoC and the internal memory are coupled to the power management unit, the power management unit supplies power to the SoC through a first power domain and supplies power to the internal memory through a second power domain, the power management unit is configured to receive a first indication sent by the SoC, where the first indication is used to instruct the processing apparatus to enter a standby state, control to disconnect the first power domain, and keep a part or all of power supplies of the second power domain in a power supply state, where the SoC is in a fully powered-down state and a part or all of devices of the internal memory are in a powered-up state after the processing apparatus enters the standby state, and send a first control signal to the internal memory, where the first control signal is used to maintain the internal memory in a first mode, where the internal memory stores currently stored data in the first mode.
In the embodiment of the application, after the processing device enters the standby state, the SoC can control the internal memory to enter the self-refresh mode, then the power management unit takes over part of control signals of the internal memory to maintain the internal memory in the self-refresh state, and then the power management unit can turn off the whole power supply of the SoC, thereby reducing the whole standby power consumption of the processing device. Further, when the processing device is awakened (i.e., the processing device is restored to a normal operating state), since the data in the internal memory is not lost, it is unnecessary to re-read the related data from the external memory to the internal memory (i.e., the processing device does not need to walk to the power-on initialization process again), thereby reducing the power-on restoration time of the processing device. In the prior art, after the processing device enters the standby state, the SoC needs to continuously control and manage the internal memory, that is, the SoC needs to maintain the internal memory in the self-refresh mode, so as to ensure that the data stored in the internal memory is not lost, so that the SoC cannot be completely powered down in the prior art. In summary, in the present application, by improving the power management unit in the processing device, after the processing device enters the standby state, the power management unit can take over the internal memory after the SoC is completely powered down, and maintain the internal memory in the self-refresh mode, thereby not only ensuring that the processing device can recover to the normal working state in a shorter time, but also reducing the standby power consumption of the processing device, increasing the standby time, and improving the user experience.
In one possible implementation manner, the power management unit comprises a state register and a first control module, and is specifically configured to set the state register to a first state after receiving the first instruction sent by the SoC, mask, in the first state, a signal output by the SoC to the internal memory by the first control module, and send the first control signal to the internal memory to maintain the internal memory in the first mode.
In the embodiment of the present application, the power management unit includes a status register and a first control module, and when the power management unit receives a first instruction sent by the SoC, the status register may be set to 1 (i.e. the first state), so as to indicate that the processing apparatus enters a standby state, and then the power management unit may take over the internal memory. In this process, in order to avoid that the signal sent to the internal memory by the SoC through the power management unit is unstable after the SoC is powered down, the control signal sent to the internal memory by the power management unit is disordered, and the self-refresh state of the internal memory is damaged, so that the first control module in the power management unit can mask the signal sent to the internal memory by the SoC (for example, the signal sent to the internal memory by the SoC can be masked before the SoC is completely powered down), the internal memory is completely controlled and managed by the power management unit, and then the first control module of the power management unit can send the first control signal to the internal memory to maintain the internal memory in the self-refresh mode, so that the internal memory can still store the currently stored data when the processing device is in the standby state. In summary, after the processing device enters the standby state, the SoC is in a completely powered-down state, and the internal memory can still retain the currently stored data, so that the processing device can be ensured to be in a normal working state in a shorter time, the standby power consumption of the processing device is reduced, the standby time is prolonged, and the user experience is improved.
In one possible implementation, the internal memory is configured to receive the first control signal sent by the power management unit and maintain the first mode to save currently stored data.
In the embodiment of the application, after the power management unit takes over the internal memory, the power management unit can control and manage the state of the internal memory. Therefore, when the internal memory receives the first control signal sent by the power management unit, the self-refresh mode (i.e. the first mode) can be maintained, that is, the internal memory continuously refreshes the currently stored data, so that the internal memory can still retain the currently stored data after the processing device enters the standby state. In summary, after the processing device enters the standby state, the SoC is in a completely powered-down state, and the internal memory can still retain the currently stored data, so that the processing device can be ensured to be in a normal working state in a shorter time, the standby power consumption of the processing device is reduced, the standby time is prolonged, and the user experience is improved.
In one possible implementation manner, the processing device further comprises an external memory, the power management unit is further coupled with the external memory, the power management unit supplies power to the external memory through a third power domain, the power management unit is further used for keeping part or all of power of the third power domain in a power supply state after receiving the first indication sent by the SoC, wherein after the processing device enters the standby state, part or all of devices of the external memory are in a power-on state, and a second control signal is sent to the external memory, and the second control signal is used for maintaining the external memory in a second mode, wherein in the second mode, the external memory keeps current configuration parameters.
In the embodiment of the application, after the power management unit receives the first instruction sent by the SoC, in order to avoid the problem that the current configuration parameters of the external memory are lost after the processing device enters the standby state, the power management unit keeps the third power domain in the power supply state. In order to reduce the power consumption of standby, part of the power domains in the third power domain may be powered down, that is, some or all devices that do not affect the current configuration parameters stored in the external memory may be powered down. Further, after the processing device enters the standby state, the SoC may be powered down and the internal memory and the external memory may be taken over by the power management unit. When the power management unit takes over the external memory, a second control signal may be sent to the external memory to maintain the external memory in the second mode, i.e. the second mode may be understood as a low power consumption mode of the external memory. In the low power mode, the external memory can still retain the current configuration parameters and configuration states. In summary, after the processing device enters the standby state, the SoC is in a completely powered-down state, the internal memory can still retain the currently stored data, and the external memory also retains the current configuration parameters, so that the processing device can be ensured to recover the normal working state in a shorter time, the standby power consumption of the processing device is reduced, the standby time is prolonged, and the user experience is improved.
In one possible implementation manner, the power management unit further comprises a second control module, and when the status register is set to the first state, the power management unit is specifically configured to mask, by the second control module, a signal output by the SoC to the external memory, and send the second control signal to the external memory, so as to maintain the external memory in the second mode.
In the embodiment of the application, the power management unit may further include a second control module in addition to the multiple power domains, the first control module and the status register. When the power management unit receives the first instruction sent by the SoC, the status register may be set to 1 (i.e. the first state), so that the processing device may be indicated to enter the standby state, and then the power management unit may take over the external memory. In this process, in order to avoid that the signal sent to the external memory by the SoC through the power management unit is unstable after the SoC is powered down, which causes that the signal sent to the external memory by the power management unit is disordered, the second control module in the power management unit shields the signal sent to the external memory by the SoC, and the power management unit completely controls and manages the external memory, so that the second control module of the power management unit sends the second control signal to the external memory, so that the external memory can be maintained in a low power consumption mode, and the external memory still can store the current configuration parameters and the current configuration state when the processing device is in a standby state. In summary, after the processing device enters the standby state, the SoC is in a completely powered-down state, the internal memory can still retain the currently stored data, and the external memory also retains the current configuration parameters, so that the processing device can be ensured to recover the normal working state in a shorter time, the standby power consumption of the processing device is reduced, the standby time is prolonged, and the user experience is improved.
In one possible implementation, the external memory is configured to receive the second control signal sent by the power management unit and maintain the second mode to preserve the current configuration parameters.
In the embodiment of the application, after the power management unit takes over the external memory, the power management unit can control and manage the state of the external memory. Therefore, when the external memory receives the second control signal sent by the power management unit, the external memory can be maintained in the low power consumption mode (second mode), that is, the external memory can still keep the current configuration information and configuration state after the processing device enters the standby state. In summary, after the processing device enters the standby state, the SoC is in a completely powered-down state, the internal memory can still retain the currently stored data, and the external memory also retains the current configuration parameters, so that the processing device can be ensured to recover the normal working state in a shorter time, the standby power consumption of the processing device is reduced, the standby time is prolonged, and the user experience is improved.
In one possible implementation manner, the power management unit is further configured to restore the first power domain and supply power to the SOC after receiving an instruction that the processing device needs to restore an operating state, receive a second instruction sent by the SOC, set the status register to a second state, unmask a signal output by the SOC to the internal memory and forward the signal output by the SOC to the internal memory in the second state, or unmask a signal output by the SOC to the external memory and forward the signal output by the SOC to the external memory.
In the embodiment of the application, after the power management unit receives the instruction of waking up the processing device, the first power domain can be restored and the power for the SoC can be continuously supplied, and after the SoC is powered on, the internal memory and the external memory can be continuously controlled and managed. Further, after the SoC is powered on, a second instruction may be sent to the power management unit, and after the power management unit receives the second instruction, the power management unit may set the status register to a second state (i.e. sr=0), which indicates that the processing apparatus is in a normal working state, or may indicate that the power management unit may not need to continuously control and manage the internal memory and the external memory. Next, the SoC may unmask the control signal from the SoC to the power management unit by controlling the power management unit related logic while transparently transmitting the related control signal to the internal memory and the external memory through the power management unit. Finally, the processing device resumes normal operation. In summary, after the processing device enters the standby state, the SoC is in a completely powered-down state, the internal memory can still retain the currently stored data, and the external memory also retains the current configuration parameters, so that the processing device can be ensured to recover the normal working state in a shorter time, the standby power consumption of the processing device is reduced, the standby time is prolonged, and the user experience is improved.
In one possible implementation, the SoC is configured to determine whether the status register in the power management unit is in the first state after the first power domain is turned on, and if the status register is in the first state, send the second indication to the power management unit.
In the embodiment of the application, after the SoC is powered on again, whether the status register in the power management unit is in the first state can be judged first, if the status register is in the first state, a second instruction can be sent to the power management unit to control the relevant logic of the power management unit to unmask the control signal sent by the SoC to the power management unit, and meanwhile, the SoC can transparently transmit the relevant control signal to the internal memory and the external memory through the power management unit. If the status register is not in the first state, the processing device performs a power-on restart procedure, i.e. the external memory needs to be reconfigured and the required data is read from the external memory to the internal memory again. In summary, after the processing device enters the standby state, the SoC is in a completely powered-down state, the internal memory can still retain the currently stored data, and the external memory also retains the current configuration parameters, so that the processing device can be ensured to recover the normal working state in a shorter time, the standby power consumption of the processing device is reduced, the standby time is prolonged, and the user experience is improved.
In a second aspect, an embodiment of the present invention provides a low-power standby control method, which is applied to a processing device, and is characterized in that the processing device includes a power management unit, a system on chip SoC and an internal memory, where the SoC and the internal memory are coupled to the power management unit, the power management unit supplies power to the SoC through a first power domain and supplies power to the internal memory through a second power domain, the method includes receiving, by the power management unit, a first instruction sent by the SoC, the first instruction being used to instruct the processing device to enter a standby state, controlling, by the power management unit, to disconnect the first power domain and keep a part or all of power supplies of the second power domain in a power supply state, wherein the SoC is in a fully powered-down state and a part or all of devices of the internal memory are in a powered-up state after the processing device enters the standby state, sending, by the power management unit, a first control signal to the internal memory, the first control signal being used to maintain the internal memory in a first mode, wherein the first mode stores current data in the internal memory.
In one possible implementation, the power management unit includes a status register and a first control module, and the sending, by the power management unit, a first control signal to the internal memory includes setting the status register to a first state after receiving the first indication sent by the SoC, and in the first state, masking, by the first control module, a signal output by the SoC to the internal memory, and sending the first control signal to the internal memory to maintain the internal memory in the first mode.
In one possible implementation, the method further includes receiving, by the internal memory, the first control signal sent by the power management unit and maintaining the internal memory in the first mode to save the currently stored data.
In one possible implementation manner, the processing device further comprises an external memory, the power management unit is further coupled with the external memory, the power management unit supplies power to the external memory through a third power domain, the method further comprises the steps of keeping part or all of power supplies of the third power domain in a power supply state after receiving the first indication sent by the SoC through the power management unit, wherein part or all of devices of the external memory are in a power-on state after entering the standby state, and sending a second control signal to the external memory through the power management unit, wherein the second control signal is used for keeping the external memory in a second mode, and the external memory keeps current configuration parameters in the second mode.
In one possible implementation, the power management unit further includes a second control module, and when the status register is set to the first state, the sending, by the power management unit, a second control signal to the external memory includes shielding, by the second control module, a signal output by the SoC to the external memory, and sending the second control signal to the external memory to maintain the external memory in the second mode.
In one possible implementation, the method further includes receiving, by the external memory, the second control signal sent by the power management unit and maintaining the external memory in the second mode to preserve current configuration parameters.
In one possible implementation manner, the method further comprises the steps of recovering the first power domain and supplying power to the SoC through the power management unit after receiving an indication that the processing device needs to recover the working state, receiving a second indication sent by the SoC through the power management unit, setting the state register to be in a second state, unmasking a signal output by the SoC to the internal memory through the power management unit and forwarding the signal output by the SoC to the internal memory, or unmasking the signal output by the SoC to the external memory and forwarding the signal output by the SoC to the external memory.
In one possible implementation, the method further includes determining, by the SoC, whether the status register in the power management unit is in the first state after switching on the first power domain, and if the status register is in the first state, sending, by the SoC, the second indication to the power management unit.
In a third aspect, the present application provides a terminal device having a function of implementing any one of the above low power consumption standby control methods. The functions can be realized by hardware, and can also be realized by executing corresponding software by hardware. The hardware or software includes one or more modules corresponding to the functions described above.
In a fourth aspect, an embodiment of the present invention provides a computer program including instructions which, when executed by a computer, cause the computer to perform the flow in the low power consumption standby control method of any one of the above second aspects.
In a fifth aspect, the present application provides a semiconductor chip, wherein the semiconductor chip includes the processing apparatus according to any one of the first aspects.
In a sixth aspect, the present application provides an electronic device, which includes the semiconductor chip according to the fifth aspect.
DrawingsFig. 1 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of a processing apparatus according to an embodiment of the present invention.
Fig. 3 is a schematic diagram of a power domain in a power management unit according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of a user interface of an electronic device entering a standby state according to an embodiment of the present invention.
Fig. 5 is a schematic diagram of a power domain of a processing device in a standby state according to an embodiment of the present invention.
Fig. 6 is a schematic diagram of a power management unit after a processing device enters a standby state according to an embodiment of the present invention.
Fig. 7 is a schematic diagram of a power management unit after another processing apparatus according to an embodiment of the present invention is in a standby state.
Fig. 8 is a schematic structural diagram of a power management unit after a processing device is in a standby state according to another embodiment of the present invention.
Fig. 9 is a schematic structural diagram of another processing apparatus according to an embodiment of the present invention.
Fig. 10 is a schematic diagram of another power management unit after another processing device provided in an embodiment of the present invention is in a standby state.
Fig. 11 is a schematic diagram of a power management unit in a working state of a processing device according to an embodiment of the present invention.
Fig. 12 is a schematic diagram of a power management unit in an operating state of another processing device according to an embodiment of the present invention.
Fig. 13 is a schematic diagram of a user interface of a wake-up electronic device according to an embodiment of the present invention.
Fig. 14 is a schematic flow chart of a processing device entering a standby state according to an embodiment of the present invention.
Fig. 15 is a flowchart of a low power consumption standby control method according to an embodiment of the present invention.
Detailed DescriptionEmbodiments of the present invention will be described below with reference to the accompanying drawings in the embodiments of the present invention.
The terms "first," "second," "third," and "fourth" and the like in the description and in the claims and drawings are used for distinguishing between different objects and not necessarily for describing a particular sequential or chronological order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
As used in this specification, the terms "component," "module," "system," and the like are intended to refer to a computer-related entity, either hardware, firmware, a combination of hardware and software, or software in execution. For example, a component may be, but is not limited to being, a process running on a processor, an object, an executable, a thread of execution, a program, and/or a computer. By way of illustration, both an application running on a computing device and the computing device can be a component. One or more components may reside within a process and/or thread of execution and a component may be localized on one computer and/or distributed between 2 or more computers. Furthermore, these components can execute from various computer readable media having various data structures stored thereon. The components may communicate by way of local and/or remote processes such as in accordance with a signal having one or more data packets (e.g., data from two components interacting with one another in a local system, distributed system, and/or across a network such as the internet with other systems by way of the signal).
Based on the above, the embodiment of the invention provides an electronic device. Referring to fig. 1, fig. 1 is a schematic structural diagram of an electronic device according to an embodiment of the present invention, and the electronic device 100 may include, but is not limited to, smart phones, smart wearable devices (such as smart watches), tablet computers, personal digital assistants, and other devices that need to be powered by batteries. The electronic device 100 may incorporate a chip or chipset or a circuit board carrying a chip or chipset that may operate under the necessary software drivers. The chip or chip set or a circuit board on which the chip or chip set is mounted may include the power management unit 101, the system on a chip 102, the internal memory 103, the external memory 104, the battery 105, and further may further include components such as interfaces, peripherals, and the like, which are not shown in fig. 1. In particular, the method comprises the steps of,
The power management unit 101 may manage power of the electronic device 100. The power management unit 101 may be used to connect devices such as a battery 105, a system on a chip 102, an internal memory 103, an external memory 104, and the like. The power management unit 101 may receive inputs from the battery 105 and/or the charge management unit to power the system on chip 102, the internal memory 103, the external memory 104, etc. The power management unit 101 may also be configured to monitor battery capacity, battery cycle number, battery health (leakage, impedance) and other parameters. The battery 105 may include a rechargeable battery, and/or a lithium battery, among others. In some embodiments, after the electronic device 100 enters the standby state, the power management unit 101 may completely power down the system on chip 102, and the power management unit 101 may take over the internal memory 103 and the external memory 104 to maintain the internal memory 103 in a self-refresh state and the external memory 104 in a low power consumption state, so that not only can the standby power consumption be reduced, the standby time period be increased, the user experience is improved, and the power-up recovery of the system on chip 102 can be quickly realized. In the following embodiments, how the power management unit 101 takes over the internal memory 103 and the external memory 104 in the standby state will be described in detail, and will not be described here again.
A System On Chip (SoC) 102 may include a processor 1021 and a controller 1022. When the electronic device 100 is in a normal operation state, the power management unit 101 supplies power to the system on chip 102, and the processor 1021 in the system on chip 102 may run an operating system, a file system (e.g., a flash memory file system), or an application program, etc., to control a plurality of hardware or software elements connected to the processor 1021, and may process various data and perform operations. The processor 1021 can load the instructions or data stored in the external memory 104 into the internal memory 103, and call the instructions or data to be operated into the processor 1021 for operation, and when the operation is completed, the processor 1021 temporarily stores the result in the internal memory 103, and stores the instructions or data to be stored for a long time into the external memory 104 through the controller 1022. The processor 1021 may include one or more processing units (also referred to as processing cores), such as: the processor 1021 may include a Central Processing Unit (CPU), an application processing unit (application processor, AP), a modem processing unit, a graphics processing unit (graphics processing unit, GPU), image signal processing unit (IMAGE SIGNAL processor, ISP), video encoding and decoding unit, digital signal processing unit (DIGITAL SIGNAL processor, DSP), Baseband processing unit and neural Network Processing Unit (NPU), etc. Wherein the different processing units may be separate devices or may be integrated in one or more devices. Optionally, a memory may be provided in the processor 1021 for storing instructions and data. In some embodiments, the memory in the processor 1021 is a Cache (Cache). The Cache may store instructions or data that has just been used or recycled by the processor 1021. If the processor 1021 needs to reuse the instruction or data, it can be called directly from the Cache. Repeated accesses are avoided and the latency of the processor 1021 is reduced, thereby improving the efficiency of the system. A controller 1022 in the system on chip 102 may be used to manage and control data read and write between the processor 1021 and the internal memory 103 and external memory 104, and provide a standardized interface (e.g., universal flash storage UFS standard) for communication between the processor 1021 and the internal memory 103, and between the processor 1021 and the external memory 104. In some embodiments, for instructions or data sent from the processor 1021, the controller 1022 may convert the instructions or data into packets supporting a certain protocol in a packed manner, while the controller 1022 performs the reverse operation for data received by the processor 1021. In some embodiments, when electronic device 100 is in a standby state, all devices in system-on-chip 102 may be in a powered-down state, i.e., power management unit 101 may cease to supply power to system-on-chip 102.
The internal Memory 103, typically a power-down volatile Memory, loses its stored contents when powered down, and may also be referred to as a Memory (Memory) or main Memory. The internal memory 103 of the present application includes a readable and writable running memory, which is used to temporarily store the operation data in the processor 1021, and to interact with the external memory 104 or other external memories, and may be used as a storage medium for temporary data of an operating system or other running programs. For example, an operating system running on the processor 1021 transfers data to be operated from the internal memory 103 to the processor 1021 for operation, and when the operation is completed, the processor 1021 then transmits the result. In some embodiments, after the electronic device 100 enters the standby state, the power management unit 101 continues to supply power to the internal memory 103, and makes the internal memory 103 in the self-refresh mode, so as to ensure that the data currently stored in the internal memory 103 is not lost, avoiding that the external memory 104 needs to be loaded with data or instructions again after the system on chip 102 is powered up again into the internal memory 103, reducing the power-up recovery time of the system on chip 102, so that the electronic device 100 can be recovered to the normal working state more quickly.
The internal memory 103 may include one or more of Dynamic Random Access Memory (DRAM), static Random Access Memory (SRAM), synchronous Dynamic Random Access Memory (SDRAM), and the like. The DRAM further includes a double-rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory, DDR SDRAM) abbreviated as DDR, a second generation double-rate synchronous dynamic random access memory (DDR 2), a third generation double-rate synchronous dynamic random access memory (DDR 3), a fourth generation low power consumption double data rate synchronous dynamic random access memory (Low Power Double Data Rate, lpddr 4), a fifth generation low power consumption double data rate synchronous dynamic random access memory (Low Power Double Data Rate, lpddr 5), and the like.
The external memory 104 is a nonvolatile memory, and the stored content thereof is not lost after power failure. External memory 104 may be used to store long-term instructions and data involved in the execution of processor 1021, such as boot programs, operating systems, application programs, and data. Since the processor 1021 cannot directly read the instructions and data in the external memory 104 nor can it directly write the instructions or data to the external memory 104, the processor 1021, when executing the read (or load) instruction, actually temporarily loads the contents to be read (including the instructions and/or data) stored in the external memory 104 into the internal memory 103 through the controller 1022, and then reads out the contents from the internal memory 103 by the processor 1021, and when executing the write (i.e., store) instruction, actually temporarily writes the data to be stored (including the instructions and/or data) into the internal memory 103 by the processor 1021, and then stores the data from the internal memory 103 into the external memory 104 through the controller 1022. In some embodiments, after the electronic device 100 enters the standby state, the power management unit 101 continues to supply power to the external memory 104, and makes the external memory 104 in a low power consumption mode, so as to ensure that the external memory 104 retains the current configuration parameters, thereby avoiding the need of re-performing the power-on initialization process of the external memory 104 after the system on chip 102 is powered on again, reducing the power-on recovery time of the system on chip 102, and enabling the electronic device 100 to recover to the normal working state more quickly.
The external memory 104 may include one or more of Flash memory (e.g., NAND Flash memory, NOR Flash memory, etc.), universal Flash memory (universal Flash storage, UFS), embedded multimedia card eMMC, universal Flash memory multi-chip package uMCP memory, embedded multimedia card multi-chip package eMCP memory, solid State Drive (SSD), etc.
It is understood that the structure of the electronic device 100 in fig. 1 is merely some exemplary implementations provided by embodiments of the present invention, and the structure of the electronic device in embodiments of the present invention includes, but is not limited to, the above implementations.
Embodiments of the present invention will be described below with reference to the accompanying drawings in the embodiments of the present invention.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a processing apparatus according to an embodiment of the present application, and the processing apparatus according to the embodiment of the present application will be described in detail with reference to fig. 2. As shown in fig. 2, the processing device 200 may include, but is not limited to, a power management unit 201, a system on chip 202, and an internal memory 203, wherein the system on chip SoC202 and the internal memory 203 are coupled to the power management unit 201, the power management unit 201 powers the SoC202 through a first power domain and powers the internal memory 203 through a second power domain. It should be noted that, the processing apparatus 200 may be built into various devices that need to be powered by a battery, such as the electronic device 100 in fig. 1, the functions of the power management unit 201 may include some or all of the functions of the power management unit 101 in fig. 1, the functions of the SoC202 may include some or all of the functions of the system on chip 102 in fig. 1, and the internal memory 203 may include some or all of the functions of the internal memory 103 in fig. 1. Wherein,
The power management unit 201 is configured to receive a first instruction sent by the SoC202, where the first instruction is used to instruct the processing apparatus 200 to enter a standby state.
Specifically, the power management unit 201 may manage power of each module in the processing apparatus 200, for example, as shown in fig. 3, fig. 3 is a schematic diagram of a power domain in the power management unit according to an embodiment of the present application, where the power management unit 201 supplies power to the SoC202 through a first power domain, and the first power domain may include a plurality of sub-power domains, such as a system interface power (may also be referred to as an IO power), a low voltage normally open (Always ON, AO) power of the SoC202, a memory control signal power, and other power, and the power management unit 201 supplies power to the internal memory 203 (such as LPDDR 4) through a second power domain, and the second power domain may also include a plurality of sub-power domains, such as an IO power, a control signal power, and the like, inside the DDR. A System On Chip (SoC) 202 may refer to a complete System integrated On a single Chip, where the complete System generally includes a central processing unit (central processing unit, CPU), peripheral circuits, etc. The internal Memory 203 is typically a power-down volatile Memory, and loses its stored content when power is turned off, which may also be referred to as a Memory (Memory) or main Memory. The internal memory 203 in the present application includes a readable and writable running memory, which is used to temporarily store operation data in the SoC202, and can interact with an external memory or other external memories, and can be used as a storage medium for temporary data of an operating system or other running programs.
Optionally, when the SoC202 receives a target operation of the processing apparatus 200 by the user, or the user does not perform any operation on the processing apparatus 200 within a preset period of time, the SoC202 may be triggered to send a first indication to the power management unit 201, so that the processing apparatus 200 enters a standby state. For example, as shown in fig. 4, fig. 4 is a schematic diagram of a user interface of an electronic device in a standby state according to an embodiment of the present invention, where a processing apparatus 200 is disposed in the electronic device (such as a smart phone, a smart wearable device, a tablet computer, etc. that needs to be powered by a battery), and (a) the electronic device in fig. 4 may display an operation interface during normal operation, and when detecting a pressing operation of a user on the electronic device (such as a user pressing a power button on two sides of the electronic device), the SoC202 may be triggered to send a first indication to the power management unit 201, so that the processing apparatus 200 is in the standby state, and then, as shown in (b) in fig. 4, the electronic device may be in a black screen standby state.
The power management unit 201 is further configured to control to disconnect the first power domain and keep part or all of the power of the second power domain in a power supply state, where, after the processing apparatus 200 enters the standby state, the SoC202 is in a fully powered-down state and part or all of the devices of the internal memory 203 are in a powered-up state.
Specifically, when the power management unit 201 receives the first instruction sent by the SoC202, the power management unit 201 may disconnect the first power domain. For example, as shown in fig. 5, fig. 5 is a schematic diagram of a power domain after a processing apparatus is in a standby state, where a first power domain may include a plurality of sub-power domains, and after receiving a first instruction sent by the SoC202, the power management unit 201 turns off all the sub-power domains in the first power domain, so that the SoC202 is in a completely powered-down state when the processing apparatus 200 is in the standby state. In addition, since the internal memory 202 is a power-down volatile memory, the power management unit 201 keeps the second power domain in the power-up state in order to avoid the data loss in the internal memory 203 of the processing apparatus 200 in the standby state. Further, in order to reduce the power consumption of standby, a part of the power domains in the second power domain may be powered down, that is, some or all devices that do not affect the storage of the currently stored data in the internal memory 203 may be powered down, for example, the IO power of the internal memory 203 is powered down (the internal memory 203 does not need to interact with other modules when the processing apparatus 200 is in a standby state, so that the IO power may be powered down).
The power management unit 201 is further configured to send a first control signal to the internal memory 203, where the first control signal is used to maintain the internal memory 203 in a first mode, and in the first mode, the internal memory 203 stores currently stored data.
Specifically, after the power management unit 201 disconnects the first power domain, the SoC202 is in a power-down state and cannot continuously control and manage the internal memory 203, the internal memory 203 may be taken over by the power management unit 201, and the power management unit 201 may send a first control signal to the internal memory 203 to maintain the internal memory 203 in the first mode (i.e., the first mode may be understood as a self-refresh mode of the internal memory 203). The first control signal may be a signal (may be a signal with a fixed level) that maintains the internal memory 203 in the self-refresh mode, and may be a signal composed of a plurality of signals, such as a signal composed of a clock enable signal and a reset signal, where the internal memory 203 may be maintained in the self-refresh mode when the clock enable signal sent by the power management unit 201 to the internal memory 203 is 0 and the reset signal is 1.
Alternatively, before the SoC202 sends the first control signal to the power management unit 201, the control signal and the related control command may be sent to the internal memory 203, so that the internal memory 203 can enter the self-refresh state.
For example, as shown in fig. 6, fig. 6 is a schematic diagram of a power management unit after a processing apparatus enters a standby state according to an embodiment of the present invention, in which a control logic module (e.g., a first control module) may be added to the power management unit 201, and when the SoC202 is in a power-down state, a first control signal, that is, a reset signal is 1, and a clock enable signal is 0, may be sent to the internal memory 203 through the control logic module, so as to maintain the internal memory 203 in a self-refresh mode, so that the internal memory 203 can still store currently stored data when the processing apparatus 200 is in the standby state.
It should be noted that, when the processing apparatus 200 enters the standby state, the internal memory 203 may store the data stored currently, so as to avoid the need to read the related data from the external memory again after the processing apparatus 200 wakes up, thereby reducing the power-up recovery time of the processing apparatus 200.
Alternatively, the first control signal may be a single signal, such as a reset signal, and the SoC202 may send a clock enable signal with a value of 0 to the internal memory 203 before powering down, and the clock enable signal may be maintained to be always 0 through a pull-down resistor after powering down the SoC202, and then the internal memory 203 may be maintained in the self-brushing mode after the power management unit 201 sends a reset signal with a value of 1 to the internal memory 203. For example, as shown in fig. 5, the SoC202 and the internal memory 203 may be connected through a transmission line and a pull-down resistor, further, the SoC202 may transmit a clock enable signal of 0 to the internal memory 203 before powering down, and maintain the clock enable signal at 0 through the pull-down resistor after powering down the SoC 202. Further, after the power management unit 201 takes over the internal memory 203, a reset signal of 1 may be sent to the internal memory 203 to maintain the internal memory 203 in the self-refresh mode, so that the currently stored data can still be saved when the processing apparatus 200 is in the standby state.
In one possible implementation manner, the power management unit 201 includes a status register and a first control module, where the power management unit 201 is specifically configured to set the status register to a first state after receiving the first indication sent by the SoC202, mask, by the first control module, a signal output by the SoC202 to the internal memory in the first state, and send the first control signal to the internal memory to maintain the internal memory in the first mode.
Specifically, the status register (status regist, SR) in the power management unit 201 may have two states, when sr=0, it may indicate that the processing apparatus 200 is in a normal operation state, and when sr=1 (i.e. it may be understood that the status register is set to the first state, it should be emphasized that in the first state, sr=1) it may indicate that the processing apparatus 200 is in a standby state. The first control module in the power management unit 201 may have control logic and may send a signal to the internal memory 203.
Next, referring to fig. 7, fig. 7 is a schematic diagram of a power management unit after another processing apparatus is in a standby state, where a status register and a first control module may be added to the power management unit 201, and when the power management unit 201 receives a first instruction sent by the SoC202, the status register may be set to 1 (i.e. the first state), so as to indicate that the processing apparatus 200 enters the standby state, and then the power management unit 201 may take over the internal memory 203. In this process, after the power management unit 201 takes over the internal memory 203 and before the SoC202 is completely powered down, the SoC202 may still send a signal to the internal memory 203 through the power management unit 201, so that the first control module of the power management unit 201 may mask the signal sent by the SoC202 to the power management unit 201, and the power management unit 201 may completely control and manage the internal memory 203, so that the first control module of the power management unit 201 may send the first control signal to the internal memory 203 to maintain the internal memory 203 in the self-refresh mode, so that the internal memory 203 may still be capable of storing the currently stored data when the processing apparatus 200 is in the standby state. In addition, after SoC202 is completely powered down, since the signal sent to internal memory 203 by SoC202 through power management unit 201 is masked by power management unit 201, internal memory 203 is completely controlled and managed by power management unit 201 after SoC202 is completely powered down.
It should be noted that, before the SoC202 powers down, the SoC202 may further send configuration information of the first control module to the power management unit 201, so that the power management unit 201 configures the first control module based on the configuration information, and may send the first control signal to the internal memory 203 when sr=1.
In a possible implementation, the internal memory 203 is configured to receive the first control signal sent by the power management unit 201 and maintain the first mode to save the currently stored data.
Specifically, after the power management unit 201 takes over the internal memory 203, the power management unit 201 may manage the state of the internal memory 203. Therefore, after the internal memory 203 receives the first control signal sent by the power management unit 201, the self-refresh mode (i.e. the first mode) can be maintained, i.e. the internal memory 203 continuously refreshes the currently stored data, so that the internal memory 203 can still retain the currently stored data after the processing apparatus 200 enters the standby state. In summary, after the processing apparatus 200 enters the standby state in the present application, the SoC202 is in a completely powered-down state and the internal memory 203 can still retain the currently stored data, so that the processing apparatus 200 is ensured to be able to recover the normal working state in a shorter time, and the standby power consumption of the processing apparatus 200 is reduced.
Alternatively, as shown in fig. 7, the SoC202 and the internal memory 203 may be connected through a transmission line and a pull-down resistor, further, the SoC202 may send a clock enable signal of 0 to the internal memory 203 before powering down, and maintain the clock enable signal to be 0 all the time through the pull-down resistor after powering down the SoC 202. Further, after the power management unit 201 takes over the internal memory 203, a reset signal (i.e. the first control signal) of 1 may be actively sent to the internal memory 203, and then the internal memory 203 can be maintained in the self-refresh mode all the time in a state where the clock enable signal is 0 and the reset signal is 1, i.e. the internal memory 203 continuously refreshes the currently stored data, so that the internal memory 203 can still retain the currently stored data after the processing apparatus 200 enters the standby state.
Optionally, as shown in fig. 8, fig. 8 is a schematic structural diagram of a power management unit after the processing apparatus is in a standby state according to another embodiment of the present invention, where a first control module in the power management unit 201 may send a reset signal to the internal memory 203 and also send a clock enable signal. After the power management unit 201 takes over the internal memory 203, the power management unit 201 may actively send a reset signal of 1 and a clock enable signal of 0 to the internal memory 203 (i.e. the first control signal is composed of the reset signal of 1 and the clock enable signal of 0), and then the internal memory 203 may be maintained in the self-refresh mode all the time in a state where the clock enable signal is 0 and the reset signal is 1, i.e. the internal memory 203 may continuously refresh the currently stored data, so that the internal memory 203 may still be capable of retaining the currently stored data after the processing apparatus 200 enters the standby state.
In a possible implementation manner, the processing apparatus 200 further includes an external memory 204, and the power management unit 201 is further coupled to the external memory 204, where the power management unit 201 supplies power to the external memory 204 through a third power domain, and the power management unit 201 is further configured to, after receiving the first indication sent by the SoC202, keep part or all of power in the third power domain in a power-on state, where after the processing apparatus 200 enters the standby state, part or all of devices in the external memory 204 are in a power-on state, send a second control signal to the external memory 204, where the second control signal is used to maintain the external memory 204 in a second mode, where the external memory 204 retains current configuration parameters in the second mode.
Specifically, the external memory 204 is generally a nonvolatile memory, and the stored content thereof is not lost after power failure. Common external memory 204 may include Flash memory (e.g., NAND Flash, NOR Flash, etc.), universal Flash memory (universal Flash storage, UFS), and the like. Next, referring to fig. 9, fig. 9 is a schematic structural diagram of another processing device according to an embodiment of the present invention, where the power management unit 201 may further supply power to the external memory 204 (such as EMMC or UFS) through a third power domain, where the third power domain may include a plurality of sub-power domains, such as IO power, control signal power, etc. inside the external memory 204. When the power management unit 201 receives the first instruction sent by the SoC202, in order to avoid the problem that the current configuration parameters of the external memory 204 are lost after the processing apparatus 200 enters the standby state, the power management unit 201 keeps the third power domain in the power supply state. In order to reduce the power consumption of standby, a part of the power domains in the third power domain may be powered down, that is, some or all devices that do not affect the current configuration parameters stored in the external memory 204 may be powered down, for example, the IO power supply of the external memory 204 may be powered down (when the processing apparatus 200 is in a standby state, the external memory 204 does not need to interact with other modules, so that the IO power supply may be powered down). Further, after the processing apparatus 200 enters the standby state, the SoC202 may be powered down, and the internal memory 203 and the external memory 204 may be taken over by the power management unit 201. When the power management unit 201 takes over the external memory 204, a second control signal may be sent to the external memory 204, i.e. the second control signal may be a reset signal. Since the external memory 204 may always receive the reset signal of 1, the external memory 204 may be maintained in the second mode, i.e., the second mode may be understood as a low power consumption mode of the external memory 204. In the low power mode, the external memory 204 may still retain the current configuration parameters and configuration states.
Alternatively, before SoC202 sends the first control signal to power management unit 201, the control signal and associated control command may be sent to external memory 204 to enable external memory 204 to enter a low power mode.
It should be noted that, after the processing apparatus 200 enters the standby state, the current configuration parameters and the configuration state of the external memory 204 may be reserved, so that the external memory 204 needs to be reconfigured after the processing apparatus 200 wakes up, thereby reducing the power-on recovery time of the processing apparatus 200.
In a possible implementation manner, the power management unit 201 further includes a second control module, and when the status register is set to the first state, the power management unit 201 is specifically configured to mask, by using the second control module, a signal output by the SoC202 to the external memory 204, and send the second control signal to the external memory 204, so as to maintain the external memory 204 in the second mode.
Specifically, the power management unit 201 may further include a second control module. Next, referring to fig. 10, fig. 10 is a schematic diagram of another power management unit after another processing device provided in the embodiment of the present invention is in a standby state, where the power management unit 201 includes a plurality of power domains, a first control module, and a status register, and may further include a second control module. When the power management unit 201 receives the first instruction sent by the SoC202, the status register may be set to 1 (i.e. the first state), which may further indicate that the processing apparatus 200 enters the standby state, and then the power management unit 201 may take over the external memory 204. In this process, after the power management unit 201 takes over the external memory 204 and before the SoC202 is completely powered down, the SoC202 may still transmit signals to the external memory 204 through the power management unit 201, so that the second control module in the power management unit 201 may mask signals transmitted from the SoC202 to the external memory 204, and the power management unit 201 completely controls and manages the external memory 204, so that the second control module in the power management unit 201 may transmit the second control signals to the external memory 204 to maintain the external memory 204 in a low power consumption mode, so that the current configuration parameters and the current configuration state can still be saved when the processing apparatus 200 is in a standby state. In addition, after the SoC202 is completely powered down, the second control module also shields the nonstationary signal output by the SoC202 to the external memory 204 through the power management unit 201, so that the external memory 204 is completely controlled and managed by the power management unit 201 after the SoC202 is completely powered down.
It should be noted that, before the SoC202 powers down, the SoC202 may further send configuration information of the second control module to the power management unit 201, so that the power management unit 201 configures the second control module based on the configuration information, and may send the second control signal to the external memory 204 when sr=1.
In one possible implementation, the external memory is configured to receive the second control signal sent by the power management unit and maintain the second mode to preserve the current configuration parameters.
Specifically, after the power management unit 201 takes over the external memory 204, the power management unit 201 may control and manage the state of the external memory 204. Therefore, when the external memory 204 receives the second control signal sent by the power management unit 201, the external memory 204 can be maintained in the low power consumption mode (second mode), that is, the external memory 204 can still maintain the current configuration information and configuration state after the processing apparatus 200 enters the standby state. In summary, after the processing apparatus 200 enters the standby state in the present application, the SoC202 is in a completely powered-down state and the external memory 204 can still maintain the current configuration parameters and configuration state, so that the processing apparatus 200 is ensured to be able to recover the normal working state in a shorter time, the standby power consumption of the processing apparatus 200 is reduced, the standby time is increased, and the user experience is improved.
In a possible implementation manner, the power management unit 201 is further configured to restore the first power domain and supply power to the SoC202 after receiving an indication that the processing apparatus 200 needs to restore an operating state, receive a second indication sent by the SoC202, set the status register to a second state, unmask a signal output by the SoC202 to the internal memory 203 and forward the signal output by the SoC202 to the internal memory 203, or unmask a signal output by the SoC202 to the external memory 204 and forward the signal output by the SoC202 to the external memory 204.
Specifically, when the power management unit 201 receives an instruction of waking up the processing apparatus 200, the first power domain may be restored and the SoC202 may be continuously supplied with power, and when the SoC202 is powered up, the internal memory 203 and the external memory 204 may be continuously controlled and managed. Further, after SoC202 is powered on, a second instruction may be sent to power management unit 201, and after receiving the second instruction, power management unit 201 may set the status register to the second state (i.e. sr=0), which indicates that processing apparatus 200 is in a normal operating state, or may indicate that power management unit 201 may not continuously control and manage internal memory 203 and external memory 204. Next, soC202 may unmask control signals from SoC202 to power management unit 201 by controlling the power management unit 201 related logic, while transparently transmitting the related control signals to internal memory 203 and external memory 204 through power management unit 201. Finally, the processing device 200 resumes normal operation.
For example, as shown in fig. 11, fig. 11 is a schematic diagram of a power management unit in a working state of a processing apparatus according to an embodiment of the present invention, in the drawing, after the power management unit 201 receives a second control signal sent by the SoC202, a status register may be set to 0, which indicates that the power management unit 201 may not continuously control and manage the internal memory 203 and the external memory 204, that is, a first control module of the power management unit 201 does not continuously control and manage the internal memory 203, and a second control module of the power management unit 201 does not continuously control and manage the external memory 204. Further, the first control module may unmask the signal output by the SoC202 to the internal memory 203 and forward the signal output by the SoC202 to the internal memory 203, for example, the first control module may directly forward the reset signal sent by the SoC202 to the internal memory 203, the second control module may unmask the signal output by the SoC202 to the external memory 204 and forward the signal output by the SoC202 to the external memory 204, for example, the second control module may directly forward the reset signal sent by the SoC202 to the external memory 204.
As another example, as shown in fig. 12, fig. 12 is a schematic diagram of a power management unit in the working state of another processing apparatus according to the embodiment of the present invention, in which after the power management unit 201 receives a second control signal sent by the SoC202, a state register may be set to 0, which indicates that the power management unit 201 may not continuously control and manage the internal memory 203 and the external memory 204, that is, a first control module of the power management unit 201 does not continuously control and manage the internal memory 203, and a second control module of the power management unit 201 does not continuously control and manage the external memory 204. Further, the first control module may unmask the signal output by the SoC202 to the internal memory 203 and forward the signal output by the SoC202 to the internal memory 203, for example, the first control module may directly forward the reset signal and the clock enable signal sent by the SoC202 to the internal memory 203, the second control module may unmask the signal output by the SoC202 to the external memory 204 and forward the signal output by the SoC202 to the external memory 204, for example, the second control module may directly forward the reset signal sent by the SoC202 to the external memory 204.
Optionally, as shown in fig. 13, fig. 13 is a schematic diagram of a user interface for waking up an electronic device according to an embodiment of the present invention, where the electronic device is provided with a processing apparatus 200, when the processing apparatus 200 is in a standby state, the electronic device is in a black screen standby state as shown in fig. 13 (a), and when a pressing operation of a user on the electronic device (such as a user pressing a power button on two sides of the electronic device) is detected, the power management unit 201 receives an indication that the processing apparatus 200 needs to restore a working state, so as to wake up the processing apparatus 200, and then, as shown in fig. 13 (b), the electronic device can be lightened, and an operation interface is displayed on the electronic device.
In a possible implementation manner, the SoC202 is configured to determine whether the status register in the power management unit 201 is in the first state after the first power domain is turned on, and if the status register is in the first state, send the second indication to the power management unit 201.
Specifically, after the SoC202 is powered up again, it may be determined whether the status register in the power management unit 201 is in the first state, and if the status register is in the first state, a second instruction may be sent to the power management unit 201 to control the relevant logic of the power management unit 201 to unmask the control signal sent by the SoC202 to the power management unit 201, and at the same time, the SoC202 may transparently transmit the relevant control signal to the internal memory 203 and the external memory 204 through the power management unit 201. If the status register is not in the first state, the processing device 200 performs a power-on restart procedure, i.e. the external memory 204 needs to be reconfigured, and the required data is read from the external memory 204 to the internal memory 203 again.
Next, taking a mobile phone as an example and referring to fig. 14 for explanation from the SoC202 side, as shown in fig. 14, fig. 14 is a schematic flow chart of a processing device entering a standby state according to an embodiment of the present invention, in which the processing device 200 is built in the mobile phone, and the step S401 to S419 may be included in the mobile phone entering the standby state. The detailed description is as follows:
S401, the mobile phone enters a normal standby mode. Specifically, soC202 may first enter a normal standby mode after receiving a target operation for a mobile phone from a user. It should be emphasized that in this normal standby mode, the power management unit 201 does not completely power down the SoC202, and the internal memory 203 and the external memory 204 are still controlled and managed by the SoC 202.
S402, returning the SOC to a normal working state, and exiting the power saving mode by the PMU. Specifically, when the time for the mobile phone to enter the normal standby mode exceeds the preset value, the SoC202 may receive the timeout interrupt wakeup, so that the SoC202 returns to the normal working state, and the power management unit 201 (i.e. PMU) exits the power saving mode.
S403, the SOC stores the DDR training sequence into the FLASH. Specifically, soC202 saves the internal memory 203 (i.e., DDR) training sequence to external memory 204 (i.e., FLASH).
S404, the SOC saves the field parameters in the DDR, and configures the DDR to enter a self-refresh mode. Specifically, the SoC202 stores data in the internal memory 203, and configures the internal memory 203 to enter the self-refresh mode, so that the data stored in the internal memory 203 is not lost after the mobile phone enters the super standby mode.
S405, SOC configuration PMU Logic control1, mask input signal PMU_FLASH_RST_N, and fix output FLASH_RST_N to 1. Specifically, before SoC202 is completely powered down, soC202 may configure a logic control module in power management unit 201, so that after SoC202 is completely powered down, the logic control module can mask signals output by SoC202 to external memory 204, and output control signals to external memory 204, so that external memory 204 enters a low power consumption mode, and current configuration parameters and configuration states are reserved.
S406, SOC configuration PMU Logic control2, masks input signal PMU_DDR_RST_N, and fixes output DDR_RST_N to 1. Specifically, before the SoC202 is completely powered down, the SoC202 may configure a logic control module in the power management unit 201, so that the logic control module can mask a signal output by the SoC202 to the internal memory 203 after the SoC202 is completely powered down, and output a control signal to the internal memory 203, so that the internal memory 203 enters a self-refresh mode, and data loss in the internal memory 203 is avoided.
S407, SOC configures PMU Super SR to be 1. Specifically, before SoC202 is fully powered down, soC202 may first configure a status register in power management unit 201 so that sr=1, may indicate that the handset is to enter a deep standby state, and may take over internal memory 203 and external memory 204 by power management unit 201.
S408, the SOC controls the power down of the PMU, and the PMU enters the Super SR power down process. Specifically, soC202 may send a first indication to power management unit 201 to cause power management unit 201 to fully power down SoC 202.
S409, the whole SOC is powered down, DDR and FLASH partial power supplies are maintained, and the PMU enters a power saving (Economical, ECO) mode. Specifically, after the power management unit 201 receives the first instruction sent by the SoC202, the SoC202 may be completely powered down, or part of the power supplies of the internal memory 203 and the external memory 204 may be powered down.
S410, the SOC enters a super standby mode.
S411, the mobile phone enters super standby. Specifically, after SoC202 is fully powered down, the handset enters a super standby mode, where internal memory 203 and external memory 204 may be taken over by power management unit 201.
S412, the PMU running the Super SR power-on includes a clock-on process. Specifically, when the power management unit 201 receives a wake-up interrupt, such as the user pressing a power button of the mobile phone, the power management unit 201 may power up the Super SR to start the clock flow.
S413, the SOC is powered up to run the start code, and whether the PMU Super SR is 1 is accessed. Specifically, the power management unit 201 may supply power to the SoC202 again, and after the SoC202 resumes normal operation, it may first go to access whether the state of the status register in the power management unit 201 is 1, so as to determine whether the mobile phone is in the deep standby mode.
And S414, if yes, the SOC runs the Super standby recovery flow. Specifically, if the state of the status register in the power management unit 201 is 1 after the SoC202 resumes normal operation, it indicates that the mobile phone needs to wake up from the deep standby state. If not, the SOC runs a normal power-on reset flow, which indicates that the mobile phone needs to wake up from a power-off state.
S415, SOC configures PMU Super SR to 0. Specifically, the status register in the power management unit 201 may be configured to be 0 to indicate that the mobile phone enters a normal working state, and may also indicate that the power management unit 201 does not need to continuously control and manage the internal memory 203 and the external memory 204.
S416 SOC configuration PMU Logic control1 is in pass-through mode, i.e., signal FLAHS _rst_n equals SOC output signal pmu_flash_rst_n. Specifically, the power management unit 201 does not need to resume control of the external management memory 204, and thus the logic control module can be configured in the pass-through mode.
S417, SOC configuration PMU Logic control2 is in pass-through mode, i.e., signal ddr_rst_n equals SOC output signal pmu_ddr_rst_n. Specifically, the power management unit 201 does not need to resume control of the management internal memory 203, and thus the logic control module can be configured in the pass-through mode.
And S418, the DDR exits from self-refreshing, the FLASH completes quick initialization, and the SOC is restored to the scene.
S419, the SOC is restored to Normal mode.
In the embodiment of the invention, after the processing device enters the standby state, the SoC is in a completely powered-down state, the internal memory can still retain the currently stored data, and the external memory also retains the current configuration parameters, so that the processing device can be ensured to recover the normal working state in a shorter time, the standby power consumption of the processing device is reduced, the standby time is prolonged, and the user experience is improved.
The foregoing details the processing apparatus according to the embodiments of the present invention, and the following provides a related method according to the embodiments of the present invention.
Referring to fig. 15, fig. 15 is a flowchart of a low power consumption standby control method according to an embodiment of the present invention, where the method is applicable to a processing apparatus and a device including the processing apparatus in fig. 2. The method may include the following step S501-step S503. The processing device comprises a power management unit, a system on chip (SoC) and an internal memory, wherein the SoC and the internal memory are coupled to the power management unit, the power management unit supplies power to the SoC through a first power domain and supplies power to the internal memory through a second power domain. The detailed description is as follows:
step S501, receiving, by the power management unit, a first instruction sent by the SoC.
Specifically, the first indication is used for indicating the processing device to enter a standby state;
step S502, through the power management unit, the first power domain is controlled to be disconnected, and part or all of the power of the second power domain is kept in a power supply state.
After the processing device enters the standby state, the SoC is in a completely powered-down state, and part or all devices of the internal memory are in a powered-up state;
Step S503, through the power management unit, a first control signal is sent to the internal memory.
Specifically, the first control signal is used for maintaining the internal memory in a first mode, wherein the internal memory stores currently stored data in the first mode.
In one possible implementation, the power management unit includes a status register and a first control module, and the sending, by the power management unit, a first control signal to the internal memory includes setting the status register to a first state after receiving the first indication sent by the SoC, and in the first state, masking, by the first control module, a signal output by the SoC to the internal memory, and sending the first control signal to the internal memory to maintain the internal memory in the first mode.
In one possible implementation, the method further includes receiving, by the internal memory, the first control signal sent by the power management unit and maintaining the internal memory in the first mode to save the currently stored data.
In one possible implementation manner, the processing device further comprises an external memory, the power management unit is further coupled with the external memory, the power management unit supplies power to the external memory through a third power domain, the method further comprises the steps of keeping part or all of power supplies of the third power domain in a power supply state after receiving the first indication sent by the SoC through the power management unit, wherein part or all of devices of the external memory are in a power-on state after entering the standby state, and sending a second control signal to the external memory through the power management unit, wherein the second control signal is used for keeping the external memory in a second mode, and the external memory keeps current configuration parameters in the second mode.
In one possible implementation, the power management unit further includes a second control module, and when the status register is set to the first state, the sending, by the power management unit, a second control signal to the external memory includes shielding, by the second control module, a signal output by the SoC to the external memory, and sending the second control signal to the external memory to maintain the external memory in the second mode.
In one possible implementation, the method further includes receiving, by the external memory, the second control signal sent by the power management unit and maintaining the external memory in the second mode to preserve current configuration parameters.
In one possible implementation manner, the method further comprises the steps of recovering the first power domain and supplying power to the SOC through the power management unit after receiving an indication that the processing device needs to recover the working state, receiving a second indication sent by the SOC through the power management unit, setting the state register to be in a second state, unmasking a signal output by the SOC to the internal memory through the power management and forwarding the signal output by the SoC to the internal memory, or unmasking the signal output by the SoC to the external memory and forwarding the signal output by the SoC to the external memory.
In one possible implementation, the method further includes determining, by the SoC, whether the status register in the power management unit is in the first state after switching on the first power domain, and if the status register is in the first state, sending, by the SoC, the second indication to the power management unit.
In the embodiment of the invention, after the processing device enters the standby state, the SoC is in a completely powered-down state, the internal memory can still retain the currently stored data, and the external memory also retains the current configuration parameters, so that the processing device can be ensured to recover the normal working state in a shorter time, the standby power consumption of the processing device is reduced, the standby time is prolonged, and the user experience is improved.
The application provides a terminal device which has the function of realizing any one of the low-power consumption standby control methods. The functions can be realized by hardware, and can also be realized by executing corresponding software by hardware. The hardware or software includes one or more modules corresponding to the functions described above.
The application provides a terminal device, which comprises a processor, wherein the processor is configured to support the terminal device to execute corresponding functions in the low-power consumption standby control method. The terminal device may also include a memory for coupling with the processor, which holds the program instructions and data necessary for the terminal device. The terminal device may also include a communication interface for the terminal device to communicate with other devices or a communication network.
An embodiment of the present invention provides a computer program including instructions which, when executed by a computer, cause the computer to perform the flow in the low power consumption standby control method of any one of the above-mentioned.
The application provides a semiconductor chip, which is characterized in that the semiconductor chip comprises the processing device of any one of the above.
The application provides an electronic device characterized in that the electronic device comprises the semiconductor chip mentioned above.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.
It should be noted that, for simplicity of description, the foregoing method embodiments are all described as a series of acts, but it should be understood by those skilled in the art that the present application is not limited by the order of acts described, as some steps may be performed in other orders or concurrently in accordance with the present application. Further, those skilled in the art will also appreciate that the embodiments described in the specification are all preferred embodiments, and that the acts and modules referred to are not necessarily required for the present application.
In the several embodiments provided by the present application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and the division of elements, such as those described above, is merely a logical function division, and may be implemented in other manners, such as multiple elements or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, or may be in electrical or other forms.
The units described above as separate components may or may not be physically separate, and components shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated units described above, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on this understanding, the technical solution of the present application may be embodied in essence or a part contributing to the prior art or all or part of the technical solution, in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server or a network device, etc., in particular may be a processor in the computer device) to perform all or part of the steps of the above-mentioned method according to the embodiments of the present application. The storage medium may include various media capable of storing program codes, such as a usb disk, a removable hard disk, a magnetic disk, an optical disk, a Read-only memory (ROM), or a Random Access Memory (RAM).
While the application has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art that the foregoing embodiments may be modified or equivalents may be substituted for some of the features thereof, and that the modifications or substitutions do not depart from the spirit and scope of the embodiments of the application.