Detailed Description
The present application is described below based on examples, but the present application is not limited to only these examples. In the following detailed description of the present application, certain specific details are set forth in detail. The present application will be fully understood by those skilled in the art without the details described herein. Well-known methods, procedures, and flows have not been described in detail so as not to obscure the nature of the application. The figures are not necessarily drawn to scale.
First, partial terms or terminology appearing in the course of describing the embodiments of the application are applicable to the following explanation.
The Shmoo eye diagram is a two-dimensional graph that shows the performance of a chip under different conditions. The working principle of the system is that two key performance indexes are scanned through automatic test equipment (Automatic Test Equipment, ATE), an automatic test system (Automated TEST SYSTEM, ATS) or a traditional test platform and the like, the test result is displayed in a two-dimensional coordinate system, and the displayed test result can be in the shape of an 'eye'. The chart can intuitively show the working condition of the chip under different conditions.
Taking the key performance indexes as Vref and Timing as an example, giving working points (Vref, timing), transmitting a known code Pattern (Pattern) on the transmitting (Tx) side of a data Input/Output (I/O) channel, receiving and comparing the Pattern on the receiving (Rx) side, scanning all the working points (Vref, timing), recording whether the error codes or the number of the error codes on each (Vref, timing), and drawing a two-dimensional eye Pattern according to the test result of whether the error codes or the number of the error codes, thereby obtaining the Shmoo eye Pattern. The Shmoo eye diagram may be used as an important basis for evaluating I/O electrical performance and may also be used as the basis for signal integrity post-silicon issuance (Signoff).
The data channel, which means a signal channel for data input/output, is composed of a plurality of signal lines (lanes). One data channel includes 8 lanes if the bit width of one data channel is 1 byte, and 16 lanes if the bit width of one data channel is 2 bytes. Lane is the basic unit of a high-speed serial computer expansion bus standard (PERIPHERAL COMPONENT INTERCONNECT EXPRESS, PCIe) link, each Lane is a bi-directional serial communication channel responsible for transmitting data between two PCIe devices.
Exemplary System
FIG. 1 illustrates an exemplary system suitable for use in the hardware testing method of embodiments of the present application. As shown in fig. 1, the system includes a basic input output system (Basic Input Output System, BIOS), a first chip, and a second chip.
The physical layer 110 of the first chip includes a built-in self-test (Built-IN SELF TEST, BIST) unit 11, an Input/Output (I/O) unit 12, a comparator (comparing unit) 13, and a result register (result storing unit) 14. The built-in self-test unit 11 includes a parameter scan controller (PARAMETER SWEEP control unit) and a pattern generator (PATTERN GENERATING unit). The parameter scan controller may set a scan range of a plurality of test parameters, for example, the scan range of each test parameter may include a scan start point, a scan end point, and a scan offset point. The pattern generator may generate test patterns according to test requirements.
The physical layer 120 of the second chip includes the input-output unit 21. A transmission connection is established between the input-output unit 12 of the first chip and the input-output unit 21 of the second chip. The first chip transmits a test signal to the second chip according to a test code pattern generated by a code pattern generator through a transmission connection between the input and output unit 12 and the input and output unit 21, the second chip receives and stores the test signal, the first chip reads the stored test signal from a memory core of the second chip through the input and output unit 12 and the input and output unit 21 again to obtain a feedback signal of the second chip, the input and output unit 12 sends the read feedback signal to the comparator 13, the comparator 13 compares the test signal with the feedback signal to generate a test result, and the test result is sent to the result register 14 to be stored.
In other embodiments, the physical layer 120 of the second chip includes the comparator 22. After the second chip receives the test signal, the test signal may be input to the comparator 22 via the input/output unit 21, and the comparator 22 may determine whether the received test signal is consistent with the expected test signal, generate a test result, and send the test result to the result register 14 for storage.
In other embodiments, the physical layer 120 of the second chip may further include a result register 23, and the comparator 22 determines whether the received test signal is consistent with the expected test signal, and outputs the result to the result register 23.
In other embodiments, the physical layer 120 of the second chip may further include a built-in self-test unit 24, where the built-in self-test unit 24 includes a parameter scan controller and a pattern generator. The control signal sent by the basic input/output system can be sent to the second chip by the first chip, the built-in self-test unit 24 of the second chip executes parameter scanning and test pattern generation, then the test signal is transmitted to the first chip according to the test pattern, the input/output unit 12 of the first chip receives the test signal and inputs the test signal to the comparator 13, the comparator 13 judges whether the received test signal is expected to be consistent or not, a test result is generated, and the test result is sent to the result register 14 for storage.
It should be noted that the built-in self-test unit may be laid out on the physical layer of the chip, or may be laid out in the controller of the chip.
The test algorithm provided by the embodiment of the application is used for realizing the hardware test method provided by the embodiment of the application, wherein the hardware to be tested is the physical layer of the first chip or the second chip. The test algorithm may run inside the BIOS, or inside the chip controller, or inside the physical layer, or inside the BIST, or in the Processor (Processor), to test the hardware under test.
Hardware testing method
Based on the above system, the embodiments of the present application provide a hardware testing method that can be executed by the hardware testing device 102 in the above system embodiments, and the hardware testing method will be described in detail below through a plurality of embodiments.
FIG. 2 is a flow chart of a hardware testing method of one embodiment of the application. As shown in fig. 2, the hardware testing method includes the steps of:
in step 210, a target area is determined from a test chart, which includes a×b areas.
Wherein A, B are integers greater than 2. The test states of the various regions in the test pattern may be recorded by a state array from which the computer may determine the target region from the test pattern. The test states of the markers in the state array include tested and to-be-tested, and the target area is determined from the areas marked to be to-be-tested. And the computer sequentially determines one or more areas with corresponding test states to be tested as target areas according to the state array, or sequentially performs hardware test by adopting test parameters corresponding to each target area according to the state array.
If a region is not marked as measured and is not marked as measured, the region is in an unmeasured state and the region to be measured is determined from the unmeasured region.
The state array comprises two arrays, one for recording the tested state of the area and the other for recording the tested state of the area, for example, the state array comprises a state array 1 and a state array 2, if the value of the tested state of the area is a first value and the value of the tested state of the area is a third value in the state array 1, the tested state of the area is tested, if the value of the tested state of the area is a second value and the value of the tested state of the area is a fourth value in the state array 2, the tested state of the area is tested, and if the value of the tested state of the area is a second value and the value of the tested state of the area is a third value in the state array 2, the tested state of the area is not tested. The computer determines a target area from the areas with the third value corresponding to the test state according to the state array 2.
After the parallel test is completed under the test parameters corresponding to the target area, the state array is updated, namely, the test state of the target area is updated to be tested in the state array, and if the number of errors corresponding to at least one signal line after the parallel test is within the value range, the test state of an unmeasured area adjacent to the target area is marked as to-be-tested. If the number of the error codes of the plurality of signal lines after the parallel test is not in the value range, the state updating operation of the area to be tested is not executed. Wherein, the value range is preset. Alternatively, the value range is (0, 255), i.e., greater than 0 and less than 255. Illustratively, the computer updates the value of the test state representing the target area in the state array 1 from a first value to a second value, and updates the value of the test state representing the target area in the state array 2 from a third value to a fourth value, i.e., updates the test state of the target area to tested. The computer updates the value of the test state of the region to be tested in the state array 2 from the fourth value to the third value, namely, updates the test state of the region to be tested, wherein the region to be tested is an unmeasured region adjacent to the target region in the test chart. The state array may be a boolean matrix.
Step 220, under the test parameters corresponding to the target area, performing parallel test on a plurality of data channels included in the hardware to be tested, and determining the number of bit errors of the transmission data on the signal lines in the test process, wherein each data channel includes a plurality of signal lines.
And determining a target signal line in each data channel, and carrying out parallel test on a plurality of target signal lines corresponding to a plurality of data channels under test parameters corresponding to the target area. For example, parallel testing is performed on g target signal lines corresponding to g data channels, where g is an integer greater than 1. If the hardware to be tested comprises G data channels, the parallel test is carried out on the G data channels each time, G is an integer greater than 1, and G is smaller than or equal to G.
Optionally, each signal line in the data channel is sequentially determined as a target signal line, and the method comprises the steps of transmitting first test data and second test data in parallel through a plurality of data channels, wherein the first test data is transmitted through the target signal line, the second test data is transmitted through signal lines except the target signal line in the data channel, and determining the number of errors after the first test data is transmitted through the target signal line as the number of errors of the transmission data on the target signal line.
The method comprises the steps of performing parallel test on g signal lines in g data channels, firstly determining the s-th signal line in each data channel as a target signal line, transmitting first test data and second test data in parallel through the g data channels, respectively transmitting the first test data on the g target signal lines, respectively transmitting second test data on signal lines except the target signal lines in the g data channels, and finally obtaining the error code quantity of the first test data transmitted by each signal line in the g target signal lines.
And determining each signal line in the data channels as a target signal line in turn, and completing the test of each signal line in the g data channels through parallel test of w rounds of g data channels, wherein w is an integer greater than 1, and the value of s is less than or equal to w.
Optionally, the first test signal is a test signal generated in a signal pattern (VICTIM PATTERN) as an observation object, and the second test signal is a test signal generated in an interference signal pattern (Aggressor pattern).
The Bit width of each data channel is 1 byte, when the Test is carried out in a first round, as shown in the following table 1, the signal line on Bit0 of each data channel in 10 data channels is determined to be a target signal line, the first Test signal and the second Test signal are transmitted in parallel through 10 data channels, wherein the first Test signal is transmitted through 10 signal lines on Bit0, the second Test signal is transmitted through 70 signal lines on other bits, the number of Bit errors of data transmitted through 10 signal lines on Bit0 can be obtained, when the Test is carried out in a second round, the signal line on Bit1 of each data channel in 10 data channels is determined to be a target signal line, the first Test signal and the second Test signal are transmitted in parallel through 10 data channels, the first Test signal is transmitted through 10 signal lines on Bit1, the second Test signal is transmitted through 70 signal lines on other bits, the number of Bit errors of data transmitted through 10 signal lines on Bit1 can be obtained, and the Test is carried out in a second round, and the Test is carried out on each data channel.
TABLE 1
Optionally, in the s-th round of test, determining the s-th signal line in each data channel as a target signal line, and executing the steps of transmitting first test data and second test data in parallel through a plurality of data channels under test parameters corresponding to a target area, transmitting the first test data on the plurality of target signal lines, transmitting the second test data through signal lines except the target signal lines in the plurality of data channels to obtain the number of bit errors corresponding to each signal line in the plurality of target signal lines, updating the test state of the target area into a tested state array, and marking the test state of an unmeasured area adjacent to the target area as to be tested if the number of bit errors corresponding to at least one target signal line is in a value range after the parallel test, and determining the target area from the test chart again according to the state array until the state value to be tested does not exist in the state array. If the bit width of the data channel is w, then w rounds of testing need to be performed to complete testing of each target signal line in the plurality of data channels.
And 230, generating a test result of the hardware to be tested according to the number of bit errors corresponding to each signal line.
The test result comprises the number of error codes of each signal wire under the test parameters corresponding to each target area or the number of error codes of each signal wire under the test parameters corresponding to each area.
For example, one scan of the plurality of target signal lines is completed under the test parameters corresponding to one region, and the computer may output error data obtained by each scan of the plurality of target signal lines in each test. As shown in fig. 3, assuming that 10 data channels are tested in parallel, one scan of 10 target signal lines DQ0-DQ9 is completed under a test parameter corresponding to an area, and the number of errors obtained by each scan (scan) of 10 target signal lines DQ0-DQ9 in each test round is output in groups by a computer, for example, the test parameter corresponding to scan1 is vref_0, the number of errors corresponding to scan 0-DQ9 in turn is "FF, FF, FF, FF, FF, FF, FF, FF, FF, FF", the test parameter corresponding to scan2 is vref_0, the number of errors corresponding to scan1, and dq0-DQ9 in turn is "FF, FF, FF, FF, FF, FF, FF, FF, FF, FF", and FF is a hexadecimal numerical representation.
Alternatively, the test result may be a test result graph. After the testing of one or more sub-test patterns is completed, the computer generates a test result pattern corresponding to each signal line according to the number of bit errors obtained by testing each signal line on the test parameters corresponding to the target areas.
The test result graph may be a Shmoo eye diagram. For example, as shown in fig. 4, according to the number of bit errors corresponding to each of the target signal lines DQ0 through DQ9 shown in fig. 3, an eye pattern corresponding to each signal line is generated, resulting in 10 eye patterns corresponding to DQ0 through DQ 9.
If the test result diagram is a Shmoo eye diagram, in one possible implementation manner, a filling process is performed on the target area on the test result diagram corresponding to each signal line according to the number of bit errors corresponding to each signal line, where the filling process may be digital filling or color filling. If the data is filled, the error code quantity is filled into the target area of the test result graph. If the color filling is adopted, filling the color corresponding to the value range into a target area of the test result graph if the error code quantity is in the value range, wherein the value range comprises at least three colors, and different value ranges correspond to different filling colors. For example, if the number of errors is within (0, 255), the target area is filled with yellow, if the number of errors is 0, the target area is filled with green, and if the number of errors is 255, the target area is filled with red.
Wherein "plurality" means two or more.
TABLE 2
| Index (Index) | Scan (Scan) | Conventional test-Shmoo eye diagram | Parallel test-Shmoo eye diagram |
| 1 | Vref=0,phase=0 | DQ0 Result | DQ0-9 Result |
| 2 | Vref=1,phase=0 | DQ0 Result | DQ0-9 Result |
| ... | ... | ... | ... |
| 64 | Vref=63,phase=0 | DQ0 Result | DQ0-9 Result |
| 65 | Vref=0,phase=1 | DQ0 Result | DQ0-9 Result |
| ... | ... | ... | ... |
| 8192 | Vref=63,phase=127 | DQ0 Result | DQ0-9 Result |
| 8193 | Vref=0,phase=0 | DQ1 Result | Done |
| ... | ... | ... | |
| 81920 | Vref=63,phase=127 | DQ9 Result | |
| | Done | |
Wherein Vref represents the reference voltage, phase represents the phase, and Result represents the Result.
In summary, according to the hardware testing method provided by the embodiment, after the target area is determined from the test chart, the parallel test is performed on the plurality of data channels included in the hardware to be tested under the test parameters corresponding to the target area, and compared with the measurement performed on each signal line in each data channel one by one, the parallel test method for the plurality of data channels can greatly reduce the time consumed by the test and improve the efficiency of the hardware test. For example, as shown in table 2, if 10 data channels are tested in parallel, a round of test can output test results of 10 signal lines, and the test efficiency is improved by 10 times compared with the original test of each signal line.
In one possible implementation, the test chart may also be divided, and then the hardware to be tested is subjected to partition test, as shown in fig. 5, where the implementation steps are as follows.
Step 510, dividing the test chart into at least two subtest charts, wherein the subtest charts comprise a×b areas.
Wherein the test chart includes a×b areas, a and B are integers equal to or greater than 2, and a is smaller than a and B is smaller than B.
The total size of the test chart and the partition size for dividing the sub-test chart are preset in the computer, for example, the partition size is a row and b column, and the test chart is divided into at least two sub-test charts according to the partition size, so that each sub-test chart comprises a multiplied by b areas. If the total size of the test chart is (a×m) × (b×n), dividing the test chart into m×n sub-test charts, where m and n are integers greater than 1. For example, the total size of a test chart set in advance in a computer is 128×64, the partition size is 32×32, and the test chart may be divided into 4×2 sub-test charts according to the partition size, each sub-test chart including 32×32 areas.
The total size of the test chart is set according to the number of combinations of two test variables, for example, the two test variables are different in value, and (c×m) × (d×n) combinations, that is, (c×m) × (d×n) test operating points are obtained, and the total size of the test chart is set to (a×m) × (b×n), where c and d are integers greater than 2, a is c which is e times, b is d which is f times, and e and f are positive integers.
The above-mentioned region refers to pixel regions, and each pixel region may be composed of e×f pixel points.
Step 520, generating a sub-graph state array, wherein the sub-graph state array is used for recording the test states of the areas in the sub-test chart.
The sub-graph state array is used for recording the test states of the areas in the sub-test graphs. The sub-image state array comprises two arrays, namely a first array and a second array, wherein the first array is used for recording the measured state of the area in the sub-test chart, and the second array is used for recording the measured state of the area in the sub-test chart. Alternatively, the sub-graph state array may take the form of a matrix, such as a Boolean matrix.
The computer may generate the sub-image state array according to the size of the sub-test chart or according to the number of areas included in the sub-test chart. Optionally, the number of elements included in each array in the sub-graph state array is the same as the number of areas included in the sub-graph, and one element indicates the test state of one area. For example, if the subtest chart includes a×b regions, the subtask state array includes 2×a×b elements. If the sub-graph state arrays are boolean matrices, the boolean matrix corresponding to each array is also the same size as the sub-test pattern, both the sizes being a×b. Or the number of elements contained in each array is greater than the number of areas contained in the subtest chart and less than 2 times the number of areas contained in the subtest chart, for example, if the subtest chart includes a×b areas, the subtest state array includes 2× (a+1) × (b+1) elements.
And 530, respectively executing the following processing for one or more sub-test patterns in at least two sub-test patterns, namely determining a target area from the sub-test patterns according to the sub-test pattern state arrays, carrying out parallel test on a plurality of data channels included in the hardware to be tested under test parameters corresponding to the target area, wherein each data channel comprises a plurality of signal lines, and updating the sub-test pattern state arrays according to the error code quantity of transmission data on the signal lines in the test process until the sub-test pattern state arrays indicate that the sub-test patterns have no target area, and initializing the sub-test pattern state arrays.
The computer performs the following processing for each of the one or more subtest charts:
Determining a sub-test chart to be a target area to be tested according to the test state of the sub-chart state array mark, performing parallel test on a plurality of data channels under the test parameters corresponding to the target area to determine the error code quantity of the transmission data on the signal wire in the test process;
If the sub-graph state array is determined to further comprise state information to be tested, returning to the step of determining the target area, and continuing to perform parallel testing of a plurality of data channels on the sub-test graph;
If the sub-graph state array does not include the state information to be tested, initializing the sub-graph state array, determining the next sub-test graph, and executing the processing procedure for the next sub-test graph until the hardware test for one or more sub-test graphs is completed.
The target area may be one or more at a time determined during the test. If the data is a plurality of target areas, the following processing can be sequentially executed on each target area, namely, under the test parameters corresponding to the target areas, parallel test is carried out on a plurality of data channels, the number of bit errors of transmission data on a signal line in the test process is determined, and the state array of the sub-graph is updated according to the number of bit errors of the transmission data on the signal line in the test process.
Related parallel testing
The parallel testing of the plurality of data channels included in the hardware to be tested is performed under the test parameters corresponding to the target area, please refer to the detailed description of step 220 above, and the detailed description is omitted here.
Related status update
And after parallel testing is carried out on a plurality of data channels under the test parameters corresponding to the target areas, updating the sub-graph state array according to the error code quantity of the transmission data on the signal lines in the test process until the sub-graph state array indicates that the target areas are not present in the sub-test graph, and initializing the sub-graph state array.
After parallel testing is carried out on a plurality of data channels according to the testing parameters corresponding to the target area, the testing state of the target area is updated to be tested in the sub-graph state array, and if the number of errors corresponding to at least one signal line after the parallel testing is within the value range, the testing state of an unmeasured area adjacent to the target area is marked to be tested, so that the updating of the sub-graph state array is completed.
For example, assuming that 10 data channels are tested in parallel, one scan of 10 target signal lines DQ0-DQ9 is completed under a test parameter corresponding to one target area, so as to obtain the number of bit errors corresponding to each of the 10 target signal lines DQ0-DQ9, if the number of bit errors corresponding to at least one signal line in the 10 target signal lines DQ0-DQ9 is located in a value range, the test status of the unmeasured area adjacent to the target area is marked as to-be-tested, for example, the number of bit errors of 10 target signal lines DQ0-DQ9 is "0, FF,0, and if the error code number corresponding to DQ5 is in the value range (0.255), marking the test state of the unmeasured area adjacent to the target area as the test state.
With respect to the update of the test status of the target area, updating the value representing the test status of the target area in the first array from the first value to the second value, and updating the value representing the test status of the target area in the second array from the third value to the fourth value, indicates that the target area is updated to be tested. And updating the test state of the unmeasured area adjacent to the target area, and updating the value representing the test state of the measured area in the second group from the fourth value to the third value, wherein the measured area is the unmeasured area adjacent to the target area in the test chart. For example, the first array and the second array are both boolean matrices, if the test status of a region is tested, the value of the test status of the region is 1 in the first array, the value of the test status of the region is 0 in the second array, if the test status of a region is to be tested, the value of the test status of the region is 0 in the first array, the test status of the region is 1 in the second array, if the test status of a region is not tested, the value of the test status of the region is 0 in the first array, the test status of the region is 0 in the second array, and the "not tested" test status herein refers to a test status other than tested and to be tested. After the test, the test state of the target area is updated, the value of the test state of the target area in the first array is updated from 0 to 1, the value of the test state of the target area in the second array is updated from 1 to 0, the value of the test state of the area to be tested in the second array is updated from 0 to 1, and the value of the test state of the area to be tested in the first array is unchanged and still is 0.
Determination of target area
And respectively determining the areas with the third values corresponding to the test states in the subtest chart as target areas according to the second array, or determining the areas with the third values corresponding to the test states in the subtest chart as target areas according to the second array. For example, a region corresponding to a value of 1 in the second group is determined as the target region from the subtest chart.
And when the values in the second group representing the test states are the fourth values, representing that the areas to be tested are not in the sub-test chart of the current test, ending the test on the sub-test chart, determining the next sub-test chart, and continuing the test on the next sub-test chart.
Determination of the region to be measured
The area to be measured needs to be determined according to the number of bit errors when data is transmitted on the signal line. And presetting a value range in the computer, and marking the test state of an unmeasured area adjacent to the target area as to-be-tested if the error code number indicated by the test result is in the value range. If the error code quantity indicated by the test result is outside the value range, the state update of the area to be tested is not executed. Alternatively, the value range is (0, 255), i.e., greater than 0 and less than 255. If the number of errors indicated by the test result is within (0, 255), the test status of the unmeasured area adjacent to the target area is marked as to be tested, and if the number of errors indicated by the test result is 0 or 255, the status update of the area to be tested is not executed.
And 540, generating a test result of the hardware to be tested according to the number of bit errors corresponding to each signal line.
For a detailed implementation of step 540, please refer to the description in step 230, and the detailed description is omitted here.
In summary, in the hardware testing method provided by the embodiment of the present application, the original test chart is divided into a plurality of subtest charts, each subtest chart includes a×b areas, and a subtest state array is generated to record the test states of the areas in the subtest charts, by multiplexing the subtest chart state array, for each subtest chart in one or a part of the plurality of subtest charts, parallel testing of a plurality of data channels is executed respectively, and compared with recording the test states of the whole test chart, the memory occupied by the test states of the subtest charts is obviously reduced, thereby greatly reducing the memory requirements during hardware testing.
In one possible implementation, based on the embodiment shown in fig. 5, an edge state array is further used to record the test states of the edge regions in the plurality of subtest charts, and after the test of one subtest chart is completed, the subtest chart of the next test is determined based on the edge state array. The edge state array is described below in three sections.
Generation of edge state arrays
The computer also generates an edge state array, wherein the edge state array is used for recording the test states of the edge areas in at least two subtest charts. The edge state array comprises two arrays, namely a third array and a fourth array, wherein the third array is used for recording the measured states of the edge areas in at least two subtest charts, and the fourth array is used for recording the measured states of the edge areas in at least two subtest charts. Alternatively, the edge state array may take the form of a matrix, such as a boolean matrix.
The computer may generate an edge state array according to the size of the subtest chart or an edge state array according to the number of edge regions included in the subtest chart. Optionally, each of the edge state arrays includes the same number of elements as the sum of the edge regions in the at least two subtest charts. For example, if the subtest chart includes a×b areas, the subtest chart correspondingly uses (2a+2b-4) ×2 elements in the edge state array, and if the subtest chart includes m×n areas, the edge state array includes (2a+2b-4) ×2×m×n elements. Or the number of elements used in each array is 4 more than the number of edge areas in each subtest chart. For example, if the subtest chart includes a×b areas, the subtest chart correspondingly uses (2a+2b) ×2 elements in the edge state array, and if the subtest chart includes m×n areas, the edge state array includes (2a+2b) ×2×m×n elements.
Alternatively, the edge state array may take the form of a matrix, for example, the edge state array may be a boolean matrix. For example, each of the edge state arrays may be a Boolean matrix of size mxn× (2a+2b).
The edge state array may be used to record the test states of the edge regions of all subtest charts. In the embodiment provided by the application, the edge state array is used for recording the test state of the edge area of one or a part of the subtest chart.
The sub-graph state array and the edge state array can be generated according to the sequence or simultaneously, and the generation sequence of the sub-graph state array and the edge state array is not limited.
Updating of edge state arrays
And after parallel testing is carried out on a plurality of data channels according to the test parameters corresponding to the target area, determining that the target area is positioned at the edge of the subtest chart, and updating the test state of the target area in the edge state array to be tested.
That is, in the process of updating the test status, it is further required to determine whether the target area is located at the edge of the subtest chart, if so, the test status of the target area in the edge status array is updated. If the target area does not belong to the edge of the subtest chart, the test state of the target area is not updated on the edge state array.
And updating the edge state array, if the test state of the target area is updated to be tested, updating the value representing the test state of the target area in the third array from the fifth value to the sixth value, and updating the value representing the test state of the target area in the fourth array from the seventh value to the eighth value.
Regarding the update of the test status of the edge area, if the test status of one edge area is tested, the value of the test status of the edge area is 1 in the third array, the value of the test status of the edge area is 0 in the fourth array, if the test status of one edge area is to be tested, the value of the test status of the edge area is 0 in the third array, the test status of the edge area is 1 in the fourth array, if the test status of one edge area is not tested, the value of the test status of the edge area is 0 in the third array, and the test status of the edge area is 0 in the fourth array.
After the test, the test state of the target area is updated, if the target area is the edge area of the subtest chart, the value of the test state of the target area in the third array is updated from 0 to 1, and the value of the test state of the target area in the fourth array is updated from 1 to 0.
Optionally, after determining that the area to be tested is located at an edge of any one of the subtest charts, the computer updates a test state of the area to be tested in the edge state array, that is, if the area to be tested is located at an edge of any one of the at least two subtest charts, the test state of the area to be tested in the edge state array is marked as to be tested, where the area to be tested is an unmeasured area adjacent to the target area in the test chart.
The area under test may be located at the edge of the subtest pattern under test or may be located at the edge of other subtest patterns adjacent to the subtest pattern. If the region to be tested is positioned at the edge of the sub-test chart under test, the test state of the region to be tested in the sub-image state array and the edge state array is required to be updated to be tested, and if the region to be tested is positioned at the edge of other sub-test charts adjacent to the sub-test chart, the test state of the region to be tested in the edge state array is required to be updated to be tested. If the area to be tested does not belong to the edge of any sub-test chart, the test state of the area to be tested is not updated by the edge state array.
If the test state of the area to be tested is updated to be tested, the value representing the test state of the area to be tested in the fourth array is updated from the eighth value to the seventh value, for example, the value representing the test state of the edge area in the fourth array is updated from 0 to 1.
If there is an update of the edge state array, it may be performed simultaneously with the update of the sub-graph state array or sequentially, and the execution order of the two is not limited.
Determining a subtest pattern for a next test based on an array of edge states
After the test of each target area in the subtest chart is completed, determining the subtest chart of the next test according to the edge area which corresponds to the test state in the edge state array and is to be tested, updating the test state of the edge area of the subtest chart of the next test to the initialized subtest state array from the edge state array, and executing the test of each target area in the subtest chart of the next test.
For example, when the seventh value exists in the fourth array, determining the subtest chart corresponding to the region with the seventh value as the subtest chart of the next test, and copying the value of the test state of the edge region of the subtest chart of the next test from the fourth array to the initialized second array.
If the sub-test pattern is indicated to have no area to be tested by the sub-test pattern, the test of each target area in the sub-test pattern is completed, then the sub-test pattern with the edge area to be tested is determined to be the sub-test pattern of the next test according to the edge state array, the test state of the edge area of the sub-test pattern of the next test is updated to the corresponding position in the initialized sub-test pattern from the edge state array, then the execution step 330 is returned, and the sub-test pattern of the next test is determined again based on the edge state array until the edge state array indicates that the sub-test pattern to be tested does not exist, and the hardware test corresponding to one or more sub-test patterns is completed.
In summary, in the hardware test method provided by the embodiment of the application, the original test pattern is divided into a plurality of sub-test patterns, each sub-test pattern includes a×b areas, and a sub-test state array is generated to record the test states of the areas in the sub-test pattern, after completing the test of one sub-test pattern, the sub-test pattern state array is initialized, the initialized sub-test state array is used to continue to participate in the test of the next sub-test pattern, the test processing of one or more sub-test patterns is completed by multiplexing the sub-test pattern state array, and the sub-test state array and the edge state data can be multiplexed for each round of parallel test of a plurality of data channels.
In the method, an edge state array is also generated and used for recording the test states of the edge areas of a plurality of subtest patterns, in the process of selecting the to-be-tested area, the to-be-tested area possibly is selected from the edge areas of other subtest patterns adjacent to the subtest patterns, the to-be-tested state of the to-be-tested area is updated into the edge state array, after the test of the subtest patterns is completed, the subtest patterns of the next test can be accurately positioned through the to-be-tested state existing in the edge state array, the subtest patterns without the target area do not need to be tested, the workload of hardware test is reduced, and the speed of hardware test is improved.
FIG. 6 is a flow chart of a hardware testing method of one embodiment of the application. As shown in fig. 6, an exemplary test procedure of each of w-round tests of a plurality of data channels in the hardware test method provided in the above embodiment is described, and the steps are as follows:
step 601, start.
Step 602, partition size (a×b), total size of test pattern (a×m) × (b×n), number of subtest pattern (m×n).
The preset partition size is (a×b) and the total size of the test chart is (a×m) × (b×n), and the computer divides the test chart with the total size of (a×m) × (b×n) into (m×n) sub-test charts according to the partition size (a×b). The partition size refers to a size for dividing the subtest chart.
Wherein (a×b) represents a row×b column, (m×n) represents m row×n column, and (a×m) × (b×n) represents (a×m) row× (b×n) column.
Step 603, initialize the following Boolean array to full False visited, to_visual, edge_ visited, edge_to_visual.
The boolean array is represented by a value of 0 for False and a value of 1 for true. Boolean arrays visited, to_visual, edge_ visited, edge_to_visual, wherein visited refers to the first array, to_visual refers to the second array, edge_ visited refers to the third array, and edge_to_visual refers to the fourth array.
The boolean array is generated based on the dimensions of the subtest chart, visited and to_visual are boolean matrices of size (a×b), edge_ visited and edge_to_visual are boolean matrices of size m×n× (2a+2b).
In step 604, the center point (V0, T0) of the test chart is obtained by I/O Training.
The computer determines the center point (V0, T0) from the test chart by means of Input/Output (I/O) Training (Training).
The present example is illustrated with test variables Vref and Timing. One area in the test chart is represented by one cell, and in the test chart set according to the test variable, each cell corresponds to one working point, and one working point corresponds to one set of test parameters (Vref, timing). The center point refers to an operating point located at the center of the test chart.
Step 605, moving from (V0, T0) to one direction, running a test for its corresponding test parameter once every moving cell, testing multiple target signal lines in parallel until there is at least one bit error number corresponding to the target signal line in the interested range, and taking the last tested working point (V, T) as the initial working point.
The range of interest is the value range. The movement from (V0, T0) to one direction may be any one of up, down, left and right directions. For example, from (V0, T0), each time a cell moves downward, a test (i.e. a scan) is performed for its corresponding test parameter until there is at least one bit error number corresponding to the target signal line within (0, 255), and the operating point (V, T) of the last test is taken as the initial operating point.
Step 606, calculate the subtest chart where the initial working point is located.
The test chart is divided into m rows by n columns of sub-test charts, and the positions (ri, rj) of the initial operating points in the above m by n sub-test chart array are determined. The (ri, rj) is calculated using a floor down function:
ri=floor(V/a);
rj=floor(T/b);
Wherein, the values of i and j are positive integers.
Step 607, set visited to full False, and set to_visual to full False.
Before the test of each subtest chart starts, visited and to_visual are initialized, and visited and to_visual are set to full False.
At step 608, 2 (a+b) values in edge_to_visual [ ri, rj ] are copied to the top, bottom, left and right edges of to_visual.
Here, edge_to_visual [ ri, rj ] represents the address of the edge area of the edge_to_visual where the subtest chart (ri, rj) is recorded. The relationship of copying 2 (a+b) values from edge_to_visual [ ri, rj ] to to_visual corresponds is as follows:
upper edge: to_visit [0, ] = edge_to_visit [ ri, rj,2a:2a+b ];
lower edge: to_visit [ a-1, ] = edge_to_visit [ ri, rj,2a+b:2a+2b ];
Left edge: to_visit [: 0] = edge_to_visit [ ri, rj,: a ];
Right edge: to_visual [: b-1] = edge_to_visual [ ri, rj, a:2a ];
Wherein, to_visual is a two-dimensional Boolean matrix of a_visual [ 0], to_visual [ 0] represents b positions of an upper edge of which the start position is 0 in to_visual, [ a-1 ], to_visual [ 0] represents b positions of a lower edge of which the start position is (a-1) in to_visual, [ 0] represents a left edge of which the end position is 0 in to_visual, [ b-1] represents a position of a right edge of which the end position is (b-1) in to_visual, [ edge_to_visual ] is a three-position Boolean matrix of m×n×2 (a+b), edge_to_visual [ ri, rj ] represents a position of 2 (a+b) corresponding to (ri, rj) in an edge_to_visual, [ 2 a+1 ] in to (b), and edge_2 to [ b ] in an edge_visual, [ 2_1 ] represents a position of 2+b ] corresponding to (b+1) in an edge_to_visual, [ 2_ri ] in an edge to_2+b ] in an edge_visual, [ 2_1 ] in an edge to [ 2+b+1 ] in an edge to [ 2_visual ] in an edge to [ 2+1 ] in an edge to [ 2_visual ] in a_visual, [ 2 ] in a+1 ] in a position of the edge.
In step 609, the position (ci, cj) of the operating point (V, T) in the subtest chart is calculated.
The sub-test chart package a is row by b column, and the position (ci, cj) of the working point (V, T) in the sub-test chart of the above-mentioned a by b is determined.
Calculating (ci, cj) using a remainder (mod) function:
ci=V mod a;
cj=T mod b。
at step 610, the I/O operating point is configured as (V, T), the test is run and the results are recorded.
The computer configures the testing parameters of I/O work as V and T, runs the test, and records the result of the hardware test to be tested, such as the number of bit errors corresponding to each target signal line. For example, the hardware to be tested includes 10 data channels, each scan may obtain the number of bit errors corresponding to 10 target signal lines, and record the number of bit errors corresponding to 10 target signal lines.
At step 611, visited and to_visual are updated.
The values at positions (ci, cj) in to_visual and visited are updated:
to_visit[ci,cj]=False;
visited[ci,cj]=True。
Step 612, subroutine 1 is performed by updating edge_to_visual [ ci, cj ] and edge_ visited [ ci, cj ].
The execution of the subroutine 1 determines the position of the operating point (V, T) in the subtest chart, and updates edge_to_visual and edge_ visited if the operating point (V, T) is located at the edge of the subtest chart. As shown in fig. 7, the update procedure of the subroutine 1 is as follows:
Judging the value of ci;
if ci=0, the upper edge of the sub-test chart at the working point (V, T) is indicated, and edge_to_visual and edge_ visited are updated:
edge_to_visit[ri,rj,2a+cj]=False;edge_visited[ri,rj,2a+cj]=Ture;
If ci=a-1, the lower edge of the subtest chart representing the operating point (V, T) position is updated to update edge_to_visual and edge_ visited:
edge_to_visit[ri,rj,2a+b+cj]=False;edge_visited[ri,rj,2a+b+cj]=Ture;
if the cj is 0< ci < a-1, judging the cj value;
if cj=0, the left edge of the sub-test chart at the working point (V, T) is indicated, and edge_to_visual and edge_ visited are updated:
edge_to_visit[ri,rj,ci]=False;edge_visited[ri,rj,ci]=Ture;
if cj=b-1, then the right edge of the subtest chart representing the operating point (V, T) position is updated for edge_to_visual and edge_ visited:
edge_to_visit[ri,rj,a+ci]=False;edge_visited[ri,rj,a+ci]=Ture;
if 0< cj < b-1, it indicates that the operating point (V, T) is not located at the edge of the subtest chart.
Step 613, determining whether there is at least one error code number corresponding to the target signal line within the interested range.
If the number of bit errors corresponding to at least one target signal line is within the range of interest, step 614 is performed, and if not, step 615 is performed, i.e., if the number of bit errors corresponding to the target signal line is not within the range of interest. For example, it is determined whether the number of bit errors corresponding to at least one target signal line is within (0, 255), if yes, step 614 is performed, and if not, step 615 is performed.
At step 614, subroutine 2 is performed to update to_visual and edge_to_visual.
And executing a subroutine 2, determining whether an unmeasured area exists in the upper, lower, left and right areas adjacent to the (ci, cj), and marking the unmeasured area as to-be-measured if the unmeasured area exists. As shown in fig. 8, the update procedure of the subroutine 2 is as follows:
Judging ci value.
1) If ci=0, it indicates that the working point (V, T) is located at the upper edge of the subtest chart, and the region (ci+1, cj) below (ci, cj) is marked as to-be-measured, that is, updated to_visual:
to_visit [ ci+1, cj ] = -visited [ ci+1, cj ], wherein ". To" represents the inverse operation, for example, visited [ ci+1, cj ] = False, then-visited [ ci+1, cj ] = Ture, then updated to_visit [ ci+1, cj ] = Ture, otherwise visited [ ci+1, cj ] = Ture, then-visited [ ci+1, cj ] = False, then updated to_visit [ ci+1, cj ] = False;
after updating to_visual, judging whether ri >0;
If ri >0, it indicates that there is a sub-test chart (ri-1, rj) above the sub-test chart (ri, rj) in the sub-test chart array, and the test state of the area adjacent to and above (ci, cj) in the sub-test chart (ri-1, rj) is updated in edge_to_visit:
edge_to_visit[ri-1,rj,k]=~edge_visited[ri-1,rj,k],k=2a+b+cj;
if not, the sub-test chart (ri, rj) is located at the upper edge of the sub-test chart array, and the step of judging cj value is executed.
2) If ci=a-1, it indicates that the working point (V, T) is located at the lower edge of the subtest chart, and the region (ci-1, cj) above (ci, cj) is marked as to be tested, that is, updated to_visual is:
to_visit[ci-1,cj]=~visited[ci-1,cj];
after updating to_visual, judging whether ri < m-1;
if ri < m-1, it indicates that the subtest chart (ri+1, rj) exists below the subtest chart (ri, rj) in the subtest chart array, and the test state of the area adjacent to (ci, cj) and below (ci, cj) in the subtest chart (ri+1, rj) is updated in edge_to_visual:
edge_to_visit[ri+1,rj,k]=~edge_visited[ri+1,rj,k],k=2a+cj;
If not, ri < m-1, it means that the subtest chart (ri, rj) is located at the lower edge of the subtest chart array, and the step of "judging cj value" is executed.
3) If 0< ci < a-1, it indicates that the working point (V, T) is not located at the upper and lower edge positions of the subtest chart, and the upper area (ci-1, cj) and the lower area (ci+1, cj) are marked as to-be-measured, that is, updated to_vision is:
to_visit[ci-1,cj]=~visited[ci-1,cj];to_visit[ci+1,cj]=~visited[ci+1,cj];
After the update to_visual, a step of "judging cj value" is performed.
Judging cj to take on value.
1) If cj=0, it indicates that the working point (V, T) is located at the left edge of the subtest chart, and the area (ci, cj+1) on the right side of (ci, cj) is marked as to-be-tested, that is, updated to_visual:
to_visit[ci,cj+1]=~visited[ci,cj+1];
after updating to_visual, judging whether rj >0;
If rj >0, the test status of the area adjacent to (ci, cj) and left of (ci, cj) in the subtest chart (ri, rj-1) is updated in edge_to_visual by the subtest chart (ri, rj-1) that exists on the left side of the subtest chart (ri, rj) in the subtest chart array:
edge_to_visit[ri,rj-1,k]=~edge_visited[ri,rj-1,k],k=a+ci;
If not ri >0, then it indicates that the subtest chart (ri, rj) is located at the left edge in the subtest chart array, and step 615 is performed.
2) If cj=b-1, it indicates that the working point (V, T) is located at the right edge of the subtest chart, and the area (ci, cj-1) on the left side of (ci, cj) is marked as to-be-tested, that is, updated to_visual:
to_visit[ci,cj-1]=~visited[ci,cj-1];
after updating to_visual, judging whether rj < n-1;
If rj < n-1, it indicates that there is a subtest chart (ri, rj+1) on the right side of the subtest chart (ri, rj) in the subtest chart array, and the test state of the area adjacent to (ci, cj) and located on the right side of (ci, cj) in the subtest chart (ri, rj+1) is updated in edge_to_visual:
edge_to_visit[ri,rj+1,k]=~edge_visited[ri,rj+1,k],k=ci;
if not ri < n-1, then it indicates that the subtest pattern (ri, rj) is located at the right edge of the subtest pattern array, and step 615 is performed.
3) If 0< cj < b-1, it indicates that the working point (V, T) is not located at the left and right edge positions of the subtest chart, and the left area (ci, cj-1) and the right area (ci, cj+1) are marked as to-be-measured, that is, updated to_vision is:
to_visit[ci,cj-1]=~visited[ci,cj-1];to_visit[ci,cj+1]=~visited[ci,cj+1];
after updating to_visual, step 615 is performed.
Step 615, determine if to_visual is False.
After the test of the working point (V, T) is completed, it is determined whether to_visual is False, that is, it is determined whether there is any region to be tested in the subtest chart, if yes, step 618 is executed, and if not, step 616 is executed.
At step 616, a new set of (ci, cj) is found such that to_visit [ ci, cj ] =true and visited [ ci, cj ] =false.
In the subtest chart, one (ci, cj) is redefined, and the redefined (ci, cj) is to_visual [ ci, cj ] =true and visited [ ci, cj ] =false, that is, this is a region to be measured.
Step 617 calculates the new (ci, cj) corresponding operating point.
According to the corresponding working point of the redetermined (ci, cj) in the test chart, the calculation mode is as follows:
v=ri×a+ci;
t=rj×b+cj。
after step 617 is performed, the process returns to step 610.
Step 618 determines if edge_to_visual is False.
Judging whether the edge_to_visual is False, namely judging whether there are more sub-test patterns to be tested, if yes, indicating that there are no sub-test patterns to be tested, executing step 620; if not, that is, if edge_to_visual is not False, it indicates that there is a subtest chart to be tested, step 619 is executed.
Step 619, find a new set of (ri, rj) such that edge_to_visual [ ri, rj ] is not False.
Among the subtest charts, a subtest chart (ri, rj) is newly determined, and the edge_to_visual [ ri, rj ] of the newly determined subtest chart (ri, rj) is not False, that is, the subtest chart to be tested.
As shown in fig. 9, the test run is illustrated. First, a plurality of data channels included in hardware to be tested are tested in parallel for the sub test chart (ri, rj) on the right side of the dividing line. Running a test at the working point 701, recording the average error number (errcnt) as 64, marking the state of the working point 701 as the measured state of the region, and marking the working points positioned at the left, right, lower three sides of the working point 701 as the measured state of the region if 0< errcnt=64 < maximum error number (err_max); moving one grid leftwards, performing a test at an operating point 702, recording the average error number as 133, marking the operating point 702 in a state of being tested in the area, marking the operating point at the left lower side of the operating point 702 as being tested in the area, moving one grid leftwards, performing the test at the operating point 703, recording the average error number as 169, marking the operating point 703 in a state of being tested in the area, marking the operating point at the left edge of a sub-test chart (ri, rj) as being tested in the area, marking the operating point at the upper side and the lower side of the operating point 703 as being tested in the area, marking the operating point at the left side of the operating point 703 as being tested in the edge, moving downwards one grid, performing the test at the operating point 704, recording the average error number as 194, marking the operating point 704 in the area, measuring the state of 0< err=194 err_max, marking the operating point 704 in the left edge of the sub-test chart (ri, rj) as being tested in the area, marking the operating point at the left side of being tested in the area, marking the operating point at the operating point 704 at the right side of being tested in the area, marking the operating point at the position of 0< err=169, and starting the operating point at the end of being tested in the area, marking the operating point at the left side of being tested at the end of 1.209, starting the operating point at the end of the average test point (rj), rj-1) marks the working points located on the upper, lower, left and right sides of the working point 705 as the local area to be measured, and. The average error code number refers to an average value of error code numbers corresponding to a plurality of target signal lines during one scanning. Referring to fig. 10, after the measurement of the subtest chart 801 is completed, the measurement of the subtest chart 802 is started according to the mark to be measured at the edge, and then the test of the subtest chart 803, the subtest chart 804, the subtest chart 805, and the subtest chart 806 is sequentially completed until the measurement of the test chart is completed. The method comprises the steps of marking a tested state in a sub-graph state array and marking an edge to be tested in an edge state array, wherein the marked test state is marked in the sub-graph state array after the tested state in the local area and the tested state in the local area.
Step 620, end.
The test result chart in this embodiment is an eye diagram, if an eye diagram of (a×m) × (b×n) is required to be generated, and the subtest chart is divided according to the size of a×b, then for the memory requirement, visited a×b/8 (Bytes), to_visit requires a×b/8 (Bytes), edge_to_visit requires m×n× (2×a+2×b)/8 (Bytes), edge_ visited requires m×n× (2×a+2×b)/8 (Bytes), as shown in the following table 3, the memory required for testing the hardware to be tested is given by the combination of different eye diagram sizes and different partition sizes, if the eye diagram size is 128×128, the partition size is 32×32, and the total memory required for testing is 0.75kB (kilobytes). Where Bytes are Bytes, 1 kb=1024 Bytes. As shown in table 3, if the partition size is 32×32, shmoo measurements below 128×128 can be satisfied by 1kB memory.
TABLE 3 Table 3
The hardware testing method provided by the embodiment of the application reduces the memory requirement required during hardware testing, and can solve the problems that the Basic Input/Output System (BIOS) resources are limited, the memory use is limited to be within 1kB, and for 128×128 eye diagrams, 34kB memory is required to be occupied when the Shoo measurement is performed in a recursive manner, and 4kB memory is required to be occupied when the Shoo measurement is performed in a non-recursive manner, so that the memory requirement cannot be met.
Hardware testing device
Corresponding to the above method embodiment, fig. 11 shows a schematic diagram of a hardware testing apparatus. As shown in fig. 11, the hardware testing apparatus includes:
The area selection module 901 is configured to determine a target area from a test chart, where the test chart includes a×b areas, and A, B are integers greater than 2;
The parallel test module 902 is configured to perform parallel test on a plurality of data channels included in the hardware to be tested under test parameters corresponding to the target area, and determine the number of bit errors of transmission data on the signal lines in the test process, where each data channel includes a plurality of signal lines;
the result generating module 903 is configured to generate a test result of the hardware to be tested according to the number of bit errors corresponding to each signal line.
In one possible implementation, the parallel test module 902 performs parallel test on a plurality of data channels included in the hardware to be tested, and determines the number of bit errors of the transmission data on the signal line in the test process, where the parallel test module includes:
Determining each signal line in the data channels as a target signal line in sequence, and executing the parallel transmission of first test data and second test data through a plurality of data channels, wherein the first test data is transmitted through the target signal line, and the second test data is transmitted through the signal lines except the target signal line in the data channels; and determining the number of the error codes of the first test data transmitted through the target signal line as the number of the error codes of the transmission data on the target signal line.
In one possible implementation, the parallel test module 902 determines a target area from a test chart, where the test chart is divided into at least two sub-test charts, the sub-test charts include a×b areas, a and B are integers equal to or greater than 2, a is less than a, B is less than B, a sub-chart state array is generated, where the sub-chart state array is used to record a test state of an area in the sub-test charts, and the sub-chart state array is initialized after the target area is determined from the sub-test charts according to the sub-chart state array and a plurality of data channels are tested in parallel under test parameters corresponding to the target area, according to an error number of data transmitted on a signal line in a test process until the sub-chart state array indicates that the sub-test chart has no target area.
In one possible implementation manner, the parallel test module 902 updates the sub-image state array according to the number of errors of transmission data on signal lines in the test process, and the method comprises the steps of updating the test state of a target area into a tested state in the sub-image state array, marking the test state of an unmeasured area adjacent to the target area as to-be-tested if the number of errors corresponding to at least one signal line is in a value range after parallel test, and determining the target area from the areas marked as to-be-tested in the sub-test chart.
In one possible implementation, the sub-graph state array includes a first array and a second array;
The parallel test module 902 updates the test state of the target area to tested in the sub-graph state array, including updating the value representing the test state of the target area in the first array from a first value to a second value and updating the value representing the test state of the target area in the second array from a third value to a fourth value;
The parallel test module 902 marks the test status of the unmeasured area adjacent to the target area as to be tested, including updating the value representing the test status of the measured area in the second array from the fourth value to the third value, wherein the measured area is the unmeasured area adjacent to the target area in the test chart.
In one possible implementation, the parallel test module 902 determines the target areas from the subtest chart according to the subtree state array, including determining the areas with the third values corresponding to the test states in the subtest chart as the target areas according to the second array.
In a possible implementation manner, the parallel test module 902 is further configured to generate an edge state array, where the edge state array is configured to record test states of edge areas in at least two subtest charts, and after parallel test is performed on a plurality of data channels under test parameters corresponding to a target area, it is determined that the target area is located at an edge of the subtest chart, and the test states of the target area in the edge state array are updated to be tested.
In one possible implementation, the edge state array includes a third array and a fourth array;
The parallel test module 902 updates the to-be-tested state of the target area in the edge state array to tested, including updating a value representing the test state of the target area in the third array from a fifth value to a sixth value and updating a value representing the test state of the target area in the fourth array from a seventh value to an eighth value.
In a possible implementation manner, the parallel test module 902 is further configured to mark the test state of the area to be tested in the edge state array as to be tested if the area to be tested is located at an edge of any one of the at least two subtest charts, where the area to be tested is an unmeasured area adjacent to the target area in the test chart.
In one possible implementation, the parallel test module 902 marks the test state of the region under test in the edge state array as under test, including updating the value representing the test state of the region under test in the fourth array from the eighth value to the seventh value.
In a possible implementation manner, the parallel test module 902 is further configured to determine, after completing the test on each target area in the subtest chart, a subtest chart of the next test according to the edge area to be tested in the edge state array corresponding to the test state, update the test state of the edge area of the subtest chart of the next test from the edge state array to the initialized subtest state array, and execute the test on each target area in the subtest chart of the next test.
In one possible implementation, the result generating module 903 generates a test result diagram corresponding to each signal line according to the number of bit errors corresponding to each signal line, where the test result of the hardware to be tested includes the number of bit errors obtained by testing each signal line on test parameters corresponding to a plurality of target areas after the test of one or more subtest diagrams is completed.
It should be noted that, the hardware testing device of the present embodiment is configured to implement the corresponding hardware testing method in the foregoing method embodiment, and has the beneficial effects of the corresponding method embodiment, which is not described herein again.
Electronic equipment
Fig. 12 is a schematic block diagram of an electronic device according to an embodiment of the present application, which is not limited to the specific implementation of the electronic device. As shown in FIG. 12, the electronic device may include a processor 1002, a communication interface (Communications Interface) 1004, a memory 1006, and a communication bus 1008. Wherein:
the processor 1002, communication interface 1004, and memory 1006 communicate with each other via a communication bus 1008.
Communication interface 1004 is used to communicate with other electronic devices or servers.
The processor 1002 is configured to execute the program 1010, and may specifically perform relevant steps in any of the foregoing embodiments of the hardware testing method.
In particular, program 1010 may include program code including computer operating instructions.
The processor 1002 may be a central processing unit (Center Processing Unit, CPU), or an Application SPECIFIC INTEGRATED Circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the application. The one or more processors included in the smart device may be the same type of processor, such as one or more CPUs, or different types of processors, such as one or more CPUs and one or more ASICs.
RISC-V is an open source instruction set architecture based on the principle of Reduced Instruction Set (RISC), which can be applied to various aspects such as single chip microcomputer and FPGA chip, and can be particularly applied to the fields of Internet of things security, industrial control, mobile phones, personal computers and the like, and because the real conditions of small size, rapidness and low power consumption are considered in design, the RISC-V is particularly suitable for modern computing equipment such as warehouse-scale cloud computers, high-end mobile phones, micro embedded systems and the like. With the rise of the artificial intelligence internet of things AIoT, the RISC-V instruction set architecture is also receiving more and more attention and support, and is expected to become a CPU architecture for the next generation and wide application.
The computer operating instructions in embodiments of the present application may be computer operating instructions based on a RISC-V instruction set architecture, and correspondingly, the processor 1002 may be RISC-V based instruction set design. Specifically, the chip of the processor in the electronic device provided by the embodiment of the application may be a chip designed by adopting a RISC-V instruction set, and the chip may execute executable codes based on the configured instructions, thereby implementing the hardware testing method in the embodiment.
Memory 1006 for storing programs 1010. The memory 1006 may include high-speed RAM memory or may further include non-volatile memory (non-volatile memory), such as at least one magnetic disk memory.
The program 1010 is specifically operable to cause the processor 1002 to perform the hardware testing method of any of the embodiments described above.
The specific implementation of each step in the program 1010 may refer to corresponding steps and corresponding descriptions in units in any of the foregoing embodiments of the hardware testing method, which are not repeated herein. It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the apparatus and modules described above may refer to corresponding procedure descriptions in the foregoing method embodiments, which are not repeated herein.
Computer storage medium
The present application also provides a computer readable storage medium storing instructions for causing a machine to perform a hardware testing method as described herein. Specifically, a system or apparatus provided with a storage medium on which a software program code realizing the functions of any of the above embodiments is stored, and a computer (or CPU or MPU) of the system or apparatus may be caused to read out and execute the program code stored in the storage medium.
In this case, the program code itself read from the storage medium may realize the functions of any of the above-described embodiments, and thus the program code and the storage medium storing the program code form part of the present application.
Examples of storage media for providing program code include floppy disks, hard disks, magneto-optical disks, optical disks (e.g., CD-ROMs, CD-R, CD-RWs, DVD-ROMs, DVD-RAMs, DVD-RWs, DVD+RWs), magnetic tapes, nonvolatile memory cards, and ROMs. Alternatively, the program code may be downloaded from a server computer by a communication network.
Computer program product
Embodiments of the present application also provide a computer program product comprising computer instructions that instruct a computing device to perform any corresponding operations of the above-described method embodiments.
It should be noted that, according to implementation requirements, each component/step described in the embodiments of the present application may be split into more components/steps, or two or more components/steps or part of operations of the components/steps may be combined into new components/steps, so as to achieve the objects of the embodiments of the present application.
The above-described methods according to embodiments of the present application may be implemented in hardware, firmware, or as software or computer code storable in a recording medium such as a CD ROM, RAM, floppy disk, hard disk, or magneto-optical disk, or as computer code originally stored in a remote recording medium or a non-transitory machine-readable medium and to be stored in a local recording medium downloaded through a network, so that the methods described herein may be stored on such software processes on a recording medium using a general purpose computer, special purpose processor, or programmable or special purpose hardware such as an ASIC or FPGA. It is understood that a computer, processor, microprocessor controller, or programmable hardware includes a storage component (e.g., RAM, ROM, flash memory, etc.) that can store or receive software or computer code that, when accessed and executed by a computer, processor, or hardware, performs the methods described herein. Furthermore, when a general purpose computer accesses code for implementing the methods illustrated herein, execution of the code converts the general purpose computer into a special purpose computer for performing the methods illustrated herein.
Those of ordinary skill in the art will appreciate that the elements and method steps of the examples described in connection with the embodiments disclosed herein can be implemented as electronic hardware, or as a combination of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the embodiments of the present application.
The above embodiments are only for illustrating the embodiments of the present application, but not for limiting the embodiments of the present application, and various changes and modifications may be made by one skilled in the relevant art without departing from the spirit and scope of the embodiments of the present application, so that all equivalent technical solutions also fall within the scope of the embodiments of the present application, and the scope of the embodiments of the present application should be defined by the claims.