Disclosure of Invention
The invention aims to provide a capacitance sensing unit and a system, which can realize capacitance detection with high signal to noise ratio under the condition of severe noise interference.
In order to solve the technical problems, the invention provides a capacitance sensing unit which comprises a GM module, an integral storage module, a quantization circuit module and a counting module;
The first input end of the GM module is used for receiving a sensing signal representing a system to be tested, the second input end of the GM module is connected with a reference voltage, the first output end of the GM module is connected with the first input end to generate a first current, the second output end of the GM module outputs a second current with an adjustable proportion with the first current, and the adjustable proportion is used for amplifying or shrinking the signal;
the integral storage module is connected with the second output end and is used for carrying out integral storage on the current output by the GM module;
the quantization circuit module is connected with the integral storage module and is used for quantizing the charge on the integral storage module and controlling the voltage on the integral storage module to be stable within a set range;
the counting module is connected with the quantization circuit module and is used for counting the output of the quantization circuit module to obtain a counting value representing the capacitance value of the system to be tested.
Further, the integral storage module comprises a switch circuit and an integral capacitor;
the switch circuit is connected with the second output end and used for converting the second current into the same-direction current under the control of a clock signal, and the integrating capacitor is connected with the switch circuit and used for integrating the same-direction current.
Further, the quantization circuit module comprises a plurality of comparison voltages and a plurality of current sources;
the plurality of comparison voltages comprise target voltages, and the plurality of current sources are used for charging and discharging the integration storage module according to the magnitude relation between the voltage on the integration storage module and the plurality of comparison voltages, so that the voltage on the integration storage module is stabilized near the target voltages.
Further, the quantization circuit module further comprises a plurality of voltage comparators and a current source control circuit;
the first input ends of the voltage comparators are connected with the integral storage module, the second input ends of the voltage comparators are respectively connected with the comparison voltages and used for comparing the magnitude relation between the voltage on the integral storage module and the comparison voltages, and the current source control circuit is used for controlling the opening quantity of the current sources according to the difference value between the voltage on the integral storage module and the target voltage.
Further, the plurality of current sources includes a discharge current source and a charge current source;
the discharging current source is used for discharging the integral storage module, and the charging current source is used for charging the integral storage module.
Further, when the voltage on the integral storage module is higher than the target voltage, the discharging current source discharges, and when the voltage on the integral storage module is lower than the target voltage, the charging current source charges.
In addition, the invention further provides a capacitance sensing system which comprises the capacitance sensing unit, a system to be tested and a data processing module, wherein the system to be tested is connected with the GM module, and the data processing module is used for carrying out data analysis processing on the count value output by the counting module.
Further, the data analysis process includes at least one of data storage, data filtering, and data extraction.
Further, the system to be tested comprises a mutual capacitance system, wherein the mutual capacitance system comprises a transmitting electrode TX, a receiving electrode RX, a transmitting capacitance Ctx, a mutual capacitance Cm and a receiving capacitance Crx;
The two ends of the mutual capacitance Cm are respectively connected with the transmitting electrode TX and the receiving electrode RX, one end of the receiving electrode RX far away from the mutual capacitance Cm is connected with the GM module, one end of the transmitting capacitance Ctx is connected with the transmitting electrode TX, the other end of the transmitting capacitance Ctx is grounded, and one end of the receiving capacitance Crx is connected with the receiving electrode RX, and the other end of the receiving capacitance Ctx is grounded.
Further, the system to be tested comprises a self-capacitance system, wherein the self-capacitance system comprises a receiving electrode RX and a receiving capacitor Crx, the receiving electrode RX is connected with the first input end of the GM module, one end of the receiving capacitor Crx is connected with the receiving electrode RX, and the other end of the receiving capacitor Crx is grounded.
Through the technical scheme, the invention has the following beneficial effects:
The sensing signal of the system to be tested is converted into current through the GM module, the second output end of the GM module outputs second current proportional to the first current, the integration storage module is combined for integrating storage, the charge on the integration storage module is quantized through the quantization circuit module, meanwhile, the voltage on the integration storage module is controlled to be stabilized in a set range, and finally, the counting module obtains a counting value representing the capacitance value of the system to be tested, so that stable and reliable capacitance detection is realized.
The GM module can amplify the signal by A times, so that the signal quantity and the signal-to-noise ratio are obviously improved, the quantization circuit module adopts a plurality of current sources to control the charge and discharge of the integral storage module (namely, a current control mode of Kn multiplied by Iurnit is adopted), the quantization range is enlarged under the condition of not increasing the area of an integral capacitor, the advantages of the small area of the chip are ensured, the system cost is reduced, the current is converted into the current in the same direction through the switch circuit to integrate, the opening quantity of the current sources is controlled according to the difference value between the voltage on the integral storage module and the target voltage, the faster quantization speed is realized, and meanwhile, the system supports two detection modes of mutual capacitance and self capacitance, and the application range is wide.
Detailed Description
A capacitive sensing cell and system of the present invention will be described in more detail below with reference to the accompanying drawings, in which preferred embodiments of the present invention are shown, it being understood that one skilled in the art may modify the invention described herein while still achieving the beneficial effects of the invention. Accordingly, the following description is to be construed as broadly known to those skilled in the art and not as limiting the invention.
The invention is more particularly described by way of example in the following paragraphs with reference to the drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
As shown in fig. 1 and 3, an embodiment of the present invention proposes a capacitive sensing unit, which includes a GM module, an integral storage module, a quantization circuit module (Quantization Circuit), and a Counter module (Counter).
Specifically, the first input end of the GM module is configured to receive a sensing signal Vrx representing a system to be tested, the second input end of the GM module is connected to a reference voltage Vcm, the first output end of the GM module is connected to the first input end to generate a first current Iout, and the second output end of the GM module outputs a second current axiout having an adjustable ratio with the first current, where the adjustable ratio is used to amplify or reduce the signal. Wherein A is an adjustable amplitude modulation factor, and the ratio can be set according to practical situations, and can be amplified or reduced, so that the signal (namely the sensing signal Vrx, the sensing signal Vrx is the sensing signal on the receiving electrode RX in a mutual capacitance mode, and the sensing signal Vrx is the sensing signal on the receiving electrode RX in a self capacitance mode) can be scaled. The integral storage module is connected with the second output end and is used for carrying out integral storage on the current output by the GM module; the quantization circuit module is connected with the integral storage module and is used for quantizing the charge on the integral storage module and controlling the voltage Vint on the integral storage module to be stable in a set range; the counting module is connected with the quantization circuit module and is used for counting the output of the quantization circuit module to obtain a counting value representing the capacitance value of the system to be tested.
In one embodiment, the GM module comprises a transconductance operational amplifier. The first input end is an operational amplifier inverting input end and is connected with a system to be tested, the second input end is an operational amplifier non-inverting input end and is coupled with a reference voltage Vcm, the first output end is connected with the first input end to generate a first current Iout, the second output end generates a second current A×Iout, namely the second current A×Iout of the second output end is the copy of the first current Iout of the first input end, and the current size can be scaled by A times. Wherein a is an adjustable amplitude modulation coefficient, and the signal can be amplified by adjusting a to improve the signal-to-noise ratio, but the signal amplification can increase the cost of the circuit, such as the chip area, the working time length and the like.
In addition, the signals of the first input end and the second input end of the GM module, which are specifically connected, may be different according to different working modes. For example, in the self-capacitance mode, the first input terminal is connected to the receiving electrode RX for receiving a voltage change on the receiving electrode RX. Also for example in mutual capacitance mode, the first input terminal is connected to the receive electrode RX for receiving a voltage change coupled to the receive electrode RX by the transmit electrode TX. Regardless of the mode of operation, the first current Iout generated is related to the capacitance in the system under test and the swing of the applied excitation signal. For example, in the mutual capacitance mode, the mutual capacitance Cm and the charge cm×Δvtx generated by the emitter electrode excitation signal swing Δvtx are provided by the first current Iout.
In one embodiment, the integrating storage module includes a switching circuit CH and an integrating capacitor C1. Specifically, the switching circuit CH is connected to the second output end and configured to convert the second current axiout into a current in the same direction under the control of the clock signal CK, and the integrating capacitor C1 is connected to the switching circuit CH and configured to integrate the current in the same direction.
In this embodiment, the switch circuit CH is connected to the second output terminal of the GM module and is coupled to the integrating capacitor C1 and the quantization circuit module. The main purpose of the switching circuit CH is to demodulate the current generated by the GM module with forward and reverse directions under the control of the clock signal CK, convert the current into a current with the same direction, and send the current to the integrating capacitor C1 for integration. The integrating capacitor C1 is used for integrating the current demodulated by the switching circuit CH. The size of the integrating capacitor C1 determines the size of the integrable signal, but it should be noted that the capacitor consumes a large area in the chip.
In an embodiment, the quantization circuit module includes a plurality of comparison voltages and a plurality of current sources. Specifically, the plurality of comparison voltages include a target voltage, and the plurality of current sources are configured to charge and discharge the integration storage module according to a magnitude relation between the voltage Vint on the integration storage module and the plurality of comparison voltages, so that the voltage Vint on the integration storage module is stabilized near the target voltage.
Further, the quantization circuit module further includes a plurality of voltage comparators (i.e., CMP1, CMP2, CMP3, CMP4, and CMP5 in fig. 5) and a current source control circuit. Specifically, the first input ends of the voltage comparators are connected with the integral storage module, and the second input ends of the voltage comparators are respectively connected with the comparison voltages and used for comparing the magnitude relation between the voltage Vint on the integral storage module and the comparison voltages; the current source control circuit is used for controlling the opening quantity of the current sources according to the difference value between the voltage Vint on the integral storage module and the target voltage.
In this embodiment, the plurality of current sources includes a discharge current source and a charge current source. Specifically, the discharging current source is used for discharging the integral storage module, and the charging current source is used for charging the integral storage module.
Preferably, the discharging current source discharges when the voltage Vint on the integral storage module is higher than the target voltage, and the charging current source charges when the voltage Vint on the integral storage module is lower than the target voltage.
Preferably, the current values of the plurality of current sources satisfy in=kn×iunit, where Kn is a positive integer, iunit is a reference current, the current value ratio of adjacent gears In the discharging current sources is a first set threshold (for example, 2), and the current value ratio of adjacent gears In the charging current sources is a second set threshold (for example, 2).
In this embodiment, fig. 2 is a voltage and current waveform diagram of the main node when operating in the mutual capacitance mode in this embodiment. As can be seen from the figure, when the excitation signal VTX is input to the transmitting electrode TX, a corresponding voltage change Vrx is generated on the receiving electrode RX. The GM module converts the voltage variation into a first current Iout and a second current a×iout. After demodulation by the switching circuit CH, the voltage Vint on the integrating capacitor C1 changes accordingly. The quantization circuit module finally stabilizes Vint near the target voltage Vref3 by controlling the charge-discharge current.
In this embodiment, fig. 4 is a voltage and current waveform diagram of the main node in the self-capacitance mode according to another embodiment. As can be seen from the figure, the graph shows the voltage and current variations at each main node in self-capacitance mode, including the variation of the reference voltage Vcm, the voltage signal Vrx generated at the receiving electrode RX, the current Iout generated by the GM module and its amplified current a×iout, and the voltage Vint variation at the integrating capacitor C1. The diagram shows that when the reference voltage Vcm jumps, the self-capacitance Crx from the receiving electrode to the ground exists, so that the charge change is generated on the receiving electrode RX, and the charge change is converted into current output through the GM module, and finally the voltage Vint on the integrating capacitor is controlled to be stabilized near the target voltage Vref3 through the quantization circuit module.
Fig. 6 is a schematic diagram of the quantization circuit module controlling the voltage Vint on the integrating capacitor C1 in the present embodiment. The solid line in the figure shows the change process of Vint in the multi-stage charge-discharge control, namely when Vint is in different voltage intervals, vint is changed with different slopes by controlling different numbers of current sources to be started, and finally, the Vint is quickly stabilized near the target voltage Vref 3. The dashed line in the figure shows the Vint change in charge and discharge with only a single rate, requiring a longer quantization time in comparison.
In a specific example, as shown in fig. 5 and 6, while integrating the current by the integrating capacitor C1, the quantization circuit module also quantizes the current synchronously and removes or supplements the quantized charge from the integrating capacitor C1, preventing the voltage on the integrating capacitor C1 from being too high or too low.
Specifically, when the voltage Vint on the integrating capacitor C1 is higher or lower than a certain comparison voltage, the quantization circuit module charges or discharges the integrating capacitor C1 at a corresponding speed. The farther Vint deviates from the target voltage, the faster the charge or discharge speed, eventually stabilizing Vint near the target comparison voltage.
For example, a comparison voltage Vref1> Vref2> Vref3> Vref4> Vref5 is set, wherein Vref3 is a target voltage, and the number and the size of the comparison voltages can be set according to actual needs. When Vint > Vref1, the starting currents I1, I2 and I3 discharge the integrating capacitor C1, when Vref1> Vint > Vref2, the starting currents I2 and I3 discharge the integrating capacitor C1, when Vref2> Vint > Vref3, the starting current I3 discharges the integrating capacitor C1, when Vref3> Vint > Vref4, the starting current I4 charges the integrating capacitor C1, when Vref4> Vint > Vref5, the starting currents I4 and I5 charge the integrating capacitor C1, and when Vref5> Vint, the starting currents I4, I5 and I6 charge the integrating capacitor C1. The current magnitude of each current source satisfies in=kn×iunit (Kn is a positive integer), and the directions of the currents I1, I2, I3 are opposite to the directions of the currents I4, I5, I6, preferably i3=i4=iunit. The minimum charge-discharge time unit is tclk, and preferably the minimum charge-discharge charge amount is iunit× tclk, so that Vint eventually stabilizes around Vref3 with a deviation of iunit× tclk/C1. Wherein CLK shown in fig. 1 and 3 is a system clock signal, tclk is a period of the CLK clock signal, i.e., a minimum charge-discharge time unit.
With continued reference to fig. 6, vint changes at different slopes when it is in different voltage intervals, i.e., the quantized circuit charges and discharges at different speeds. When Vint deviates from the target voltage Vref3, the charge and discharge speed is faster, and finally, it stabilizes around Vref 3. By controlling the current direction and the current magnitude in the quantization circuit, the quantization speed, the quantization precision and the charge and discharge speed are controlled, the excessive high or low voltage on the integration capacitor C1 is prevented, the area required by the integration capacitor C1 is reduced, the quantization range is increased, and the quantization speed is improved.
In summary, the current direction and the current magnitude in the quantization circuit module are controlled, so that the quantization speed, the quantization precision and the charge-discharge speed are controlled, the excessive high or low voltage on the integration capacitor C1 is prevented, the area of the integration capacitor C1 is reduced, the quantization range is increased, and the quantization speed is improved.
In addition, with continued reference to fig. 1 and 3, the present embodiment further proposes a capacitive sensing system, including a capacitive sensing unit as described above, a system under test and a data processing module (Digital Processor).
The system to be tested is connected with the GM module, and the data processing module is used for carrying out data analysis processing on the count value output by the counting module.
In this embodiment, the data analysis processing includes at least one of data storage, data filtering, and data extraction.
In a specific example, the system to be tested comprises a mutual capacitance system, wherein the mutual capacitance system comprises a transmitting electrode TX, a receiving electrode RX, a transmitting capacitance Ctx, a mutual capacitance Cm and a receiving capacitance Crx;
Specifically, two ends of the mutual capacitor Cm are respectively connected with the transmitting electrode TX and the receiving electrode RX, one end, far away from the mutual capacitor Cm, of the receiving electrode RX is connected with the GM module, one end of the transmitting capacitor Ctx is connected with the transmitting electrode TX, the other end of the transmitting capacitor Ctx is grounded, and one end of the receiving capacitor Crx is connected with the receiving electrode RX, and the other end of the receiving capacitor Crx is grounded.
In another specific example, the system under test comprises a self-capacitance system, and the self-capacitance system comprises a receiving electrode RX and a receiving capacitor Crx.
Specifically, the receiving electrode RX is connected to the first input end of the GM module, one end of the receiving capacitor Crx is connected to the receiving electrode RX, and the other end is grounded.
In the present embodiment, as shown in fig. 2 and fig. 4 to 6, the inverting input terminal of the op-amp is directly connected to the receiving electrode RX in the self-capacitance mode. When the reference voltage Vcm goes high and low, a charge change crx×Δvcm occurs due to the self-capacitance of the receiving electrode to ground (i.e., the receiving capacitance Crx of the self-capacitance system). The GM module converts the charge change to a current output.
In the mutual capacitance mode, a mutual capacitance Cm is formed between the transmitting electrode TX and the receiving electrode RX due to the presence of a medium. When TX inputs an excitation signal of amplitude VTX, a charge variation Cm x VTX is generated at the RX end due to the mutual capacitance Cm. The GM module also converts this charge change into a current output. External touches change the mutual capacitance value Cm.
Therefore, in the self-capacitance mode, the generated current is related to the variation Δvcm of the reception capacitance Crx and the reference voltage Vcm, and in the mutual capacitance mode, the generated current is related to the mutual capacitance Cm and the transmission electrode excitation signal VTX. Under the control of a clock signal CK, the switching circuit CH demodulates forward and reverse currents generated by the GM module into the same-direction currents, and sends the same-direction currents to the integrating capacitor C1 for integration. The quantization circuit module quantizes the charge on the integrating capacitor C1.
For example, 5 reference voltages Vref1> Vref2> Vref3> Vref4> Vref5, vref3 are set as target voltages. When the voltage Vint on the integrating capacitor C1 is in different intervals, the current sources with different combinations are turned on:
Vint > Vref1, opening discharge of I1, I2, I3;
vref1> Vint > Vref2, opening the I2, I3 discharge;
vref2> Vint > Vref3, opening the I3 discharge;
vref3> Vint > Vref4, opening charging of I4;
vref4> Vint > Vref5, opening charging I4, I5;
Vref5> Vint, turn on charging I4, I5, I6.
The current source size satisfies in=kn×iunit, preferably i3=i4=iunit. The minimum charge-discharge time is tclk, and the minimum charge-discharge charge amount is iunit× tclk. Vint is quickly stabilized near Vref3 by multi-stage current control with a bias Iunit x tclk/C1. And finally, the counting module counts and accumulates the output of the quantization circuit to obtain a counting value related to the capacitance value to be measured.
Therefore, the signal to noise ratio is improved through A-time amplification of the GM module, the quantization range is enlarged and the quantization speed is accelerated through multistage quantization current control, meanwhile, the requirement on the area of the integrating capacitor C1 is reduced, and the method has good cost advantage. In addition, the embodiment can effectively work in two modes of self capacitance and mutual capacitance, and high-sensitivity and high-accuracy touch sensing is realized.
In summary, the capacitive sensing unit and the capacitive sensing system provided by the invention have the following advantages:
The sensing signal of the system to be tested is converted into current through the GM module, the second output end of the GM module outputs second current proportional to the first current, the integration storage module is combined for integrating storage, the charge on the integration storage module is quantized through the quantization circuit module, meanwhile, the voltage on the integration storage module is controlled to be stabilized in a set range, and finally, the counting module obtains a counting value representing the capacitance value of the system to be tested, so that stable and reliable capacitance detection is realized.
The GM module can amplify the signal by A times, so that the signal quantity and the signal-to-noise ratio are obviously improved, the quantization circuit module adopts a plurality of current sources to control the charge and discharge of the integral storage module (namely, a current control mode of Kn multiplied by Iurnit is adopted), the quantization range is enlarged under the condition of not increasing the area of an integral capacitor, the advantages of the small area of the chip are ensured, the system cost is reduced, the current is converted into the current in the same direction through the switch circuit to integrate, the opening quantity of the current sources is controlled according to the difference value between the voltage on the integral storage module and the target voltage, the faster quantization speed is realized, and meanwhile, the system supports two detection modes of mutual capacitance and self capacitance, and the application range is wide.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.