Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings rather than the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
In the present application, it should be noted that, as terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., appear, the indicated orientation or positional relationship is based on that shown in the drawings, only for convenience of description and simplification of the description, and does not indicate or imply that the apparatus or element in question must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the application. Furthermore, the terms "first," "second," and the like, as used herein, are used for descriptive and distinguishing purposes only and are not to be construed as indicating or implying a relative importance.
Exemplary memory device:
In practical applications, memory devices often have multiple memory cells, each of which may enable storage of data. The memory device provided by the application can be a nonvolatile memory based on MOSFET. The threshold voltage in the memory cell can be used as the stored data, and the data can be read through reading the threshold voltage. For example, the actual data corresponding to different threshold voltage values may be determined first, and the actual data stored in the memory cell may be determined by reading the threshold voltage and combining the correspondence between the actual data and the threshold voltage value.
In order to improve the storage capacity of a single storage unit, the application integrates an N-type storage subunit and a P-type storage subunit in one storage unit. The N-type storage subunit and the P-type storage subunit are nonvolatile MOSFET memories based on floating gate structures.
The N-type memory subcell may be an N-type metal oxide semiconductor, with the conductivity of the N-type memory subcell being primarily dependent on free electrons. When the N-type memory subunit gate Voltage (VGS) is higher than the threshold voltage, the N-type memory subunit turns on. The data recorded by the N-type memory sub-unit can be reflected by the threshold voltage when the N-type memory sub-unit is conducted.
The substrate of the N-type storage subunit is doped with P-type ions, and the source electrode and the drain electrode of the N-type storage subunit are N-type ion doped regions. The threshold voltage described by the N-type memory sub-unit is a positive voltage.
The P-type memory subcell may be a P-type metal oxide semiconductor, with conductivity of the P-type memory subcell being primarily dependent on holes. When the P-type memory subunit gate Voltage (VGS) is below the threshold voltage, the P-type memory subunit turns on. The data recorded by the P-type memory sub-unit can be reflected by the threshold voltage when the P-type memory sub-unit is conducted.
The substrate of the P-type storage subunit is doped with N-type ions, and the source electrode and the drain electrode of the P-type storage subunit are P-type ion doped regions. The threshold voltage described by the P-type memory sub-cell is a negative voltage.
In practical applications, the N-type memory subcell and the P-type memory subcell may be OTP (one time programming) devices with non-rewritable threshold voltages, or MTP (multi time programming) devices with rewritable threshold voltages. The following description of the present application uses an MTP device as an example, and if there is a need, the MTP device may be partially replaced by an OTP device, and the adaptability is improved.
In order to construct the N-type memory subunit and the P-type memory subunit into one memory unit, the drain electrodes of the N-type memory subunit and the P-type memory subunit are connected with each other, so that the N-type memory subunit and the P-type memory subunit can independently store data. In order to further illustrate the memory cell provided by the application, the application also provides a schematic structure diagram of the memory cell.
As shown in fig. 1, the memory cell 100 may include an N-type memory sub-cell 110, a P-type memory sub-cell 120, an isolation trench 130, and a control lead. The N-type memory sub-unit 110 and the P-type memory sub-unit 120 may be disposed on two sides of the isolation trench 130, respectively.
As described above, both the N-type memory subunit 110 and the P-type memory subunit 120 are non-volatile MOSFET memories. The N-type memory sub-cell 110 includes an N-type drain 111, an N-type source 112, and an N-type gate 113. The N-type Gate 113 may include a control Gate (Poly Control Gate) and a Floating Gate (Floating Gate), among others, to enable recording of the threshold voltage. Correspondingly, the P-type memory subunit 120 includes a P-type drain 121, a P-type source 122, and a P-type gate 123.
To interconnect the N-type drain 111 of the N-type memory subunit 110 with the P-type drain 121 of the P-type memory subunit 120, the N-type drain 111 of the N-type memory subunit 110 is disposed proximate to the isolation trench 130 and the P-type drain 121 of the P-type memory subunit 120 is disposed proximate to the isolation trench 130.
Thus, the control lead may include a common drain lead 141 connected to both the N-type drain 111 and the P-type drain 121.
In some embodiments, to achieve the connection of the common drain lead 141 to both the N-type drain 111 and the P-type drain 121. In the memory cell 100 shown in fig. 1, the memory cell 100 may further include a drain connection structure 150 that communicates the P-type drain 121 and the N-type drain 111 across the isolation trench 130. Thus, the common drain lead 141 can be electrically connected to the drain connection structure 150 to simultaneously connect to the P-type drain 121 and the N-type drain 111.
In some embodiments, the common drain lead 141 may also omit the drain connection structure 150 by adjusting the width in order to simplify the internal structure. To further illustrate this, the present application also includes another schematic structure of the memory cell (fig. 2). As shown in fig. 2, the common drain lead 141 has a certain width in the lateral direction so as to be connected to both the P-type drain 121 and the N-type drain 111 laterally across the isolation trench 130.
As shown in fig. 1, the control leads may also include other leads for the N-type memory subcell 110 and the P-type memory subcell 120. Specifically, the control leads further include an N-type source lead 142 connected to the N-type source 112 of the N-type memory subunit 110, an N-type gate lead 143 connected to the N-type gate 113 of the N-type memory subunit 110, a P-type source lead 144 connected to the P-type source 122 of the P-type memory subunit 120, and a P-type gate lead 145 connected to the P-type gate 123 of the P-type memory subunit 120.
The control leads may also include N-type substrate leads (not shown) connected to the doped substrate of N-type memory subcell 110 and P-type substrate leads (not shown) connected to the doped substrate of P-type memory subcell 120. In order to clearly show the names of the partial structures, in fig. 1 and the following figures, the names in the structures are added with ground color to avoid the influence of ground patterns of the structures where the names are located on the name display, and ground patterns are arranged under the partial names. It should be noted that the ground tint does not mean an additional structure, but is merely a display style for displaying clear text.
Exemplary control method of the memory device:
In practical application, the operation state of the memory cell 100 can be controlled by controlling the voltage of each specific lead in the leads, so as to realize operations such as data reading.
Specifically, based on the storage principle of the nonvolatile MOSFET memory, the reading process of the N-type memory subcell 110 is as follows:
When the driving voltage of the N-type gate lead 143 is identical to (or greater than) the threshold voltage stored by the N-type memory subcell 110 and the memory cell 100 is in the N-type read state, the common drain lead 141 is turned on with the N-type source lead 142. Wherein the memory cell 100 is in an N-type read state when a positive voltage is applied to the common drain lead 141 and a voltage greater than the common drain lead 141 is also applied to the P-type substrate lead.
As just one example, when the memory cell 100 is in the N-read state, the N-type source voltage (VsN), the N-type substrate voltage (VbN), the P-type gate voltage (VgP), and the P-type source voltage (VsP) are all 0. Drain voltage (VdN/VdP) =1.1v < p-type substrate voltage (VbP) =2.2 v. At this time, if the N-type gate voltage (VgN) is equal to or greater than the threshold voltage, the N-type memory subcell 110 is turned on (i.e., the common drain lead 141 is turned on with the N-type source lead 142).
Similar to the N-type memory subunit 110 described above, the P-type memory subunit 120 is read as follows:
When the driving voltage of the P-type gate lead 145 is identical to (or less than) the threshold voltage stored by the P-type memory subunit 120 and the memory cell 100 is in the P-type read state, the common drain lead 141 is turned on with the P-type source lead 144. The memory cell 100 is in a P-type read state when a negative voltage is applied to the common drain lead 141 and a voltage less than the common drain lead 141 is also applied to the N-type substrate lead.
As just one example, when the memory cell 100 is in the P-read state, the N-type gate voltage (VgN), the N-type source voltage (VsN), the P-type source voltage (VsP), and the P-type substrate voltage (VbP) are all 0. Drain voltage (VdN/VdP) = -1.1v > n-type substrate voltage (VbN) = -2.2v. At this time, if the P-type gate voltage (VgP) is less than or equal to the threshold voltage, the P-type memory subunit 120 is turned on (i.e., the common drain lead 141 is turned on with the P-type source lead 144).
In the case where the present application is not additionally described, the voltage comparison is calculated with a sign, for example, -1.1v > -2 v.
As shown in fig. 1, the N-type gate 113 and the P-type gate 123 each include a control gate and a floating gate that are stacked, so that the N-type memory subunit 110 and the P-type memory subunit 120 can also be used as erasable nonvolatile MOSFET memories, so as to support writing and erasing of threshold voltages.
Based on the memory principle of the erasable nonvolatile MOSFET memory, the process of writing the threshold voltage of the N-type memory subcell 110 is as follows:
When the driving voltage of the N-type gate lead 143 is the writing voltage and the memory cell 100 is in the N-type writing state, the floating gate of the N-type memory sub-cell 110 pulls in electrons to form a threshold voltage. The writing voltage is generally high voltage (e.g. 9.5V), and the N-type writing state is similar to the N-type reading state, and it is required to ensure that the common drain lead 141 is applied with a positive voltage and the P-type substrate lead is also applied with a voltage greater than the common drain lead 141, but specific voltage values are different.
As just one example, when the memory cell 100 is in an N-type write state, the N-type source voltage (VsN), the N-type substrate voltage (VbN), the P-type gate voltage (VgP), and the P-type source voltage (VsP) are all 0. Drain voltage (VdN/VdP) =3.8v < p-type substrate voltage (VbP) =5.8 v. At this time, if a high voltage (e.g., 9.5V) is applied to the N-type gate voltage (VgN), the floating gate of the N-type memory sub-cell 110 is pulled in electrons to change the threshold voltage to a threshold voltage to be memorized. The adjustment value of the threshold voltage is generally related to the time when the high voltage is applied by the N-type gate voltage (VgN), and the specific relationship can be determined by laboratory measurement to guide the data writing in the subsequent operation.
Correspondingly, the process of writing the threshold voltage into the P-type memory sub-cell 120 is as follows:
When the driving voltage of the P-type gate lead 145 is the writing voltage and the memory cell 100 is in the P-type writing state, the floating gate of the P-type memory subunit 120 sinks holes to form a threshold voltage. The threshold voltage of the P-type memory sub-cell 120 is typically negative. The P-type gate lead 145 is typically written with a negative voltage (e.g., -9.5V) having a relatively large absolute value, and the P-type writing state is similar to the P-type reading state described above, and it is ensured that the common drain lead 141 is applied with a negative voltage and the N-type substrate lead is also applied with a negative voltage smaller than the common drain lead 141, but the specific voltage values are different.
As just one example, when the memory cell 100 is in the P-type write state, the N-type gate voltage (VgN), the N-type source voltage (VsN), the P-type source voltage (VsP), and the P-type substrate voltage (VbP) are all 0. Drain voltage (VdN/VdP) = -3.8v > n-type substrate voltage (VbN) = -5.8v. At this time, if the P-type gate voltage VgP is applied with a negative voltage (e.g., -9.5V) having a larger absolute value, the floating gate of the P-type memory sub-cell 120 is pulled into holes to change the threshold voltage to form a threshold voltage to be memorized.
Based on the storage principle of the erasable nonvolatile MOSFET memory, the process of erasing the threshold voltage of the N-type memory subcell 110 is as follows:
When the driving voltage of the N-type gate lead 143 is the erase voltage and the memory cell 100 is in the N-type erased state, the floating gate of the N-type memory subcell 110 releases electrons to erase the threshold voltage. When the memory cell 100 is in the N-type erase state, the N-type source voltage (VsN), the N-type substrate voltage (VbN), and the drain voltage (VdN/VdP) are all greater than the maximum value of the threshold voltage range, and the P-type substrate voltage (VbP) is greater than the drain voltage (VdN/VdP). At this time, the N-type gate voltage (VgN) is at a negative voltage, thereby causing the floating gate to release electrons and erase the threshold voltage.
As just one example, when the threshold voltage of the N-type memory sub-cell 110 is 0-6V when the memory cell 100 is in the N-type erase state, the N-type source voltage (VsN) =n-type substrate voltage (VbN) =drain voltage (VdN/VdP) =7.7V < p-type substrate voltage (VbP) =8.8V. Then at this time, the driving voltage of the N-type gate lead 143 (i.e., N-type gate voltage (VgN)) = -8.1V, thereby causing the floating gate to release electrons and erase the threshold voltage.
Similar to the process of erasing the threshold voltage of the N-type memory subcell 110 described above, the process of erasing the threshold voltage of the P-type memory subcell 120 is as follows:
When the drive voltage of the P-type gate lead 145 is the erase voltage and the memory cell 100 is in the P-type erased state, the floating gate of the P-type memory subunit 120 releases holes to erase the threshold voltage. When the memory cell 100 is in the P-type erase state, the drain voltage (VdN/VdP), the P-type source voltage (VsP), and the P-type substrate voltage (VbP) are all smaller than the minimum value of the threshold voltage range, and the N-type substrate voltage (VbN) is smaller than the drain voltage (VdN/VdP).
As just one example, when the threshold voltage of the P-type memory sub-cell 120 is 0-6V when the memory cell 100 is in the N-type erase state, the P-type source voltage (VsP) =p-type substrate voltage (VbP) =drain voltage (VdN/VdP) = -7.7V > P-type substrate voltage (VbP) = -8.8V. Then at this time, the drive voltage of the P-type gate lead 145 (i.e., P-type gate voltage (VgP))=8.1v, thereby causing the floating gate to release holes and erase the threshold voltage.
In some embodiments, in practice, the foregoing writing of the threshold voltage may be regarded as a process of increasing the absolute value of the threshold voltage value (making the threshold voltage more distant from 0V), and the erasing of the threshold voltage may be regarded as a process of decreasing the absolute value of the threshold voltage value (making the threshold voltage more close to 0V).
In actually adjusting the threshold voltage, erasing may be performed before writing based on the foregoing process. Alternatively, one of the erase and write may be selected directly based on the difference in threshold voltages.
In some embodiments, the threshold voltage may be verified after the write/erase is completed, where the memory cell 100 may be in a corresponding read state and a scan voltage is applied to its gate to determine the actual threshold voltage.
It is considered that the foregoing process only illustrates that the memory sub-unit is turned on in the corresponding case. In actually reading the threshold voltage, a scan voltage may be applied to the gate from 0V, thereby determining the gate voltage at which the memory sub-cell is turned on and noting the read threshold voltage.
As an exemplary illustration only, the voltage schematic values for the various states in the foregoing process may be found in the following table:
based on the different control states of the memory sub-units, the application also provides a control method of each memory unit 100 in the memory device, which specifically may include a threshold voltage reading method (fig. 3) and a threshold voltage adjusting method (fig. 4).
As shown in fig. 3, the process P300 may include the following steps:
s310, determining a target storage subunit from the N-type storage subunit and the P-type storage subunit.
S320, controlling the storage unit to be in a read state corresponding to the target storage subunit.
S330, applying a scanning voltage to the grid lead of the target storage subunit.
S340, in response to conduction of the source electrode and the drain electrode of the target storage subunit, determining the gate voltage at the conduction moment and taking the gate voltage as the threshold voltage of the target storage subunit.
In the foregoing S310, the target storage subunit may be a storage subunit that performs data reading. In practical applications, each storage subunit in a storage unit of the present application is operated independently, but only one storage subunit can be controlled at a time. Therefore, in the use process of the memory device provided by the application, the related equipment needs to determine the target memory subunit for control.
In some embodiments, the selection of individual storage subunits may also be made according to their actual nature. Wherein for storage tasks requiring fast response, an N-type storage subunit may be invoked. And for the storage tasks with low speed requirements and high stability requirements, the P-type storage subunit can be preferentially called.
After determining the target memory subunit, the voltage of the control lead may be adjusted to enable the memory unit to be in a read state corresponding to the target memory subunit. Specific voltage application conditions can be seen from the foregoing description of the read state.
Based on the above, the N-type memory sub-cell is turned on when the threshold voltage of the N-type memory sub-cell is positive and greater than the threshold voltage, and the P-type memory sub-cell is turned on when the threshold voltage of the P-type memory sub-cell is negative and less than the threshold voltage. Then the scan can be started at 0V when the voltage scan is performed, and the absolute value becomes gradually larger as the scan voltage is increased. When the corresponding target storage subunit is turned on, the gate voltage value at the moment is the threshold voltage.
As shown in fig. 4, the threshold voltage adjustment procedure P400 may include the steps of:
S410, determining a target storage subunit from the N-type storage subunit and the P-type storage subunit.
S420, determining the current threshold voltage of the target storage subunit.
S430, determining a target operation and a process parameter of the target operation from the write operation and the erase operation based on the expected threshold voltage and the current threshold voltage.
S440, executing target operation on the target storage subunit based on the technological parameters of the target operation.
The aforementioned S410 is similar to the aforementioned S310, and will not be described herein. The aforementioned S420 may be implemented based on the aforementioned steps of P400.
In view of the foregoing, the write threshold voltage is understood to be an absolute value of an increased threshold voltage, and the erase threshold voltage is understood to be an absolute value of a decreased threshold voltage. The voltage adjustment value (=desired threshold voltage-current threshold voltage) may be determined first after the desired threshold voltage is determined. If it is positive, the absolute value of the threshold voltage needs to be increased and a write operation can be employed. If it is negative, the absolute value of the threshold voltage needs to be reduced, and an erase operation can be employed.
Before the actual use of the memory device, the influence of different process parameters (such as the process duration) on the threshold voltage may be calibrated through experiments, and when the foregoing step S430 is performed, an appropriate process parameter may be determined based on the specific value of the foregoing voltage adjustment value, so as to perform a corresponding target operation, so as to adjust the threshold voltage of the target memory subunit from the current threshold voltage to the desired threshold voltage.
In some embodiments, after the foregoing adjustment operation is performed, the threshold voltage may be checked again to determine whether the adjustment is completed. And when the adjustment is not completed, the aforementioned P400 is re-executed until the threshold voltage adjustment is the desired threshold voltage.
In some embodiments, the adjustment of the threshold voltage may also be achieved by rewriting. That is, the erase operation may be performed on the target memory subcell first and then the write operation may be performed based on the desired threshold voltage, thereby bringing the threshold voltage of the target memory subcell to the desired threshold voltage.
Exemplary method of manufacturing a memory device:
In order to form the memory cell (such as the memory cell 100) of the memory device, the application further provides a preparation method of the memory cell. The method for manufacturing the memory cell is described below with reference to fig. 5 to 7. Wherein fig. 5 reflects a flow chart of the preparation method. Fig. 6 may reflect a substrate being processed. Fig. 7 may reflect a sink with a lead dielectric layer.
As shown in fig. 5, the process P500 of the preparation method may include the steps of:
s510, providing a substrate.
S520, depositing a lead dielectric layer on the substrate.
And S530, etching the lead dielectric layer to form a lead groove penetrating through the lead dielectric layer.
S540, filling the lead grooves to form control leads of the memory device.
The substrate in the aforementioned S510 may be provided with an N-type memory subunit, a P-type memory subunit, and an isolation trench. As shown in fig. 6, an N-type memory subunit 110, a P-type memory subunit 120, and an isolation trench 130 are disposed on a substrate 160.
The substrate 160 may be subjected to a metal ion doping process to form a P-type doped bottom (i.e., P-Well) at the N-type memory subcell 110 and an N-type doped bottom (i.e., N-Well) at the P-type memory subcell 120.
The present application is not limited to the method of preparing the substrate 160, which may be implemented according to existing semiconductor (particularly CMOS) preparation processes. As long as it provides the appropriate N-type memory sub-cell 110, P-type memory sub-cell 120, and isolation trench 130.
For example, two N-type lightly doped regions (NLDD) may be formed in the N-type memory subcell 110 of the substrate 160, and an N-type doped region (n+) is formed on the N-type lightly doped region. The N-doped region may serve as an N-type source and an N-type drain (the N-type drain being adjacent to the isolation trench 130). Similarly, the P-type memory subunit 120 may have a P-type lightly doped region (PLDD) formed on the N-type bottom and further provided with a P-type doped region (P+)
To further optimize the wire performance, the area to be connected to the wire may be provided with a metal silicide layer (e.g., low resistance NIPTSi, abbreviated NISI) on the surface to optimize the wire performance. Specifically, in fig. 6, the source, drain, and gate (i.e., control gate) surfaces may each form NISI layers. Wherein the control gate may be formed of polysilicon and is referred to as a poly control gate (Poly Control Gate).
Further, spacers formed of silicon nitride and oxide may be provided between the control gate and the floating gate, and on the sides of the control gate, not shown in fig. 6. The foregoing structures (such as lightly doped regions, NISI, isolation layers, etc.) may be implemented based on the prior art, and are not described herein.
Silicon oxide may be deposited to form a lead dielectric layer based on the substrate shown in fig. 6. In consideration of the thickness of the lead dielectric layer, chemical vapor deposition (e.g., deposition 200A) may be performed before ILD deposition (e.g., deposition 2100A) is performed during formation of the lead dielectric layer. In view of the deposition surface irregularities shown in fig. 5, a Chemical Mechanical Polishing (CMP) process may be performed after redeposition to form a planar surface.
After the lead dielectric layer is formed by redeposition, the lead positions in the lead dielectric layer may be etched, so as to form lead grooves (as shown in fig. 7) penetrating the lead dielectric layer corresponding to the respective lead positions. As shown in fig. 7, a lead dielectric layer 170 is formed on the substrate 160, and a plurality of lead grooves 171 are formed in the lead dielectric layer 170.
In particular, in the present application, considering the common drain design of the N-type memory sub-cell 110 and the P-type memory sub-cell 120, the lead grooves may form grooves that leak the drains of the N-type memory sub-cell 110 and the P-type memory sub-cell 120 across the isolation groove 130.
In some embodiments, it is contemplated that the aforementioned connection of the drains of the N-type memory subunit 110 and the P-type memory subunit 120 may also be implemented by a drain connection structure. The drain connection structure may be formed after the aforementioned S510 and then the subsequent steps may be performed. At this time, the width of the lead corresponding to the drain connection structure may be determined based on conventional arrangement without crossing the isolation trench.
In some embodiments, the aforementioned S530 may be performed through a mask layer. Illustratively, 1900A of an a-C (diamond-like carbon film) may be deposited over the aforementioned lead dielectric layer, followed by an anti-reflective coating (ARC SION+50A Oxide (OX) of 220A), followed by a bottom anti-reflective coating (BARC) of 200A, followed by a photoresist (Photo resin) of 1000A. The photoresist is then exposed and developed based on the lead locations, exposing the surface to be etched (i.e., the area is not coated with photoresist).
Based on the mask layer, a multi-step etching is performed to obtain the result shown in fig. 7. Wherein, the polymer remained in the groove can be cleaned after etching.
Based on the structure shown in fig. 7, the control leads can be formed by executing S540 described above to form the memory cell shown in fig. 2. Wherein it is generally necessary to deposit metal into the lead grooves 171 and planarize the surface to form corresponding leads. Specifically, 100A of Titanium (TI) and 50A of titanium nitride (TIN) may be deposited, refilled with tungsten (W), and subjected to chemical mechanical polishing to form the structure shown in fig. 2 described above.
Based on the above process, each memory unit of the memory device provided by the application can be formed, and a specific wire drawing and wiring process can be executed subsequently, so that a corresponding memory chip can be prepared. Further details regarding the subsequent processes are not described here.
Exemplary storage Structure:
In order to further optimize the performance of the memory cell, the application optimizes the specific structure of each specific memory subunit. Specifically, the floating gate in the storage subunit can be embedded into the substrate by adopting an embedded structure, so that the contact area of the floating gate and the substrate is increased, and the attraction capability of the floating gate to electrons/holes is improved.
Thus, the present application also provides a memory structure (fig. 8), in which the P-type memory subcell and the N-type memory subcell can both be designed (the memory device adopting the design can see fig. 10), so as to increase the threshold voltage writing/erasing speed.
As shown in fig. 8, the memory structure 200 may include a doped substrate 210, a source 220, a drain 230, a control gate 240, and a floating gate 250. The source 220 and the drain 230 are disposed at both ends of the doped substrate 210, and the control gate 240 is disposed between the source 220 and the drain 230. Floating gate 250 is disposed below control gate 240 and embedded in doped substrate 210, floating gate 250 including at least two extensions 251, at least two extensions 251 extending into the substrate.
The doped substrate 210, the source 220, and the drain 230 may be determined according to the actual types. If the memory structure 200 is configured as a P-type memory sub-cell, the doped substrate 210 may be an N-type doped substrate, and the source 220 and the drain 230 may be configured based on P-type doped regions on the surface of the N-type doped substrate. If the memory structure 200 is configured as an N-type memory sub-cell, the doped substrate 210 may be a P-type doped substrate, and the source 220 and the drain 230 may be configured based on N-type doped regions on the surface of the P-type doped substrate.
The foregoing embedding of floating gate 250 into doped substrate 210 may mean that floating gate 250 is at least partially structurally disposed within doped substrate 210. As shown in fig. 8, the extension 251 of the floating gate 250 may be disposed entirely within the doped substrate 210.
The extension 251 is generally formed as a filling structure of a trench in the doped substrate 210, that is, to form the extension 251, a plurality of trenches may be formed in the doped substrate 210, so that the floating gate 250 is filled in the trench, and the filling structure corresponding to the trench in the floating gate 250 is referred to as the extension 251.
When the floating gate 250 sucks electrons/holes, the extension 251 and the doped substrate 210 may form a larger contact area, thereby improving the efficiency of the sucking process.
In some embodiments, to connect the aforementioned at least two extensions 251, the floating gate 250 may further include a connection structure of the extensions 251. The connection structure may connect the respective extension portions 251. And may be provided in various portions of the extension 251 as desired.
In some embodiments, the aforementioned connection structure may be disposed proximate to control gate 240 for convenience in correspondence with control gate 240. That is, floating gate 250 may also include a connection 252, with connection 252 being disposed below control gate 240 (i.e., near control gate 240 and away from the bottom surface of doped substrate 210), including a drive surface 2521 toward control gate 240 and an extension surface 2522 toward the substrate. At least two extensions 251 extend from the extension plane 2522 toward the substrate (e.g., the bottom surface of the doped substrate 210) in a direction away from the connection 252.
In some embodiments, the sides and bottom of control gate 240 should be formed with isolation structures, taking into account the nature of the gate. While taking into account that control gate 240 is typically disposed over doped substrate 210, it is typically flanked by drain lead 231 and source lead 221. A first isolation layer 241 is provided between the control gate 240 and the floating gate 250 and a second isolation layer 242 is provided between the control gate 240 and the source lead 221 in order to secure the electrical properties of the control gate 240. A second isolation layer 242 is disposed between the control gate 240 and the drain lead 231. The first isolation layer 241 and the second isolation layer 242 each include at least one oxide isolation layer (e.g., silicon oxide) and at least one silicon nitride isolation layer.
Illustratively, the first isolation layer 241 includes a layer of silicon oxide and a layer of silicon nitride. The second isolation layer 242 includes three layers of silicon oxide and two layers of silicon nitride.
To further improve the floating gate immunity, the floating gate 250 may be fully embedded in the doped substrate 210 as described above. To this end, the application also provides a schematic structural diagram of another memory structure (fig. 9).
As shown in fig. 9, the connection 252 of floating gate 250 is embedded in doped substrate 210 such that drive surface 2521 is flush with the substrate surface of doped substrate 210.
Thereby, floating gate 250 is completely submerged into doped substrate 210 to store a signal. On the one hand, by burying the floating gate 250 to increase the anti-disturb capability of the device and on the other hand, by increasing the contact area of the floating gate 250 and the doped substrate 210 (e.g., the side of the connection 252), signals can be written into the floating gate 250 from multiple dimensions, thereby increasing the speed of writing. Meanwhile, the channel length of the semiconductor device is increased, and short channel effect caused by the reduced device size due to the progress of the process is avoided.
Alternatively, the aforementioned connection 252 may be further embedded in the doped substrate 210, such that the first isolation layer or the control gate is embedded in the doped substrate 210.
In some embodiments, the memory structure shown in fig. 9 described above may be combined with the memory device shown in fig. 2 described above, and the structure of the memory device may be referred to as fig. 10. That is, in fig. 10, the N-type gate of the N-type memory subunit and the P-type gate of the P-type memory subunit are both shown as the embedded floating gate and control gate combination shown in fig. 9.
In some embodiments, the present application also provides a method for preparing the memory structure shown in fig. 9. In forming the memory structure shown in fig. 9, this can be achieved by:
First, a substrate is provided and isolation trenches are formed on the substrate. The substrate is typically a silicon substrate, and the isolation trench may be etched based on a mask layer and filled with silicon oxide, which is not described herein.
Then, ion doping is carried out on the substrate to form a doped substrate. The specific doping ions can be selected according to actual needs, and for the combination of the PMOS and the NMOS, step doping can be performed based on the mask layer.
Then, the substrate is etched to form a first trench. The first trench corresponds to the connection portion 252 in fig. 9, and may be formed by mask etching.
Then, etching the first grooves to form at least two second grooves. The second trench corresponds to the extension portion 251 in fig. 9, and is formed based on the first trench, and may be implemented by mask etching.
And filling the first groove and the second groove to form a floating gate. In filling the floating Gate, a Gate Oxide layer (approximately 23A) may be formed, polysilicon (poly) may be deposited, and chemical mechanical polishing may be performed.
Next, a control gate and a first isolation layer between the control gate and the floating gate are formed. The isolation layer (first silicon oxide and then silicon nitride) and the polysilicon of the control gate may be deposited first during the re-execution. And then forming a control gate and a first isolation layer by mask etching.
Then, a source and a drain may be formed. Specifically, the lightly doped region may be formed first and then the doped region may be formed. Among them, PLDD is generally realized by sequentially implanting Ge, C, AS (pockect) to a certain depth. NLDD is typically achieved by sequentially implanting Ge, C, B (pockect) to a certain depth. The N+ region is mainly and sequentially implanted with P\GE\P\As\F with a certain depth. The P+ region is mainly implanted with Ge\B\BF2 to a certain depth in sequence.
Next, a metal silicide layer (such as low resistance NIPTSi, abbreviated NISI) is formed on the source, drain and control gate surfaces.
Subsequently, the preparation process of fig. 5 may be referred to for subsequent processing, which is not described herein.
In some embodiments, the second isolation layer at the side of the control gate may be performed during the formation of the source and drain electrodes. For example, a layer of silicon oxide may be formed on the side of the control gate, then a layer of silicon nitride may be formed on the side of the control gate, then the preparation process of the lightly doped region is performed, after the preparation process is completed, a layer of silicon oxide and a layer of silicon nitride may be formed on the side of the control gate, and in the subsequent wire-guiding process, a layer of silicon oxide (i.e., a portion of the dielectric material remains on the side) may be formed to form the second isolation layer.
The technical effects are as follows:
in summary, the memory device, the control method and the manufacturing method thereof provided by the application have the following unexpected effects:
① The memory device provided by the application has the advantages that one memory cell is provided with two sub-cells and is connected with each other through the drain electrodes, and the threshold voltages stored in the sub-cells can be read independently through configuration of different voltage signals, so that each sub-cell has independent memory capacity, the memory capacity of a single memory cell in the memory device is improved, and the memory device can store more information.
② The two subunits in one memory cell can be a P-type memory subunit and an N-type memory subunit respectively, and a complementary semiconductor structure is formed, so that the memory cell has better electrical performance and stability.
③ Each storage subunit can be set based on the floating gate, so that nonvolatile multi-time compiling can be realized, different working voltages can be realized, and the written working voltages can be erased according to requirements.
④ The memory cell is internally provided with a P-type memory subunit and an N-type memory subunit. Different data have different storage effects so as to adapt to different storage requirements.
⑤ The application also optimizes the read-write-erase process of the memory cell, especially when the threshold voltage is changed, an operation can be directly executed according to the adjusted threshold voltage, thereby improving the speed of the threshold voltage changing process.
⑥ The floating gate structure is optimized, so that the floating gate structure is provided with a plurality of extending parts extending towards the substrate, the contact area between the floating gate and the substrate is increased, and the writing speed is increased.
⑦ The channel length of the semiconductor device is increased by arranging the extension part, so that short channel effect caused by the reduction of the device size due to the progress of the process is avoided.
⑧ The floating gate of the application can be completely sunk into the doped substrate to store signals. Thus, the anti-interference capability of the device is increased by burying the floating gate, and the contact area (such as the side surface of the connecting part) between the floating gate and the doped substrate is further increased, so that signals can be written into the floating gate from multiple dimensions, and the writing speed is increased.
The embodiments of the invention disclosed above are intended only to help illustrate the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best understand and utilize the invention. The invention is limited only by the following claims, along with their full scope and equivalents.