Detailed Description
The following description of certain embodiments is merely exemplary in nature and is in no way intended to limit the scope of the disclosure, its application, or uses. In the following detailed description of embodiments of the present systems and methods, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration specific embodiments in which the described systems and methods may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the presently disclosed systems and methods, and it is to be understood that other embodiments may be utilized and that structural and logical changes may be made without departing from the spirit and scope of the present disclosure. Moreover, for the purposes of clarity, detailed descriptions of certain features will not be discussed as such to obscure the description of the embodiments of the disclosure as will be readily apparent to those of ordinary skill in the art. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present disclosure is defined only by the appended claims.
Information in the memory array may be accessed through one or more access operations, such as read or write operations. During example access operations, the word lines may be activated based on row addresses, and then the memory cells selected along the active word lines may be read or written with their information based on which bit lines are accessed, which bit lines are accessed may be based on column addresses. The memory array may be refreshed row by row (e.g., as part of an auto-refresh and/or self-refresh mode) with memory cells along each row being periodically refreshed. The speed of refreshing rows (e.g., the maximum time any given row experiences between refreshes) may be determined based on the expected rate of decay of information.
Various access patterns to rows (aggressor rows) can result in increased information decay rates in nearby memory cells (e.g., along victim rows). For example, "row hammering (row hammer)" may involve repeated access to an aggressor row, which may increase the decay rate in adjacent rows (and/or more distant rows). Thus, it may be important to track the number of accesses to each row to determine if it is an aggressor so that the victim row can be identified and refreshed as part of the targeted refresh operation. For example, each word line may have an associated count value that is used to determine how many times the word line is accessed. Based on those access counts, rows for the target refresh operation may be identified and stored in the target refresh queue or aggressor queue.
The memory may determine when to perform a targeted refresh operation based on internal logic. In addition to, or instead of, the internal logic, the controller may issue a refresh management (RFM) command. In response to the RFM command, the memory may perform one or more target refresh operations based on the address in the target refresh queue. The controller may also monitor access operations and provide Direct RFM (DRFM) commands, where the controller specifies an aggressor address and instructs the memory to perform a targeted refresh on a victim of the aggressor. However, it may happen that if many DRFM commands are performed on the same aggressor, repeated refreshing of the same victim word line may in turn cause those victim word lines to become aggressors again, resulting in an increase in the rate of decay of information in word lines outside the victim range of address refresh specified by the DRFM commands. Since this may result in information loss, it may be important to track the address specified by the DRFM command in order to prevent repeated refreshing of the address.
The present disclosure relates to devices, systems, and methods for direct refresh management attack identification. The memory device receives a DRFM command and a DRFM aggressor address. The DRFM logic circuit compares the DRFM aggressor address with a stored previous DRFM aggressor address. If there is no match, then a target refresh operation is performed on the victim of the DRFM aggressor address and the DRFM aggressor address is stored as the previous DRFM aggressor address. If so, the DRFM operation may be skipped.
In some embodiments, the DRFM logic circuit may skip N duplicate DRFM commands in a row that have the same DRFM aggressor address, then allow M of those operations before skipping N duplicate addresses again. For example, if a single DRFM address is constantly provided, the DRFM logic may perform one DRFM operation, skip 3, then perform one DRFM operation, skip 3, and so on. In some embodiments, the DRFM logic circuit may implement different skip logic for different victim address calculations. For example, the DRFM logic circuit may calculate different values of applications N and M for different victim addresses. In example implementations, if the same address is provided, refresh operations (e.g., +/-1 refresh) for victims closer to the DRFM aggressor may occur more frequently than refresh operations (e.g., +/-3 refreshes) for victims farther away. In other words, more distant victim addresses may be skipped more frequently.
In some embodiments, the memory may alternatively perform some other action when skipping the DRFM operation. For example, in response to the DRFM operation beginning to be skipped, the memory may perform a target refresh (e.g., a normal RFM operation) on the victim of the address stored in the target refresh queue.
In some embodiments, the DRFM aggressor address may be captured from the row address bus in response to a DRFM sample command, and then the address may be refreshed in response to a DRFM refresh command. In some embodiments, the controller may issue these as separate commands. In some embodiments, the controller may issue a single command and the memory may generate the sample and refresh commands. In response to a DRFM sample command, the current address along the row address bus is stored in a first register and compared to the previous DRFM address in a second register, the result of the comparison determining what happens in response to a DRFM refresh command. Fig. 1 is a block diagram of a semiconductor device in accordance with at least one embodiment of the present disclosure. The semiconductor device 100 may be a semiconductor memory device, such as a DRAM device integrated on a single semiconductor chip. Also shown is a controller 150 that may operate the memory device 100. Controller 150 may represent a processor or other unit that stores and retrieves data from memory device 100. In some embodiments, the controller 150 and the memory 100 may be integrated onto a single circuit or chip. In some embodiments, controller 150 and memory 100 may be separate components. Memory 100 and controller 150 are communicatively coupled along a plurality of buses (e.g., a data bus, a clock bus, and a command/address bus) not shown in fig. 1.
The semiconductor device 100 includes a memory array 118. The memory array 118 is shown to include a plurality of memory banks. In the embodiment of FIG. 1, memory array 118 is shown to include eight BANKs BANK0 through BANK7. More or fewer banks may be included in the memory array 118 of other embodiments. Each bank includes a plurality of word lines WL (rows), a plurality of bit lines BL (columns), and a plurality of memory cells MC arranged at intersections of the plurality of word lines WL and the plurality of bit lines BL.
The selection of the word line WL is performed by the row decoder 108 and the selection of the bit line BL is performed by the column decoder 110. In the embodiment of FIG. 1, row decoder 108 includes a respective row decoder for each bank, and column decoder 110 includes a respective column decoder for each bank. The bit lines BL are coupled to respective Sense Amplifiers (SAMP). The data read from the bit line BL is amplified by the sense amplifier SAMP and transferred to the read/write amplifier 120 through the complementary local data line (LIOT/B), transfer Gate (TG), and complementary main data line (MIOT/B). In contrast, the write data output from the read/write amplifier 120 is transferred to the sense amplifier SAMP through the complementary main data line MIOT/B, the transfer gate TG, and the complementary local data line LIOT/B, and written into the memory cell MC coupled to the bit line BL.
The semiconductor device 100 may employ a plurality of external terminals including command and address terminals coupled to a command and address (C/a) bus to receive command and address and CS signals, clock terminals to receive clocks CK and/CK, data terminals DQ to provide data, and power supply terminals to receive power supply potentials VDD, VSS, VDDQ and VSSQ. One or more of the external terminals may be coupled to the controller 150.
The clock terminal is supplied with external clocks CK and/CK supplied to the input circuit 112 through the controller 150. The external clocks may be complementary. The input circuit 112 generates an internal clock ICLK based on CK and/CK clocks. The ICLK clock is provided to command decoder 110 and internal clock generator 114. The internal clock generator 114 supplies various internal clocks LCLK based on the ICLK clock. The LCLK clock may be used to time the operation of various internal circuits. The internal data clock LCLK is provided to the input/output circuit 122 to time operation of the circuits included in the input/output circuit 122, for example, is provided to the data receiver to time reception of write data.
The C/a terminal may be supplied with a memory address through the controller 150. The memory address supplied to the C/a terminal is transferred to the address decoder 104 via the command/address input circuit 102. The address decoder 104 receives the address and supplies a decoded row address XADD to the row decoder 108 and a decoded column address YADD to the column decoder 110. The address decoder 104 may also supply a decoded bank address BADD, which may indicate a bank of the memory array 118 containing a decoded row address XADD and a column address YADD. The C/a terminal may be supplied with commands. Examples of commands include timing commands for controlling the timing of various operations, access commands for accessing memory (e.g., read commands for performing read operations and write commands for performing write operations), and other commands and operations. The access command may be associated with one or more row address XADD, column address YADD, and bank address BADD to indicate the memory cell(s) to be accessed.
The commands may be provided as internal command signals to the command decoder 106 via the command/address input circuit 102. The command decoder 106 includes circuitry for decoding internal command signals to generate various internal signals and commands for performing operations. For example, the command decoder 106 may provide a row command signal to select a word line and a column command signal to select a bit line.
The device 100 may receive an access command as a read command. In response to a read command, data is read out of the memory array 118 to the data terminals DQ. Data is read from memory cells in a bank specified by BADD at the intersection of a word line specified by XADD and a bit line specified by YADD. The read command is received by the command decoder 106, and the command decoder 106 provides internal commands such as a row activate signal ACT and a read signal R. In response to ACT and row address XADD, row decoder 108 activates the specified word line, and in response to R and column address YADD, column decoder 110 couples sense amplifiers coupled to the specified bit lines to read/write amplifier 120 to read out the values along those bit lines as read data from the memory cells at the intersection with the active word line to IO circuit 122. The read data is output from the data terminal DQ to the outside via the input/output circuit 122. The precharge command Pre precharges the word line and deactivates (or turns off) it.
The device 100 may receive an access command as a write command. In response to the write command, data received along the DQ terminals is written to the memory array 118. Data is written to memory cells in a bank specified by BADD at the intersection of a word line specified by XADD and a bit line specified by YADD. The read command is received by the command decoder 106, and the command decoder 106 provides internal commands such as ACT and write signal W. IO circuit 122 receives data from the DQ terminals, which is provided to read/write amplifier 120. In response to ACT, the row decoder activates the word line specified by XADD and in response to W, the column decoder 110 couples the write data from the read/write amplifier 120 to the bit line specified by YADD, where the sense amplifier amplifies the write data so that it is written to the memory cell at the intersection with the active word line. The precharge Pre turns off the word line.
The device 100 may also receive commands from the controller 150 to cause the device 100 to perform refresh operations. For example, the controller 150 of the memory may place the device 100 in an auto-refresh mode and provide a refresh signal REF. The device 100 may also enter a self-refresh mode in which a refresh signal is internally generated. The controller 150 may also provide RFM or DRFM commands that cause the memory 100 to perform a target refresh operation, as described in more detail herein.
The refresh signal REF is supplied to the refresh address control circuit 116. The refresh address control circuit 116 supplies a refresh row address RXADD to the row decoder 108, and the row decoder 108 refreshes memory cells along the word line WL identified by the refresh row address RXADD. The refresh control circuit 116 may perform a sequential or normal refresh operation in which the refresh address RXADD is generated based on sequential logic of the refresh control circuit 116, or may perform a targeted refresh operation in which the refresh address RXADD is based on an identified aggressor address stored in an aggressor queue of the refresh control circuit 116.
During sequential or normal refresh operations, the refresh control circuit 116 may use sequential logic to determine the next RXADD. For example, RXADD may be based on the previous value of RXADD (e.g., RXADD (i+1) =rxadd (i) +1). A counter circuit may be used to generate sequential refresh addresses. During a targeted refresh operation, refresh control circuit 116 may generate RXADD based on the identified aggressor address. For example, a refresh address may represent a word line that is physically adjacent to a word line associated with an aggressor address. In some embodiments, sequential refresh addresses may be associated with more word lines than target refresh addresses. During an internally directed target refresh operation or a target refresh operation performed based on RFM commands, the aggressor address is an address identified by refresh control circuit 118. The aggressor address is a DRFM aggressor address provided by the controller during a target refresh operation performed based on the DRFM command.
When the refresh control circuit 116 receives the refresh signal REF, it may perform a set of refresh operations, and may determine, based on internal logic, whether those refresh operations are sequential or targeted refresh operations. For example, in response to a REF, the refresh control circuit may perform a set of refresh operations, and may perform one or more target refresh operations every N sequential refresh operations. When refresh control circuit 116 receives the RFM signal from RFM timing circuit 132, it performs one or more targeted refresh operations.
Refresh control circuit 116 uses one or more criteria to identify an aggressor address. For example, access patterns to different addresses may be used. In the example of fig. 1, an aggressor detection scheme using per row access count or Per Row Hammer Tracking (PRHT) is shown. However, other schemes for detecting aggressor addresses may be used in other example embodiments instead of or in addition to PRHT.
In the example of fig. 1 as part of a PRHT, each word line includes a plurality of counter memory cells 126 that store a count value XCount associated with the word line. The count value XCount may represent the number of times the word line has been accessed. When a row is accessed (e.g., by ACT and XADD), the count value XCOUNT is read out and updated (e.g., by incrementing). If the updated count value has crossed the threshold, the row address XADD is determined to be an aggressor and added to the aggressor queue. The count value in counter memory unit 126 may be reset when an address is added to the queue. If the count does not cross the threshold, the updated count value is written back to the counter memory unit 126.
The controller 150 may also perform its own tracking of the aggressor address. For example, controller 150 may include target refresh or Row Hammer Refresh (RHR) logic 152 that monitors the address provided to memory 100 and determines whether it is an aggressor address. If the address is determined to be an aggressor, RHR logic circuit 152 may issue a DRFM command to memory 100. The DRFM command may specify a DRFM aggressor address and instruct the memory 100 to perform one or more target refresh operations based on the DRFM aggressor address. For example, the controller 150 may provide a DRFM command (e.g., as part of an access operation) when providing a DRFM aggressor address along the C/a bus, and the command decoder 106 may cause the refresh control circuit 116 to sample (or latch) the DRFM aggressor address.
When the refresh control circuit 116 receives a DRFM aggressor address, it compares the DRFM aggressor address with the previous DRFM aggressor address. If not, a target refresh operation responsive to the DRFM command may be performed on the DRFM aggressor address. If so, the target refresh operation for the DRFM aggressor address may be skipped. In this way, refresh control circuit 116 may prevent multiple consecutive DRFM operations from being performed on the same DRFM aggressor address. In some embodiments, refresh control circuit 116 may include a counter and may count the number of times the DRFM aggressor address matches a previous address. When the counter has a certain value or values, the counter may allow all or part of normal DRFM operation to proceed. In example implementations, the counter may be incremented each time an address matches, and may count from 0 to 3 before being reset back to 0. When the counter is 0 or 1, the DRFM logic may skip operations, but allow operations on 2 and 3. Other example implementations may be used in other examples.
The power supply terminals are supplied with power supply potentials VDD and VSS. The power supply potentials VDD and VSS are supplied to the internal voltage generator circuit 124. The internal voltage generator circuit 124 generates various internal potentials VPP, VARY, VPERI and the like based on the power supply potentials VDD and VSS supplied to the power supply terminals. The internal potential VPP is mainly used in the row decoder 108, the internal potential VARY is mainly used in the sense amplifier SAMP included in the memory array 118, and the internal potential VPERI is used in many other peripheral circuit blocks.
The power supply terminals are also supplied with power supply potentials VDDQ and VSSQ. The power supply potentials VDDQ and VSSQ are supplied to the input/output circuit 122. In an embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminal may be the same potentials as the power supply potentials VDD and VSS supplied to the power supply terminal. In another embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminal may be different potentials from the power supply potentials VDD and VSS supplied to the power supply terminal. The power supply potentials VDDQ and VSSQ supplied to the power supply terminals are used for the input/output circuit 122, so that power supply noise generated by the input/output circuit 122 does not propagate to other circuit blocks.
Fig. 2 is a block diagram of a portion of a memory according to some embodiments of the present disclosure. FIG. 2 shows an example of a portion of a memory related to a refresh operation. Certain components and signals are omitted from the view of fig. 2. In some embodiments, memory 200 may implement a portion of memory device 100 of fig. 1 in some embodiments.
The memory 200 of FIG. 2 shows a DRAM interface 240 that represents the various components of the memory that provide signals such as row address XADD, row activate signal ACT and refresh signal REF, and RFM command RFM. The refresh control circuit 216 (e.g., 116 of fig. 1) performs a refresh operation in response to the refresh signal REF or RFM command RFM. In response to the signal REF or RFM, the refresh control circuit 216 provides a refresh address RXADD and the row decoder 208 (e.g., 108 of FIG. 1) performs a refresh operation on the memory cells of the array 218 (e.g., 118 of FIG. 1).
The DRAM interface 240 also provides signals related to DRFM operations. The DRAM interface 240 provides a DRFM refresh signal DRFM and a DRFM sample signal DRFM_Samp. In some embodiments, both signals may be provided in response to a DRFM command from the controller (e.g., by a command decoder). The DRFM logic circuit 260 receives the DRFM sample command drfm_samp and stores the row address XADD as the DRFM aggressor address DRFMXADD. The DRFM logic circuit 260 determines whether the DRFM Skip signal drfm_skip should be provided based on a comparison of the sampling address with the previous sampling address. In response to the DRFM refresh signal DRFM, the refresh control circuit 216 performs a target refresh based on DRFMXADD unless the signal drfm_skip is active, in which case the operation is skipped (or a different type of target refresh operation is performed).
The refresh control circuit 216 includes a refresh state control circuit 242, the refresh state control circuit 242 determining whether a target refresh operation or a sequential refresh operation is to be performed by issuing an internal refresh signal IREF and/or a target refresh signal RHR. In response to the refresh signal IREF/RHR, the refresh address generator circuit 250 provides a refresh address RXADD. Refresh control circuit 216 also includes an aggressor detector circuit 217 that identifies and stores aggressor addresses in aggressor queue 244. When the refresh state control circuit 242 signals a target refresh operation (e.g., by providing RHR), the refresh address generator circuit 250 uses one of the addresses in the aggressor queue 244 to generate the refresh address RXADD. When the refresh state control circuit 242 instructs DRFM operation, the refresh address generator 250 uses the address DRFMXADD to generate RXADD.
In fig. 2, a dashed box is used to represent components that may be duplicated on a bank-by-bank basis within the memory. For example, each bank may have its own row decoder 208, refresh control circuit 216, and memory array 218. In other example embodiments, other arrangements of components that repeat on a per bank basis and that are shared by multiple banks may be used.
The refresh state control circuit 242 controls which refresh operations are performed and how many refresh operations are performed in response to the signals REF and/or RFM/DRFM. The refresh state control circuit 242 provides an internal refresh signal IREF and a target refresh signal RHR. Signal IREF may indicate a sequential refresh operation, while RHR may indicate a target refresh operation. In some embodiments, separate IREF may indicate a sequential or normal refresh operation, while IREF and RHR are simultaneously active in indicating a target refresh operation. In some embodiments, IREF and RHR may be individually active to indicate different types of refresh operations.
In response to the refresh signal REF, the refresh state control circuit 242 may perform a plurality of refresh operations or pumps. For example, the number of activations of IREF. In response to REF, the refresh state control circuit 242 may perform a mix of sequential refresh operations and targeted refresh operations based on internal logic. For example, a certain number N of sequential refresh operations (e.g., by providing IREF) may be performed with a certain number M of target refresh operations (e.g., by providing RHR). For example, the refresh state control circuit 242 may perform four pumps, two of which are normal refresh operations and two of which are target refresh operations. In response to the signal RFM, the refresh state control circuit 242 performs a plurality of target refresh operations (e.g., two or four target refresh operations) by providing the signal RHR.
In response to the DRFM operation, as indicated by the DRFM refresh signal DRFM when the DRFM Skip signal drfm_skip is inactive, the refresh state control circuit 242 performs one or more target refresh operations. The refresh state control circuit 242 may provide a signal, such as a DRFM, to the refresh address generator (e.g., in place of or in addition to signal RHR) to indicate that the refresh address RXADD should be generated based on the DRFM aggressor address DRFMXADD. In response to the skipped DRFM operation, the refresh state control circuit 242 may Skip the DRFM operation as indicated by the signal DRFM and the signal drfm_skip being active. In some embodiments, the refresh state control circuit 242 may perform other refresh operations, such as a target refresh operation, during the time that the DRFM operation has been performed. For example, when drfm_skip is active, the refresh state control circuit 242 may provide IREF and/or RHR in response to the signal DRFM without providing DRFM.
The refresh address generator circuit 250 includes a sequential refresh address generator circuit 252 that provides sequential refresh addresses as RXADD in response to (or only in response to) IREF. The sequential refresh address generator circuit 252 generates refresh addresses based on sequential logic. For example, the refresh address may be generated based on addresses provided as part of a previous sequential refresh operation.
The refresh address generator circuit 250 includes a target refresh address generator circuit 254, the target refresh address generator circuit 254 providing a target refresh address as RXADD in response to RHR and the identified aggressor address HitXADD from the aggressor queue 244, or RXADD based on DRFMXADD in response to the signal DRFM (or DRFM and RHR together). Since the logic for generating the target refresh address may be similar except for the source of the aggressor address for the target refresh operation, the operation of the target refresh address generator circuit 254 will be described in general with respect to HitXADD, however, in the case of a DRFM operation, DRFMXADD may be replaced.
The target refresh address generator circuit 254 generates a refresh address based on the aggressor address HitXADD. For example, refresh address RXADD can represent a word line adjacent to the word line represented by HitXADD (e.g., RXADD = HitXADD +/-1). In other example embodiments, other relationships between refresh addresses and aggressor addresses may be used (e.g., hitXADD +/2, +/3, etc.). In some embodiments, multiple target refresh operations may be performed on a single aggressor address to capture multiple victims (e.g., refresh addresses may be generated for +/-1, +/-2, etc.).
Refresh control circuit 216 includes an aggressor detector circuit 217, which aggressor detector circuit 217 determines whether or not the accessed address XADD should be added to aggressor queue 244 as aggressor address HitXADD. Various schemes may be used to determine whether an address should be added to a queue. Fig. 2 shows an example embodiment in which a PRHT in a counter memory unit 226 (e.g., 126 of fig. 1) is used. Other aggressor tracking schemes may be used in other example embodiments.
When a row is accessed, its count value XCount is read out from counter memory unit 226 to aggressor detector 217. The counter circuit 246 updates the count value to an updated count value XCount'. In some embodiments, counter circuit 246 may update the count value by incrementing XCount (e.g., XCount' =xcount+1). The aggressor detector circuit 217 includes a comparator circuit 248, the comparator circuit 248 comparing the updated count value XCount' with a threshold value. If the count does not cross the threshold (e.g., is less than the threshold), the updated count value is written back to the counter memory unit 226. If the count has crossed the threshold (e.g., is greater than or equal to the threshold), then the aggressor detector circuit provides a signal AGG to indicate that the current row address is an aggressor. The updated count value is reset (e.g., to an initial value such as 0) and written back to the counter memory cell 226.
In some embodiments, the threshold may represent a maximum value of a binary number of the count value. The count value may cross the threshold by "scrolling" from a maximum value to a minimum value. In such embodiments, the comparator 248 may be omitted and the counter 246 may send the signal AGG when counting the scrolling.
In response to signal AGG, aggressor queue 244 adds current row address XADD to the queue. Aggressor queue 244 can be a register that includes a plurality of slots, each slot storing a row address. Each slot includes a plurality of latch circuits, such as Content Addressable Memory (CAM) cells or other types of latches, that store bits of an address stored in that slot. The number of slots in the queue may be generally referred to as the "depth" of the aggressor queue 244.
In response to signal RHR, aggressor queue 244 provides an address to target refresh address generator circuit 254 as aggressor address HitXADD. After the address is provided, the address is removed from the queue (or the slot is marked as empty so that it can be overwritten). The queue 244 may use various logic to determine which address to provide. For example, it may act as a FIFO queue. In some embodiments, if the queue 244 is full when the signal AGG is received, the refresh control circuit 216 may provide a signal to indicate an alarm. In some embodiments, the controller may issue an RFM command sequence to clear the queue in response to a queue full alarm. In response to signal AGG, aggressor queue 244 may search open slots (e.g., slots that do not store addresses or slots for which addresses have been provided as HitxADD) and store current address XADD in the open slots.
The DRFM logic 260 determines whether the DRFM operation should be skipped based on a comparison between the current DRFM aggressor address and the previous DRFM aggressor address. In response to the DRFM sample command drfm_samp, the DRFM logic 260 stores the address XADD in the latch 262 and compares it with the previous DRFM address. If there is a match, the signal drfm_skip is provided at an active level. If there is no match, then the signal DRFM_skip is not provided and the address is stored as the previous address for the next comparison.
In some embodiments, the DRFM logic circuit 260 may include a counter circuit that counts the number of times drm_skip is provided. When the counter reaches a threshold, it is reset and no drfm_skip signal is provided even if the sample address and the previous address match. The counter may also be reset when the sampling address changes (e.g., when there is no match). In some embodiments, certain values of the counter may cause the DRFM logic 260 to skip DRFM operations, while other values may cause the DRFM logic 260 to allow DRFM operations.
In some embodiments, the DRFM logic 260 may employ different logic (e.g., different counters) for different computations of the refresh address. For example, if there is no match, the refresh address generator 250 may provide DRFMXADD +/1, +/2, +/3, and+/4 as refresh addresses (e.g., 8 refresh addresses) as part of the DRFM operation. The DRFM logic circuit 260 may use different counter logic to skip some of those victim calculations compared to other victim calculations. In some embodiments, different logic may be applied to groups that are remote from the aggressor. For example, all refreshes (+/-1, +/-2, +/-3, +/-4) may be skipped at a first rate, +/-2, +/-3, and+/-4 at a second rate, +/-3, and+/-4 at a third rate, +/-3, and+/-4 at a fourth rate. Other groups of address computations and rates may be used in other example embodiments. In example implementations, a four-bit counter may be used and incremented each time an address matches. With values of 0 and 1, all refreshes can be skipped. With values of 2 and 3, +/-1 and +/-2 refreshes can be performed, with +/-3 and +/-4 skipped. When there is no match, all refreshes are performed.
Fig. 3 is a block diagram of a DRFM logic circuit according to some embodiments of the disclosure. In some embodiments, the DRFM logic 300 may implement the DRFM logic 260 of fig. 2. The DRFM logic circuit 300 includes one or more address management circuits 310 and a DRFM control circuit 308. The address management circuits 310 each store a previous DRFM aggressor address and compare the current address to the addresses stored in the address management circuits. Each DRFM logic circuit includes a first register 302, a second register, and a comparator circuit 304. Based on the output from the address management circuit 310, the DRFM control circuit 308 determines whether to provide a DRFM Skip signal drfm_skip.
Since the DRFM address management circuit 310 may generally be similar to each other, only a single address management circuit is described in detail herein. In some embodiments, only a single address management circuit may be used. In some embodiments, multiple address management circuits may be used, such as two, three, or more address management circuits. Each address management circuit allows the DRFM logic circuit 300 to track additional previous DRFM aggressor addresses.
In an example embodiment having a single address tracking circuit 310, the address XADD is stored in the first register 302 in response to a DRFM sample signal (e.g., drfm_samp of fig. 2). The comparator circuit 304 compares the address stored in the first register 302 with the address stored in the second register 306. If so, the comparator provides a skip signal SameSkip to the control circuit 308. If there is no match, the comparator circuit 304 provides a reset signal NotSameReset to the control circuit 308.
In response to a DRFM update signal (e.g., the DRFM of fig. 2), the address from the first register 302 is moved to the second register 306. In this way, the second register 306 stores the previous DRFM address.
The control circuitry 308 changes the count value (e.g., by incrementing the count value) in response to SameSkip. If the count value is below the threshold, the control circuit 308 provides the DRFM Skip signal DRFM_skip at an active level. If the count value is at the threshold, the count value is reset and the signal DRFM_skip is not provided in response to signal SameSkip. In some embodiments, the count value may reach a maximum value and "scroll" to an initial value, and when the count value scrolls, it may act as the count reaching a threshold. For example, if the counter is a two-bit counter, drfm_skip may be provided for 3 out of each four activations of SameSkip (assuming NotSameReset is not provided). When the control circuit 308 receives the reset signal NotSameReset, the count value is reset to an initial value and the signal drfm_skip is not provided.
In some embodiments, there may be multiple address tracking circuits 310. For example, in an embodiment with two address tracking circuits, there may be two comparators 304 and two second registers 306. When an address is sampled, two comparators compare the sampled address with their corresponding second registers. Each comparator separately provides a signal SameSkip or NotSameReset based on the comparison. Control circuitry 308 receives the signals and determines what to do based on the signals. For example, if the sample address does not match the stored address (e.g., both signals are NotSameReset), then one of the two second registers is reset and the sample address is written to that register. For example, the older of the two memory addresses may be overwritten. If one of the signals SameSkip is active, the control circuitry may update the count value associated with the address tracking circuitry and provide a DRFM_skip signal until the counter reaches a threshold or is reset.
In some embodiments, the first latch 302 may be shared by multiple address tracking circuits 310 such that the same DRFM aggressor address is provided to each comparator.
Fig. 4 is a table of example patterns of DRFM addresses according to some embodiments of the disclosure. Table 400 shows four different address modes provided as part of the DRFM operation. Three different addresses are shown, labeled A, B and C. Table 400 shows how DRFM logic circuits (e.g., 260 of fig. 2 and/or 300 of fig. 3) may respond to different example address sequences. The behavior represented by table 400 is just one example of how the DRFM logic circuit may respond to an address pattern, and different operations may be used in other example embodiments. The example of fig. 4 shows the operation of a DRFM logic circuit with two address tracking circuits, each associated with a two-bit counter (e.g., threshold 4). The pattern and which addresses to skip are based on circuit initialization just before the first address is shown in each example pattern. Skipped addresses are shown in the box.
Table 400 shows four example address patterns. In the first mode, the sequence of the DRFM address AAB is repeated repeatedly. In this mode, the memory performs the target refresh operation for address a, skips (for a) the next DRFM operation, and then performs the next DRFM operation for B and a, then skips the second DRFM operation for a, and so on.
In the second mode, the reception address a is repeated as a DRFM address. In this mode, the DRFM operation is performed the first time address a is received. The next three DRFM operations for a are skipped (e.g., when the counter is incremented). The fifth time a is provided, the counter is reset and the DRFM operation is performed again on a.
In the third mode, the address AB is repeated repeatedly. The first time a is provided, it is stored in the first address management circuit and DRFM is performed on a. The first time B is provided, it is stored in the second address management circuit, and DRFM operation is performed on B. The second time a is provided, it is compared to the first and second management circuits and because of the match, the DRFM operation on a is skipped. The second time B is provided, it is compared to the address management circuit and matched to the second circuit but not to the first circuit, which resets the first address management circuit (and associated counter). Because of the matching with the second circuit, the DRFM operation for B is skipped. When a is received for the third time since the first address management circuit reset, a DRFM operation is performed on a and the second DRFM address management circuit is reset. The third time B is received, DRFM is performed on B, and so on.
In the fourth example mode, address ABC is repeatedly received. Since this mode resets two address management circuits at a time, the DRFM operation is not skipped.
Fig. 5 is a timing diagram of example operation of a refresh control circuit according to some embodiments of the present disclosure. In some embodiments, the timing diagram 500 may be implemented by one or more of the apparatus or systems described herein. For example, the timing diagram may represent operation of refresh control circuit 116 of fig. 1 and/or 200 of fig. 2. Timing diagram 500 illustrates operations in a memory having a DRFM logic circuit (e.g., DRFM logic circuit 260 of fig. 2 and/or 300 of fig. 3).
In the example of fig. 5, as part of performing the DRFM operation, the refresh control circuit performs a total of four refresh operations, two of which are DRFM operations and two of which are target refresh operations (e.g., using addresses from the aggressor queues). The timing diagram shows 4 consecutive DRFM operations, each of which may be associated with the same DRFM aggressor address (e.g., mode 2 of table 400 of fig. 4). At some time before the initial time t0, an address is provided with the sampling signal. At a first time t0, a DRFM command is received and four refresh pumps RRAST are generated. The first two pumps are DRFM pumps DRFMpump. The next two pumps are the target update pumps RHRpump. At the next three times t1, t2 and t3 when the DRFM update command is received, the skip signal is active and thus four refresh pumps are still generated, but all four are target refresh pumps because the target refresh operation is replacing the skipped DRFM operation.
Fig. 6 is a schematic diagram of a DRFM logic circuit with two comparators, according to some embodiments of the disclosure. In some embodiments, the DRFM logic circuit 600 of fig. 6 may implement the DRFM logic circuit 260 of fig. 2 and/or 300 of fig. 3. In particular, the DRFM logic circuit 600 of fig. 6 represents an example embodiment in which there are two address management circuits, each comparing a received DRFM aggressor address with a first or second previous DRFM aggressor address, respectively.
The DRFM logic circuit 600 includes a DRFM control circuit 630 (e.g., 308 of fig. 3) and two comparator circuits 610 and 620 (e.g., comparator circuits 304 in the first and second address management circuits, such as 310 of fig. 3). Latches, such as latches 302 and 306 of fig. 3, are not shown. However, the DRFM logic 600 may include three latches, one for storing the current sampled DRFM address DRFM_ADDR_SAMP, one for storing the first previous DRFM address DRFM_ADDR_Flush, and one for storing the second previous DRFM address DRFM_ADDR_Flush2nd.
Each comparator circuit 610 and 620 may be similar in operation except for the signals it receives. Both comparators 610 and 620 receive system power, e.g., VPERI, and a DRFM aggressor address DRFM ADDR SAMP (and its inverse DRFM ADDRF SAMP, which inverts all bits) and a control signal tmfzDRFMSkipCtrl that determines whether the DRFM skip logic is enabled, a block enable signal BlockEn that determines whether the operation of the comparator is blocked, a compare enable signal CompareEn that causes the comparator to perform its compare function, and a DRFM signal DrfmrisePulse that determines whether to perform the DRFM operation. The first comparator 610 receives a first previous address drfm_addr_flush (and its opposite address) and a first reset signal rst3, and the second comparator 620 receives a second previous address drfm_addr_ Flus2nd (and its opposite address) and a second reset signal rst4.
The comparator circuit may be operable when tmfzDRFMSkipCtrl is active (e.g., the DRFM skip feature is enabled in a setting such as a fuse array and/or a mode register of the memory) and signal CompareEn is active and signal BlockEn is inactive. When operating (e.g., compareEn is active), the first comparator 610 provides a first Match signal Match if the address drfm_addr_flush matches drfm_addr_samp. When in operation (e.g., compareEn is active), if the address drfm_addr_flush2nd matches drfm_addr_samp, then the second comparator 620 provides a second Match signal Match2nd.
The control circuit 630 receives a plurality of input signals, such as fnCbrCntRstBuf, DRFM, DRFM _flag_out and tmfzDRFMSkipCtrl, that indicate that the device is active and in a DRFM mode that enables skip DRFM operation. The control circuit 630 receives a DRFM sample signal ARMSAMPLED that indicates when the new DRFM address is sampled. The control circuit 630 also receives two Match signals Match and Match2nd output from the two comparators 610 and 620.
The control circuit 630 provides reset signals rst3 and rst4, and signals that reset the two comparators rst_tot. Control circuit 630 provides block enable signal BlockEn and compare enable signal CompareEn. The control circuit 630 also provides DRFM control signals DrfmallPulse, drfmrisePulse, drfmfallPulse and DrfmfallPusleDD. The control circuit also provides a skip signal SAMEADDRDRFM.
During example operation, signal ARMSAMPLED indicates that the new DRFM aggressor address has been sampled as drfm_addr_samp. The control circuit 630 provides a signal CompareEn to cause the two comparators 610 and 620 to compare the address drfm_addr_samp with its corresponding previous DRFM address. The control circuit 630 receives signals Match and Match2nd, which indicate whether either of the two comparators 610 and 620 find a Match. If there is no match, the control circuit 630 provides a DRFM signal, such as DRFMallPulse, to indicate that a DRFM refresh operation should be performed. If there is no match, a reset signal, such as rst3 or rst4, may be sent to instruct one of the comparators 610 or 620 to apply a new previous address reset, and the current address DRFM_ADDR_SAMP may be saved as DRFM_ADDR_Flush or DRFM_ADDR_Flush2nd. For example, the control circuit 630 may track which of the stored previous addresses is older and replace the older address first.
If a Match and Match or Match2nd are valid, control circuit 630 may provide skip signal SAMEADDRDRFM.
Fig. 7 is a flowchart of a method of determining whether to skip DRFM operations according to some embodiments of the disclosure. In some embodiments, the method 700 may be implemented by one or more of the apparatus or systems described herein. For example, the method 700 may be performed by the memory device 100 of fig. 1, 200 of fig. 2, the DRFM logic circuit 300 of fig. 3, and/or 600 of fig. 6.
The method 700 may begin at block 710, with block 710 describing receiving a DRFM aggressor address as part of a DRFM operation. The method 700 may include receiving a DRFM aggressor address from a controller of a memory, and receiving the DRFM aggressor address at the memory. For example, the method may include the controller providing an address along the address bus and latching the address out of the address bus as a DRFM aggressor address in response to a DRFM sample command. The method may include receiving a DRFM sample command from the controller or generating a DRFM sample command in response to a DRFM command from the controller.
Block 710 may be followed by block 720, block 720 describing comparing the DRFM aggressor address with a previous DRFM aggressor address. For example, a comparator (e.g., 304 of FIG. 3 and/or 610/620 of FIG. 6) may compare. The DRFM aggressor address may be stored in a first latch (e.g., 302 of fig. 3), while the previous DRFM aggressor address may be stored in a second latch (e.g., 306 of fig. 3). Block 720 is followed by block 730, block 730 describing determining whether there is a match between the DRFM aggressor address and the previous DRFM aggressor address. If there is a match, the method continues to block 740. If there is no match, then method 700 continues to block 750.
Block 740 depicts skipping the DRFM operation if the addresses match. For example, the method may include providing a DRFM skip signal, and skipping a DRFM operation in response to the DRFM skip signal. In some embodiments, the method may include counting the number of times that the DRFM operation is skipped, and performing the DRFM operation even if the address matches when the count value reaches a threshold (e.g., block 750). For example, the method may include performing 1 out of every N DRFM operations upon address matching. In some embodiments, the method 700 may include tracking an aggressor address (e.g., in an aggressor queue such as 244 of fig. 2) and performing a target refresh operation on the aggressor address from the queue instead of a skipped DRFM operation.
Block 750 depicts performing a DRFM operation if the addresses do not match. Performing the DRFM operation may include generating one or more refresh addresses based on the DRFM aggressor address, and performing a refresh operation on the word lines associated with the refresh addresses. The method 700 may include receiving a DRFM update signal (e.g., from a controller), or generating a DRFM update signal (e.g., based on a DRFM command from a controller), and performing a DRFM operation in response to the DRFM update command (e.g., when the DRFM skip signal is inactive).
In some embodiments, the method 700 may include determining whether to skip DRFM operations on a victim address-by-victim address calculation basis. For example, the method 700 may include determining that the DRFM aggressor address matches a previous DRFM aggressor address, and performing some DRFM operations while skipping other DRFM operations. For example, the method 700 may include refreshing victims closer to the word line associated with the DRFM aggressor address while skipping victims farther from the DRFM aggressor address. For example, if block 750 generally involves performing a DRFM operation on a first number of refresh addresses, block 740 may involve performing a DRFM operation on a second number of refresh addresses that is less than the first number.
It is to be appreciated that any of the examples, embodiments, or processes described herein may be combined with one or more other examples, embodiments, and/or processes, or separated and/or performed among separate devices or device portions in accordance with the present systems, devices, and methods.
Finally, the above-discussion is intended to be merely illustrative of the present system and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Thus, while the present system has been described in particular detail with reference to exemplary embodiments, it should also be appreciated that numerous modifications and alternative embodiments may be devised by those having ordinary skill in the art without departing from the broader and intended spirit and scope of the present system as set forth in the claims that follow. Accordingly, the specification and drawings are to be regarded in an illustrative manner and are not intended to limit the scope of the appended claims.