Disclosure of Invention
In view of the above-mentioned shortcomings and disadvantages of the prior art, the present application provides a CPU reset method, device, system and storage medium based on CPLD, which solves the problems of DDR data loss, long CPU reset waiting time, failure in responding to interrupt in some states of CPU, and possible abnormal CPU reset caused by CPLD in the prior art by the collaborative design of hardware and software, so as to realize accurate control of CPU reset, improve stability and reliability of system, and simultaneously retain key information before reset to facilitate system maintenance and fault investigation.
The application discloses a CPU resetting method based on CPLD, which is characterized by comprising CPLD for controlling CPU resetting and watchdog for controlling CPLD resetting, wherein the method comprises the following steps:
The CPLD receives the pulse signal sent by the CPU, judges whether the signal exceeds a first time threshold, and if so, sends a CPU reset pulse to the CPU;
the watchdog receives a feeding signal sent by the CPLD, judges whether the feeding signal exceeds a second time threshold, if yes, sends CPLD reset pulse to the CPLD and the CPU, and the CPU reset pulse and the CPLD reset pulse are mutually independent and do not interfere with each other.
Further, after receiving the CPU reset pulse, the CPU resets and restarts according to the register information on the CPLD.
Further, the CPLD register includes:
An active reset control register, wherein the CPU writes specific data into the register to enable the CPLD to output pulse signals to trigger the CPU to reset;
the DDR reset control register is used for setting the CPU in normal operation and clearing the CPU by the CPLD in abnormal reset or whole board cold start, and the state of the register determines whether the CPU resets the DDR in start;
The CPU reset reason register is used for judging the processing logic after the CPU is restarted, the CPU marks normal reset when the register is reset by writing the CPLD register, the CPLD judges that the CPU marks abnormal reset when the CPU is overtime reset, and the whole board is powered off and started and marks power-off reset;
CPLD state register, CPLD after firmware loading and initialization, switching the register from BUSY state to READY state, CPU can access CPLD other registers only in READY state;
And the communication setting register is used for configuring parameters of UART communication between the CPLD and the CPU, including baud rate, communication bit width and verification mode.
Further, the CPU is provided with a monitoring task with high priority, the monitoring task is triggered by a hardware timer, runs according to a preset period and sends a pulse signal to the CPLD;
and the monitoring task sets a counter for other tasks, and when the counter value of the other tasks exceeds a preset threshold value, the CPU identifies an abnormal state and initiates active reset.
Further, when the CPU identifies that the program is abnormal, actively writing the program into the CPLD, and triggering active reset, the active reset method includes:
The main core refreshes the cache, and updates the data in the cache to DDR;
the method comprises the steps that a master core notifies and waits for a slave core to close through inter-core interrupt, the slave core closes task scheduling and global interrupt after receiving the notification, and refreshes a cache and closes the slave core;
After the master core confirms that the slave core is closed, closing global interrupt, calling specific service to suspend the CPU, and configuring DDR to enter self-refresh;
Writing an instruction into an active reset control register of the CPLD to enable the CPLD to output a CPU reset pulse to the CPU for resetting and restarting the CPU.
Further, the method for passively resetting the CPU comprises the following steps:
The CPLD receives the pulse signal sent by the CPU and judges whether the signal exceeds a first time threshold;
If yes, marking a CPU reset reason register of the CPLD as abnormal, and sending a CPU reset pulse to the CPU;
After receiving a CPU reset pulse sent by the CPLD, the CPU reads a CPU reset reason register on the CPLD, clears the DDR if the mark is abnormal, and resets and restarts the CPU according to cold start.
Further, the resetting method of the CPLD comprises the following steps:
the watchdog receives a feeding signal sent by the CPLD, judges whether the feeding signal exceeds a second time threshold, and if yes, sends CPLD reset pulse to the CPLD and the CPU;
the CPLD receives CPLD reset pulse of the watchdog, resets again, and clears register information;
And the CPU receives CPLD reset pulse sent by the watchdog, and after waiting for resetting and restarting of the CPLD, the CPU re-writes information into a register of the CPLD.
The application also discloses a CPU resetting device based on the CPLD, which comprises:
The CPU is used for monitoring the running task, initiating an active reset pulse to the CPLD according to the monitoring abnormality, receiving whether the CPLD transmits the CPU reset pulse, and resetting and restarting the CPU according to the CPLD register information;
the CPLD is connected with the CPU and used for realizing hardware dog logic to monitor the operation of the CPU;
the watchdog is connected with the CPLD and used for monitoring the operation of the CPLD;
And the DDR is connected with the CPU, and performs data zero clearing when the CPU is restarted by cold start active abnormal reset.
The application also discloses a CPU reset system based on CPLD, comprising:
one or more processors;
A computer readable storage medium storing one or more programs,
Wherein the one or more programs, when executed by the one or more processors, cause the one or more processors to implement the steps of the method of any of claims 1 to 7.
The application also discloses a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the method of any of claims 1 to 7.
The application has the beneficial effects that the application discloses a CPU resetting method, device, system and storage medium based on CPLD, solves the problems existing in the prior art through the cooperative design of hardware and software, and realizes:
1. Two-stage monitoring is designed on hardware, so that the reset of the CPLD and the reset of the CPU are mutually independent and are not interfered with each other, the reset waiting time is shortened, and the reset risk is reduced.
2. The method has the advantages that the overtime condition of the CPU program feeding dog is actively identified through the software dog, so that the CPU can identify all active reset conditions including abnormal interrupt.
3. A series of registers are designed on the CPLD, the DDR is not reset when the CPU is actively reset, the information and data before the reset are reserved, and the CPU and the DDR are ensured to be reset simultaneously when the CPU is passively reset, so that the CPU can be started normally.
Detailed Description
The application will be better explained by the following detailed description of the embodiments with reference to the drawings. It is to be understood that the specific embodiments described below are merely illustrative of the related application, and not restrictive of the application. In addition, it should be noted that, without conflict, the embodiments of the present application and features in the embodiments may be combined with each other, and for convenience of description, only the portions related to the application are shown in the drawings.
As known from the background art, in the existing control system, when the CPU is reset, the CPU is easily disabled, or the CPU and the DDR are all reset, so that key information before the CPU is reset cannot be recorded, and the difficulty of system maintenance and fault detection is increased.
Aiming at the problems, the application provides a CPU resetting method based on CPLD, which solves the problems of DDR data loss, long CPU resetting waiting time, incapability of responding to interrupt in certain states of the CPU, abnormal CPU resetting possibly caused by CPLD and the like in the prior art through the cooperative design of hardware and software, realizes the accurate control of CPU resetting, improves the stability and the reliability of a system, and simultaneously reserves key information before resetting so as to facilitate the maintenance and the fault investigation of the system. The method is shown in fig. 1, and comprises a CPLD for controlling CPU reset and a watchdog for controlling CPLD reset, and the specific method comprises the following steps:
The CPLD receives the pulse signal sent by the CPU, judges whether the signal exceeds a first time threshold, and if so, sends a CPU reset pulse to the CPU;
the watchdog receives a feeding signal sent by the CPLD, judges whether the feeding signal exceeds a second time threshold, if yes, sends CPLD reset pulse to the CPLD and the CPU, and the CPU reset pulse and the CPLD reset pulse are mutually independent and do not interfere with each other.
As shown in fig. 2, a schematic circuit diagram of the CPLD-based CPU reset method of the present application is shown, in which, during operation, the CPU sends a pulse signal to the CPLD via CWDI signals, and the CPLD sends a pulse signal to the watchdog via WDI. When the CPLD exceeds the first time threshold time, the CPLD transmits a CPU reset pulse signal to the CPU to reset the CPU through CWDO, and when the watchdog piece does not receive a dog feeding signal of the CPLD within the second time threshold time, the watchdog transmits a CPLD reset pulse signal to the CPLD and the CPU through WDO to reset the CPLD, and the CPU reset pulse signal and the CPLD reset pulse signal are mutually independent and do not interfere with each other. The reset of the CPLD does not affect the CWDO signal, i.e., the reset of the CPU is not caused, and similarly, the reset of the CPU does not cause the reset of the CPLD.
Further, after receiving the CPU reset pulse, the CPU resets and restarts according to the register information on the CPLD.
Wherein, the register in the CPLD includes:
An active reset control register, wherein the CPU writes specific data into the register to enable the CPLD to output pulse signals to trigger the CPU to reset;
the DDR reset control register is used for setting the CPU in normal operation and clearing the CPU by the CPLD in abnormal reset or whole board cold start, and the state of the register determines whether the CPU resets the DDR in start;
The CPU reset reason register is used for judging the processing logic after the CPU is restarted, the CPU marks normal reset when the register is reset by writing the CPLD register, the CPLD judges that the CPU marks abnormal reset when the CPU is overtime reset, and the whole board is powered off and started and marks power-off reset;
CPLD state register, CPLD after firmware loading and initialization, switching the register from BUSY state to READY state, CPU can access CPLD other registers only in READY state;
And the communication setting register is used for configuring parameters of UART communication between the CPLD and the CPU, including baud rate, communication bit width and verification mode.
The read-write permission of the CPU for the register in the CPLD is shown in the following table:
Wherein RW means that the CPU can read and write the register, R means that the CPU can only read the register.
As shown in fig. 2, the CPU can read and write the CPLD register through UART communication, thereby realizing a specific function. The active reset control register is just like a key, and when the CPU writes specific data into the active reset control register, the CPLD can be precisely controlled to immediately output pulse signals, so that the CPU reset is triggered; the CPLD is used for determining whether the DDR is in a hardware reset operation or not when the CPU is started, and provides flexible control means for DDR processing of the system under different reset scenes, a CPU reset reason register is like a black box of the system, can be marked with a reset reason of the CPU in detail, can be marked as normal reset when the CPU is reset by writing an instruction into the CPLD, can be marked as abnormal reset when the CPLD judges to reset the CPU according to timeout, can be marked as power-off reset when the whole board is powered off, provides information basis with extremely valuable for system fault investigation and subsequent analysis, and is in a CPLD firmware loading initial stage, after the firmware is loaded and a series of initialization actions are completed, the CPLD is switched to a READY state, the CPLD register can be accessed only under the READY state, and the communication setting of the CPLD internal data safety and stability is ensured, and the communication accuracy and the communication parameters of the CPLD are ensured, and the communication parameters are particularly in the communication parameters of the communication and the communication parameters of the CPLD, and the communication parameters are mutually ensured, and the communication parameters of the communication parameters are mutually ensured.
In the normal operation process of the system, a high-priority monitoring task is configured in the CPU, the monitoring task is triggered by a hardware timer, operates according to a preset period, and sends a pulse signal to the CPLD. When the CPU operates normally, the CPLD receives the pulse sent by the CPU within the time threshold, and at the moment, the CPLD realizes the function of a hardware watchdog to monitor the CPU.
Meanwhile, the CPU sets a counter for other tasks through the monitoring task, if other tasks encounter unexpected situations in the running process, such as blocking caused by resource competition or abnormality caused by data transmission errors, so that the corresponding counter exceeds a preset threshold value, or when the CPU kernel executes complex instructions, the system immediately triggers an active reset event under the abnormal conditions of hardware layers such as prefetching instruction errors, illegal access addresses, instruction running errors and the like.
In this embodiment, a dual core CPU based on the ARMv8 architecture will be described as an example. The method of active reset is shown in fig. 3, and includes:
s11, refreshing the cache by the main core, and updating the data in the cache to the DDR. When the CPU recognizes an abnormality through the monitoring task, the main core immediately starts a data protection mechanism, and video data in the cache and relevant decoding state information are quickly updated into the DDR, so that the important data are ensured not to be lost due to reset operation.
And S12, the master core notifies and waits for the slave core to close through inter-core interrupt, and the slave core closes task scheduling and global interrupt after receiving the notification, refreshes the cache and closes the slave core. The master core sends a notification to the slave core through inter-core interrupt, and the slave core can quickly stop current task scheduling and global interrupt processing after receiving the notification, so that new data entry or wrong operation is prevented. Then, the slave core can refresh its own cache, save the unprocessed data which may exist in the DDR, and then call the SMC service to close the slave core, so as to make the slave core enter a dormant state, and avoid the interference to the system in the resetting process.
And S13, after the master core confirms that the slave core is closed, closing the global interrupt, calling a specific service to suspend the CPU, and configuring the DDR to enter self-refresh. After the master core confirms that the slave core is successfully closed, the global interrupt is closed, SMC service is called to suspend the master core, and DDR is configured to enter a self-refresh state, so that the risk of data loss is reduced.
And S14, writing an instruction into an active reset control register of the CPLD to enable the CPLD to output a CPU reset pulse to the CPU for resetting and restarting the CPU. The CPU writes specific reset instruction data into the active reset control register of the CPLD, and after the CPLD receives the instruction, the CPLD sends a pulse signal to the CPU through CWDO to accurately reset the CPU.
After the CPU is restarted, communication is carried out with the CPLD at the first time, and state information of the CPLD register is obtained. If the DDR reset control register is set, this indicates that the data in the DDR before reset is complete and valid. At this time, the CPU will process according to the hot reset procedure, and quickly resume the video decoding task according to the video data and decoding status information retained in the DDR, and continue the decoding operation from the place where the last interrupt occurs, so as to greatly reduce the video playing time or interruption time of the system caused by the reset, and improve the user experience and the overall performance of the system.
When an abnormality, such as a hardware burst fault (e.g., a damaged memory chip portion, a short circuit in the CPU, etc.) or a strong external interference (e.g., electromagnetic pulse interference, electrostatic discharge, etc.), occurs in the CPU running process, and the program cannot recognize the error and does not send a pulse signal to the CPLD beyond a first time threshold (e.g., 1 second), the CPLD will respond quickly, accurately marks the CPU reset mode as abnormal reset in the internal CPU reset reason register, and simultaneously sends a pulse signal to the CPU through CWDO to force the CPU to reset.
When the CPU performs passive reset, the DDR cannot enter self-refresh before reset, data in the DDR can be lost in the reset process, and the data in the DDR is unreliable after restarting. Therefore, in the resetting and restarting process of the CPU, the state information of the CPLD register is read, and after the abnormal resetting mark is identified, the DDR data is cleared in order to ensure the stability of the system and the consistency of the data. Subsequently, the application program can process according to the cold start flow, reinitialize various parameters in the industrial control system, ensure that the system can be restarted in a stable state, and ensure the safety and stability of the industrial production process.
Meanwhile, the invention also designs a secondary watchdog monitor aiming at the CPLD, and the CPLD periodically transmits a watchdog feeding signal to the watchdog to ensure the normal operation of the CPLD, and simultaneously, the reset of the CPLD and the reset of the CPU are mutually independent and do not interfere with each other. As shown in fig. 4, the resetting method of the watchdog for the CPLD includes:
And S21, the watchdog receives a feeding signal sent by the CPLD, judges whether the feeding signal exceeds a second time threshold, and if yes, sends CPLD reset pulse to the CPLD and the CPU. After the CPLD feeding signal is overtime, the watchdog sends CPLD reset pulse WDO to the CPU and the CPLD, the WDO reset pulse of the watchdog does not influence the CPU and does not cause the CPU reset.
S22, the CPLD receives CPLD reset pulse of the watchdog, resets and resets, and clears the register information. In the resetting process, the CPLD interrupts interaction with the CPU, clears the information of each register in the CPU, adjusts the state of the CPLD state register into BUSY state, and carries out firmware loading and initializing operation. After the state is loaded, the state of the CPLD state register is adjusted to be READY state, and at this time, the CPU can access the CPLD state register.
S23, the CPU receives CPLD reset pulse sent by the watchdog, waits for resetting and restarting the CPLD, and then re-writes information into a register of the CPLD. In the resetting and restarting process, the CPLD can break communication with the CPU, and the CPLD status register is in BUSY state, so that the CPU cannot directly access, and the CPLD needs to wait for finishing resetting. After the CPLD state register is restored to the READY state, the CPU rewrites the backed-up CPLD register information into the CPLD, ensures that the CPLD can be restored to the previous normal working state, and maintains the stability and continuity of the system.
And a stable connection is established between the CPU and the CPLD through a UART communication link. In the running process of the system, the CPU performs accurate read-write operation on the CPLD register according to the baud rate, the communication bit width and the verification mode configured by the communication setting register, so that flexible control and efficient information interaction on the CPLD are realized. For example, at the beginning of system startup, the CPU may read the state of the CPLD status register, determine whether the CPLD has completed initialization and is in the READY state, to determine whether a subsequent register configuration operation may be performed. In the running process of the system, the CPU can read the information of the CPU reset reason register according to the requirement, and know the previous reset condition of the system so as to conduct fault investigation and system state analysis. Meanwhile, the CPU can trigger initiative by writing data into the initiative reset control register.
In summary, the application discloses a CPU reset method based on CPLD, which solves the problems existing in the prior art through the collaborative design of hardware and software, and realizes:
1. Two-stage monitoring is designed on hardware, so that the reset of the CPLD and the reset of the CPU are mutually independent and are not interfered with each other, the reset waiting time is shortened, and the reset risk is reduced.
2. The method has the advantages that the overtime condition of the CPU program feeding dog is actively identified through the software dog, so that the CPU can identify all active reset conditions including abnormal interrupt.
3. A series of registers are designed on the CPLD, the DDR is not reset when the CPU is actively reset, the information and data before the reset are reserved, and the CPU and the DDR are ensured to be reset simultaneously when the CPU is passively reset, so that the CPU can be started normally.
In another embodiment of the present invention, a CPU reset device based on a CPLD includes:
The CPU is used for monitoring the running task, initiating an active reset pulse to the CPLD according to the monitoring abnormality, receiving whether the CPLD transmits the CPU reset pulse, and resetting and restarting the CPU according to the CPLD register information;
the CPLD is connected with the CPU and used for realizing hardware dog logic to monitor the operation of the CPU;
the watchdog is connected with the CPLD and used for monitoring the operation of the CPLD;
And the DDR is connected with the CPU, and performs data zero clearing when the CPU is restarted by cold start active abnormal reset.
In a third embodiment of the present invention, a CPLD-based CPU reset system includes:
one or more processors;
A computer readable storage medium storing one or more programs,
Wherein the one or more programs, when executed by the one or more processors, cause the one or more processors to implement the steps of the method of any of claims 1 to 7.
A fourth embodiment of the invention is a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the method of any of claims 1 to 7.
It should be noted that in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. The use of the terms first, second, third, etc. are for convenience of description only and do not denote any order. These terms may be understood as part of the component name.
Furthermore, it should be noted that in the description of the present specification, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to a specific feature, structure, material, or characteristic described in connection with the embodiment or example being included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art upon learning the basic inventive concepts. Therefore, the appended claims should be construed to include preferred embodiments and all such variations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, the present invention should also include such modifications and variations provided that they come within the scope of the following claims and their equivalents.