Semiconductor phase change memory cell including embedded blade-like heating electrodeTechnical Field
The invention belongs to the field of microelectronics, and particularly relates to a semiconductor phase change memory unit comprising an embedded blade-shaped heating electrode.
Background
With the rise of the Internet of things, artificial intelligence, cloud computing and 5G technology, the human society enters a big data era, and related industries of information technology are also coming into vigorous development, which puts higher requirements on the performance of a memory. The phase change memory has the advantages of high memory speed, long service life, large switching ratio, compatibility with the existing CMOS process and the like. In the phase change memory, the electric operation parameters are regulated to control the current intensity passing through the heating electrode so as to regulate the temperature of the chalcogenide material, so that the chalcogenide material is subjected to reversible structural transformation between a low-resistance crystalline state and a high-resistance amorphous state, and information is stored by utilizing the difference between the high resistance state and the low resistance state. The operation from crystalline to amorphous is relatively power consuming, which limits the large-scale application of phase change memories to some extent.
In order to reduce the operation power consumption of the phase change memory, the main solutions at present are to develop a novel chalcogenide material, reduce the size of a bottom electrode or adopt a limited structure so as to reduce a phase change region, and the like. In recent years, with the rapid development of the integrated circuit industry and the semiconductor process technology, more possibilities are provided for the low-power consumption development of the phase change memory. The invention provides an embedded blade-shaped heating electrode, which enables heat to be concentrated in a chalcogenide material, and through the memory cell structure, heat loss in the operation process can be reduced, heating efficiency is improved, device reliability is improved, and finally operation power consumption of a phase change memory is reduced.
Disclosure of Invention
The invention aims to provide a semiconductor phase change memory unit containing an embedded blade-shaped heating electrode and a preparation method thereof, so as to realize higher thermal efficiency, lower operation energy consumption and lower device loss.
The invention provides a semiconductor phase change memory unit comprising an embedded blade-shaped heating electrode, which comprises a bottom contact circuit, a heating electrode, a blocking layer, a chalcogenide material layer, a hard mask, a top electrode and an insulating medium layer, wherein the upper part of the chalcogenide material layer is electrically connected with the top electrode through the hard mask, the heating electrode is of a blade-shaped structure, the top of the heating electrode is embedded in the chalcogenide material layer and is connected with the chalcogenide material layer, and the bottom of the heating electrode is connected with the bottom contact circuit.
Preferably, the insulating dielectric layer includes a first insulating dielectric layer, a second insulating dielectric layer, a third insulating dielectric layer, a fourth insulating dielectric layer and a fifth insulating dielectric layer.
Preferably, the first insulating dielectric layer is located on the surface of the bottom contact circuit, the second insulating dielectric layer is located on the surface of the first insulating dielectric layer and located on the periphery of the heating electrode, the blocking layer is located on the periphery of the heating electrode, the third insulating dielectric layer is located on the periphery of the blocking layer, the lower portion of the third insulating dielectric layer is in contact with the bottom contact circuit, the upper portion of the third insulating dielectric layer is in contact with the chalcogenide material layer, the fourth insulating dielectric layer is located on the periphery of the hard mask and the chalcogenide material layer, and the fifth insulating dielectric layer is located on the periphery of the fourth insulating dielectric layer.
Preferably, the bottom contact circuit is provided with a semiconductor device, a metal interconnection structure and an isolation structure.
The invention also provides a preparation method of the semiconductor phase change memory unit containing the embedded blade-shaped heating electrode, which comprises the following steps:
S1, providing a bottom contact circuit;
s2, depositing a first insulating medium layer on the surface of the bottom contact circuit;
S3, forming a groove on the bottom contact circuit by etching the first insulating medium layer, and forming a second insulating medium layer on the side wall of the first insulating medium layer in the groove;
s4, forming a heating electrode on the surface of the second insulating dielectric layer, forming a barrier layer on the surface of the heating electrode, and separating the heating electrode at the bottom of the groove from the barrier layer;
S5, forming a third insulating dielectric layer on the barrier layer, exposing the top of the blade-shaped heating electrode through chemical mechanical polishing, and enabling the blade-shaped heating electrode to be higher than the first insulating dielectric layer and the third insulating dielectric layer through plasma etching;
S6, depositing a chalcogenide material layer and a hard mask on the top of the heating electrode, and embedding the heating electrode into the chalcogenide material layer and connecting the heating electrode with the chalcogenide material layer;
S7, etching the chalcogenide material layer and the hard mask, and depositing a fourth insulating medium layer on the periphery;
s8, forming a loop contact hole on the fourth insulating medium layer and the fifth insulating medium layer, and penetrating through the fourth insulating medium layer and the fifth insulating medium layer;
and S9, depositing a top electrode in the loop contact hole to serve as a contact electrode connected with an external circuit, and forming mutually independent memory units through a patterning process.
Preferably, the preparation method of the heating electrode layer comprises atomic layer deposition, and the material of the heating electrode layer comprises any one of Ti, W, ta, cu, WCN, WN, tiN, tiSiN and TaN.
Preferably, the preparation method of the first insulating dielectric layer, the second insulating dielectric layer, the barrier layer, the third insulating dielectric layer, the fourth insulating dielectric layer and the fifth insulating dielectric layer comprises chemical vapor deposition, but is not limited to the method, and the materials of the insulating dielectric layer and the barrier layer comprise any one of silicon nitride, silicon oxide or silicon oxynitride.
Preferably, the preparation method of the chalcogenide material layer comprises physical vapor deposition, wherein the material of the chalcogenide material layer comprises any one of a GeTe-Sb2Te3 system, a GeTe-SnTe system, a Sb2 Te system, an In3SbTe2 system or a GeTe-Sb2Te3 system containing a doping element, a GeTe-SnTe system, a Sb2 Te system and an In3SbTe2 system, and the doping element comprises at least one of Sc, ag, in, al, C, S, se, N, cu or W.
Preferably, the preparation method of the hard mask comprises physical vapor deposition, and the material of the hard mask comprises Ti, W, ta, cu, WCN, WN, tiN or any one of TaN.
Preferably, the preparation method of the top electrode comprises chemical vapor deposition, and the material of the top electrode comprises any one of Ti, W, ta, cu, WCN, WN, tiN and TaN.
Advantageous effects
(1) According to the semiconductor phase change memory cell device, the L-shaped blade-shaped heating electrode is embedded into the chalcogenide material layer, so that the operating current directly acts inside the chalcogenide material layer, the heat loss in the operating process can be reduced, the heat efficiency is improved, and the operating power consumption is reduced;
(2) The invention can limit the phase change area of the effective structure to the inside of the chalcogenide material layer, thereby reducing thermal disturbance and atomic migration at the interface of the chalcogenide material layer and the dielectric layer and improving the stability of the phase change memory device;
(3) The preparation process is simple and has low production cost.
Drawings
Fig. 1 is a schematic diagram of a semiconductor phase change memory device with embedded blade-shaped heating electrodes according to embodiment 1 of the present invention.
Fig. 2 is a graph showing the internal temperature distribution of a semiconductor phase change memory having blade-shaped heating electrodes with different embedded depths according to embodiment 1 of the present invention.
Fig. 3 is a schematic diagram showing a process flow of fabricating a semiconductor phase change memory device including an embedded blade-shaped heating electrode according to embodiment 1 of the present invention.
Fig. 4 is a schematic diagram of the structure of the bottom contact circuit in embodiment 1 of the present invention.
Fig. 5 is a schematic structural diagram of the embodiment 1 of the present invention after depositing a first insulating dielectric layer.
Fig. 6 is a schematic diagram of the structure of the embodiment 1 after etching to form a groove.
Fig. 7 is a schematic structural diagram of the embodiment 1 of the present invention after depositing a second insulating dielectric layer.
Fig. 8 is a schematic structural diagram of a second insulating dielectric layer only on the sidewall of the remaining recess in embodiment 1 of the present invention.
Fig. 9 is a schematic diagram of the structure of the heating electrode in embodiment 1 of the present invention.
Fig. 10 is a schematic structural diagram of the barrier layer formed in embodiment 1 of the present invention.
Fig. 11 is a schematic diagram of the structure of embodiment 1 of the present invention after separating the bottom heating electrode and the barrier layer.
Fig. 12 is a schematic structural diagram of the embodiment 1 of the present invention after depositing a third insulating dielectric layer.
Fig. 13 is a schematic view showing the structure of example 1 of the present invention after exposing the top of the blade-shaped heating electrode.
Fig. 14 is a schematic structural diagram of the deposited chalcogenide material layer and hard mask in example 1 of the present invention.
Fig. 15 is a schematic diagram of the structure of the chalcogenide material layer and the hard mask after etching in example 1 of the present invention.
Fig. 16 is a schematic structural diagram of the embodiment 1 of the present invention after depositing a fourth insulating dielectric layer and a fifth insulating dielectric layer.
Fig. 17 is a schematic diagram of the structure of the embodiment 1 of the present invention after forming the loop contact hole.
Reference numerals are 01-bottom contact circuit, 02-first insulating dielectric layer, 03-second insulating dielectric layer, 04-heating electrode, 05-barrier layer, 06-third insulating dielectric layer, 07-chalcogenide material layer, 08-hard mask, 09-fourth insulating dielectric layer, 10-fifth insulating dielectric layer, and 11-top electrode.
Detailed Description
The application will be further illustrated with reference to specific examples. It is to be understood that these examples are illustrative of the present application and are not intended to limit the scope of the present application. Furthermore, it should be understood that various changes and modifications can be made by one skilled in the art after reading the teachings of the present application, and such equivalents are intended to fall within the scope of the application as defined in the appended claims.
Examples
The embodiment provides a semiconductor phase change memory cell comprising an embedded blade-shaped heating electrode, the structure of the semiconductor phase change memory cell is shown in fig. 1, the semiconductor phase change memory cell comprises a bottom contact circuit 01, a heating electrode 04, a barrier layer 05, a chalcogenide material layer 07, a hard mask 08, a top electrode 11 and an insulating medium layer, wherein the upper part of the chalcogenide material layer 07 is electrically connected with the top electrode 11 through the hard mask 08, the heating electrode 04 is in a blade-shaped structure, the top of the heating electrode 04 is embedded in the chalcogenide material layer 07 and is connected with the chalcogenide material layer 07, and the bottom of the heating electrode is connected with the bottom contact circuit 01.
The insulating dielectric layers include a first insulating dielectric layer 02, a second insulating dielectric layer 03, a barrier layer 05, a third insulating dielectric layer 06, a fourth insulating dielectric layer 09, and a fifth insulating dielectric layer 10.
The first insulating dielectric layer 02 is located on the surface of the bottom contact circuit 01, the second insulating dielectric layer 03 is located on the surface of the first insulating dielectric layer 02 and located on the periphery of the heating electrode 04, the blocking layer 05 is located on the periphery of the heating electrode 04, the third insulating dielectric layer 06 is located on the periphery of the blocking layer 05, the lower portion of the third insulating dielectric layer 06 is in contact with the bottom contact circuit 01, the upper portion of the third insulating dielectric layer 06 is in contact with the chalcogenide material layer 07, the fourth insulating dielectric layer 09 is located on the periphery of the hard mask 08 and the chalcogenide material layer 07, the fifth insulating dielectric layer 10 is located on the periphery of the fourth insulating dielectric layer 09, the blade-shaped heating electrode 04 of each unit is isolated by the first insulating dielectric layer 02 and the third insulating dielectric layer 06, and the chalcogenide material layer 07 and the hard mask 08 of each unit are isolated by the fourth insulating dielectric layer 09 and the fifth insulating dielectric layer 10. In this embodiment, the materials of the first insulating dielectric layer 02, the third insulating dielectric layer 06 and the fifth insulating dielectric layer 10 are silicon dioxide, the materials of the second insulating dielectric layer 03, the fourth insulating dielectric layer 09 and the barrier layer 05 are silicon nitride, the material of the heating electrode 04 is TaN, and the material of the chalcogenide material layer 07 is Ge2Sb2Te5.
Fig. 2 is a result example of the internal temperature distribution of a device having blade-shaped heating electrodes with different embedding depths according to an embodiment of the present invention. The thermal simulation model contained a 5nm wide blade-like heating electrode and a 100nm thick layer of chalcogenide material, simulating the temperature distribution of the blade-like heating electrode at embedding depths of 0nm, 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, and 70nm, respectively, at the same operating current. When the embedded depth of the blade-shaped heating electrode is 40nm, the highest temperature in the chalcogenide material layer is 390K higher than when the heating electrode is not embedded, which indicates that the embedded blade-shaped heating electrode phase change memory structure can realize higher heating efficiency. With the increase of the embedding depth, the heat concentration area inside the chalcogenide material layer is far away from the bottom interface, which is helpful to improve the stability of the interface, thereby improving the reliability of the device.
The embodiment provides a method for manufacturing the semiconductor phase change memory unit comprising the embedded blade-shaped heating electrode, which comprises the following steps:
S1, providing a bottom contact circuit 01, as shown in FIG. 4;
s2, depositing a first insulating medium layer 02 on the surface of the bottom contact circuit 01 by a chemical vapor deposition method, as shown in FIG. 5;
S3, exposing and etching the first insulating medium layer 02 through a photoetching technology to form a groove above the bottom contact circuit 01 as shown in fig. 6, and forming a second insulating medium layer 03 on the surfaces of the groove and the first insulating medium layer 02 as shown in fig. 7, wherein the second insulating medium layer 03 is only reserved on the side wall of the groove through a back etching technology as shown in fig. 8;
s4, forming a heating electrode 04 on the surface of the second insulating medium layer 03, as shown in fig. 9, then forming a barrier layer 05 on the surface of the heating electrode 04, as shown in fig. 10, and exposing and etching by a photoetching technology to separate the heating electrode 04 at the bottom of the groove from the barrier layer 05, as shown in fig. 11;
S5, forming a third insulating medium layer 06 on the barrier layer 05 by a chemical vapor deposition method, as shown in FIG. 12, exposing the top of the blade-shaped heating electrode 04 by chemical mechanical polishing, and making the blade-shaped heating electrode 04 higher than the first insulating medium layer 02 and the third insulating medium layer 06 by plasma etching, as shown in FIG. 13;
S6, forming a chalcogenide material layer 07 and a hard mask 08 on top of the heating electrode 04 by a physical vapor deposition method, so that the heating electrode 04 is embedded in the chalcogenide material layer 07 and connected with the chalcogenide material layer 07, as shown in FIG. 14;
S7, exposing and etching the chalcogenide material layer 07 and the hard mask 08 by photolithography, as shown in fig. 15, forming a fourth insulating dielectric layer 09 on the periphery of the chalcogenide material layer 07 and the hard mask 08 by chemical vapor deposition, and then depositing a fifth insulating dielectric layer 10 on the fourth insulating dielectric layer 09, as shown in fig. 16;
s8, exposing and etching through a photoetching technology, forming loop contact holes on the fourth insulating dielectric layer 09 and the fifth insulating dielectric layer 10, and penetrating through the fourth insulating dielectric layer 09 and the fifth insulating dielectric layer 10, as shown in FIG. 17;
And S9, depositing a top electrode 11 in the loop contact hole by a chemical vapor deposition method to serve as a contact electrode connected with an external circuit, forming mutually independent memory units after a patterning process, and connecting with a subsequent metal interconnection line, wherein the figure 1 shows.