Disclosure of Invention
One of the purposes of the present invention is to provide a semiconductor structure and a method for manufacturing the same, which can effectively inhibit the diffusion limiting effect when etching a marking groove when etching a contact hole and the marking groove simultaneously, improve the definition of the boundary of the marking groove, and improve the precision of the overlay precision measurement value.
In order to achieve the above object, an aspect of the present invention provides a method for manufacturing a semiconductor structure. The manufacturing method of the semiconductor structure comprises the steps of providing a substrate, wherein the substrate comprises a first area and a second area, a dielectric layer is formed on the substrate, an anisotropic first dry etching process is performed to etch the dielectric layer and the substrate and stop in the substrate, a plurality of through holes are formed in the first area, an anisotropic second dry etching process is performed to etch the dielectric layer and the substrate in the second area to form contact holes, and meanwhile the dielectric layer and the substrate on the side edges of the through holes are etched to enlarge the through holes to form marking grooves.
Optionally, the method for performing an anisotropic second dry etching process to etch the dielectric layer and the substrate in the second region to form a contact hole and simultaneously etching the dielectric layer and the substrate on the side of the via hole to enlarge the via hole to form a mark trench includes forming a patterned second mask layer on the substrate, wherein the patterned second mask layer has a contact hole pattern and a mark trench pattern, one of the mark trench patterns corresponds to at least a portion of the via hole position and exposes the corresponding via hole, performing the second dry etching process under the masking of the patterned second mask layer to form the contact hole and the mark trench, and removing the patterned second mask layer.
Optionally, the method for forming the patterned second mask layer on the substrate comprises the steps of coating photoresist on the substrate to form a photoresist layer, wherein the photoresist layer covers the substrate and fills the through holes, exposing the photoresist layer, developing the photoresist layer to form the patterned second mask layer, and developing the photoresist layer twice to remove the photoresist in the through holes.
Optionally, in the step of performing the anisotropic second dry etching process, the dielectric layer and the substrate on the side edge of the through hole are etched, so that more than two through holes are communicated to form the marking groove.
Optionally, the first dry etching process and the second dry etching process are performed on the same machine.
Optionally, the manufacturing method of the semiconductor structure further comprises the steps of forming a blocking layer after the anisotropic second dry etching process is performed, wherein the blocking layer covers the side wall of the contact hole and the side wall of the marking groove, forming a conductive material layer on the dielectric layer, wherein the conductive material layer covers the dielectric layer and fills the contact hole and the marking groove, and grinding and removing the conductive material layer on the top surface of the dielectric layer to form a contact hole structure, and the contact hole structure comprises the contact hole, the blocking layer in the contact hole and the conductive material layer in the contact hole.
Optionally, the manufacturing method of the semiconductor structure further comprises the steps of forming a metal wiring layer on the dielectric layer after grinding and removing the conductive material layer on the top surface of the dielectric layer, wherein the metal wiring layer is electrically connected with the substrate through the contact hole structure, the metal wiring layer comprises a mark pattern corresponding to the mark groove, and the mark groove and the mark pattern are used for measuring the alignment precision between the metal wiring layer and the substrate.
Optionally, the substrate comprises a substrate and an epitaxial layer on the substrate, and the marking groove is located in the epitaxial layer.
Optionally, the first region is a scribe line region.
The invention also provides a semiconductor structure. The semiconductor structure is manufactured by the manufacturing method of the semiconductor structure.
In the semiconductor structure and the manufacturing method thereof, after the dielectric layer is formed on the substrate, the anisotropic first dry etching process is firstly performed to etch the dielectric layer and the substrate and stop in the substrate, a plurality of through holes are formed in the first area, then the anisotropic second dry etching process is performed to etch the dielectric layer and the substrate in the second area to form the contact hole, and simultaneously the dielectric layer on the side of the through hole and the substrate expand the through hole to form the mark groove, so that when the contact hole and the mark groove are etched at the same time, under the condition that the pattern and the size of the contact hole are qualified, the diffusion limiting effect generated when the mark groove is etched can be effectively restrained, the bottom surface of the formed mark groove is smoother, thereby improving the boundary definition of the mark groove, reducing the measurement interference caused by unclear boundary of the mark groove, improving the precision measurement value precision of the overlay, further reducing reworking and measured value caused by abnormal overlay precision caused by unclear boundary of the mark groove, being beneficial to saving manufacturing resources and productivity, and further, the formed bottom surface of the mark groove is leveled, and the conductive material can be filled in the substrate more comprehensively and can be beneficial to improving the contact stress of a wafer.
Detailed Description
The semiconductor structure and the method for fabricating the same according to the present invention are described in further detail below with reference to the accompanying drawings and the detailed description. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
As used in this disclosure, the singular forms "a," "an," and "the" include plural referents unless the content clearly dictates otherwise. As used in this disclosure, the term "or" is generally employed in its sense including "and/or" unless the content clearly dictates otherwise. As used in this disclosure, the term "plurality" is generally employed in its sense including "at least one" unless the content clearly dictates otherwise. As used in this disclosure, the term "at least two" is generally employed in its sense including "two or more", unless the content clearly dictates otherwise. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", and "a third" may include one or at least two of the feature, either explicitly or implicitly, unless the context clearly dictates otherwise.
Fig. 3 is a flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present application. Referring to fig. 3, the method for manufacturing a semiconductor structure provided by the present application includes:
step S1, providing a substrate, wherein the substrate comprises a first area and a second area, and a dielectric layer is formed on the substrate;
Step S2, performing an anisotropic first dry etching process to etch the dielectric layer and the substrate and stop in the substrate, forming a plurality of through holes in the first region, and
And S3, executing an anisotropic second dry etching process, etching the dielectric layer and the substrate in the second area to form a contact hole, and simultaneously etching the dielectric layer and the substrate on the side edge of the through hole to enlarge the through hole to form a marking groove.
Fig. 4 to 15 are schematic process diagrams of a method for fabricating a semiconductor structure according to an embodiment of the present application, wherein fig. 6, 8, 11 and 15 are top views, and the rest are cross-sectional views. The method for manufacturing the semiconductor structure of the present application will be described below with reference to fig. 3 and fig. 4 to 15.
In one embodiment of the present application, referring to fig. 4, a base 100 includes a substrate 101 and an epitaxial layer 102 on the substrate 101. Subsequently formed vias, contact holes, and marker trenches may be located in epitaxial layer 102. Illustratively, the materials of the substrate 101 and the epitaxial layer 102 include, but are not limited to, silicon or germanium. In another embodiment of the application, the base may comprise only the substrate.
Referring to fig. 4, the substrate 100 includes a first region 100a and a second region 100b. Illustratively, the first region 100a may be a scribe line region in which the marking grooves may be formed, which may help to improve the utilization of the wafer area, and the second region 100b may be a device region for forming devices. The application uses only the first region and the second region to distinguish the formation regions of the contact hole and the marking groove, and does not limit the specific regions and functions of the first region and the second region on the wafer.
In this embodiment, the substrate 100 may be a substrate for which any front-end process has been completed. For example, a variety of active devices, such as planar MOS transistors, may be formed on the substrate 100, where the structure includes a gate oxide layer and a gate electrode sequentially formed on a source, a drain, and a channel region between the source and the drain, and a sidewall on the gate oxide layer and a sidewall of the gate electrode. Metal silicide may also be formed on the source, drain, gate of the MOS transistor to reduce contact resistance.
Referring to fig. 4, a dielectric layer 103 is formed on a substrate 100, and the dielectric layer 103 may cover the top surface of the substrate 100. The material of the dielectric layer 103 may be silicon dioxide, but is not limited thereto.
Step S2 is performed, and referring to fig. 5 and 6, an anisotropic first dry etching process is performed to etch the dielectric layer 103 and the substrate 100 and stop in the substrate 100, forming a plurality of through holes 105 in the first region 100 a.
Specifically, step S2 may include forming a patterned first mask layer 104 on the dielectric layer 103, as shown in fig. 4, the patterned first mask layer 104 defining a plurality of locations and opening patterns of the through holes 105, performing the first dry etching process under the masking of the patterned first mask layer 104, as shown in fig. 5, to form a plurality of through holes 105, and removing the patterned first mask layer 104.
Step S3 is performed, and referring to fig. 10 and 11, an anisotropic second dry etching process is performed to etch the dielectric layer 103 and the substrate 100 in the second region 100b to form the contact hole 108, and simultaneously etch the dielectric layer 103 and the substrate 100 on the side of the via 105 to enlarge the via to form the mark trench 107.
In this embodiment, the mark trench 107 is used to measure overlay accuracy. In an embodiment of the present application, the opening size of the marking trench 107 and the opening size of the contact hole 108 may be different, for example, the opening width of the marking trench 107 is larger than the opening width of the contact hole 108, but is not limited thereto. In the second dry etching process, when the etching conditions are set, firstly, the pattern size of the contact hole 108 is ensured to be normal, and secondly, the etching requirement of the marking groove 107 is considered.
Specifically, step S3 may include forming a patterned second mask layer 106 on the substrate 100, as shown in fig. 7 and 8, where the patterned second mask layer 106 has a contact hole pattern 106b and a mark trench pattern 106a, and one mark trench pattern 106a corresponds to at least a portion of the via 105 and exposes the corresponding via 105, performing a second dry etching process under the masking of the patterned second mask layer 106, as shown in fig. 9, to form a contact hole 108 and a mark trench 107, and removing the patterned second mask layer 106, as shown in fig. 10 and 11.
In this embodiment, the method of forming the patterned second mask layer 106 on the substrate 100 may include coating a photoresist layer on the substrate 100 to form a photoresist layer covering the substrate 100 and filling the plurality of through holes 105, exposing the photoresist layer, and developing the photoresist layer to form the patterned second mask layer 106.
Note that since the photoresist fills the via hole 105, the photoresist layer at the via hole 105 is thicker, in this embodiment, the photoresist layer may be developed twice to completely remove the photoresist in the via hole 105, which is helpful for forming the mark trench 107 with a set size.
In an embodiment of the present application, referring to fig. 8, one marking groove pattern 106a may correspond to more than two through holes 105, and the second dry etching process may be performed to connect the more than two through holes 105 to form the marking groove 107. It should be noted that the number of through holes 105 corresponding to one marking groove pattern 106a may be selected according to needs, and in another embodiment of the present application, one marking groove pattern may correspond to only one through hole.
For example, the patterned second mask layer 106 may have a plurality of marking trench patterns 106a therein, one marking trench pattern 106a corresponding to each set of through holes 105. The plurality of through holes 105 in the group of through holes 105 may be arranged according to the opening area and the opening shape of the marking groove 107 to be formed, for example, the group of through holes 105 may be arranged in a line (as shown in fig. 6), the group of through holes 105 may be arranged in a plurality of columns, and dislocation may exist between two adjacent columns of through holes 105, but is not limited thereto.
The opening shape of the through hole 105 may be rectangular or circular, and the opening shape of the through hole 105 may be selected according to practical situations. In this embodiment, the marking trench pattern 106a in the patterned second mask layer 106 exposes the corresponding via hole 105, and the opening size of the marking trench 107 is formed to be larger than the opening size of the via hole 105, and the opening size includes a length and a width perpendicular to each other. The opening width of the via 105 may also be smaller than the opening width of the contact hole 108. The opening width of the via 105 is, for example, 90nm to 120nm, but not limited thereto.
The depth of the via 105 is less than or equal to the depth of the marking trench 107, and the depth of the via 105 may be set according to the depth of the marking trench 107. Illustratively, the depth of the via 105 may be greater than or equal to 4500 a and less than or equal to 5000 a, such as 4800 a, but is not limited thereto.
Since the etching performance of different dry etching machines is different, in this embodiment, the first dry etching process and the second dry etching process are performed on the same machine, so that the diffusion limiting effect when etching the mark trench 107 can be better suppressed.
In this embodiment, after the patterned second mask layer 106 is formed, the overlay accuracy between the patterned second mask layer 106 and the substrate 100 and the critical dimension of the contact hole pattern 106b may be measured, so that when the overlay accuracy between the patterned second mask layer 106 and the substrate 100 is abnormal and/or the critical dimension of the contact hole pattern 106b is abnormal, the overlay accuracy and the critical dimension of the contact hole pattern 106b may be timely processed, which helps to ensure the alignment between the contact hole 108 and the substrate 100 and ensure the obtained critical dimension of the contact hole 108. After the patterned second mask layer 106 is removed, the critical dimension of the contact hole 108 may also be detected so that the critical dimension of the contact hole 108 may be timely processed when it is abnormal.
After removing the patterned second mask layer 106, a barrier layer 109 may be formed, as shown with reference to fig. 13, the barrier layer 109 covering sidewalls of the contact hole 108 and sidewalls of the marking trench 107. Specifically, as shown in fig. 12, a barrier layer 109 is formed on the dielectric layer 103, the barrier layer 109 covering the top surface of the dielectric layer 103, the sidewalls and bottom surfaces of the mark trench 107, and the sidewalls and bottom surfaces of the contact hole 108, and as shown in fig. 13, the barrier layer 109 on the mark trench 107 and the bottom surfaces of the contact hole 108 is removed, and at least the sidewalls of the contact hole 108 and the barrier layer 109 on the sidewalls of the mark trench 107 remain.
The barrier layer 109 may prevent the conductive material in the subsequently filled contact hole 108 from diffusing into the dielectric layer 103 to affect the conductive performance of the contact hole structure, and may further improve adhesion between the conductive material and the substrate 100.
The material of the barrier layer 109 includes, but is not limited to, tantalum nitride, titanium, or titanium nitride. The barrier layer 109 may be a double-layered structure including, for example, a titanium layer and a titanium nitride layer laminated on the titanium layer, by way of example and not limitation.
Referring to fig. 14, a conductive material layer 110 is formed on the dielectric layer 103, the conductive material layer 110 covers the dielectric layer 103 and fills the contact hole 108 and the mark trench 107, wherein the conductive material layer 110 at least fills the contact hole 108, and the conductive material layer 110 on the top surface of the dielectric layer 103 is removed by grinding to form a contact hole structure, and the contact hole structure includes the contact hole 108, the barrier layer 109 in the contact hole 108, and the conductive material layer 110 in the contact hole 108. Illustratively, the material of the conductive material layer 110 includes, but is not limited to, tungsten (W).
Next, referring to fig. 15, a metal wiring layer 111 is formed on the dielectric layer 103, and the metal wiring layer 111 and the substrate 100 are electrically connected through a contact hole structure.
Referring to fig. 15, the metal wiring layer 111 includes a marking pattern 111a corresponding to the marking groove 107, and an overlay accuracy between the metal wiring layer 111 and the substrate 100 can be measured using the marking groove 107 and the marking pattern 111 a. The shape of the marking pattern 111a may be set according to the pattern of the marking grooves 107.
Fig. 16 is an SEM cross-sectional view of a marking trench of a semiconductor structure according to an embodiment of the present application. Referring to fig. 16, the bottom surface of the marking trench 107 formed in the substrate 100 by the method for manufacturing a semiconductor structure provided by the present application is relatively flat, and no central area of the bottom surface is raised with respect to the edge area, i.e., the diffusion limiting effect during etching of the marking trench 107 is effectively suppressed.
Fig. 17 is an SEM plan view of a marking trench of a semiconductor structure according to an embodiment of the present invention. After the metal wiring layer 111 is formed, referring to fig. 17, the outline of the mark trench 107 is clearly easy to recognize, which contributes to improving the accuracy of the overlay accuracy measurement value obtained by measurement with the mark trench 107.
The application also provides a semiconductor structure which can be manufactured by the manufacturing method of the semiconductor structure.
Specifically, referring to fig. 14 and 15, the semiconductor structure includes a substrate 100 and a dielectric layer 103 formed on the substrate 100, wherein the substrate 100 includes a first region 100a and a second region 100b, a marking trench 107 is formed in the first region 100a, a contact hole 108 is formed in the second region 100b, the marking trench 107 and the contact hole 108 penetrate through the dielectric layer 103, and a bottom surface is located in the substrate 100.
Illustratively, the opening size of the marking trench 107 and the opening size of the contact hole 108 may be different, for example, the opening width of the marking trench 107 is larger than the opening width of the contact hole 108, but is not limited thereto.
The semiconductor structure may further include a barrier layer 109 and a conductive material layer 110, the barrier layer 109 covering sidewalls of the contact hole 108 and sidewalls of the marking trench 107, the conductive material layer 110 filling the contact hole 108 and the marking trench 107, wherein the conductive material layer 110 may at least fill the contact hole 108 to form a contact hole structure, the contact hole structure including the contact hole 108, the barrier layer 109 within the contact hole 108, and the conductive material layer 110 within the contact hole 108.
Referring to fig. 15, a metal wiring layer 111 may be formed on the dielectric layer 103, and the metal wiring layer 111 and the substrate 100 may be electrically connected through a contact hole structure. The metal wiring layer 111 may further include a marking pattern 111a corresponding to the marking trench 107, and an overlay accuracy between the metal wiring layer 111 and the substrate 100 may be measured using the marking trench 107 and the marking pattern 111 a. The shape of the marking pattern 111a may be set according to the pattern of the marking grooves 107.
In the semiconductor structure and the manufacturing method thereof provided by the invention, after the dielectric layer 103 is formed on the substrate 100, firstly, the anisotropic first dry etching process is carried out to etch the dielectric layer 103 and the substrate 100 and stop in the substrate 100, a plurality of through holes 105 are formed in the first area 100a, secondly, the anisotropic second dry etching process is carried out to etch the dielectric layer 103 and the substrate 100 in the second area 100b to form the contact holes 108, and simultaneously, the dielectric layer 103 on the side of the through holes 105 and the substrate 100 are etched to enlarge the through holes 105 to form the mark grooves 107, so that when the contact holes 108 and the mark grooves 107 are etched at the same time, under the condition that the graph and the size of the contact holes 108 are qualified, the diffusion limiting effect generated when the mark grooves 107 are etched can be effectively restrained, the bottom surface of the formed mark grooves is smoother, so that the boundary definition of the mark grooves can be improved, the measurement interference caused by unclear boundary of the mark grooves can be reduced when the overlay accuracy is measured, the precision measurement value of overlay accuracy can be improved, the reworked and the measurement value caused by the abnormal boundary of the mark grooves can be reduced, the reworked and the measurement value of the overlay accuracy is improved, and the bottom surface of the mark grooves can be more completely filled with the conductive material can be better, and the bottom surface of the conductive material can be filled in the wafer.
The foregoing description is only illustrative of the preferred embodiments of the present invention, and is not intended to limit the scope of the claims, and any person skilled in the art may make any possible variations and modifications to the technical solution of the present invention using the method and technical content disclosed above without departing from the spirit and scope of the invention, so any simple modification, equivalent variation and modification made to the above embodiments according to the technical matter of the present invention fall within the scope of the technical solution of the present invention.