Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention is directed to providing a register structure and a writing method for writing multi-bit wide data into a memory, so as to solve the problems of low data transmission efficiency, high occupation of hardware resources and lack of efficient cooperative working mechanism in the application of the conventional register structure in processing multi-bit wide data writing into the memory.
The technical scheme of the invention is as follows:
In a first aspect, the present invention provides a memory multi-bit wide data write oriented register structure comprising a command receiving register set and a parameter cache register set;
The command receiving register set is connected with the parameter cache register set, and is used for receiving an input command, identifying command data and outputting a command completion signal to trigger the parameter cache register set to start after the command data is received;
The parameter buffer register group is used for being connected with the target storage unit, is used for receiving an input command and identifying parameter data, receiving and packaging corresponding parameter data according to the type of the command data after receiving the command completion signal, and generating a data packaging completion signal of the corresponding parameter data so as to input the parameter data into the corresponding target storage unit.
The invention further provides that the command receiving register set comprises a plurality of first triggers and a command identifying unit;
The data input end of the first trigger is connected with the input command, and the output end of the first trigger is respectively connected with the data input end of the next first trigger and the data input end of the command identification unit;
The command recognition unit is connected with the parameter cache register set, and is used for judging the receiving state of the command data, outputting a command completion signal to identify that the receiving of the command data is completed after the receiving of the command data is judged to be completed, and inputting the command completion signal into the parameter cache register set;
The clock input of the first flip-flop is connected to a clock signal.
The invention further provides that the first triggers at least comprise 8, each first trigger corresponds to one bit, and the first trigger is a D trigger.
According to the invention, the parameter buffer register group comprises a plurality of second triggers and parameter identification units;
the data input end of the first second trigger is connected with the input end of the next second trigger and the data input end of the parameter identification unit respectively;
The command data input end of the parameter identification unit is connected with the output end of the command identification unit, the trigger signal input end of the parameter identification unit is connected with the enabling end of the command identification unit, the output end of the parameter identification unit is connected with the target storage unit, and the signal trigger end of the parameter identification unit is connected with the target storage unit;
the parameter identification unit is used for receiving and packaging corresponding parameter data according to the type of the command data after receiving the command completion signal, and generating a data packaging completion signal of the corresponding parameter data so as to input the parameter data into the corresponding target storage unit;
the second trigger is connected with the clock input end of the parameter identification unit to a clock signal.
In a further arrangement of the present invention, the second flip-flops include at least 280, and each of the second flip-flops corresponds to one bit.
In a further arrangement of the invention, the second trigger is a D-trigger.
In a further arrangement of the invention, when the command completion signal is high, receipt of the command data is identified as complete.
In a further arrangement of the present invention, when the data packing completion signal is at a high level, the reception of the identification parameter data is completed, and the corresponding read-write operation is performed on the target storage unit.
In a further arrangement of the present invention, the input commands include a status register configuration command, a read command, and a write command.
In a second aspect, the present invention provides a writing method for writing multi-bit wide data into a memory based on the register structure for writing multi-bit wide data into a memory, which includes:
The control command receiving register set identifies and receives command data in an input command;
outputting a command completion signal and triggering the starting of the parameter buffer register set after the receiving of the command data is completed;
controlling a parameter buffer register group to identify and receive parameter data of an input command according to the type of the command data, and packaging the corresponding parameter data;
And after the packaging of the parameter data is completed, generating a data packaging completion signal of the corresponding parameter data, and inputting the parameter data into the corresponding target storage unit.
The invention provides a register structure and a writing method for writing multi-bit wide data of a memory. The command receiving register set is used for receiving an input command, identifying command data and outputting a command completion signal to trigger the parameter buffer register set to start after the command data is received, wherein the input command comprises command data and parameter data, and the types of different command data correspond to the bit number of the parameter data. The parameter buffer register sets the input command and identifies the parameter data, receives and packages the corresponding parameter data according to the type of the command data after receiving the command completion signal, and generates a data package completion signal of the corresponding parameter data to input the parameter data into the corresponding target storage unit. Therefore, the invention can realize the identification of the command type and the flexible transmission of multi-bit wide data through the cooperative work of the command receiving register group and the parameter buffer register group, improves the data transmission efficiency, reduces the waste of hardware resources, reduces the waiting time of the identification of the command data and the receiving of the parameter data, and ensures the accuracy of the data transmission and the overall performance of the system.
Detailed Description
The invention provides a register structure and a writing method for writing multi-bit wide data into a memory, which are used for making the purposes, technical schemes and effects of the invention clearer and more definite, and the invention is further described in detail below by referring to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
In the description and claims, unless the context specifically defines the terms "a," "an," "the," and "the" include plural referents. If there is a description of "first", "second", etc. in an embodiment of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature.
It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. The term "and/or" as used herein includes all or any and all combinations of one or more of the associated listed items.
It will be understood by those skilled in the art that all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs unless defined otherwise. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present invention.
The inventor researches find that in the application of processing multi-bit wide data writing into a memory, the conventional register structure has the problems of low data transmission efficiency, high occupation of hardware resources and the like, and the overall performance of the system is limited. First, the existing register set generally only supports data transmission with a fixed bit width, and cannot flexibly adapt to multi-bit-width data requirements under different command types, which results in additional control overhead when complex commands and parameter transmission are processed. Secondly, the separation processing of the command and the parameter of the memory writing is often insufficient in the existing design, and long waiting time exists between the command identification and the parameter reception, so that the response speed of the system and the utilization efficiency of hardware resources are further limited.
Aiming at the technical problems, the invention provides a register structure and a writing method for writing multi-bit wide data into a memory, which can realize the identification of a command type and the flexible transmission of the multi-bit wide data through the cooperative work of a command receiving register group and a parameter buffer register group, improve the data transmission efficiency, reduce the waste of hardware resources, reduce the waiting time of the identification of the command data and the reception of the parameter data, and ensure the accuracy of data transmission and the overall performance of a system.
Referring to fig. 1 to 6, the present invention provides a register structure for writing multi-bit wide data into a memory.
In some embodiments, as shown in FIG. 1, the present invention provides a register structure for memory-oriented multi-bit wide data writing, which includes a command receiving register set 100 and a parameter cache register set 200. The command receiving register set 100 is connected with the parameter buffer register set 200, the command receiving register set 100 is used for receiving an input command and identifying command data, and outputting a command completion signal to trigger the parameter buffer register set 200 to start after the command data is received, the input command comprises command data and parameter data, the types of different command data correspond to the bit number of the parameter data, the parameter buffer register set 200 is connected with a target storage unit and is used for receiving the input command and identifying the parameter data, receiving and packaging corresponding parameter data according to the types of the command data after the command completion signal is received, and generating a data packaging completion signal of the corresponding parameter data so as to input the parameter data into the corresponding target storage unit.
Specifically, the target memory cells include, but are not limited to, status registers, read data latches, write data latches, and the like. Correspondingly, the input commands include, but are not limited to, status register configuration commands, read commands, write commands, etc., while corresponding status register configuration commands (8 ' h 01), having 8 bits of parameter data, require a wider bit width for read commands for address information (8 ' h 03), i.e., 24 bits of parameter data, and 280 bits of parameter data for write commands for large data volume transmission (8 ' h 02).
The command receiving register set 100 has a data input, a clock input, an output, and an enable. The parameter buffer register set 200 has a data input, a clock input, a command data input, and a trigger signal input.
The data input of the command receiving register set 100 is connected to an input command (MOSI), and a shift register function is implemented under the control of a clock signal (CLK). When the command data (cmd [7:0 ]) is not received, the command reception register set 100 will continue the shift reception until the shift forms a specific command structure. After the command data (cmd [7:0 ]) is received, a command completion signal (cmd_complete) is outputted to identify that the reception of the command has been completed, the command data is inputted to the command data input terminal of the parameter cache register set 200 through the output terminal of the command receiving register set 100, and the command completion signal (cmd_complete) is inputted to the trigger signal input terminal of the parameter cache register set 200 through the enable terminal to trigger the parameter cache register set 200 to be started as an activation signal, so that the parameter cache register set 200 immediately enters a parameter reception state in the next clock cycle.
When the command completion signal (cmd_complete) is at a high level, reception of command data is identified as completed. When the parameter cache register set 200 receives a command completion signal (cmd_complete) of a high level, the parameter cache register set 200 shifts in reference data bit by bit from a data input terminal according to the type of command data. And after judging that the reference data packaging is finished, generating a data packaging finishing signal (package_complete) according to the command type, wherein when the data packaging finishing signal (package_complete) is at a high level, the receiving of the parameter data (package [ X:0 ]) is finished, and performing corresponding read-write operation on the target storage unit.
It can be seen that the present invention can realize the identification of the command type and the flexible transmission of the multi-bit wide data (can dynamically adapt to different bit wide data) through the cooperative work of the command receiving register set 100 and the parameter buffer register set 200, compared with the traditional fixed bit wide data transmission scheme, the present invention improves the data transmission efficiency, reduces the waste of hardware resources, reduces the waiting time of the command data identification and the parameter data reception (avoids the waiting time of the command data and the parameter data switching), and ensures the accuracy of the data transmission and the overall performance of the system, wherein the overall performance improvement can be embodied in the improvement of the response speed and the improvement of the hardware resource utilization efficiency.
In some embodiments, as shown in fig. 1 and 2, the command receiving register set 100 includes a plurality of first flip-flops and a command identifying unit 110. The first flip-flops are sequentially connected, wherein a data input end of a first flip-flop is connected to an input command, an output end of the first flip-flop is connected to a data input end of a next first flip-flop and a data input end of the command identifying unit 110 respectively, the command identifying unit 110 is connected to the parameter buffer register set 200, the command identifying unit 110 is used for judging a receiving state of command data, and when the receiving of the command data is judged to be completed, a command completion signal is output to identify that the receiving of the command data is completed, and the command completion signal is input to the parameter buffer register set 200, and a clock input end of the first flip-flop and a clock input end of the command identifying unit 110 are connected to a clock signal.
Specifically, since the command data has 8 bits, the first flip-flop has 8 (i.e., Q00-Q07 in fig. 2, where Q00-Q07 represents an output terminal of the first flip-flop), the first flip-flop is a D flip-flop, a data input terminal of the first flip-flop is connected to an input command, an output terminal is connected to a data input terminal of a next first flip-flop and a data input terminal of the command identifying unit 110, an inverting output terminal is empty, each flip-flop corresponds to one bit, and the first flip-flop implements a shift register function under the control of the clock signal. The input end of the command recognition unit 110 is a data input end, the output end is the output end of the command receiving register set 100, and the enabling end is the enabling end of the command receiving register set 100.
The command recognition unit 110 can determine the receiving state of the command data, and once a preset complete command is satisfied, it outputs a command complete signal (cmd_complete) to identify that the receiving of the command data has been completed. In addition, the command completion signal not only indicates that the current command data reception has been completed, but also can be used as an activation signal to be input into the parameter cache register set 200 to trigger the parameter cache register set 200 to start, so that the parameter cache register set 200 immediately enters a parameter receiving state in the next clock period, thereby avoiding the waiting time of switching between the command data and the parameter data and improving the response speed of the system.
In some embodiments, as shown in fig. 1 to 3, the parameter buffer register set 200 includes a plurality of second flip-flops and parameter identification units 210. The second triggers are sequentially connected, wherein the data input end of a first second trigger is connected with an input command, the output end of the first second trigger is connected with the input end of a next second trigger and the data input end of the parameter identification unit 210 respectively, the command data input end of the parameter identification unit 210 is connected with the output end of the command identification unit 110, the trigger signal input end of the parameter identification unit 210 is connected with the enabling end of the command identification unit 110, the output end of the parameter identification unit 210 is connected with the target storage unit, the signal trigger end of the parameter identification unit 210 is connected with the target storage unit, the parameter identification unit 210 is used for receiving and packaging corresponding parameter data according to the type of command data after receiving the command completion signal and generating a data packaging completion signal of the corresponding parameter data so as to input the parameter data into the corresponding target storage unit, and the second trigger is connected with the clock input end of the parameter identification unit 210.
Specifically, to flexibly cope with writing of multi-bit wide data, the second flip-flops include at least 280, for example, 280 in this embodiment (i.e., Q0-Q279 in fig. 3, where Q0-Q279 represents an output terminal of the second flip-flop), and each of the second flip-flops corresponds to one bit, and the second flip-flop may be a D flip-flop.
The parameter identification unit 210 has a data input terminal, a clock signal terminal, an output terminal, a trigger signal input terminal, and a signal output terminal.
An input command (MOSI) is input from the data input terminal of the first and second flip-flops, and the parameter recognition unit 210 is activated after the parameter recognition unit 210 receives a command completion signal (cmd_complete) of a high level. The parameter identification unit 210 is capable of determining the bit width of the parameter data according to the type of command data, which is bit-wise shifted into the parameter identification unit 210 by a second flip-flop under the control of the clock signal (CLK). The parameter identification unit 210 can perform and package the received parameter data, and can determine whether the data package is completed according to the command type and the preset bit width, for example, when an 8-bit data packet is transmitted for the status register configuration, the parameter identification unit 210 detects an 8-bit data regeneration data package completion signal (package_complete), and in a 24-bit data packet reading operation, the parameter identification unit 210 waits for the 24-bit data regeneration data package completion signal, and for the write operation, the parameter identification unit 210 detects a 280-bit data packet before generating the data package completion signal. That is, when determining that the data packaging is completed, the parameter identification unit 210 generates a data packaging completion signal (package_complete), so as to achieve flexible and efficient data receiving and processing according to the lengths and requirements of different command types.
As shown in fig. 4, 5 and 6, fig. 4, 5 and 6 show timing diagrams of writing 8-bit, 24-bit and 280-bit parameter data, respectively, and data of different types of commands can be smoothly transferred to a target memory unit through cooperation of the command receiving register set 100 and the parameter cache register set 200. When the command receiving register set 100 receives an input command and generates a command completion signal (cmd_complete), the parameter buffer register set 200 is activated and receives a data packet of a corresponding bit width according to the type of the command. Once the parameter cache register set 200 completes the data packing and generates a data packing complete signal, the system transfers the data packet to a designated target memory location, such as a status register, a read data latch, or a write data latch, etc. At this time, the system can perform corresponding read/write operation on the memory when the data package completion signal (package_complete) is at a high level according to the data in the status register, the read data latch or the write data latch. In practical application, the invention can support data packets with different bit widths of 8 bits, 24 bits, 280 bits and the like, and is suitable for different operation scenes from simple state configuration to large data volume writing.
In some embodiments, as shown in fig. 7, the present invention provides a writing method for writing multi-bit wide data into a memory based on the register structure for writing multi-bit wide data into a memory, which includes the steps of:
S100, the control command receiving register set identifies and receives command data in the input command, and is specifically described in the embodiment of a register structure for writing multi-bit wide data into the memory, which is not described herein.
S200, outputting a command completion signal and triggering the parameter buffer register set to start after receiving the command data, wherein the command completion signal is specifically described in the embodiment of a register structure for writing multi-bit wide data into a memory, and the description is omitted herein.
S300, the parameter buffer register group is controlled according to the type of the command data to identify and receive the parameter data of the input command and package the corresponding parameter data, and the details are not repeated here, as described in the embodiment of the register structure for writing the multi-bit wide data of the memory.
S400, after the packaging of the parameter data is completed, a data packaging completion signal of the corresponding parameter data is generated, and the parameter data is input into a corresponding target storage unit. In particular, the embodiment of the register structure for writing multi-bit wide data into the memory is described, and will not be described herein.
In summary, the register structure and the writing method for writing multi-bit wide data into the memory provided by the invention have the following beneficial effects:
The command type identification and the flexible transmission of multi-bit wide data can be realized through the cooperative work of the command receiving register set and the parameter buffer register set, so that the data transmission efficiency is improved, and the waste of hardware resources is reduced;
The command completion signal generated by the command receiving register group not only indicates that the current command data reception is completed, but also can be used as an activation signal to be input into the parameter buffer register group to trigger the parameter buffer register group to start, so that the parameter buffer register group immediately enters a parameter receiving state in the next clock period, the waiting time of switching between the command data and the parameter data is avoided, and the accuracy of data transmission and the overall performance of a system are ensured.
It is to be understood that the invention is not limited in its application to the examples described above, but is capable of modification and variation in light of the above teachings by those skilled in the art, and that all such modifications and variations are intended to be included within the scope of the appended claims.