Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. Examples of the embodiments are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements throughout or elements having like or similar functionality. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the invention. Furthermore, it should be understood that the detailed description is presented merely to illustrate the invention and is not intended to limit the invention.
In the description of the present invention, it should be understood that the orientation or positional relationship indicated in the description of the direction and positional relationship is based on the orientation or positional relationship shown in the drawings, only for convenience of description of the present invention and simplification of the description, and is not indicative or implying that the apparatus or element in question must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more of the described features. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
The following disclosure provides many different embodiments, or examples, for implementing different structures of the invention. In order to simplify the present disclosure, components and arrangements of specific examples are described below. Of course, the above materials are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, and which do not themselves indicate the relationship between the various embodiments and/or arrangements discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the application of other processes and/or the use of other materials.
The 3D-DRAM memory device includes one or more memory device layers stacked in a direction perpendicular or approximately perpendicular to the substrate (e.g., a Z-axis direction), each memory device layer including a plurality of memory cells distributed in an array. Each memory cell may comprise a 2T0C-DRAM, i.e. the memory cell comprises 2 transistors and 0 capacitors. The 2 transistors are a write transistor and a read transistor, respectively. The drain of the writing transistor is connected to the gate of the reading transistor, and a Reading Word Line (RWL), a Reading Bit Line (RBL), a Writing Word Line (WWL) and a Writing Bit Line (WBL) are respectively arranged at corresponding positions and connected with corresponding positions on the transistor.
For example, the gate of the write transistor is connected to the write word line, the source of the write transistor is connected to the write bit line, the source of the read transistor is connected to the read word line, and the drain of the read transistor is connected to the read bit line.
Referring to fig. 1 and fig. 2a and 2b, a memory device 1000 of the present invention includes a substrate 200 and at least one memory device layer 100 disposed on the substrate 200. As in the embodiment shown in the above figures, the substrate 200 may include a semiconductor substrate 201 and an insulating layer 202 on a side of the semiconductor substrate 201 near the memory device layer 100, a surface of the insulating layer 202 remote from the semiconductor substrate 201 being formed as an insulating surface of the substrate 200.
The semiconductor substrate 201 may include a semiconductor material, for example, at least one of silicon (e.g., single crystal silicon Si), silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), and silicon carbide (SiC), among others.
In one embodiment, the substrate 200 may be a single-layer structure, for example, a single-layer structure that may be made of at least one of silicon, germanium, gallium arsenide, or the like.
In another embodiment, the substrate 200 may also be a multi-layer structure, such as a composite substrate including a stack of silicon and silicon germanium, a stack of silicon and silicon carbide, silicon-on-insulator, germanium-on-insulator, silicon-germanium-on-insulator, or the like.
The semiconductor substrate 201 may be a monocrystalline silicon substrate, for example, and optionally logic circuits are included in the semiconductor substrate 201.
In other embodiments, the substrate 200 is an insulating substrate. The insulating substrate may be, for example, a non-conductive material made of glass, plastic, or sapphire wafer. Alternatively, the substrate 200 may be an insulating dielectric material such as silicon dioxide (SiO2), silicon nitride (SiN), or the like.
In one embodiment, the insulating layer 202 may comprise an insulating material commonly used in the art, such as silicon dioxide (SiO2), silicon nitride (SiNx), or the like.
The memory device layer 100 includes at least a memory cell 110, a write word line 120, a write bit line 130, a read word line 140, and a read bit line 150, and the memory cell 110 includes a write transistor 111 and a read transistor 112.
Referring to the embodiment shown in fig. 2a and 3a, the writing transistor 111 includes a first gate electrode 1111, a first active layer 1112, a first gate insulating layer 1113, and a first source electrode 1114, the first gate electrode 1111 is disposed on the substrate 200 along the Z-axis direction, i.e. vertically, the first active layer 1112 is disposed at least partially around the first gate electrode 1111, the first gate insulating layer 1113 is disposed between the first gate electrode 1111 and the first active layer 1112, and the first source electrode 1114 is connected to a source end of the first active layer 1112.
Referring to fig. 2b and 3b, in another embodiment of the present invention, the writing transistor 111 includes a first gate electrode 1111, a first active layer 1112, a first gate insulating layer 1113, and a first source electrode 1114, the first gate electrode 1111 is disposed on the substrate 200 along the Z-axis direction, i.e., vertically, the first active layer 1112 is disposed at least partially around the first gate electrode 1111, the first gate insulating layer 1113 is disposed between the first gate electrode 1111 and the first active layer 1112, and the first source electrode 1114 is connected to a source terminal of the first active layer 1112.
Referring to fig. 2a, 2b and 4, the read transistor 112 includes a second gate electrode 1121, a second active layer 1122, a second gate insulating layer 1123, a second source electrode 1124 and a second drain electrode 1125, the second active layer 1122 is disposed on the substrate 200 along the Z-axis direction, i.e., vertically, the second gate electrode 1121 is disposed at least partially around the second active layer 1122, the second gate insulating layer 1123 is disposed between the second gate electrode 1121 and the second active layer 1122, the second source electrode 1124 is connected to the source end of the second active layer 1122, and the second drain electrode 1125 is connected to the drain end of the second active layer 1122.
Referring to fig. 2a to 4, the second gate electrode 1121 further includes a horizontal extension 11211, and the horizontal extension 11211 is connected to a drain terminal of the first active layer 1112.
In the embodiment of the present invention, the second gate electrode 1121 further includes a horizontal extension portion 11211, and the horizontal extension portion 11211 is connected to the drain terminal of the first active layer 1112 to electrically connect the writing transistor 111 and the reading transistor 112, that is, the horizontal extension portion 11211 includes the first drain electrode of the writing transistor 111, so that the memory cell 110 has a simple structure, and the process difficulty and the production cost are reduced.
Wherein the horizontal extension 1121 is parallel or approximately parallel to the substrate 200. Preferably, the second gate electrode 1121 is parallel or approximately parallel to the substrate 200.
The first gate electrode 1111 is connected to the write word line 120, the first source electrode 1114 is connected to the write bit line 130, the second source electrode 1124 is connected to the read word line 140, and the second drain electrode 1125 is connected to the read bit line 150. In the Z-axis direction, i.e., the vertical direction, the write word line 120 is located on the side of the first source electrode 1114 remote from the horizontal extension 11211. When the first source electrode 1114 is formed integrally with the write bit line 130, the write word line 120 is located on a side of the write bit line 130 away from the horizontal extension 11211.
It should be noted that, the write word line 120 and the write bit line 130 are signal lines providing corresponding functions at corresponding positions of the memory device 100, specifically:
The write word line 120 is electrically connected to the gate of the write transistor 111 in the memory cell 110, and when a write operation is performed, a voltage is applied through the write word line 120 to turn on the write transistor 111. That is, the write word line 120 is a signal line electrically connected to the gate of the write transistor 111, and a voltage is applied to turn on the write transistor during a write operation;
The write bit line 130 is electrically connected to the source of the write transistor 111 in the memory cell 110, and when the write transistor 111 is turned on, a voltage is applied through the write bit line 130 to charge or discharge the storage node SN through the write transistor 111, so that a high voltage or a low voltage is present at the storage node SN, representing data 1 and 0, respectively, thereby completing the write operation. That is, the write bit line 130 is a signal line electrically connected to the source of the write transistor 111, and applies a voltage to charge or discharge the storage node SN through the write transistor 111 when the write transistor 111 is turned on.
In addition, specifically for read word line 140 and read bit line 150:
a read word line 140, i.e., a signal line to which a read voltage is applied to the second source electrode 1124 of the read transistor 112 to which it is connected, a read bit line 150, i.e., a signal line to which the second drain electrode 1125 is connected and in which data is written from the read storage node SN by detecting the magnitude of a current, or
The read bit line 150 is a signal line to which a read voltage is applied to the second drain electrode 1125 of the read transistor 112 to which it is connected, and the read word line 150 is a signal line to which the second source electrode 1124 is connected and to which data is written from the read storage node SN by detecting the magnitude of a current in a read operation.
The second source electrode 1124 and the first source electrode 1114 are located on the same side of the second gate electrode 1121, and the second drain electrode 1125 is located on the side of the second gate electrode 1121 away from the first source electrode 1114. It is understood that for the read transistor 112, the second source electrode 1124, the second drain electrode 1125 do not define the channel current flow direction of the read transistor 112 during a read operation.
In the memory cell 110 of one embodiment of the memory device 1000 of the present invention, the first gate electrode 1111 of the writing transistor 111 is vertically disposed on the substrate 200, the first active layer 1112 is disposed on at least a portion of the periphery of the first gate electrode 1111, the second active layer 1122 of the reading transistor 112 is vertically disposed on the substrate 200, the second gate electrode 1121 is disposed on at least a portion of the periphery of the second active layer 1122, the second gate electrode 1121 further includes a horizontal extension 11211, and the horizontal extension 11211 is connected to the drain terminal of the first active layer 1112.
That is, the write transistor 111 and the read transistor 112 in the memory cell 110 of the present invention are vertical channel transistors, and have a higher storage density than the horizontal channel transistors of the prior art. In addition, the write transistor 111 and the read transistor 112 are horizontally arranged and overlap in the vertical direction, and compared with two vertical channel transistors vertically stacked in 2T0C of the prior art, the space in the vertical direction is saved, so that the vertical channel transistors are horizontally arranged and designed to overlap in the vertical direction, and the space utilization in the vertical direction and the horizontal direction is improved, so that the storage density of the memory cell 110 is effectively improved.
Wherein the first gate electrode 1111 may be a solid column structure. In other embodiments, the first gate electrode 1111 may also have a hollow structure, such as a groove or a cylinder structure, where a dielectric layer may be filled in the hollow of the first gate electrode 1111, the dielectric layer may include an insulating material, the dielectric layer may have a single-layer structure or a multi-layer structure, and an air gap (air gap) may be included in the dielectric layer, which is not particularly limited herein.
The first active layer 1112 is disposed at least partially around the first gate electrode 1111, which may be disposed circumferentially around the first gate electrode 1111, or may be disposed only partially around the first gate electrode 1111.
Preferably, the first active layer 1112 completely surrounds the first gate electrode 1111, increasing the channel width of the write transistor, and increasing the write current when the write transistor is turned on.
Wherein the second active layer 1122 may be a solid pillar structure. In other embodiments, the second active layer 1122 may also be a hollow structure, such as a trench or a cylinder structure, where a dielectric layer may be filled in the hollow of the second active layer 1122, the dielectric layer may include an insulating material, the dielectric layer may be a single-layer structure or a multi-layer structure, and an air gap (air gap) may be included in the dielectric layer, which is not particularly limited herein.
The second gate electrode 1121 is disposed at least partially around the second active layer 1122, which may be understood that the second gate electrode 1121 is disposed circumferentially around the second active layer 1122, and may completely surround the second active layer 1122 or may partially surround the second active layer 1122.
Preferably, the second gate electrode 1121 completely surrounds the second active layer 1122, increasing the channel width of the read transistor, and a larger read current can be obtained in the read operation, thereby increasing the read margin.
In the embodiment shown in fig. 1, the memory device layer 100 includes a plurality of memory cells 110, and the plurality of memory cells 110 are distributed in an array in the memory device layer 100. Illustratively, the plurality of memory cells 110 in the memory device layer 100 are arranged in an array in the first horizontal direction and the second horizontal direction.
The write word line 120 and the read bit line 150 are each provided in plurality and are arranged at intervals in the second horizontal direction to extend in the first horizontal direction, the write word line 120 is connected to the first gate electrodes 1111 of the plurality of write transistors 111 arranged in the first horizontal direction, and the read bit line 150 is connected to the second drain electrodes 1125 of the plurality of read transistors 112 arranged in the first horizontal direction.
The write bit line 130 and the read word line 140 are prepared in the same layer and are each provided in a plurality and alternately arranged at intervals in the first horizontal direction and extend in the second horizontal direction, the write bit line 130 is connected to the first source electrode 1114 of the plurality of write transistors 111 arranged in the second horizontal direction, and the read word line 140 is connected to the second source electrode 1124 of the plurality of read transistors 112 arranged in the second horizontal direction.
The write bit line 130 and the read word line 140 alternately arranged at intervals in the first horizontal direction include:
As in the embodiment of FIG. 1, the write bit lines 130 and read word lines 140 are alternately spaced one by one;
In other embodiments, two memory cells 110 adjacent in the first horizontal direction are symmetrically arranged, and the write bit line 130 and the read word line 140 connected to the two symmetrical memory cells 100 are also symmetrically arranged, that is, the write bit line 130 and the read word line 140 are alternately spaced apart from each other.
It is understood that the first and second horizontal directions are two directions extending parallel or approximately parallel to the substrate 200, and that the first and second horizontal directions intersect. The first horizontal direction is perpendicular to the second horizontal direction, but the present invention does not specifically limit the included angle between the first horizontal direction and the second horizontal direction, and the first horizontal direction and the second horizontal direction may intersect.
In the embodiment shown in fig. 1, the first horizontal direction is the X-axis direction and the second horizontal direction is the Y-axis direction.
As such, one write word line 120 can be connected to the plurality of write transistors 111 arranged at intervals along the first horizontal direction, one write bit line 130 can be connected to the plurality of write transistors 111 arranged at intervals along the second horizontal direction, one read word line 140 can be connected to the plurality of read transistors 112 arranged at intervals along the second horizontal direction, and one read bit line 150 can be connected to the plurality of read transistors 112 arranged at intervals along the first horizontal direction.
Since the write word line 120 and the write bit line 130 cross each other, and the read word line 140 and the read bit line 150 cross each other, the transistor at the crossing can be selected by the crossing of the signal line, and thus any memory cell 110 in the memory device layer 100 can be selected for read/write operation.
In the memory cell 110, the arrangement direction of the writing transistor 111 and the reading transistor 112 may be the same as or different from any one of the first and second horizontal directions, and the present invention is not limited thereto.
Still further, in an embodiment of the present invention, the materials of the write word line 120, the write bit line 130, the read word line 140, the read bit line 150, the first gate electrode 1111, the first source electrode 1114, the second gate electrode 1121, the second source electrode 1124 and the second drain electrode 1125 are the same or different, and include conductors.
Wherein the conductor comprises at least one of aluminum, titanium, tungsten, titanium nitride, and doped polysilicon.
In one embodiment, the material of the write bit line 130 may be the same as the material of the first source electrode 1114, the material of the read bit line 150 may be the same as the material of the second drain electrode 1125, and the material of the read word line 140 may be the same as the material of the second source electrode 1124.
Thus, the above components having the same material may be prepared and formed integrally with the layers, that is, the write bit line 130 may be formed integrally with the first source electrode 1114 connected thereto, the read bit line 150 may be formed integrally with the second drain electrode 1125 connected thereto, and the read word line 140 may be formed integrally with the second source electrode 1124 connected thereto, thereby simplifying the manufacturing process and reducing the manufacturing cost.
It is understood that the write bit line 130 may be integral with the source electrode 1114 to which it is coupled, the read bit line 150 may be integral with the second drain electrode 1125 to which it is coupled, the read word line 140 may be integral with the second source electrode 1124 to which it is coupled, a portion of the write bit line 130 may be formed as the first source electrode 1114, a portion of the read bit line 150 may be formed as the second drain electrode 1125, and a portion of the read word line 140 may be formed as the second source electrode 1124, respectively.
In a preferred embodiment of the present invention, the write bit line 130 is made of the same material and the same layer as the first source electrode 1114, the read word line 140 and the second source electrode 1124, the write bit line 130 is formed integrally with the first source electrode 1114, and the read word line 140 is formed integrally with the second source electrode 1124, so that the preparation of the write bit line 130, the first source electrode 1114, the read word line 140 and the second source electrode 1124 can be completed in one patterning film preparation process, which simplifies the manufacturing process and reduces the production cost.
In addition, the material of the write word line 120 may be the same as or different from that of the first gate electrode 1111, the material of the read bit line 150 and the read word line 140 may be the same as or different from that of the second gate electrode 1121, and the materials of the first gate electrode 1111 and the second gate electrode 1121 may be set according to actual needs to achieve good electrical characteristics of the write transistor 111 and the read transistor 112.
It is to be noted that when the material of the write word line 120 is the same as that of the first gate electrode 1111, both may be prepared simultaneously so as to be formed as one body.
Referring to fig. 1, fig. 2a and fig. 2b, in the memory cell 110 according to the embodiment of the invention, the first active layer 1112 is disposed on the periphery of the first gate electrode 1111, the first source electrode 1114 is connected to the source end of the first active layer 1112, the write bit line 130 is connected to the first source electrode 1114, and the read word line 140 is connected to the second source electrode 1124.
Therefore, the write bit line 130 and the read word line 140 can be disposed on the same layer, and are disposed at intervals and extend in the same direction to be respectively connected with the write transistor 111 and the read transistor 112, so that the height of the memory cell 110 in the Z-axis direction is further reduced, the write bit line 130 and the read word line 140 can be prepared in the same process step, and the process difficulty and the production cost are reduced.
It should be noted that although not all of fig. 1, 2a, 2b, and 6 to 9 are shown, insulating spacers are filled between the write transistor 111 and the read transistor 112 and between the write word line 120, the write bit line 130, the read word line 140, the read bit line 150 and the second gate electrode 1121 (including the horizontal extension 11211), and the insulating spacers include insulating materials, such as silicon oxide SiO2, silicon nitride Si3N4, and the like, and may also be TEOS (Tetraethoxysilane) or low dielectric constant materials.
The first active layer 1112 and the second active layer 1122 include an oxide semiconductor material, and the materials of the first active layer 1112 and the second active layer 1122 may be the same or different. The oxide semiconductor material comprises at least one of indium oxide In2O3, tin oxide SnO2, gallium oxide Ga2O3, indium tin oxide ITO, indium gallium zinc oxide IGZO, zinc oxide ZnO and indium zinc oxide IZO.
In the embodiment of the present invention, the material of the first active layer 1112 and the second active layer 1122 is indium gallium zinc oxide IGZO.
Further, the first gate insulating layer 1113 and the second gate insulating layer 1123 include an insulating material such as silicon oxide SiOx, silicon nitride SiNx, a high dielectric constant material, or the like, or a combination material, a stacked material, or a combined stacked material of the above materials.
Referring to fig. 1, 2a, 2b, and 6 to 9, the memory device layer 100 further includes a plurality of memory cells 110, and the plurality of memory cells 110 are distributed in an array in the memory device layer 100. Illustratively, the plurality of memory cells 110 in the memory device layer 100 are arranged in an array in a first horizontal direction and a second horizontal direction.
The write word line 120 and the read bit line 150 are each provided in plurality and each are arranged at intervals in the second horizontal direction to extend in the first horizontal direction, the write word line 120 is connected to the first gate electrode 1111 of the plurality of write transistors 111 arranged in the first horizontal direction, and the read bit line 150 is connected to the second drain electrode 1125 of the plurality of read transistors 112 arranged in the first horizontal direction.
The write bit lines 130 and the read word lines 140 are each provided in plural and alternately arranged at intervals in the first horizontal direction and extend in the second horizontal direction, the write bit lines 130 are connected to the first source electrodes 1114 of the plurality of write transistors 111 arranged in the second horizontal direction, and the read word lines 140 are connected to the second source electrodes 1124 of the plurality of read transistors 112 arranged in the second horizontal direction.
In some embodiments, the first source electrode 1114 and the second source electrode 1124 are located in the same layer. When the first source electrode and the write bit line 130 are formed as a unit and the second source electrode 1124 and the read word line 140 are formed as a unit, the write bit line 130 and the read word line 140 are located at the same layer.
In some embodiments, the write bit lines 130 and read word lines 140 are located in different layers, but still alternately spaced apart in a first horizontal direction, extending in a second horizontal direction.
In one embodiment, the second source electrode 1124 and the first source electrode 1114 are fabricated in the same layer, i.e., they are in the same layer, and the distance between the second source electrode 1124 and the opposite surface of the second gate electrode 1121 is smaller than the distance between the first source electrode 1114 and the opposite surface of the horizontal extension 11211 in the vertical direction.
In this way, the distance between the opposite surfaces of the first source electrode 1114 and the horizontal extension 11211 can be increased, i.e., the distance between the first source electrode 1114 and the first drain electrode can be extended, and the resistance between the source and drain terminals of the writing transistor 111 can be increased, thereby reducing the leakage current.
If the second source electrode 1124 and the first source electrode 1114 are located on the same layer, and if the distance between the surface of the second source electrode 1124 and the first source electrode 1114, which is close to the side of the second gate electrode 1121, is the same as the distance between the second gate electrode 1121, the leakage current of the writing transistor 111 is reduced, and meanwhile, the impedance between the source and the drain when the reading transistor 112 is turned on is also improved, and the reading margin is reduced. By the distance between the second source electrode 1124 and the opposite surface of the second gate electrode 1121 being smaller than the distance between the first source electrode 1114 and the opposite surface of the horizontal extension 11211 in the vertical direction, it is possible to achieve both improvement of the leakage current of the write transistor 111 and the read margin of the memory cell 110.
As in the embodiment shown in fig. 5a, the distance between the second source electrode 1124 and the opposite surface of the second gate electrode 1121 is made smaller than the distance between the first source electrode 1114 and the opposite surface of the horizontal extension 11211, i.e., the distance between the surface of the second active layer 1122 away from the second gate electrode 1121 and the surface of the second gate electrode 1121 on the side close to the first source electrode 1114 is made smaller than the distance between the opposite surfaces of the first source electrode 1114 and the second gate electrode 1121.
For example, referring to fig. 5a, 13a to 14c, the second active layer 1122 is prepared in the first hole 7, by making the second active layer 1122 closer to the second gate electrode 1121 than the surface of the second gate electrode 1121 is to the opening of the first hole 7, i.e., the second active layer 1122 fills only a partial depth of the first hole 7 from the bottom up, it is possible to realize that the first source electrode 1114 and the second source electrode 1124 are located at the same layer, and the distance between the second source electrode 1124 and the opposite surface of the second gate electrode 1121 is smaller than the distance between the first source electrode 1114 and the opposite surface of the horizontal extension 11211.
For example, the surface of the second active layer 1122 distant from the second gate electrode 1121 may be brought closer to the second gate electrode 1121 than the opening of the first hole 7, as shown in fig. 5a, or the surface of the second active layer 1122 distant from the second gate electrode 1121 and the end of the second gate insulating layer distant from the second gate electrode 1121 may be brought closer to the second gate electrode 1121 than the opening of the first hole 7.
In practice, the distance between the second source electrode 1124 and the opposite surface of the second gate electrode 1121 and the distance between the first source electrode 1114 and the opposite surface of the horizontal extension 11211 may be adjusted as desired.
In addition, if the channel length of the write transistor 111 is to be increased, the thickness of the insulating spacer between the write bit line 130 and the horizontal extension 11211 may be increased to increase the distance between the first source electrode 1114 and the horizontal extension 11211.
In another embodiment, referring to fig. 5b and 31, the read bit line 150 is formed integrally with the second drain electrode 1125, and the second active layer 1122 is prepared in the fifth hole 17 by making the surface of the second active layer 1122 remote from the second gate electrode 1121 closer to the second gate electrode 1121 than the opening of the fifth hole 17, i.e., the second active layer 1122 fills only a partial depth of the fifth hole 17 from bottom to top.
Thus, the distance between the second drain electrode 1125 and the opposite surface of the second gate electrode 1121 can be made smaller than the distance between the read bit line 150 and the opposite surface of the second gate electrode 1121, so that the channel length of the read transistor 112 can be independently adjusted while reducing the coupling between the read bit line 150 and the second gate electrode 1121.
For example, the surface of the second active layer 1122 distant from the second gate electrode 1121 may be brought closer to the second gate electrode 1121 than the opening of the fifth hole 17, as shown in fig. 5b, or the surface of the second active layer 1122 distant from the second gate electrode 1121 and the end of the second gate insulating layer distant from the second gate electrode 1121 may be brought closer to the second gate electrode 1121 than the opening of the fifth hole 17.
In practice, the distance between the second drain electrode 1125 and the opposite surface of the second gate electrode 1121 and the distance between the first source electrode 1114 and the opposite surface of the horizontal extension 11211 may be adjusted according to actual needs.
Referring to fig. 2a to 4 and fig. 14a to 15b, further, in the memory unit 110:
The first active layer 1112 overlaps with the orthographic projections of the first source electrode 1114 and the horizontal extension 11211 on the substrate 200, the first source electrode 1114 and the horizontal extension 11211 are connected to the first active layer 1112, and the first active layer 1112 overlaps with the orthographic projections of the write bit line 130 and the horizontal extension 11211 on the substrate 200 when the first source electrode 1114 is integrated with the write bit line 130;
The second active layer 1122 overlaps with the orthographic projections of the second source electrode 1124 and the second drain electrode 1125 on the substrate 200, the second source electrode 1124 and the second drain electrode 1125 are connected to the second active layer 1122, the second source electrode 1124 is integrated with the read word line 140, and the second drain electrode 1125 is integrated with the read bit line 150, the second active layer 1122 overlaps with the orthographic projections of the read word line 140 and the read bit line 150 on the substrate;
meanwhile, a structure composed of the second active layer 1122 and the second gate insulating layer 1123 is overlapped with the orthographic projection of the second gate electrode 1211 on the substrate 200 such that the second gate electrode 1121 is at least partially located at the periphery of the second active layer 1122.
Optionally, the second active layer 1122 overlaps with the orthographic projection of the second gate electrode 1211 on the substrate 200.
Preferably, the front projection of the first active layer 1112 on the substrate 200 falls within the front projection overlapping range of the first source electrode 1114 and the horizontal extension 11211 on the substrate 200, and the front projection of the structure formed by the second active layer 1122 and the second gate insulating layer 1123 on the substrate 200 falls within the front projection overlapping range of the second source electrode 1124, the second gate electrode 1121 and the second drain electrode 1125 on the substrate 200.
When the first source electrode 1114 is formed integrally with the write bit line 130, the second source electrode 1124 is formed integrally with the read word line 140, and the second drain electrode 1125 is formed integrally with the read bit line 150, the front projection of the first active layer 1112 on the substrate 200 falls within the front projection overlapping range of the write bit line 130 and the horizontal extension 11211 on the substrate 200, and the front projection of the structure formed by the second active layer 1122 and the second gate insulating layer 1123 on the substrate 200 falls within the front projection overlapping range of the read word line 140, the second gate electrode 1121, and the read bit line 150.
With continued reference to fig. 2 a-4, 12 a-12 c, 14a, 14b and 34 a-34 c, further in orthographic projection on the substrate 200:
The second gate electrode 1121 overlaps the opposite sides of the read bit line 150 in parallel with the opposite sides of the read bit line 150 in the extending direction, the second gate electrode 1121 overlaps the write bit line 130, the read word line 140, and the second gate electrode 1121 is located at the opposite sides of the write bit line 130, the read word line 140 in the extending direction and overlaps the sides of the write bit line 130, the read word line 140, respectively, overlapping the second gate electrode 1121.
It will be appreciated that in preparing the second gate electrode 1211, two sides of the second gate electrode 1211 extending in the X-axis direction may be prepared in the same patterning process as two sides of the read bit line 150 extending in the X-axis direction, and thus, in front projection on the substrate 200, opposite sides of the second gate electrode 1121 parallel to the extending direction of the read bit line 150 overlap opposite sides of the read bit line 150.
Further, the width of the second gate electrode 1121 in the Y-axis direction is equal to the width of the read bit line 150.
Similarly, in preparing the second gate electrode 1211, two sides of the second gate electrode 1211 extending in the Y-axis direction may be prepared in the same patterning process as two sides of the write bit line 130 and the read word line 140 away from each other, and thus, in front projection on the substrate 200, the second gate electrode 1121 is located at opposite sides of the write bit line 130 and the read word line 140 extending direction, and overlaps with sides of the write bit line 130 and the read word line 140 overlapping the second gate electrode 1121, respectively.
It is worth mentioning that the above mentioned overlapping is not limited to complete overlapping.
For example, in preparing the second gate electrode 1211, two sides of the second gate electrode 1211 extending in the X-axis direction may be prepared in the same patterning process as opposite sides of the read bit line 150 extending direction, two sides of the second gate electrode 1211 extending in the Y-axis direction may be prepared in the same patterning process as two sides of the write bit line 130, the read word line 140 away from each other, but the second gate electrode 1121 is in different layers from the read bit line 150, the write bit line 130, and the read word line 140, and thus there may be a certain error, but such an error is within an overlapping range, that is, overlapping includes complete overlapping and approximate overlapping.
Similarly, equal width also includes perfect equality and approximate equality.
Referring to fig. 2a and 3a, the first active layer 1112 has a trench structure, and a bottom end of the trench structure contacts or is buried in the horizontal extension 11211.
The groove-shaped structure may be understood as a U-shaped bottom structure, that is, the first active layer 1112 has a surface-shaped bottom in contact with the horizontal extension portion 11211 in a larger area, so that the effective contact connection between the first active layer 1112 and the horizontal extension portion 11211 is realized, the connection impedance between the first active layer 1112 and the horizontal extension portion 11211 is reduced, the bottom end of the groove-shaped structure is embedded into the horizontal extension portion 11211, the connection impedance can be further reduced, and the process difficulty for preparing the memory unit 100 is reduced.
Referring to fig. 2b and 3b, the first active layer 1112 has a cylindrical structure, and an end portion of the drain end of the first active layer 1112 of the cylindrical structure penetrates through the horizontal extension portion 11211. The cylindrical structure is understood to mean, among other things, a hollow bottomless structure.
Preferably, in the same memory device layer 100, the first active layer 1112 is all of a groove-shaped structure or all of a cylindrical structure, simplifying the manufacturing process.
Referring to fig. 6, the memory device 1000 includes a plurality of memory device layers 100, and the plurality of memory device layers 100 are vertically (in the Z-axis direction) stacked on a substrate 200. The memory device 1000 further includes an insulating spacer layer 160, where the insulating spacer layer 160 is disposed between two adjacent memory device layers 100.
The insulating isolation layer 160 is used for insulating and isolating adjacent memory device layers 100, so that short circuit between the adjacent memory device layers 100 is avoided, and read-write operations between the adjacent memory device layers 100 can be independently controlled. The insulating spacer 160 may be made of an insulating material such as silicon oxide SiO2, silicon nitride Si3N4, TEOS (Tetraethoxysilane), or a low dielectric constant material. Thus, by stacking a plurality of memory device layers 100 in the vertical direction to form the memory device 1000, the memory density per unit area can be improved.
It should be noted that, in the memory apparatus 1000 shown in fig. 6, each memory device layer 100 is a memory device layer 100 including a memory cell as shown in fig. 3a, but the present invention is not limited thereto, and the plurality of memory device layers 100 in the memory apparatus 1000 may be memory device layers 100 including a memory cell as shown in fig. 3a, or memory device layers 100 including a memory cell as shown in fig. 3b, or part of the memory device layers 100 in the plurality of memory device layers 100 in the memory apparatus 1000 may be memory device layers 100 including a memory cell as shown in fig. 3a, and part of the memory device layers 100 may be memory device layers 100 including a memory cell as shown in fig. 3b, and the insulating isolation layer 160 may be disposed between two adjacent memory device layers 100.
The first horizontal direction may be the same or different and the second horizontal direction may be the same or different in different memory device layers 100.
Referring to the embodiment shown in fig. 7a to 9, the memory device 1000 includes a plurality of memory device layers 100, a first active layer 1112 in at least one layer of the plurality of memory device layers 100 is in a groove structure, a bottom end of the groove structure contacts or is embedded into a horizontal extension 11211, that is, at least one memory device layer 100 is a memory device layer 100 including a memory cell as shown in fig. 3a, and a first active layer 1112 in at least another layer of the plurality of memory device layers 100 is in a cylindrical structure, an end portion of the cylindrical structure corresponding to a drain end of the first active layer 1112 penetrates through the horizontal extension 11211, that is, at least one memory device layer 100 is a memory device layer 100 including a memory cell as shown in fig. 3b, the plurality of memory device layers 100 are divided into at least one common unit 300 along a vertical direction, and the common unit 300 includes two memory device layers 100 adjacent in the vertical direction. In the common cell 300, the two adjacent memory device layers 100 share the write word line 120 as shown in fig. 7a, or the two adjacent memory device layers 100 share the read bit line 150 as shown in fig. 7 b.
Specifically, each of the common cells 300 may include at least two memory cells 110 disposed in mirror image in a vertical direction, and the two memory cells 110 share the same write word line 120 or read bit line 150. Compared with a memory structure in which the memory cells 110 are directly stacked in the horizontal and vertical directions, the design of the common cell 300 can reduce the number of one layer of write word lines 120 or read bit lines 150 without affecting the memory density of the memory device 1000, simplify the structure of the memory device 1000, reduce the production cost, and further improve the memory density of the memory device 1000.
It should be noted that, although the two memory cells 110 in the common unit 300 are arranged in a mirror image manner, the structures in the two memory cells 110 may not be identical, but may be arranged in a mirror image manner on the "functional structure", that is, the two memory cells 110 have corresponding structures, but the actual compositions of the corresponding structures are not necessarily identical, for example, the structures of the first active layers 1112 in the two writing transistors 111 may be different.
As illustrated in fig. 7a and 7b, the common unit 300 includes adjacent memory device layers 100 that share the write word line 120 or the write bit line 150, one memory device layer 100 is a memory device layer 100 including the memory cell illustrated in fig. 3a, the other memory device layer 100 is a memory device layer 100 including the memory cell illustrated in fig. 3b, the first active layer 1112 has a cylindrical structure, an end portion of the cylindrical structure corresponding to a drain end of the first active layer 1112 penetrates the horizontal extension 11211, and the two memory device layers 100 are disposed as mirror images of each other.
Referring to fig. 8, further, the memory device 1000 further includes an insulating spacer 160, wherein the insulating spacer 160 is disposed between the common unit 300 and the memory device layer 100 adjacent to the common unit 300. Illustratively, the common cells 300 are vertically stacked on the substrate 200 after the insulating spacers 160 are spaced apart from each other, and illustratively, the common cells 300 and the memory device layers 100 are vertically stacked on the substrate 200 after the insulating spacers 160 are spaced apart from each other.
The insulating isolation layer 160 is used for insulating and isolating the common unit 300 and the memory device layers 100 adjacent to the common unit 300, so that short circuits between the memory device layers 100 in the common unit 300 and the memory device layers 100 adjacent to the common unit 300, which are respectively located at two sides of the insulating isolation layer 160, are avoided, and the memory device layers 100 in the common unit 300 and the memory device layers 100 adjacent to the common unit 300 can be independently controlled and independently perform read-write operations. The insulating spacer 160 may be made of an insulating material such as silicon oxide SiO2, silicon nitride Si3N4, TEOS (Tetraethoxysilane), or a low dielectric constant material.
In addition, since the write transistor 111 and the read transistor 112 need to be connected to peripheral circuits to realize read/write control, the peripheral circuits need to be electrically connected to the write transistor 111 and the read transistor 112, that is, the peripheral circuits need to be electrically connected to the write word line 120, the write bit line 130, the read word line 140, and the read bit line 150.
Illustratively, the ends of the write word line 120, the write bit line 130, the read word line 140, and the read bit line 150 are formed in a stepped structure, and vertical vias are prepared to connect to the stepped structure, so that the signal lines (i.e., the write word line 120, the write bit line 130, the read word line 140, and the read bit line 150) of the memory device 1000 are led out, which facilitates the electrical connection of peripheral circuits.
In some embodiments, the peripheral circuits are disposed in the semiconductor substrate 201, but the present invention is not limited thereto, and the positions of the peripheral circuits may be specifically set according to actual needs.
Referring to fig. 9, the write word line 120 or the read bit line 150 is shared between the shared cell 300 and the memory device layer 100 adjacent to the shared cell 300, the read bit line 150 is shared between the shared cell 300 and then vertically stacked on the substrate 200, and the read bit line 150 is shared between the shared cell 300 and the memory device layer 100 adjacent to the shared cell 300 and then vertically stacked on the substrate 200.
In other embodiments, specifically, the common unit 300 may include two memory cells 110 adjacent in the vertical direction and disposed in mirror image, the two memory cells 110 share the read bit line 150, and two memory cells 110 respectively located in the adjacent two common units 300 adjacent in the vertical direction and disposed in mirror image share the write word line 120, or two memory cells 110 respectively located in the common unit 300 and the memory device layer 100 adjacent to the common unit 300 and disposed in mirror image in the vertical direction share the write word line 120.
Compared with the memory structure in which the memory cells 110 are directly stacked in the horizontal and vertical directions, the design of sharing the read bit lines 150 or the write word lines 120 between the shared cells 300 can reduce the number of one layer of write word lines 120 or read bit lines 150 without affecting the memory density of the memory device 1000, simplify the structure of the memory device 1000, reduce the production cost, and further improve the memory density of the memory device 1000.
The method for manufacturing the memory device 1000 according to the embodiment of the present invention is used for manufacturing the memory device 1000 according to any one of the above, and includes the following steps:
step S1, providing a first substrate 1.
Specifically, the first substrate 1 may be a temporary substrate or a substrate 200. The material of the temporary substrate is not specifically limited in the present invention, and if the first substrate 1 is the substrate 200, the substrate 200 is the same as the substrate 200 in the foregoing memory device 1000, and the technical contents such as the material and the structure are not repeated herein.
Step S2 is preparing at least one memory device layer 100 on the first surface 101 of the first substrate 1.
Namely, the memory device layer 100 in the memory device 1000 in the above-described embodiment is prepared on the above-described first substrate 1, and detailed processes will be described below. In some embodiments, the first substrate 1 is a substrate 200, and fabricating at least one memory device layer 100 on the first substrate 1 includes fabricating at least one memory device layer 100 on an insulating surface of the substrate 200, i.e., on a surface of the insulating layer 202 remote from the semiconductor substrate 201.
Step S3. The first substrate 1 is the substrate 200 in the above embodiment, the first surface 101 is the insulating surface of the substrate 200, or the memory device layer 100 formed in step S2 is transferred to the insulating surface of the substrate 200.
That is, the memory device layer 100 may be prepared on the substrate 200, or may be transferred onto the substrate 200 after forming a temporary substrate (i.e., the first substrate 1 as a temporary substrate). In some embodiments, transferring the memory device layer 100 formed in step S2 to the insulating surface of the substrate 200 includes transferring the memory device layer 100 onto the insulating layer 202 of the substrate 200. The method of transfer illustratively includes bonding, and the present invention is not particularly limited to the method of transfer.
Referring to fig. 10, further, the step S2 of preparing at least one memory device layer 100 on the first surface 101 may specifically include preparing at least one first memory device layer 100 on the first surface 101, and preparing at least one first memory device layer 100 may specifically include the following steps:
Referring to FIGS. 11 to 12c (FIG. 12B is a cross-sectional view of FIG. 12a, FIG. 12c is a cross-sectional view of FIG. 12a, B-B), step S21 sequentially preparing a first conductor layer 2, a first insulating layer 3 and a second conductor layer 4 on a first surface 101, performing a first patterning process to form a first gap penetrating the second conductor layer 4, the first insulating layer 3 and the first conductor layer 2 to form a read bit line 150, a second drain electrode 1125 and the first patterned conductor layer 5, preparing a first isolation insulating layer 6, and covering the upper surface of the first patterned conductor layer 5 with the first isolation insulating layer 6.
In some embodiments, preparing the first conductor layer 2 on the first surface 101 includes preparing the first conductor layer directly on the first surface 101.
In some embodiments, preparing the first conductor layer 2 on the first surface 101 includes preparing the insulating spacer 160 on the top surface of the topmost memory device layer 100 after preparing at least one memory device layer 100 on the first surface 101 of the first substrate 1, and then preparing the first conductor layer 2 on a surface of the insulating spacer 160 remote from the first substrate 1.
In some embodiments, preparing the first conductor layer 2 on the first surface 101 includes preparing at least one memory device layer 100 on the first surface 101 of the first substrate 1, preparing a conductor layer on which the read bit line 150 of the topmost memory device layer 100 is located.
The first conductor layer 2 and the second conductor layer 4 may include a layer of titanium nitride TiN, titanium Ti, gold Au, tungsten W, molybdenum Mo, aluminum Al, copper Cu, ruthenium Ru, silver Ag, platinum Pt, or the like, or a laminate of layers of the above materials, or a laminate of layers of any combination of the above materials. The materials of the first conductor layer 2 and the second conductor layer 4 may be the same or different.
The material of the first insulating layer 3 may be silicon oxide SiOx, silicon nitride SiNx, TEOS, a low dielectric constant material, or a combination material, a laminate material, or a combination laminate material of the above materials.
In some embodiments, the first conductive layer 2, the first insulating layer 3, and the second conductive layer 4 may be formed by chemical vapor deposition (Chemical Vapor Deposition, CVD), atomic layer deposition (Atomic Layer Deposition, ALD), physical vapor deposition (Physical Vapor Deposition, PVD), and the like. It will be appreciated that any suitable materials and deposition processes may be used to form the first insulating layer 3, the first conductor layer and the second conductor layer 4 described above.
In an embodiment of the present invention, the first patterning process includes etching, such as dry etching, wet etching, or an etching process combining dry etching and wet etching.
Referring to fig. 12b and 12c, the extending direction of the first slit is the X-axis direction, so that the first conductive layer 2 and the second conductive layer 4 are divided by the first slit into a plurality of read bit lines 150 and first patterned conductive layers 5 extending along the X-axis direction, the plurality of read bit lines 150 and the plurality of first patterned conductive layers 5 are respectively distributed on the respective layers at intervals along the Y-axis direction, the first patterned conductive layers 5 are used for subsequently forming the second gate electrode 1121, and in the front projection on the first substrate 1, opposite sides of the first patterned conductive layers 5 parallel to the extending direction of the read bit lines 150 overlap with opposite sides of the read bit lines 150. It is understood that the second drain electrode 1125 is part of the read bit line 150.
In one embodiment, the first isolation insulating layer 6 may be formed on the upper surface of the first patterned conductor layer 5 by deposition such as Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), physical Vapor Deposition (PVD), or the like.
The material of the first isolation insulating layer 6 may be silicon oxide SiOx, silicon nitride SiNx, TEOS, a low dielectric constant material, or a combination material, a laminated material, or a combined laminated material of the above materials.
In the embodiment of the present invention, the first isolation insulating layer 6 covers the upper surface of the first patterned conductor layer 5, and the thickness thereof can be adjusted to adjust the distance between the second gate electrode 1121 formed subsequently and the write bit line 130, thereby adjusting the channel length of the write transistor formed subsequently, and meeting different electrical requirements for the write transistor.
In some embodiments, the first isolation insulating layer 6 fills the first gap to improve the structural stability of the memory device layer 100.
In some embodiments, the first isolation insulating layer 6 does not fill the first gap, such that an air gap (not shown) is formed in the first gap, reducing cross-talk between adjacent conductors in the memory device layer 100.
It will be appreciated that the top of the air gap is below the upper surface of the first isolation insulating layer 6 to facilitate the performance of subsequent process steps. Preferably, the upper surface of the first isolation insulating layer 6 is flat.
Referring to fig. 13a and 13b (fig. 13b is a cross-sectional view taken along the direction C-C in fig. 13 a), step S22 is to form a first hole 7 penetrating the first isolation insulating layer 6, the first patterned conductor layer 5 and the first insulating layer 3, and sequentially form a second gate insulating layer 1123 and a second active layer 1122 on the sidewall of the first hole 7.
Wherein the first hole 7 is used to accommodate the second gate insulating layer 1123 and the second active layer 1122 of the read transistor 112, the first hole 7 may be formed by an etching process, such as a dry etching, a wet etching, or an etching process combining a dry etching and a wet etching.
Optionally, the first hole 7 is partially recessed into the upper surface of the read bit line 150, which reduces the difficulty of the etching process and reduces the contact resistance between the drain terminal of the read transistor and the second drain electrode 1125.
After the first hole 7 is formed, an insulating material is deposited on the bottom wall and the sidewall of the first hole 7 to form the second gate insulating layer 1123, where the deposition manner may be Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), physical Vapor Deposition (PVD), or the like, and the present invention is not limited thereto.
In the embodiment of the present invention, the insulating material for the second gate insulating layer 1123 may include silicon oxide, silicon nitride, TEOS, a high dielectric constant material, or the like, and the present invention is not particularly limited.
Thereafter, the insulating material at the bottom wall of the first hole 7 (i.e., the upper surface of the read bit line 150) is removed, and a semiconductor material is deposited on the surface of the second gate insulating layer 1123 to form a second active layer 1122, where the second active layer 1122 is electrically connected to the read bit line 150, and the second drain electrode 1125 includes a portion of the read bit line 150 opposite to the second active layer 1122.
In some embodiments, the second active layer 1122 and the second drain electrode 1125 are in direct contact to form an electrical connection, and in other embodiments, other conductor layers or doped semiconductor layers are disposed between the second active layer 1122 and the second drain electrode 1125, which is not particularly limited in the present invention.
The deposition method may be Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), physical Vapor Deposition (PVD), or the like. In some embodiments, after depositing the semiconductor material to form the second active layer 1122, the method further comprises the step of removing a portion of the semiconductor material layer outside the first hole 7.
The material of the second active layer 1122 includes an oxide semiconductor such as at least one of indium oxide In2O3, tin oxide SnO2, gallium oxide Ga2O3, indium tin oxide ITO, indium gallium zinc oxide IGZO, zinc oxide ZnO, and indium zinc oxide IZO.
In the embodiment of the present invention, the material of the second active layer 1122 is indium gallium zinc oxide IGZO.
In some embodiments, the second active layer 1122 is a hollow structure, such as a trench or a cylinder structure, and after the second active layer 1122 is formed, an insulating material is deposited in the hollow of the second active layer 1122 to fill the hollow, so that a dielectric layer is formed in the hollow, and the dielectric layer is the same as the above and will not be described herein.
Referring to fig. 14a, 14b and 14c (fig. 14b is a cross-sectional view of fig. 14a in the direction D-D, and fig. 14c is a cross-sectional view of fig. 14a in the direction E-E), step S23, preparing a third conductor layer on the upper surface of the first isolation insulating layer 6, performing a second patterning process to form a second gap penetrating the third conductor layer, and a third gap penetrating the third conductor layer, the first isolation insulating layer 6 and the first patterned conductor layer 5 to form a second gate electrode 1121, a write bit line 130, a read word line 140, a first source electrode 1114 and a second source electrode 1124, preparing a second isolation insulating layer 9, and covering the upper surface of the first source electrode 1114 with the second isolation insulating layer 9.
The material of the third conductor layer may be a layer of titanium nitride TiN, titanium Ti, gold Au, tungsten W, molybdenum Mo, aluminum Al, copper Cu, ruthenium Ru, silver Ag, platinum Pt, or a layer of the above materials, or a layer formed by any combination of the above materials, and the material of the third conductor layer may be the same as or different from any one of the first conductor layer 2 and the second conductor layer 4.
In one embodiment, the third conductive layer may be formed on the upper surface of the first isolation insulating layer 6 by Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), physical Vapor Deposition (PVD), or the like. It will be appreciated that any suitable materials and deposition processes may be used to prepare the third conductor layer described above.
In the embodiment of the present invention, the second patterning process may be etching, such as dry etching, wet etching, or an etching process combining dry etching and wet etching. The second patterning process forms a second gap and a third gap, the depths of the second gap and the third gap are different, and the penetrating film layers are different, and the second patterning process can be performed by two times of etching, or the second patterning process is performed in one time of etching through a gray scale mask or a laminated mask combination, and the invention is not limited in particular.
For example, the second patterning process may be performed in two etches, the first etch forming a second or third gap, filling the second or third gap with a layer of insulating material, the second etch forming a third or second gap, filling the third or second gap with a layer of insulating material, the layer of insulating material being formed as part of the second isolation insulating layer 9.
Referring to fig. 14a and 14b, the extending direction of the second slit formed is the Y-axis direction, penetrating the third conductor layer, and referring to fig. 14a to 14c, the extending direction of the third slit formed is the Y-axis direction, penetrating the third conductor layer, the first isolation insulating layer 6 and the first patterned conductor layer 5. The second and third slits divide the third conductor layer into write bit lines 130 and read word lines 140 which are stripe-shaped, extend in the Y-axis direction, and are spaced apart in the X-axis direction, and the third slit also divides the first patterned conductor layer 5 into a plurality of second gate electrodes 1121 at intervals.
In addition, in the front projection on the substrate 200, opposite sides of the second gate electrode 1121 parallel to the extending direction of the read bit line 150 overlap with opposite sides of the read bit line 150, and opposite sides of the second gate electrode 1121 parallel to the extending direction of the write bit line 130 and the read word line 140 overlap with sides of the write bit line 130 and the read word line 140, respectively, which overlap with the second gate electrode 1121.
Preferably, the second slit extends into a partial depth of the first isolation insulating layer 6, and the third slit extends into a partial depth of the first insulating layer 3, so as to improve reliability of patterning the third conductor layer and the first patterned conductor layer 5 to be disconnected, and reduce difficulty of etching process.
The second gate electrode 1121 is located under the write bit line 130 and the read word line 140, and the plurality of second gate electrodes 1121 are arranged in an array in the X-axis and the Y-axis. The first source electrode 1114 and the second source electrode 1124 are respectively located on the write bit line 130 and the read word line 140, and are a part of the write bit line 130 and the read word line 140.
At this time, the second active layer 1122, the second gate insulating layer 1123, the second gate electrode 1121, the second source electrode 1124, and the second drain electrode 1125 together constitute the read transistor 112.
In one embodiment, the second isolation insulating layer 9 covering the upper surface of the first source electrode 1114 may be formed by deposition such as Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), physical Vapor Deposition (PVD), or the like.
The material of the second isolation insulating layer 9 may be silicon oxide SiOx, silicon nitride SiNx, TEOS, a low dielectric constant material, or a combination material, a laminated material, or a combined laminated material of the above materials. In some embodiments, the second isolation insulating layer 9 does not fill the second gap, such that an air gap (not shown) is formed in the second gap, reducing cross-talk between adjacent conductors in the memory device layer 100. It will be appreciated that the top of the air gap is below the upper surface of the second isolation insulating layer 9 to facilitate the subsequent process steps. Preferably, the upper surface of the second isolation insulating layer 9 is flat.
Referring to fig. 15a and 15b (fig. 15b is a cross-sectional view of fig. 15a in the direction F-F), step S24 is to form a second hole 10 penetrating the second isolation insulating layer 9, the first source electrode 1114 and the first isolation insulating layer 6, and sequentially form a first active layer 1112, a first gate insulating layer 1113 and a first gate electrode 1111 on the sidewall of the second hole 10.
The second hole 10 is used to accommodate the first active layer 1112, the first gate insulating layer 1113, and the first gate electrode 1111 of the writing transistor 111, and the second hole 10 may be formed by an etching process, such as a dry etching process, a wet etching process, or an etching process combining a dry etching process and a wet etching process. The depth of the second hole 10 reaches at least the second gate electrode 1121.
Preferably, the second hole 10 is sunk into a part of the depth of the second gate electrode 1121, so as to increase the contact area between the drain end of the first active layer 1112 and the second gate electrode 1121, reduce the connection resistance between the drain end of the first active layer 1112 and the second gate electrode 1121, and reduce the difficulty of the etching process of the second hole 10.
After the second hole 10 is formed, the first active layer 1112, the first gate insulating layer 1113, and the first gate electrode 1111 are sequentially deposited on the sidewall of the second hole 10, where the deposition methods may be Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), physical Vapor Deposition (PVD), or the like.
Illustratively, a semiconductor material layer is deposited in the second hole 10, a portion of the semiconductor material layer outside the second hole 10 is removed to form a first active layer 1112, an insulating material and a conductive material layer are sequentially deposited in the second hole 10, a patterning process is performed to form a first gate insulating layer 1113 and a first gate electrode 1111, an insulating material layer is deposited and a planarization process is performed such that the first gate electrode 1111 is exposed, and the remaining insulating material layer is formed as a portion of the second insulating isolation layer 9, resulting in the structure shown in fig. 15 a.
The material of the first active layer 1112 may include an oxide semiconductor such as at least one of indium oxide In2O3, tin oxide SnO2, gallium oxide Ga2O3, indium tin oxide ITO, indium gallium zinc oxide IGZO, zinc ZnO, indium zinc oxide IZO.
In the embodiment of the present invention, the material of the first active layer 1112 is indium gallium zinc oxide IGZO.
In the embodiment of the present invention, the material of the first gate insulating layer 1113 may be silicon oxide, silicon nitride, TEOS, or a high dielectric constant material, which is not limited in particular.
In an embodiment of the present invention, the material of the first gate electrode 1111 may be a material having conductivity, for example, a layer of titanium nitride TiN, titanium Ti, gold Au, tungsten W, molybdenum Mo, indium TiN Oxide (ITO), indium Zinc Oxide (IZO), copper Cu, ruthenium Ru, silver Ag, platinum Pt, or the like, or a stack of layers of the above materials, or a stack of layers of any combination of the above materials.
At this time, the first active layer 1112 is electrically connected to the write bit line 130 and the second gate electrode 1211, and the first source electrode 1114 includes a portion of the write bit line 130 opposite to the first active layer 1112.
In some embodiments, direct contact between first active layer 1112 and first source electrode 1114 forms an electrical connection.
In other embodiments, other conductive layers or doped semiconductor layers are disposed between the first active layer 1112 and the first source electrode 1114, and the present invention is not limited thereto.
In some embodiments, direct contact between the first active layer 1112 and the second gate electrode 1211 forms an electrical connection.
In other embodiments, other conductive layers or doped semiconductor layers are disposed between the first active layer 1112 and the second gate electrode 1211, and the present invention is not particularly limited.
In the embodiment of the present invention, the first gate electrode 1111, the first gate insulating layer 1113, the first active layer 1112, and the first source electrode 1114 together constitute the writing transistor 111.
As shown in fig. 15a, the first gate insulating layer 1113 and the first active layer 1112 have a bottom groove structure, so that the first active layer 1112 has a larger contact area and a smaller contact resistance with the horizontal extension portion 11211.
In some embodiments, the first gate insulating layer 1113 and the first active layer 1112 have a bottomless cylindrical structure, so that the first gate insulating layer 1113 is located between the first active layer 1112 and the first gate electrode 1111, and between the first gate electrode 1111 and the second gate electrode 1121.
In some embodiments, the first gate electrode 1111 is a hollow structure, such as a trench or a cylinder structure, and after the second active layer 1122 is formed, an insulating material is deposited in the hollow of the first gate electrode 1111 to fill the hollow, thereby forming a dielectric layer in the hollow, and the dielectric layer is the same as the above and will not be described herein.
Referring to fig. 16a and 16b (fig. 16b is a cross-sectional view of fig. 16a in the direction G-G), step S25 is to prepare a fourth conductive layer and perform a third patterning process on the fourth conductive layer to form a write word line 120, wherein the write word line 120 is isolated from a read word line 140.
The material of the fourth conductor layer may be a layer of titanium nitride TiN, titanium Ti, gold Au, tungsten W, molybdenum Mo, aluminum Al, copper Cu, ruthenium Ru, silver Ag, platinum Pt, or a laminate of layers of the above materials, or a laminate of layers formed by any combination of the above materials. The fourth conductor layer may be the same or different from the other conductor layers.
In one embodiment, the fourth conductive layer may be formed on the upper surface of the first isolation insulating layer 6 by Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), physical Vapor Deposition (PVD), or the like. It will be appreciated that any suitable materials and deposition processes may be used to prepare the fourth conductor layer described above.
In the embodiment of the present invention, the third patterning process may be etching, such as dry etching, wet etching, or an etching process combining dry etching and wet etching. Referring to fig. 16b, the fourth conductor layer is etched through a third patterning process to form write word lines 120 in a stripe shape extending in the X-axis direction, and the plurality of write word lines 120 are spaced apart in the Y-axis direction. Optionally, after the third patterning process etches the fourth conductor layer to form the write word lines 120, there is a further step of preparing an insulating spacer 160, the insulating spacer 160 filling at least between adjacent write word lines 120.
Further, in step S22, forming the second gate insulating layer 1123 and the second active layer 1122 on the sidewall of the first hole 7 in this order includes the following steps:
In step S221, a second gate insulating layer 1123 material is deposited, the second gate insulating layer 1123 material covers the upper surface of the first isolation insulating layer 6, the side walls and the bottom surface of the first hole 7, and anisotropic etching is performed to remove the portion of the second gate insulating layer 1123 material located on the upper surface of the first isolation insulating layer 6 and the bottom surface of the first hole 7, thereby forming a second gate insulating layer 1123 located on the side walls of the first hole 7.
Specifically, the second active layer 1122 in the embodiment of the present invention is formed in the inner wall of the second gate insulating layer 1123, so that the second gate insulating layer 1123 needs to be first prepared into a cylindrical structure, then the second gate insulating layer 1123 deposited on the bottom surface of the first hole 7 needs to be removed, the removal process is anisotropic etching, preferably, the second gate insulating layer 1123 deposited on the bottom surface of the first hole 7 is removed simultaneously with the second gate insulating layer 1123 deposited on the upper surface of the first isolation insulating layer 6, and the second gate insulating layer 1123 formed on the sidewall of the first hole 7 after the removal is a cylindrical structure.
The detailed deposition process and the material of the second gate insulating layer 1123 may be referred to the description in step S2 above, and will not be described herein.
In step S222, the second active layer 1122 is filled in the trench defined by the sidewall of the second gate insulating layer 1123 and the bottom surface of the first hole 7, and the second active layer 1122 is etched back until the top surface of the second active layer 1122 is lower than the upper surface of the first isolation insulating layer 6, thereby forming the second active layer 1122.
After the second gate insulating layer 1123 having a cylindrical shape is prepared, a material for filling the second active layer 1122 is deposited in a space surrounded by the second gate insulating layer 1123, and at this time, the material for the second active layer 1122 is etched by etching back until the top surface thereof is lower than the upper surface of the first isolation insulating layer 6, so that the second active layer 1122 in the embodiment shown in fig. 5a is prepared, and thus, the channel length of the read transistor 112 can be adjusted according to the depth of etching back.
In some embodiments, the material of the second active layer 1122 is etched back and the material of the second gate insulating layer 1123 is also etched back, so that the top surfaces of the second gate insulating layer 1123 and the second active layer 1122 are formed below the upper surface of the first isolation insulating layer 6.
The material of the second active layer 1122 can be referred to the description in step S2, and will not be described herein.
Referring to fig. 17, further, the step S2 of preparing at least one memory device layer 100 on the first surface 101 may specifically include preparing at least one first memory device layer 100 on the first surface 101, and preparing at least one first memory device layer 100 may specifically further include the steps of:
Referring to fig. 18 to 23b, step S26 is to prepare the first conductor layer 2 and perform a first patterning process on the first conductor layer 2 to form the write word line 120, prepare the first insulating layer 3 to cover the write word line 120, prepare the second conductor layer 4 on the surface of the first insulating layer 3 far from the write word line 120, and perform a second patterning process to form the write bit line 130, the read word line 140, the first source electrode 1114 and the second source electrode 1124, and prepare the first isolation insulating layer 6 to cover the write bit line 130, the read word line 140, the first source electrode 1114 and the second source electrode 1124.
Illustratively, preparing the first conductor layer 2 includes preparing the first conductor layer 2 on the first surface 101 of the first substrate 1, as shown in fig. 18, which is taken as an example for simplicity of illustration in this embodiment.
In some embodiments, preparing the first conductor layer 2 on the first surface 101 includes preparing the first conductor layer directly on the first surface 101.
In some embodiments, preparing the first conductor layer 2 on the first surface 101 includes preparing the insulating spacer 160 on the top surface of the topmost memory device layer 100 after preparing at least one memory device layer 100 on the first surface 101 of the first substrate 1, and then preparing the first conductor layer 2 on a surface of the insulating spacer 160 remote from the first substrate 1.
In some embodiments, fabricating the first conductor layer 2 on the first surface 101 includes fabricating at least one memory device layer 100 on the first surface 101 of the first substrate 1, fabricating a conductor layer on which the write word line 120 of the topmost memory device layer 100 resides.
The materials of the first conductor layer 2 and the second conductor layer 4 may be titanium nitride TiN, titanium Ti, gold Au, tungsten W, molybdenum Mo, aluminum Al, copper Cu, ruthenium Ru, silver Ag, platinum Pt, or a laminate of the above materials, or a laminate of any combination of the above materials.
The material of the first insulating layer 3 may be silicon oxide SiOx, silicon nitride SiNx, TEOS, a low dielectric constant material, or a combination material, a laminate material, or a combination laminate material of the above materials. Gaps exist between adjacent write word lines 120, and in some embodiments, the first insulating layer 3 fills the gaps to improve the structural stability of the memory device layer 100.
In some embodiments, the first insulating layer 3 does not fill the gaps, such that air gaps (not shown) are formed in the gaps, reducing cross-talk between adjacent conductors in the memory device layer 100. It will be appreciated that the top of the air gap is below the upper surface of the first insulating layer 3 to facilitate the performance of subsequent process steps. Preferably, the upper surface of the first insulating layer 3 is flat.
In one embodiment, the first insulating layer 3, the first conductive layer 2, and the second conductive layer 4 may be formed by Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), physical Vapor Deposition (PVD), or the like.
It will be appreciated that any suitable materials and deposition processes may be used to form the first insulating layer 3, the first conductor layer 2 and the second conductor layer 4, respectively, and that the materials of the first conductor layer 2 and the second conductor layer 4 may be the same or different.
In the embodiment of the present invention, the first patterning process and the second patterning process may be etching processes, such as dry etching, wet etching, or a combination of dry etching and wet etching.
As shown in fig. 20b (fig. 20b is a schematic cross-sectional view in the H-H direction in fig. 20 a), the first conductor layer 2 is divided into a plurality of write word lines 120 extending in the X-axis direction in a stripe shape by a first patterning process, and the plurality of write word lines 120 are distributed at intervals in the Y-axis direction.
As shown in fig. 23b (fig. 23b is a schematic cross-sectional view of the I-I direction in fig. 23 a), the second conductor layer 4 is divided into a plurality of write bit lines 130 and read bit lines 150 extending along the Y-axis direction in a stripe shape by a second patterning process, and the plurality of write bit lines 130 and the plurality of read bit lines 150 are distributed at intervals along the X-axis direction. The first source electrode 1114 is located above the write bit line 130 and is part of the write bit line 130. The second source electrode 1124 is on the read word line 140 and is a portion of the read word line 140.
In one embodiment, the first isolation insulating layer 6 may be formed by Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), physical Vapor Deposition (PVD), or the like.
The material of the first isolation insulating layer 6 may be silicon oxide SiOx, silicon nitride SiNx, TEOS, a low dielectric constant material, or a combination material, a laminated material, or a combined laminated material of the above materials.
Gaps exist between any adjacent write bit line 130, read bit line 150, and in some embodiments, the first isolation insulating layer 6 fills the gaps to improve the structural stability of the memory device layer 100.
In some embodiments, the first isolation insulating layer 6 does not fill the gaps, such that air gaps (not shown) are formed in the gaps, reducing cross-talk between adjacent conductors in the memory device layer 100. It will be appreciated that the top of the air gap is below the upper surface of the first isolation insulating layer 6 to facilitate the performance of subsequent process steps. Preferably, the upper surface of the first isolation insulating layer 6 is flat.
Referring to FIGS. 24 to 29b, step S27 is to prepare a third conductor layer 8 on the surface of the first isolation insulating layer 6 away from the write word line 120;
Performing a third patterning process on the third conductor layer 8 to form a second patterned conductor layer 12, the second patterned conductor layer 12 overlapping with the orthographic projections of the first source electrode 1114 and the second source electrode 1124 on the first substrate 1;
A third hole 13 penetrating the second patterned conductor layer 12 or the third conductor layer 8, the first isolation insulating layer 6, and the first source electrode 1114 is formed, a first active layer 1112 is formed on a sidewall of the third hole 13, a fourth hole 14 extending from an upper surface of the second patterned conductor layer 12 or the third conductor layer 8 to a bottom of the third hole 13 to expose the write word line 120 is formed, and a first gate insulating layer 1113 and a first gate electrode 1111 connected to the write word line 120 are sequentially formed on a sidewall of the fourth hole 14.
It should be noted that the sequence of the above-mentioned partial steps in step S27 may be exchanged, that is, "the step of performing the third patterning process on the third conductor layer 8 to form the second patterned conductor layer 12" and "the step of forming the third hole 13 to form the first gate electrode 1111" may be exchanged, so that the above-mentioned preparation steps are written as "forming the third hole 13 penetrating the second patterned conductor layer 12 or the third conductor layer 8, the first isolation insulating layer 6, the first source electrode 1114" and "forming the fourth hole 14 extending from the upper surface of the second patterned conductor layer 12 or the third conductor layer 8 to penetrate the bottom of the third hole 13 and exposing the write word line 120".
If the order of the steps is changed, that is, the steps of forming the third hole 13 and the fourth hole 14 are before the step of forming the second patterned conductor layer 12, the above preparation steps are actually "forming the third hole 13 extending through the third conductor layer 8, the first isolation insulating layer 6, the first source electrode 1114" and "forming the fourth hole 14 extending from the upper surface of the third conductor layer 8 to the bottom of the third hole 13 exposing the write word line 120" and, if the above preparation steps are in the order of the preparation provided above, the above preparation steps are actually "forming the third hole 13 extending through the second patterned conductor layer 12, the first isolation insulating layer 6, the first source electrode 1114" and "forming the fourth hole 14 extending from the upper surface of the second patterned conductor layer 12 to the bottom of the third hole 13 exposing the write word line 120".
For convenience of description, the steps for forming the second patterned conductor layer 12 are described earlier below.
The material of the third conductor layer 8 may be a layer of titanium nitride TiN, titanium Ti, gold Au, tungsten W, molybdenum Mo, aluminum Al, copper Cu, ruthenium Ru, silver Ag, platinum Pt, or a layer of the above materials, or a layer formed by any combination of the above materials, and the material of the third conductor layer 8 may be the same as or different from any one of the first conductor layer 2 and the second conductor layer 4.
In one embodiment, the third conductive layer 8 may be formed on the upper surface of the first isolation insulating layer 6 by Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), physical Vapor Deposition (PVD), or the like.
It will be appreciated that any suitable materials and deposition processes may be used to prepare the third conductor layer 8 described above.
In the embodiment of the present invention, the third patterning process may be etching, such as dry etching, wet etching, or an etching process combining dry etching and wet etching.
The second patterned conductor layer 12 is used to form a subsequent second gate electrode 1121 (including the horizontal extension 11211), and thus the second patterned conductor layer 12 overlaps with the orthographic projections of the first source electrode 1114 and the second source electrode 1124 on the first substrate 1, so that the subsequently formed second gate electrode 1121 can cover the area between the two including the write bit line 130 and the read word line 140 on the orthographic projection, whereby the write transistor 111 and the read transistor of the vertical channel can be prepared in a subsequent process step.
Optionally, after the second patterned conductor layer 12 is formed, a spacer insulating layer 15 is prepared, as shown in fig. 25 and fig. 29b (fig. 29b is a schematic cross-sectional view in the J-J direction in fig. 29 a), where the second patterned conductor layer 12 extends along the Y-axis direction and is arranged at intervals along the X-axis direction, and the spacer insulating layer 15 is at least filled between adjacent patterned conductor layers 12.
Referring to fig. 26, the third hole 13 extends vertically downward from the surface of the second patterned conductor layer 12 to penetrate the first source electrode 1114, that is, the third hole 13 penetrates the second patterned conductor layer 12 and the write bit line 130, and when the first active layer 1112 is formed by deposition on the sidewall of the third hole 13, contact connection between the first active layer 1112 and the write word line 120, that is, contact connection between the first active layer 1112 and the first source electrode 1114 is achieved, as shown in fig. 27.
In the embodiment of the present invention, the third hole 13 may be formed by etching, such as dry etching, wet etching, or an etching process in which dry etching and wet etching are combined. Preferably, the third hole 13 extends to a partial depth of the first insulating layer 3 to reduce difficulty of the etching process.
In an embodiment of the present invention, the first active layer 1112 is formed by a deposition process, such as Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), physical Vapor Deposition (PVD), and the like.
Then, a fourth hole 14 penetrating down to the surface of the write word line 120 is formed by etching down at the bottom of the first active layer 1112, i.e., the bottom of the third hole 13, to obtain the structure shown in fig. 28, and the first gate insulating layer 1113 and the first gate electrode 1111 are sequentially deposited in the fourth hole 14, so that the first gate electrode 1111 can be directly connected to the write word line 120, and the third hole 13 penetrates the write bit line 130 and the first gate insulating layer 1113 is prepared along the wall of the fourth hole 14, thereby avoiding shorting of the first gate electrode 1111 and the write bit line 130, as shown in fig. 29 a.
In the embodiment of the present invention, the fourth hole 14 may be formed by etching, such as dry etching, wet etching, or an etching process in which dry etching and wet etching are combined.
In the embodiment of the present invention, the first gate insulating layer 1113 and the first gate electrode 1111 may be formed by a deposition process, such as Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), physical Vapor Deposition (PVD), and the like.
The material of the first gate insulating layer 1113 may be silicon oxide SiOx, silicon nitride SiNx, aluminum oxide Al2O3, hafnium oxide HfO2, zirconium dioxide ZrO2, titanium dioxide TiO2, yttrium oxide Y2O3, or a combination material, a stacked material, or a combined stacked material of the above materials, or may be TEOS.
The material of the first gate electrode 1111 may be a conductive material, such as titanium nitride TiN, titanium Ti, gold Au, tungsten W, molybdenum Mo, indium TiN Oxide (ITO), indium Zinc Oxide (IZO), copper Cu, ruthenium Ru, silver Ag, platinum Pt, or any combination thereof.
In the embodiment of the present invention, the third hole 13 is configured to accommodate the first gate electrode 1111, the first gate insulating layer 1113, and the first active layer 1112 of the writing transistor 111, and the first gate electrode 1111, the first gate insulating layer 1113, the first active layer 1112, and the first source electrode 1114 form the writing transistor 111.
Referring to fig. 30 to 32, in step S28, a second insulating layer 16 is formed to cover the second patterned conductive layer 12 and the first gate electrode 1111, a fifth hole 17 is formed to penetrate the second insulating layer 16, the second patterned conductive layer 12, the first isolation insulating layer 6 and expose the second source electrode 1124, and a second gate insulating layer 1123 and a second active layer 1122 connected to the second source electrode 1124 are sequentially formed on the sidewall of the fifth hole 17.
The second insulating layer 16 may be formed by a deposition process, such as Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), physical Vapor Deposition (PVD), and the like. In some embodiments, the coupling between the read bit line 150 and the second gate electrode 1121 may be reduced by increasing the thickness of the second insulating layer 16.
The material of the second insulating layer 16 may be silicon oxide SiOx, silicon nitride SiNx, TEOS, a low dielectric constant material, or a combination material, a laminate material, or a combination laminate material of the above materials.
In the embodiment of the present invention, the fifth hole 17 is for accommodating the second active layer 1122 and the second gate insulating layer 1123 of the read transistor 112, and preferably, the fifth hole 17 extends into a partial depth of the second source electrode 1124. The fifth hole 17 may be formed by etching, such as dry etching, wet etching, or an etching process in which dry etching and wet etching are combined.
In an embodiment of the present invention, the second gate insulating layer 1123 and the second active layer 1122 may be formed by a deposition process, such as Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), physical Vapor Deposition (PVD), and the like. When the second active layer 1122 is deposited on the sidewall of the fifth hole 17, the second active layer 1122 may directly form a contact connection with the second source electrode 1124 at the bottom end of the fifth hole 17.
The material of the second active layer 1122 includes an oxide semiconductor, such as at least one of indium oxide In2O3, tin oxide SnO2, gallium oxide Ga2O3, indium tin oxide ITO, indium gallium zinc oxide IGZO, indium gallium tin oxide ITZO, and zinc oxide ZnO.
In the embodiment of the present invention, the material of the second active layer 1122 is indium gallium zinc oxide IGZO.
The material of the second gate insulating layer 1123 may be a material such as silicon oxide SiOx, silicon nitride SiNx, aluminum oxide Al2O3, hafnium oxide HfO2, zirconium dioxide ZrO2, titanium dioxide TiO2, or yttrium oxide Y2O3, or a combination material, a stacked material, or a combined stacked material of the above materials, or may be TEOS.
Referring to FIGS. 33 to 34c (FIG. 34b is a schematic cross-sectional view of the K-K direction in FIG. 34a, and FIG. 34c is a schematic cross-sectional view of the L-L direction in FIG. 34 a), step S29 is to form a fourth conductive layer 11 on the side of the second insulating layer 16 away from the write word line 120, and perform a third patterning process to form a fourth gap penetrating the fourth conductive layer 11, the second insulating layer 16, and the second patterned conductive layer 12 to form a read bit line 150 and a second gate electrode 1121.
Referring to fig. 34a to 34c, an insulating spacer 160 may be optionally filled in the fourth gap.
The material of the fourth conductor layer 11 may be titanium nitride TiN, titanium Ti, gold Au, tungsten W, molybdenum Mo, aluminum Al, copper Cu, ruthenium Ru, silver Ag, platinum Pt, or any combination thereof.
In one embodiment, the fourth conductive layer 11 may be formed by Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), physical Vapor Deposition (PVD), or the like.
It will be appreciated that any suitable materials and deposition processes may be used to prepare the fourth conductor layer 11 described above.
In the embodiment of the present invention, the third patterning process may be etching, such as dry etching, wet etching, or an etching process combining dry etching and wet etching.
The extending direction of the fourth slit formed through the third patterning process is the X-axis direction, the fourth conductor layer 11 is divided into a plurality of read bit lines 150 which are stripe-shaped and extend along the X-axis direction, as shown in fig. 34b, and the second patterned conductor layer 12 is divided into a plurality of second gate electrodes 1121 at intervals, and the plurality of second gate electrodes 1121 are distributed in an array along X, Y directions, as shown in fig. 34 c.
In addition, in the front projection on the substrate 200, opposite sides of the second gate electrode 1121 parallel to the extending direction of the read bit line 150 overlap opposite sides of the read bit line 150.
The portion of the read bit line 150 in contact with the second gate electrode 1121 is a second drain electrode 1125.
At this time, the second active layer 1122, the second gate insulating layer 1123, the second gate electrode 1121, the second source electrode 1124, and the second drain electrode 1125 together constitute the read transistor 112.
In some embodiments, part of the order of steps in the above method may be reversed.
For example, referring to fig. 21, the second conductor layer 4 is formed, the patterning process is performed such that the second conductor layer 4 is formed as a third patterned conductor layer extending in the Y-axis direction, a fifth slit extending in the Y-axis direction is formed between adjacent third patterned conductor layers, the first isolation insulating layer 6 is formed to fill the fifth slit and cover the third patterned conductor layer, the third conductor layer 8 is formed over the first isolation insulating layer 6, the patterning is performed such that the third conductor layer 8 is formed as a second patterned conductor layer 12, a sixth slit is formed between adjacent second patterned conductor layers 12, the sixth slit extends in the Y-axis direction, and the sixth slit also penetrates the first isolation insulating layer 6 and the third patterned conductor layer, the fifth slit, the sixth slit such that the second conductor layer 4 is patterned to form the write bit line 130 and the read word line 140. Optionally, the spacer insulating layer 15 fills the sixth gap. Thus, the difficulty of the patterning process can be reduced.
In this embodiment, opposite sides of the second gate electrode 1121 extending in the second horizontal direction overlap sides of the write bit line 130 and the read word line 140 overlapping the second gate electrode 1121 on the front projection of the first substrate 1.
Further, in step S28, forming the second gate insulating layer 1123 and the second active layer 1122 connected to the second source electrode 1124 in sequence on the sidewall of the fifth hole 17 includes the following steps:
In step S281, a second gate insulating layer 1123 is deposited, the second gate insulating layer 1123 covers the upper surface of the second insulating layer 16, the sidewalls and bottom surface of the fifth hole 17, and anisotropic etching is performed to remove the portion of the second gate insulating layer 1123 material on the upper surface of the second insulating layer 16 and on the bottom surface of the fifth hole 17, thereby forming a second gate insulating layer 1123 on the sidewalls of the fifth hole 17.
Specifically, the second active layer 1122 in the embodiment of the present invention is formed in the inner wall of the second gate insulating layer 1123, so that the second gate insulating layer 1123 needs to be first prepared into a cylindrical structure, the second gate insulating layer 1123 deposited on the bottom surface of the fifth hole 17 needs to be removed, the removal process is anisotropic etching removal, preferably, the second gate insulating layer 1123 deposited on the bottom surface of the fifth hole 17 is removed simultaneously with the second gate insulating layer 1123 deposited on the upper surface of the first isolation insulating layer 6, and the second gate insulating layer 1123 formed on the sidewall of the fifth hole 17 after the removal is a cylindrical structure.
The detailed deposition manner and the material of the second gate insulating layer 1123 may be referred to the description in step S2 above, and will not be described herein. The advantages of the cylindrical second active layer 1122 are described above and will not be described herein.
In step S282, the second active layer 1122 is filled in the trench defined by the sidewall of the second gate insulating layer 1123 and the bottom surface of the fifth hole 17, and the second active layer 1122 is etched back until the top surface of the second active layer 1122 is lower than the upper surface of the second insulating layer 16, thereby forming a second active layer 1122.
After the second gate insulating layer 1123 having a cylindrical shape is prepared, a material for filling the second active layer 1122 is deposited in a space surrounded by the second gate insulating layer 1123, and at this time, the material for the second active layer 1122 is etched by etching back until the top surface thereof is lower than the upper surface of the second insulating layer 16, so as to obtain the second active layer 1122 in the embodiment shown in fig. 5b, thereby adjusting the channel length of the read transistor 112 according to the depth of etching back.
In some embodiments, the second active layer 1122 material is etched back while also etching back the second gate insulating layer 1123 material such that both the second gate insulating layer 1123 and the second active layer 1122 top surface are formed below the upper surface of the second insulating layer 16.
The material of the second active layer 1122 can be referred to the description in step S2, and will not be described herein. The advantages of the cylindrical second active layer 1122 are described above and will not be described herein.
Referring to the circuit schematic of the memory cell 110, the write word line 120, the write bit line 130, the read word line 140, and the read bit line 150 connections shown in FIG. 35:
The step of performing a write operation on the memory cell 110 according to an embodiment of the present invention may include applying a voltage to the write word line 120 such that the write transistor 111 is turned on, and applying a voltage to the write bit line 130 to charge the storage node SN such that the storage node SN exhibits a high voltage or a low voltage representing data 1 and 0, respectively;
The step of performing a read operation on the memory cell 110 according to an embodiment of the present invention may include applying a voltage to the read word line 140 to provide a voltage signal to the second source electrode 1124 electrically connected to the read word line 140 when reading "1", wherein a current passes between the read bit line 150 and the read word line 140 due to a certain charge in the read bit line 150, and performing a read operation on the read bit line 150 by detecting the magnitude of the current in the read bit line 150, and applying a read voltage to the read word line 140 in the read transistor when reading "0", wherein no current passes between the read bit line 150 and the read word line 140 or a small current passes between the read bit line 150 due to no charge in the read bit line SN, thereby completing a read process of data 0.
In the description of the present specification, the descriptions of the terms "embodiment one", "embodiment two", and the like, mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.