Detailed Description
Embodiments of the present application will be described in further detail below with reference to the drawings and examples. It should be understood that the particular embodiments described herein are illustrative only and are not limiting of embodiments of the application. It should be further noted that, for convenience of description, only some, but not all structures related to the embodiments of the present application are shown in the drawings, and those skilled in the art will appreciate that any combination of technical features may constitute alternative embodiments as long as the technical features are not contradictory to each other after reading the present specification.
The terms first, second and the like in the description and in the claims, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, as appropriate, such that embodiments of the present application may be implemented in sequences other than those illustrated or described herein, and that the objects identified by "first," "second," etc. are generally of a type and not limited to the number of objects, e.g., the first object may be one or more. Furthermore, in the description and claims, "and/or" means at least one of the connected objects, and the character "/" generally means a relationship in which the associated object is an "or" before and after. In the description of the present application, "a plurality" means two or more, and "a number" means one or more.
In the current edge gateway design, the stability and reliability of the power supply system are key factors for ensuring continuous and stable operation of the equipment. However, existing power supply designs often suffer from the major problems of inadequate power supply stability, lack of automatic switching mechanisms, and limited voltage adaptability. Despite the above drawbacks, there are also some prior art attempts to improve the stability and reliability of power supplies in different ways. For example, some schemes employ a dual power backup design, i.e., adding a backup power source in addition to the primary power source. However, these schemes often do not implement a truly automatic switching mechanism, or the switching speed is slow, and power cannot be quickly restored at critical times. In addition, some schemes improve the voltage conversion efficiency and stability of the power supply by optimizing the power supply conversion circuit. However, these schemes generally only improve the power performance to a certain extent, but cannot fundamentally solve the problems of insufficient power stability and lack of an automatic switching mechanism.
In this regard, the present application provides a gateway power circuit, which may be applied to an edge gateway device to solve the problem of poor stability of the edge gateway device. It is conceivable that the edge gateway device is connected to a main power supply and a secondary power supply, and for this purpose, the gateway power supply circuit is used to connect to the main power supply and the secondary power supply, so that the gateway power supply circuit of the present application can track the working state of the main power supply in real time by integrating a high-precision real-time monitoring technology and an intelligent switching logic. Once an abnormal or fault signal of the main power supply is detected, an automatic switching mechanism is immediately started and is seamlessly transited to a secondary power supply mode or other power supply modes, so that the continuity and stability of power supply of the system are ensured, and data loss and service interruption are avoided.
Fig. 1 is a schematic structural diagram of a gateway power circuit according to an embodiment of the present application, where the gateway power circuit includes a main power access module 110, a power switching module 120, a power-down protection module 130, and a power output module 140. The input end of the main power supply access module 110 is used for accessing a main power supply to step down the main power supply, the output end of the main power supply access module 110 is connected with the first input end of the power supply switching module 120, the second input end of the power supply switching module 120 is used for accessing a secondary power supply, and the power supply switching module 120 is used for outputting one path of power supply voltage under the condition of accessing the main power supply and/or the secondary power supply. It is conceivable that although the power switching module 120 can switch in two voltages provided by the main power supply and the auxiliary power supply, the power switching module 120 only provides one voltage signal for the subsequent circuit, that is, can switch to the auxiliary power supply when the main power supply is abnormal, so as to supply power to the edge gateway device.
In addition, the power-down protection module 130 includes a power-down detection unit 131, a logic control unit 132, and a capacitor power supply unit 133, where a detection end of the power-down detection unit 131 is connected to an output end of the power supply switching module 120, an output end of the power-down detection unit 131 is connected to a signal access end of the logic control unit 132, a control output end of the logic control unit 132 is connected to a power supply control end of the capacitor power supply unit 133, a power supply access end of the capacitor power supply unit 133 is further connected to an output end of the power supply switching module 120, the power-down detection unit 131 is configured to detect a power supply voltage output by the power supply switching module 120 for the logic control unit 132 and determine whether to power down, so as to output a corresponding electrical signal to the logic control unit 132 when power is lost, and the logic control unit 132 is configured to output a control signal to control the capacitor power supply unit 133 to start power supply when power is received and to charge by using the power supply voltage when power is not started. It can be understood that the power-down protection module 130 detects the power voltage output by the power switching module 120 through the power-down detection unit 131 thereon, that is, collects the power voltage output by the power switching module 120, so as to provide an electrical signal for detecting whether the main power source and the auxiliary power source are powered down to the logic control unit 132, and the logic control unit 132 controls the capacitor power supply module to discharge when determining that the power-down occurs, so as to supply power to the subsequent circuit.
The first input end of the power output module 140 is connected to the output end of the power switching module 120, the second input end of the power output module 140 is connected to the power supply output end of the capacitor power supply unit 133, and the power output module 140 is used for performing voltage conversion to enable the circuit to output a voltage adapted to the load. It is conceivable that the power output module 140 is connected to the power voltage output by the power switching module 120 and supplies power to the device when the main power or the sub power is supplied, and is connected to the voltage output by the capacitor power supply unit 133 and supplies power to the device when the main power or the sub power is powered down and the capacitor power is supplied.
Therefore, the gateway power supply circuit of the application realizes real-time monitoring of the main power supply voltage, once the main power supply voltage is detected to exceed the preset safety range, the system immediately triggers the power supply switching mechanism to seamlessly switch to the auxiliary power supply for supplying power, thereby greatly shortening the equipment downtime caused by power failure and ensuring the continuity and stability of the system. And the power supply of the key circuit can be cut off rapidly when the power supply is interrupted suddenly, and the key circuit is used as a backup power supply to provide power support rapidly through the high-performance super capacitor, so that key data are not lost, and the data safety and the integrity of the system are effectively protected.
Fig. 2 is a schematic circuit diagram of a power switching module according to an embodiment of the application, wherein the power switching module includes a first PMOS transistor Q1, a second PMOS transistor Q2, a first voltage dividing resistor R1, a second voltage dividing resistor R2, a third voltage dividing resistor R3, a fourth voltage dividing resistor R4, a fifth voltage dividing resistor R5, a sixth voltage dividing resistor R6, a first diode D1, a first NPN transistor Q3, and an electrostatic discharge diode D2.
Specifically, the drain end of the first PMOS transistor Q1 is used as the first input end of the power switching module, the drain end of the first PMOS transistor Q1 is connected to the first end of the first voltage dividing resistor R1, the second end of the first voltage dividing resistor R1 is connected to the first end of the second voltage dividing resistor R2, and the second end of the second voltage dividing resistor R2 is grounded.
The source end of the first PMOS transistor Q1 is used as the output end of the power switching module, the source end of the first PMOS transistor Q1 is connected to the first end of the third voltage dividing resistor R3, the second end of the third voltage dividing resistor R3 is connected to the first end of the fourth voltage dividing resistor R4, and the first end of the fourth voltage dividing resistor R4 is also connected to the gate end of the first PMOS transistor Q1.
The collector end of the first NPN triode Q3 is connected to the second end of the fourth voltage dividing resistor R4, the base end of the first NPN triode Q3 is connected to the input voltage through the fifth voltage dividing resistor R5, the base end of the first NPN triode Q3 is also connected to the emitter end of the first NPN triode Q3 through the sixth voltage dividing resistor R6, and the emitter end of the first NPN triode Q3 is also grounded.
The drain end of the second PMOS transistor Q2 is used as the second input end of the power switching module, the drain end of the second PMOS transistor Q2 is further connected to the grounded esd diode D2, the gate end of the second PMOS transistor Q2 is connected to the first end of the second voltage divider resistor R2, the source end of the second PMOS transistor Q2 is connected to the anode end of the first diode D1, and the cathode end of the first diode D1 is connected to the source end of the first PMOS transistor Q1.
It can be understood that, under the condition that the main power supply is normal, the drain end of the first PMOS transistor Q1 is connected to the main power supply, and the parasitic diode on the first PMOS transistor Q1 is turned on, so that the source end of the first PMOS transistor Q1 generates a voltage drop. The base end of the first NPN triode Q3 is connected to the input voltage through the fifth voltage dividing resistor R5, the base end of the first NPN triode Q3 is further connected to the emitter end of the first NPN triode Q3 through the sixth voltage dividing resistor R6, so that under the voltage dividing action of the fifth voltage dividing resistor R5 and the sixth voltage dividing resistor R6, the first NPN triode Q3 is conducted, the third voltage dividing resistor R3 and the fourth voltage dividing resistor R4 divide the voltage, the voltage of the gate end of the first PMOS tube Q1 is raised, the first PMOS tube Q1 is conducted, and the power supply switching module can provide the power supply voltage corresponding to the main power supply for the later-stage circuit.
Under the condition that the auxiliary power supply normally supplies power, the electrostatic discharge diode D2 can play a role in protecting the auxiliary power supply from electrostatic discharge damage, the drain end of the second PMOS tube Q2 is connected to the auxiliary power supply, and the parasitic diode on the second PMOS tube Q2 is conducted, so that the source end of the second PMOS tube Q2 generates voltage drop, and the voltage drop is transmitted to the output end of the power supply switching module through the first diode D1.
It is conceivable that the power switching module provides one voltage signal output even in the case where the main power supply and the sub power supply are simultaneously supplied normally. The second input end of the auxiliary power supply is connected to the power supply switching module, namely the drain end of the second PMOS tube Q2, and the gate end of the second PMOS tube Q2 can be connected to corresponding voltage under the voltage division action of the first voltage dividing resistor R1 and the second voltage dividing resistor R2. And because the parasitic diode on the second PMOS transistor Q2 is turned on, the source terminal of the second PMOS transistor Q2 generates a voltage drop, so that the second PMOS transistor Q2 is turned on and transferred to the output terminal of the power switching module through the first diode D1. However, since the voltage drop is formed on the first diode D1, the voltage provided by the secondary power supply is slightly lower than the voltage provided by the primary power supply, and therefore, the power supply switching module can provide the voltage provided by the primary power supply under the condition that the primary power supply and the secondary power supply are simultaneously and normally powered.
The parasitic diode on the first PMOS transistor Q1 can prevent the voltage provided by the secondary power supply from flowing backward to the primary power supply, and the parasitic diode on the first diode D1 and the second PMOS transistor Q2 can prevent the voltage provided by the primary power supply from flowing backward to the secondary power supply.
In this way, the power supply switching module can supply power to the rear-stage circuit under the condition that the main power supply normally supplies power, and is connected to transition to use the auxiliary power supply to supply power to the rear-stage circuit after the main power supply fails, so that automatic switching of the power supply is realized, continuity and stability of system power supply of the edge gateway equipment are guaranteed, and data loss and service interruption are avoided.
Fig. 3 is a schematic circuit diagram of a power-down detection unit according to an embodiment of the present application, where the power-down detection unit is configured to detect a power supply voltage output by the power supply switching module, so as to provide a corresponding detection signal for the logic control unit to determine whether the logic control unit is powered down. It is conceivable that the power-down detection unit may indicate whether a power-down situation exists by comparing the power supply voltage that is connected to the power supply unit with a corresponding voltage threshold value, and further outputting a corresponding electrical signal, for example, providing an electrical signal of a high level when a power-down situation exists and providing an electrical signal of a low level when a power-down situation does not exist.
As shown in fig. 3, in an embodiment, the power failure detection unit includes an operational amplifier a1, a seventh voltage dividing resistor R7, an eighth voltage dividing resistor R8, a ninth voltage dividing resistor R9, a tenth voltage dividing resistor R10, a feedback resistor Rf, and a first pull-up resistor Rpu1.
The non-inverting input end of the operational amplifier A1 is connected with the first end of a seventh voltage dividing resistor R7, the first end of the seventh voltage dividing resistor R7 is also connected with an eighth voltage dividing resistor R8 which is grounded, the second end of the seventh voltage dividing resistor R7 is connected with the power supply voltage output by the power supply switching module, the non-inverting input end of the operational amplifier A1 is also connected with the output end of the operational amplifier A1 through a feedback resistor Rf, the inverting input end of the operational amplifier A1 is connected with the first end of a ninth voltage dividing resistor R9, the first end of the ninth voltage dividing resistor R9 is also connected with a tenth voltage dividing resistor R10 which is grounded, the second end of the ninth voltage dividing resistor R9 is connected with the power supply voltage, and the output end of the operational amplifier A1 is also connected with the power supply voltage through a first pull-up resistor Rpu1.
It is understood that the ninth voltage dividing resistor R9 and the tenth voltage dividing resistor R10 can provide corresponding input voltages to the inverting input terminal of the operational amplifier a1, that is, as voltage thresholds. The non-inverting input terminal of the operational amplifier a1 is connected to the power supply voltage output by the power supply switching module as an input voltage, for which, the operational amplifier a1 can determine whether to power down by comparing the input voltages connected to the two input terminals thereof, that is, comparing the power supply voltage output by the power supply switching module with the voltage threshold. Of course, when there is a power failure condition and when there is no power failure condition, the operational amplifier a1 can respectively provide different electrical signals to transmit to the logic control unit located at the subsequent stage, so as to implement the power failure detection function.
Fig. 4 is a schematic circuit structure diagram of a logic control unit according to an embodiment of the present application, where the logic control unit is configured to output a control signal to control a capacitor power supply unit to start power supply when power is turned off, that is, when the logic control unit determines that a current power supply connected to the capacitor power supply unit has a power-off condition, the logic control unit controls the capacitor power supply unit to start, so as to provide a power-off protection function for a device through discharging a capacitor, thereby providing a short but sufficient power guarantee for a critical circuit, enabling a system to complete storage, state recording and orderly shutdown operations of important data, effectively preventing data loss and system damage, and improving data security and system stability of the device.
As shown in fig. 4, in an embodiment, the logic control unit includes a microcontroller U1, a second NPN triode Q3, a first current limiting resistor Rc1, an eleventh voltage dividing resistor R11, a twelfth voltage dividing resistor R12, a first filter capacitor C1, a second filter capacitor C2, a third filter capacitor C3, and a third PMOS tube Q4.
The microcontroller U1 is an MCU (Microcontroller Unit ), the first GPIO pin of the microcontroller U1 is used as a signal access terminal of the logic control unit, the second GPIO pin of the microcontroller U1 is connected to the first terminal of the first current limiting resistor Rc1, the second terminal of the first current limiting resistor Rc1 is connected to the base terminal of the second NPN triode Q3, and the second GPIO pin of the microcontroller U1 outputs an enable signal when power is turned off.
The collector terminal of the second NPN triode Q3 is grounded, the gate terminal of the second NPN triode Q3 is connected to the collector terminal of the second NPN triode Q3 through an eleventh voltage dividing resistor R11, and the first filter capacitor C1 is connected in parallel to the eleventh voltage dividing resistor R11. The emitter terminal of the second NPN triode Q3 is connected to the drain terminal of the third PMOS transistor Q4, the emitter terminal of the second NPN triode Q3 is further connected to the source terminal of the third PMOS transistor Q4 through a twelfth voltage dividing resistor R12, and the second filter capacitor C2 is connected in parallel to the twelfth voltage dividing resistor R12. The drain terminal and the source terminal of the third PMOS transistor Q4 are respectively used as the control output terminal of the logic control unit, and the drain terminal of the third PMOS transistor Q4 is further connected to the third filter capacitor C3 that is grounded.
It is understood that the microcontroller U1 outputs a corresponding enable signal so that the base terminal of the second NPN transistor Q3 can be connected to a corresponding voltage. While the source terminal of the third PMOS transistor Q4 is connected to the capacitor power supply unit, it is conceivable that the capacitor power supply unit charges the capacitor by using the power supply voltage when the power supply is not turned on, that is, the capacitor power supply unit may charge the capacitor by connecting to the output terminal of the power supply switching module, and turn on the power supply when the power is turned off. In this regard, the source terminal of the third PMOS transistor Q4 can be connected to the voltage provided by the capacitor when there is a power failure, and under the voltage division of the twelfth voltage dividing resistor R12, the second NPN transistor Q3 meets the conducting condition, so that the second NPN transistor Q3 is conducted, and the third PMOS transistor Q4 is also conducted, so that the capacitor power supply unit can supply power to the later stage circuit.
The power supply access end of the capacitor power supply unit is connected with the output end of the power supply switching module, and then the capacitor power supply unit is charged by using the power supply voltage when power supply is not started. In an embodiment, the capacitor power supply unit includes a capacitor subunit and a boost subunit, where a power supply end of the capacitor subunit is connected to an output end of the power supply switching module, so as to charge a capacitor of the capacitor subunit by a power supply voltage output by the power supply switching module, and an output end of the capacitor subunit is connected to a control output end of the logic control unit, and in addition, an input end of the boost subunit is also connected to a control output end of the logic control unit, an input end of the boost subunit is used as a power supply control end of the capacitor power supply unit, and an output end of the boost subunit is connected to a second input end of the power supply output module, and it is conceivable that the boost subunit is communicated with the capacitor subunit when the logic control unit outputs a control signal, so as to perform boost conversion on a voltage provided by the capacitor subunit.
Fig. 5 is a schematic circuit diagram of a capacitor subunit according to an embodiment of the application, as shown in fig. 5, in an embodiment of the application, the capacitor subunit includes a thirteenth voltage dividing resistor R13, a fourteenth voltage dividing resistor R14, a fifteenth voltage dividing resistor R15, a sixteenth voltage dividing resistor R16, a seventeenth voltage dividing resistor R17, a first PNP transistor Q5, a second PNP transistor Q6, a second diode D3, a schottky diode D4, a super capacitor Cs1 and a voltage regulator U2.
Specifically, the emitter terminal of the first PNP transistor Q5 is connected to the output terminal of the power switching module, the emitter terminal of the first PNP transistor Q5 is connected to the base terminal of the first PNP transistor Q5 through a thirteenth voltage dividing resistor R13, the base terminal of the first PNP transistor Q5 is further connected to the emitter terminal of the second PNP transistor Q6, and the collector terminal of the first PNP transistor Q5 is connected to the base terminal of the second PNP transistor Q6.
The base end of the second PNP triode Q6 is connected with a grounded fourteenth divider resistor R14, the collector end of the second PNP triode Q6 is connected with the anode end of a Schottky diode D4, the cathode end of the Schottky diode D4 is connected with the positive end of a super capacitor Cs1, and the negative end of the super capacitor Cs1 is grounded. And, the second diode D3 is connected in parallel with the schottky diode D4, that is, the anode terminal of the second diode D3 is connected to the anode terminal of the schottky diode D4, and the cathode terminal of the second diode D3 is connected to the cathode terminal of the schottky diode D4.
In addition, the first end of the fifteenth voltage dividing resistor R15 is connected to the positive electrode of the super capacitor Cs1, the second end of the fifteenth voltage dividing resistor R15 is connected to the input end of the voltage stabilizing tube U2, the first end of the fifteenth voltage dividing resistor R15 is further connected to the first end of the sixteenth voltage dividing resistor R16, the second end of the sixteenth voltage dividing resistor R16 is connected to the first end of the seventeenth voltage dividing resistor R17, the second end of the seventeenth voltage dividing resistor R17 is connected to the output end of the voltage stabilizing tube U2, and the ground end of the voltage stabilizing tube U2 is connected to the second end of the sixteenth voltage dividing resistor R16.
It should be noted that, in some embodiments, the capacitor subunit may further include a plurality of super capacitors, such as2, 3, etc., and two super capacitors are shown in fig. 5, where each super capacitor is sequentially connected in series, and each super capacitor is configured with a circuit structure including a fifteenth voltage dividing resistor R15, a sixteenth voltage dividing resistor R16, a seventeenth voltage dividing resistor R17, and a voltage stabilizing tube U2 as described above. The voltage stabilizing tube can be used for stabilizing the voltage when power supply fluctuation occurs in the charging and discharging process of the super capacitor so as to protect a subsequent circuit from being damaged, the circuit structure comprising the fifteenth voltage dividing resistor R15, the sixteenth voltage dividing resistor R16, the seventeenth voltage dividing resistor R17 and the voltage stabilizing tube U2 can balance the voltage output by the super capacitor, wherein the fifteenth voltage dividing resistor R15 plays a role in limiting current, and the sixteenth voltage dividing resistor R16 and the seventeenth voltage dividing resistor R17 control the output voltage of the voltage stabilizing tube U2 through voltage division.
It can be appreciated that, when the main power supply or the auxiliary power supply supplies power, based on the thirteenth voltage dividing resistor R13, the emitter terminal and the base terminal of the first PNP transistor Q5 can access the corresponding voltages and generate currents, so that the first PNP transistor Q5 is turned on. Similarly, since the first PNP transistor Q5 is turned on, the current can pass through the fourteenth voltage dividing resistor R14 and generate a voltage drop across the fourteenth voltage dividing resistor R14, and the base terminal of the second PNP transistor Q6 can be connected to the corresponding current, and the conduction condition is satisfied. Moreover, since the schottky diode D4 is forward connected and no power down condition has occurred at this time, the logic control unit does not connect the capacitor subunit and the boost subunit, and for this reason, the grounded supercapacitor Cs1 can start charging.
Meanwhile, the second PNP triode Q5, the thirteenth voltage dividing resistor R13 and the fourteenth voltage dividing resistor R14 also form an overcurrent protection branch, and a large current can flow through the second PNP triode Q5 and the fourteenth voltage dividing resistor R14 to the ground end, so that the current is drained to the ground. And the second diode D3 and the Schottky diode D4 can play a role in preventing reverse connection, and meanwhile, the super capacitor can be prevented from flowing backward to the main power supply and the auxiliary power supply after being fully charged.
When the power failure occurs, the current of the base terminal and the emitter terminal of the first PNP transistor Q5 is changed due to the change of the connected voltage, so that the first PNP transistor Q5 is turned off, and similarly, the second PNP transistor Q6 is turned off without meeting the on condition. And when the power failure condition occurs, the logic control unit is used for communicating the capacitor subunit with the boosting subunit, and for this purpose, the super capacitor Cs1 can start discharging, so that short-term and sufficient power guarantee is provided for the key circuit.
Therefore, the capacitor subunit provides a power-down protection function for the equipment through capacitor discharging, namely, short-term and sufficient power guarantee can be provided, so that the edge gateway equipment can finish the storage, state recording and orderly shutdown operation of important data, data loss and system damage are effectively prevented, and the data safety and system stability of the equipment are improved.
Fig. 6 is a schematic circuit diagram of a boosting subunit according to an embodiment of the present application, where the boosting subunit boosts a voltage released by a super capacitor after the boosting subunit is connected to the voltage, so as to provide a sufficient voltage for a subsequent circuit. As shown in fig. 6, in an embodiment, the boost subunit includes a boost converter U3, a first inductor L1, an eighteenth voltage dividing resistor R18, a nineteenth voltage dividing resistor R19, a twentieth voltage dividing resistor R20, a twenty first voltage dividing resistor R21, a second current limiting resistor Rc2, a third current limiting resistor Rc3, a fourth current limiting resistor Rc4, a second pull-up resistor Rpu2, a fourth filter capacitor C4, a fifth filter capacitor C5, a sixth filter capacitor C6, a seventh filter capacitor C7, an eighth filter capacitor C8, a ninth filter capacitor C9, and a third diode D5.
The frequency selection pin FSEL of the boost converter U3 is connected with a grounded second current limiting resistor Rc2, one grounded end of the second current limiting resistor Rc2 is connected with the first end of a fourth filter capacitor C4, the second end of the fourth filter capacitor C4 serves as an input end of a boost subunit, the second end of the fourth filter capacitor C4 is also connected with a grounded fifth filter capacitor C5, and the second current limiting resistor Rc2 and the fourth filter capacitor C4 form a filter circuit so as to filter signals of the frequency selection pin FSEL.
The enable pin EN of the boost converter U3 is further connected to the first end of the eighteenth voltage dividing resistor R18 through the third current limiting resistor Rc3, the second end of the eighteenth voltage dividing resistor R18 is connected to the second end of the fourth filter capacitor C4, the first end of the eighteenth voltage dividing resistor R18 is further connected to the nineteenth voltage dividing resistor R19 which is grounded, the eighteenth voltage dividing resistor R18 and the nineteenth voltage dividing resistor R19 are used for setting an enable voltage dividing ratio to the enable pin EN, and the third current limiting resistor Rc3 is used for limiting the current accessed by the enable pin EN.
The input pin IN of the boost converter U3 is connected to the second end of the fourth filter capacitor C4, the input pin IN of the boost converter U3 is further connected to the first end of the first inductor L1, the second end of the first inductor L1 is connected to the switch pin SW of the boost converter U3, the second end of the first inductor L1 is further connected to the anode end of the third diode D5, the cathode end of the third diode D5 is used as the output end of the boost subunit, the cathode end of the third diode D5 is further grounded through the seventh filter capacitor C7, and the eighth filter capacitor C8 is connected to the seventh filter capacitor C7 IN parallel.
The feedback pin FB of the boost converter U3 is connected to the feedback voltage through the second pull-up resistor Rpu2, the feedback pin FB of the boost converter U3 is connected to the first end of the nineteenth voltage dividing resistor R19, the second end of the nineteenth voltage dividing resistor R19 is connected to the cathode end of the third diode D5, the second end of the nineteenth voltage dividing resistor R19 is further connected to the twenty-first voltage dividing resistor R20 which is grounded, the nineteenth voltage dividing resistor R19 and the twenty-first voltage dividing resistor R20 are used for setting a feedback voltage dividing ratio to the feedback pin FB, and the second pull-up resistor Rpu2 is used for limiting the current by the feedback signal.
In addition, the synchronous rectification select pin SS of the boost converter U3 is connected to the grounded sixth filter capacitor C6. The monitor pin COMP of the boost converter U3 is grounded through a ninth filter capacitor C9 and a twenty-first voltage dividing resistor R21 connected in series, and the ninth filter capacitor C9 and the twenty-first voltage dividing resistor R21 form a filter circuit, so as to filter the signal of the monitor pin COMP.
The first inductor L1 is used for energy storage and filtering of the boost converter U3, and particularly during switching operation, the first inductor L1 can smooth current and reduce noise caused by switching. And the third diode D5 is matched with the first inductor L1 to convert energy released by the inductor into direct current, and provides a path when the inductor current changes to prevent the current from flowing reversely.
In this regard, after the boost converter U3 is connected to the voltage provided by the super capacitor, it boosts the voltage, and then, the voltage is transmitted to the power output module located at the subsequent stage through the cathode end of the third diode D5, so as to implement the power-down protection function when the power-down condition exists.
In some embodiments, the power output module includes a common cathode diode and a voltage conversion sub-module, a first input terminal of the common cathode diode is connected to an output terminal of the power switching module, a second input terminal of the common cathode diode is connected to a power supply output terminal of the capacitor power supply unit, and an output terminal of the common cathode diode is connected to an input terminal of the voltage conversion sub-module. It can be understood that the two input ends of the common cathode diode are respectively connected with the output end of the power supply switching module and the power supply output end of the capacitor power supply unit, when the power is not lost, the voltage provided by the power supply switching module is connected to the voltage conversion sub-module, and when the power is lost, the voltage provided by the capacitor power supply unit is connected to the voltage conversion sub-module. In addition, the common cathode diode can also prevent the voltage at the other end from flowing backwards, thereby playing a role in protection. It should be noted that two common cathode connected diodes may be used in some embodiments instead of the common cathode diode described above.
The voltage conversion sub-module is used for performing voltage conversion, such as step-up and/or step-down processing, on the voltage connected through the common-cathode diode. And the voltage conversion sub-module and the main power supply access module comprise an input filtering unit, a voltage conversion unit and an output filtering unit which are sequentially connected, wherein the input filtering unit is used for filtering accessed voltage signals, and the output filtering unit is used for filtering converted voltage signals, for example, a plurality of capacitors connected in parallel are used for filtering input and output. For the voltage conversion unit, the voltage conversion sub-module and the main power supply access module can adopt voltage conversion units with the same circuit structure, and of course, voltage conversion units with different circuit structures can also be adopted.
Fig. 7 is a schematic circuit diagram of a voltage conversion sub-module according to an embodiment of the present application, as shown in fig. 7, in an embodiment, the voltage conversion sub-module is connected with 4 parallel capacitors at an input end and an output end, so as to be used as an input filtering unit and an output filtering unit, respectively, to filter the input end and the output end, and through the parallel capacitors, the voltage conversion sub-module can smooth voltage fluctuation, reduce noise interference, effectively filter high frequency noise, and protect a post-stage circuit from interference, thereby improving stability of output voltage.
The voltage conversion unit includes a first DCDC chip U4, a twenty-third voltage dividing resistor R22, a twenty-third voltage dividing resistor R23, a twenty-fourth voltage dividing resistor R24, a tenth filter capacitor C10, an eleventh filter capacitor C11, and a second inductor L2.
Specifically, the input pin IN of the first DCDC chip U4 is connected to the output end of the input filter unit, the input pin IN of the first DCDC chip U4 is further connected to the first end of the twenty-third voltage dividing resistor R22, the second end of the twenty-third voltage dividing resistor R22 is grounded through the tenth filter capacitor C10, the ground pin GND and the enable pin EN of the first DCDC chip U4 are both connected to the second end of the second voltage dividing resistor R22, the frequency selection pin LX of the first DCDC chip U4 is connected to the first end of the second inductor L2, the second end of the second inductor L2 is connected to the output end of the output filter unit, the second end of the second inductor L2 is also connected to the first end of the twenty-third voltage dividing resistor R23, the second end of the twenty-third voltage dividing resistor R23 is connected to the first end of the twenty-fourth voltage dividing resistor R24, the second end of the twenty-fourth voltage dividing resistor R24 is grounded, and the feedback pin FB of the first DCDC chip U4 is connected to the second end of the twenty-third voltage dividing resistor R23, and the twenty-fourth voltage dividing resistor R24 is connected to the twenty-fourth filter resistor R11 IN parallel.
The twenty-second voltage-dividing resistor R22 and the tenth filter capacitor C10 form an RC filter circuit, so as to filter and decouple the enable pin EN. The twenty-third voltage dividing resistor R23 and the twenty-fourth voltage dividing resistor R24 are used for dividing the feedback pin FB, and the twenty-fourth voltage dividing resistor R24 and the eleventh filter capacitor C11 form an RC filter, so as to filter and decouple the signal of the feedback pin FB. The second inductor L2 is used to store energy during the switching operation and release energy when the switch is turned off, so as to maintain the continuous current of the circuit, and has a function of suppressing the current variation, thus helping to smooth the output current and reducing the fluctuation and ripple of the current.
Fig. 8 is a schematic circuit diagram of a main power access module according to an embodiment of the present application, as shown in fig. 8, in an embodiment, the main power access module is also connected with 4 parallel capacitors at an input end and an output end, so as to be used as an input filter unit and an output filter unit, respectively, to filter the input end and the output end, and by using the parallel capacitors, voltage fluctuation can be smoothed, noise interference can be reduced, high-frequency noise can be effectively filtered, and a post-stage circuit can be protected from interference, so that stability of output voltage can be improved.
In addition, the voltage conversion unit of the main power access module includes a second DCDC chip U5, a twenty-fifth voltage dividing resistor R25, a twenty-sixth voltage dividing resistor R26, a twenty-seventh voltage dividing resistor R27, a twenty-eighth voltage dividing resistor R28, a twelfth filter capacitor C12, a thirteenth filter capacitor C13, a bootstrap capacitor Cb, and a third inductor L3.
Specifically, the input pin VIN of the second DCDC chip U5 is connected to the output end of the input filter unit, the input pin VIN of the second DCDC chip U5 is further connected to the first end of the twenty-fifth voltage dividing resistor R25, the second end of the twenty-fifth voltage dividing resistor R25 is grounded through the twenty-sixth voltage dividing resistor R26, the enable pin EN of the second DCDC chip U5 is connected to the second end of the twenty-fifth voltage dividing resistor R25, the twelfth filter capacitor C12 is connected in parallel to the twenty-sixth voltage dividing resistor R26, the switch pin SW of the second DCDC chip U5 is connected to the first end of the third inductor L3, the second end of the third inductor L3 is connected to the output end of the output filter unit, the second end of the third inductor L3 is further connected to the first end of the twenty-seventh voltage dividing resistor R27, the second end of the twenty-seventh voltage dividing resistor R27 is connected to the first end of the twenty-eighth voltage dividing resistor R28, the second end of the twenty-eighth voltage dividing resistor R28 is grounded, the switch pin SW 43 of the second DCDC chip U5 is connected to the twenty-eighth voltage dividing resistor C3498, and the switch pin SW 43 is connected to the twenty-eighth voltage dividing resistor C7248 in parallel to the second dc chip.
The twenty-seventh voltage dividing resistor R27 and the twenty-eighth voltage dividing resistor R28 can adjust the output of the second DCDC chip U5, and the third inductor L3 can also be used for storing and releasing energy to maintain the continuous current of the circuit, and has a function of inhibiting the current variation, so as to help smooth the output current and reduce the fluctuation and ripple of the current. It can be appreciated that when the main power input voltage fluctuates within an allowable wide range, the main power access module can filter out high frequency noise and interference through the input filtering unit thereon, and then convert the input voltage into a stable intermediate voltage according to an internal regulation mechanism by using the voltage conversion unit to maintain the output voltage. In this way, the main power supply access module can provide a wide voltage input range in consideration of power supply input requirements under different application scenes, and then can access different voltages, so that the edge gateway equipment can stably operate in different countries and regions and under different voltage environments, and the applicability and flexibility of the equipment are improved.
In addition, the voltage conversion sub-module and the main power supply access module adopt high-efficiency DC-DC voltage reduction circuits, so that the power supply conversion efficiency is improved, and the energy consumption of the whole system is reduced.
The application also provides a circuit board which comprises the gateway power supply circuit, wherein the gateway power supply circuit can realize real-time monitoring of the main power supply voltage, and once the main power supply voltage is detected to exceed the preset safety range, the system immediately triggers a power supply switching mechanism and seamlessly switches to the auxiliary power supply to supply power, so that the equipment downtime caused by power failure is greatly shortened, and the continuity and stability of the system are ensured. And the power supply of the key circuit can be cut off rapidly when the power supply is interrupted suddenly, and the key circuit is used as a backup power supply to provide power support rapidly through the high-performance super capacitor, so that key data are not lost, and the data safety and the integrity of the system are effectively protected.
The application also provides edge gateway equipment, which comprises the circuit board, wherein the edge gateway equipment is connected with the main power supply and the auxiliary power supply, and the main power supply and the auxiliary power supply of the system are switched through the circuit board, so that the continuity and the stability of the system are ensured, and the high-performance super capacitor is used as a backup power supply, so that the power failure protection capability of the equipment is improved, and further, the equipment can quickly acquire electric energy support when the power supply is abnormal, thereby ensuring that key data is not lost, and effectively protecting the data safety and the integrity of the system.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.
Note that the above is only a preferred embodiment of the present application and the technical principle applied. It will be understood by those skilled in the art that the present application is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the application. Therefore, while the application has been described in connection with the above embodiments, the application is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the application, which is set forth in the following claims.