Disclosure of Invention
Accordingly, embodiments of the present disclosure provide a semiconductor structure and a method for forming the same to solve at least one of the problems in the prior art.
In order to achieve the above object, the technical solution of the embodiments of the present disclosure is implemented as follows:
In a first aspect, embodiments of the present disclosure provide a semiconductor structure, comprising:
The substrate comprises a substrate, a stacking structure arranged on the substrate, wherein the stacking structure comprises a first electrode layer and a first dielectric layer which are alternately stacked, the stacking structure comprises a plurality of sub-stacking structures, each sub-stacking structure extends along a first direction and is arranged along a second direction, at least one of two opposite side walls of each sub-stacking structure along the second direction at least comprises a curved surface, and two opposite side walls of each sub-stacking structure along the thickness direction of the substrate are planes parallel to the substrate;
The second dielectric layer is conformally covered on the outer wall of each sub-stack structure and the bottom surface of a first groove formed between two adjacent sub-stack structures;
and the second electrode layer is conformally covered on the second dielectric layer.
In some embodiments, the substrate comprises a first region and a second region arranged side by side along the first direction, each sub-stack structure comprises a first part and a second part, wherein the first part is positioned on the first region, the second part extends to the second region, the second part comprises alternately stacked first electrode layers and first dielectric layers, the first part comprises the first dielectric layers, and the second dielectric layers and the second electrode layers are positioned between adjacent second parts;
At least one of two opposite side walls of the second part along the second direction at least comprises a curved surface, and two opposite side walls of the first part along the second direction are planes parallel to the first direction.
In some embodiments, the sub-stack structure comprises a first sub-portion and a second sub-portion alternately arranged along a first direction, wherein at least one of two opposite side walls of the first sub-portion along the second direction and two opposite side walls of the second sub-portion along the second direction is curved.
In some embodiments, the curved surface is parallel to a thickness direction of the substrate, and the curved surface is recessed toward another sidewall of the sub-stack structure opposite in the second direction.
In some embodiments, the first portion further comprises a plurality of transistors, each transistor being located between two adjacent first dielectric layers in the first portion, each transistor comprising a source and a drain at opposite ends along a first direction, a channel region located between the source and the drain;
and each word line structure extends along the thickness direction of the substrate, and one word line structure is connected with channel regions of a plurality of transistors in one first part.
In some embodiments, the first portion further comprises a plurality of bit line structures, each bit line structure extends along the second direction, and each bit line structure is located between two adjacent first dielectric layers along the thickness direction of the substrate and is connected with sources or drains of a plurality of transistors in one layer, and the transistors are connected with the first electrode layer.
In some embodiments, each of the first electrode layers in each of the sub-stacks includes a first sub-electrode layer and a second sub-electrode layer spaced apart along the second direction, the first electrode layer further including a first connection structure between the first sub-electrode layer and the second sub-electrode layer.
In a second aspect, embodiments of the present disclosure further provide a method for forming a semiconductor structure, including:
Forming an initial stacked structure in which semiconductor layers and sacrificial layers are alternately stacked on a substrate;
forming a plurality of first grooves penetrating through the initial stacked structure, wherein each first groove extends along a first direction and is distributed along a second direction, the first grooves divide the initial stacked structure into a plurality of initial sub-stacked structures distributed along the second direction, and at least one of two opposite side walls of each initial sub-stacked structure along the second direction at least comprises a curved surface;
removing the sacrificial layer to form a first filling region;
Forming a first dielectric layer in the first filling area;
removing at least part of each semiconductor layer in each initial sub-stack structure to form a second filling region;
Forming a first electrode layer in the second filling region to form a sub-stack structure;
And forming a second dielectric layer which conformally covers the outer wall of the sub-stack structure and the bottom wall of the first groove and a second electrode layer which conformally covers the second dielectric layer.
In some embodiments, the substrate comprises a first region and a second region arranged side by side along the first direction, the first groove extends from the first region to the second region, each initial sub-stack structure comprises a first part positioned on the first region and a second part extending to the second region, and at least one side wall of two side walls of the second part opposite along the second direction at least comprises a curved surface;
the removing at least a portion of each semiconductor layer in each of the initial sub-stack structures includes:
Removing at least part of each semiconductor layer in each second portion along the first grooves; and performing metallization processing on the semiconductor layer remained on the second region to form a first connection structure.
In some embodiments, the first electrode layer includes a first sub-electrode layer and a second sub-electrode layer spaced apart along the second direction, the first electrode layer further includes a first connection structure between the first sub-electrode layer and the second sub-electrode layer, and the performing a metallization process on the semiconductor layer remaining on the second region to form a first connection structure includes:
forming a first metal layer on sidewalls of the semiconductor layers remaining on the second region after removing at least a portion of each semiconductor layer in each of the initial sub-stack structures;
Forming the semiconductor layer and part of the first metal layer remained on the second region into the first connection structure through a heat treatment process;
And removing the residual first metal layer to form the second filling area.
In some embodiments, the method further comprises:
After forming a plurality of first grooves penetrating through the stacked structure, removing a portion of each semiconductor layer of each initial sub-stacked structure on the first region from one of two sides of the stacked structure perpendicular to the first direction, which is located on the first region, to form a third filling region;
and forming a bit line structure in the third filling region, wherein the bit line structure is connected with the semiconductor layer remained on the first region.
In some embodiments, the method further comprises:
doping the remaining part of each semiconductor layer on the first region along two ends of the first direction to form a source electrode and a drain electrode, so that a plurality of transistors are formed, the semiconductor layers between the source electrode and the drain electrode form a channel region of the transistor, and the transistor is connected with the first electrode layer;
a plurality of word line structures are formed, each extending in a thickness direction of the substrate, one of the word line structures being connected to channel regions of a plurality of transistors in one of the first portions.
In some embodiments, the sub-stack structure comprises a first sub-portion and a second sub-portion alternately arranged along a first direction, at least one of two opposite side walls of the first sub-portion along the second direction and two opposite side walls of the second sub-portion along the second direction is curved, the forming a plurality of first grooves throughout the initial stack structure comprises:
Forming a plurality of first strip-shaped grooves penetrating through the initial stacking structure, wherein each first strip-shaped groove extends along a first direction, and the plurality of first strip-shaped grooves are arranged along a second direction;
filling a sacrificial filling layer in the first strip-shaped groove;
forming a hole type groove penetrating through the sacrificial filling layer and the rest initial stacking structure, wherein the hole type groove and the strip-shaped groove form the first groove, the size of the hole type groove along the second direction is larger than that of the strip-shaped groove along the second direction, and the hole type grooves are arranged at intervals along the first direction and the second direction;
and removing the remaining sacrificial filling layer.
In some embodiments, the removing the sacrificial layer forms a first filled region, comprising:
Forming a third dielectric layer in the first groove;
Removing part of the third dielectric layer to form a second groove penetrating through the stacking structure, wherein the second groove exposes part of the side wall of the sacrificial layer;
Removing the sacrificial layer exposed from the side wall to form a first sub-filling area;
Forming a portion of the first dielectric layer in the first sub-fill area;
Removing the rest of the third dielectric layer to form a third groove penetrating through the stacked structure, wherein the third groove exposes the rest of the side wall of the sacrificial layer;
Removing the rest of the sacrificial layer to form a second sub-filling area;
And forming another part of the first dielectric layer in the second sub-filling area.
In some embodiments, the first recess extends through the stacked structure and into the substrate;
removing at least part of each semiconductor layer in each initial sub-stack structure to form a second filling area, wherein the second filling area comprises the following steps:
and removing a part of each semiconductor layer and a part of the substrate in each initial sub-stack structure, thereby forming the second filling area.
In the technical scheme provided by the disclosure, the first electrode layer of the stacked structure can be used as a lower electrode of the capacitor, the second dielectric layer can be used as a dielectric layer of the capacitor, and the second electrode layer can be used as an upper electrode of the capacitor. In addition, at least one of the two opposite side walls of the sub-stack structure along the second direction at least comprises a curved surface, the area of the first electrode layer is enlarged relative to the fact that the two opposite side walls of the sub-stack structure along the second direction are both plane surfaces, the second dielectric layer is conformally covered on the outer wall of each sub-stack structure and the bottom surface of a first groove formed between the two adjacent sub-stack structures, the second electrode layer is conformally covered on the second dielectric layer, the area of the second dielectric layer and the area of the second electrode layer are correspondingly enlarged, the capacity of the capacitor is increased, and the storage capacity of the capacitor is improved.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, well-known functions and constructions are not described in detail to avoid obscuring the present disclosure, i.e., not all features of an actual embodiment are described herein.
In the drawings, like numbers refer to like elements throughout.
It should be understood that spatially relative terms, such as "under," "above," "over," and the like, may be used herein for convenience of description to describe one element or feature as illustrated in the figures as compared to another element or feature. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
The embodiment of the disclosure further provides a method for forming a semiconductor structure, and fig. 1 is a schematic flow chart of the method for forming a semiconductor structure according to the embodiment of the disclosure. As shown in fig. 1, the method for forming the semiconductor structure includes the following steps:
step S10, forming an initial stacked structure formed by alternately stacking semiconductor layers and sacrificial layers on a substrate;
Step S20, forming a plurality of first grooves penetrating through the initial stacking structure, wherein each first groove extends along a first direction, and the plurality of first grooves are arranged along a second direction; the first groove divides the initial stacked structure into a plurality of initial sub-stacked structures which are arranged along a second direction, and at least one of two opposite side walls of each initial sub-stacked structure along the second direction at least comprises a curved surface;
Step S30, removing the sacrificial layer to form a first filling area;
Step S40, forming a first dielectric layer in the first filling area;
Step S50, removing at least part of each semiconductor layer in each initial sub-stack structure to form a second filling area;
step S60, forming a first electrode layer in the second filling area to form a sub-stack structure;
And S70, forming a second dielectric layer which conformally covers the outer wall of the sub-stack structure and the bottom wall of the first groove and a second electrode layer which conformally covers the second dielectric layer.
In the embodiment of the disclosure, the first direction is taken as an X direction, the second direction is taken as a Y direction, and the thickness direction of the substrate is taken as a Z direction as an example, and the above directions are not limited thereto, and in the embodiment of the disclosure, it is only required to meet that the first direction intersects with the second direction, and the first direction and the second direction are perpendicular to the thickness direction of the substrate. An exemplary explanation will be given below taking the first direction and the second direction as perpendicular examples.
In the technical scheme provided by the disclosure, the first electrode layer of the stacked structure can be used as a lower electrode of the capacitor, the second dielectric layer can be used as a dielectric layer of the capacitor, and the second electrode layer can be used as an upper electrode of the capacitor. In addition, at least one of the two opposite side walls of the sub-stack structure along the second direction at least comprises a curved surface, the area of the first electrode layer is enlarged relative to the fact that the two opposite side walls of the sub-stack structure along the second direction are both plane surfaces, the second dielectric layer is conformally covered on the outer wall of each sub-stack structure and the bottom surface of a first groove formed between the two adjacent sub-stack structures, the second electrode layer is conformally covered on the second dielectric layer, the area of the second dielectric layer and the area of the second electrode layer are correspondingly enlarged, the capacity of the capacitor is increased, and the storage capacity of the capacitor is improved.
Fig. 2 to 23 are schematic structural views of a semiconductor structure forming process according to an embodiment of the present disclosure, and a method for forming a semiconductor structure according to an embodiment of the present disclosure will be described in detail with reference to fig. 1 to 23.
Referring to fig. 1, step S10 is performed to form an initial stacked structure in which semiconductor layers and sacrificial layers are alternately stacked on a substrate.
In some embodiments, as shown in fig. 2, the substrate 100 comprises a semiconductor substrate. The semiconductor substrate may be an elemental semiconductor material substrate (e.g., a silicon substrate, a germanium substrate, etc.), a composite semiconductor material substrate (e.g., a silicon germanium substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc.
In some embodiments, forming the initial stacked structure 200 shown in fig. 2 includes forming semiconductor layers 201 and sacrificial layers 202 alternately arranged in sequence in a Z direction by a deposition process.
Note that the number of the semiconductor layers 201 and the sacrificial layers 202 in the drawing is merely an example, and the present disclosure is not limited to the specific number of the semiconductor layers 201 and the sacrificial layers 202.
In embodiments of the present disclosure, deposition processes include, but are not limited to, chemical Vapor Deposition (Chemical Vapor Deposition, CVD), low pressure chemical Vapor Deposition (Low Pressure Chemical Vapor Deposition, LPCVD), plasma enhanced chemical Vapor Deposition (PLASMA ENHANCED CHEMICAL Vapor Deposition, PECVD), physical Vapor Deposition (Physical Vapor Deposition, PVD), and atomic layer Deposition (Atomic Layer Deposition, ALD).
In an embodiment of the present disclosure, the material of the semiconductor layer 201 includes at least one of silicon and germanium. The material of the sacrificial layer 202 includes, but is not limited to, silicon germanium (SiGe). Here, the material of the sacrificial layer 202 has a higher etching selectivity with respect to the material of the semiconductor layer 201.
In some specific examples, the method of forming a semiconductor structure further includes forming a first mask layer on the initial stacked structure, the material of the first mask layer including, but not limited to, silicon oxide.
Referring to fig. 1, step S20 is performed to form a plurality of first recesses 210 penetrating the initial stacked structure shown in fig. 3a, and fig. 3a is a top view of the semiconductor structure. The first grooves 210 divide the initial stacked structure into a plurality of initial sub-stacked structures 220 arranged along the Y direction, and at least one of two opposite sidewalls of each initial sub-stacked structure 220 along the Y direction comprises at least a curved surface.
In some embodiments, the plurality of first grooves may be formed by one etching process. It will be appreciated that the etched pattern is the same shape as the first recess in the XY plane. In the disclosed embodiments, the etching process includes, but is not limited to, wet etching and dry etching.
In other embodiments, the plurality of first grooves may be formed by a secondary etching process. For example, the initial stack may be etched first in the Z direction to form a stripe-shaped recess that extends in the X direction. And etching part of the strip-shaped grooves along the Y direction to form hole-shaped grooves, wherein the strip-shaped grooves and the hole-shaped grooves jointly form a first groove. For another example, the hole-type groove may be formed first, then a strip-type groove penetrating the hole-type groove along the X-direction may be formed, and finally the first groove may be formed.
The process of forming the first recess will be specifically described below by taking a secondary etching process as an example.
In some embodiments, forming a plurality of first recesses throughout the initial stacked structure includes:
a plurality of first strip-shaped grooves penetrating through the initial stacked structure can be formed through a first etching process, each first strip-shaped groove extends along a first direction (for example, the X direction), and the first strip-shaped grooves are distributed along a second direction;
the first stripe-shaped grooves may then be filled with a sacrificial fill layer using a deposition process or a growth process, the material of the sacrificial fill layer including, but not limited to, silicon germanium, silicon nitride.
Then, a part of the sacrificial filling layer and a part of the initial stacked structure in contact with the part of the sacrificial filling layer can be etched through a second etching process to form a hole type groove penetrating through the sacrificial filling layer and the rest of the initial stacked structure, the hole type groove and the strip type groove form a first groove, the size of the hole type groove along the second direction is larger than that of the strip type groove along the second direction, the hole type grooves are arrayed at intervals along the first direction and the second direction, the hole type grooves can be arrayed at intervals along the X direction, and the distance between each interval along the X direction can be the same. And/or, in the Y direction, the hole-type grooves may also be arranged at intervals, and the distance between each interval in the Y direction may be the same.
Then, the remaining sacrificial fill layer is removed, forming the first recess 210 shown in fig. 3 a-3 b.
In other embodiments, the hole-type grooves may be formed first and then the first bar-type grooves may be formed.
In some embodiments, the initial stack may be etched in the Z-direction with the substrate acting as an etch stop layer to form a plurality of first recesses through the initial stack.
In some specific examples, the first recess 210 may extend into the substrate 100.
It should be noted that, the number of the first grooves 210 and the initial sub-stack structures 220 arranged along the Y direction in fig. 3a is only an example, and the present disclosure is not limited to the number of the first grooves 210 and the initial sub-stack structures 220.
Fig. 3a is a top view of a semiconductor structure including a plurality of initial sub-stack structures 220 according to an embodiment of the present disclosure, and fig. 3b is a schematic cross-sectional view along line AA 'and a schematic cross-sectional view along line BB' of the semiconductor structure including a plurality of initial sub-stack structures 220 shown in fig. 3 a.
As shown in fig. 3a, the first groove 210 divides the initial stacked structure into a plurality of initial sub-stacked structures 220 arranged along the Y direction, and at least one of two opposite sidewalls of each initial sub-stacked structure 220 along the Y direction includes at least a curved surface.
Here, as shown in fig. 2 and 3a, the substrate includes a first region 110 and a second region 120 arranged side by side in the X-direction, a first groove 210 extends from the first region 110 to the second region 120, and an initial sub-stack 220 extends from the first region 110 to the second region 120.
At least one sidewall of the initial sub-stack 220 includes at least a curved surface, and it is understood that two opposite sidewalls of the initial sub-stack 220 located on the first region 110 in the Y direction may be planar as shown in fig. 3 a. At least one of two opposite sidewalls of the initial sub-stack 220 located on the second region 120 in the Y direction includes a curved surface.
Fig. 4a to 4e show only partial top views of the initial sub-stack 220 on the second region 120. The disclosed embodiments provide a variety of cases for at least one of two sidewalls of the initial sub-stack 220 on the second region 110 that are opposite in the Y-direction to include a curved surface.
In one case, one side wall comprises a curved surface and the other side wall does not comprise a curved surface. For example, 4a illustrates a case where one sidewall of the initial sub-stack 220 is curved and the other sidewall is planar. 4b shows the case where one sidewall of the initial sub-stack 220 includes two curved surfaces and a plane, and the other sidewall is a plane. It should be noted that fig. 4b illustrates a case where one sidewall includes two curved surfaces, but is not limited to the number of curved surfaces in the embodiment of the present disclosure.
In the second case, the two side walls both comprise curved surfaces, and the number of the curved surfaces contained in the two side walls can be the same or different. For example, 4c illustrates a case where both sidewalls in the initial sub-stack 220 are curved. 4d shows a case where both sidewalls of the initial sub-stack 220 include two curved surfaces and three flat surfaces. 4e illustrates the case where one sidewall of the initial sub-stack 220 is curved, and the other sidewall includes two curved surfaces and three flat surfaces.
In the embodiment of the disclosure, the curved surface may be concave toward the other side wall of the initial sub-stack structure opposite to the other side wall in the Y direction (as shown in fig. 4a to 4 e), or may be convex toward the other side wall of the initial sub-stack structure opposite to the other side wall in the Y direction (as shown in fig. 4 e). Curved surfaces include spherical surfaces, cylindrical surfaces, free-form surfaces, and the like. It will be appreciated that when the curved surface may be recessed toward the other side wall of the initial sub-stack structure opposite in the Y direction, the distance between adjacent capacitances subsequently formed in the Y direction becomes relatively large, which makes it possible to reduce the coupling effect between the adjacent capacitances.
Referring to fig. 1, step S30 is performed to remove the sacrificial layer and form a first filling region.
In some embodiments, removing the sacrificial layer, forming the first fill region includes:
Referring to fig. 5 to 7, first, as shown in fig. 5, a third dielectric layer 310 is formed in the first recess 210, and the third dielectric layer 310 may be filled in the first recess and may cover upper surfaces of a plurality of initial sub-stack structures. The material of the third dielectric layer 310 includes, but is not limited to, silicon oxide. Fig. 5 is a schematic cross-sectional view of a semiconductor structure including a third dielectric layer 310 along line AA 'and a schematic cross-sectional view along line BB' according to an embodiment of the disclosure.
In some embodiments, as shown in fig. 6, a portion of the third dielectric layer 310 may be first removed using an etching process to form a second recess 301 extending through the stacked structure, the second recess 301 exposing a portion of the sidewalls of the sacrificial layer 202. The sacrificial layer with exposed sidewalls is then removed using a wet etch process to form the first sub-fill regions 311. The first sub-fill area 311 is located between adjacent semiconductor layers 201. Here, the remaining sacrificial layer 202 shown in fig. 6 may serve as a support for the semiconductor structure when the sacrificial layer 202 with exposed sidewalls is removed. Fig. 6 is a schematic cross-sectional view of a semiconductor structure including a first sub-fill region 311 along line AA 'and a schematic cross-sectional view along line BB' provided in an embodiment of the present disclosure.
A portion of the first dielectric layer 320 shown in fig. 7 may then be formed in the first sub-fill area 311 using a growth process or a deposition process, the material of the first dielectric layer 320 including, but not limited to, silicon oxide. The material of the first dielectric layer 320 may be the same as or different from the material of the third dielectric layer. A portion of the first dielectric layer 320 formed in the first sub-fill area 311 may also serve as a support for the semiconductor structure in a subsequent step. In embodiments of the present disclosure, the growth process includes, but is not limited to, in-situ vapor generation (In-Situ Steam Generation, ISSG). Fig. 7 is a schematic cross-sectional view of a semiconductor structure including a first dielectric layer 320 along line AA 'and a schematic cross-sectional view along line BB' according to an embodiment of the disclosure.
The remaining third dielectric layer is removed using an etching process to form a third recess 302 extending through the stacked structure as shown in fig. 7, the third recess 302 exposing the sidewalls of the remaining sacrificial layer 202.
Then, the remaining sacrificial layer 202 is removed through the third recess 302 using a wet etching process, forming a second sub-fill area 312 shown in fig. 8. In this embodiment, the first filling region includes the first sub-filling region 311 and the second sub-filling region 312 described above. Another portion of the first dielectric layer 320 may then be formed in the second sub-fill area 312 using a growth process or a deposition process. The semiconductor structure as shown in fig. 9 is finally formed. Fig. 8 is a schematic cross-sectional view of a semiconductor structure including a second sub-fill region 312 along line AA 'and along line BB' provided in an embodiment of the present disclosure.
Referring to fig. 1, step S50 is performed to remove at least a portion of each semiconductor layer in each initial sub-stack structure to form a second filling region.
In some embodiments, as shown in fig. 10, each of the initial sub-stacks 220 includes a first portion 101 located on the first region 110 and a second portion 102 extending onto the second region 120, at least one of two opposite sidewalls of the second portion 102 along the Y direction includes at least a curved surface, and two opposite sidewalls of the first portion 101 along the Y direction are planes parallel to the X direction. Fig. 10 is a top view of a semiconductor structure including a plurality of initial sub-stack structures 220 provided in an embodiment of the present disclosure.
In some embodiments, removing at least a portion of each semiconductor layer in each initial sub-stack structure in step S50 includes first removing at least a portion of each semiconductor layer 201 in each second portion along first recess 210 in fig. 11 using an etching process to form the semiconductor structure shown in fig. 12. Fig. 11 is a schematic cross-sectional view along line AA 'and a schematic cross-sectional view along line BB' of a semiconductor structure including a first recess 210 according to an embodiment of the present disclosure, and fig. 12 is a schematic cross-sectional view along line AA 'and a schematic cross-sectional view along line BB' of a semiconductor structure including a first recess 210 according to an embodiment of the present disclosure, with at least a portion of each semiconductor layer 201 removed in each second portion.
Fig. 11 and 12 also show bit line structure 400 and word line structure 500. The specific formation of the bit line structure 400 and the word line structure 500 will be described in detail in the following embodiments, and will not be described here.
In some embodiments, an etching process may be used to remove at least a portion of each semiconductor layer 201 in each of the initial sub-stack structures shown in fig. 11 in the X-direction and the Y-direction, and to leave a middle portion of each semiconductor layer 201 shown in fig. 12. In fig. 12, the intermediate portion of the remaining semiconductor layer is not visible. The semiconductor layer 201 is located between the first dielectric layers 320 adjacent in the Z direction, between the first dielectric layers 320 and the substrate 100, and between the third dielectric layers 310 adjacent in the Z direction and the first dielectric layers 320. The size of the semiconductor layer 201 etched in the X direction may be the same as or different from the size of the semiconductor layer 201 etched in the Y direction.
In some embodiments, a first recess extends through the stacked structure and into the substrate, and in step S50, removing at least a portion of each semiconductor layer in each initial sub-stacked structure to form a second fill region, comprising:
A portion of each semiconductor layer in each initial sub-stack structure and a portion of the substrate are removed to form a second fill region. Since the first grooves extend through the initial stacked structure and into the substrate, the substrate may be exposed, and when at least a portion of each semiconductor layer in each initial sub-stacked structure is removed through the first grooves, it is understood that the exposed portion of the substrate may also be removed by a certain thickness.
A metallization process is then performed on the semiconductor layer 201 remaining on the second region 120 to form a first connection structure 603 shown in fig. 13. The material used for the first connection structure 603 may be a metal silicide including, but not limited to, tiSi2 (titanium silicide), coSi2 (cobalt silicide), nickel alloys (e.g., ni-Pt, ni-Al, ni-Y) silicide, and the like.
A specific process of performing the metallization process on the semiconductor layer 201 remaining on the second region 120 in fig. 12 may be to deposit a metal (including but not limited to titanium, cobalt, and nickel) on the sidewall of the semiconductor layer 201 remaining on the second region 120, and then react the metal and the semiconductor layer 201 at a high temperature to obtain a metal semiconductor compound. When the material used for the semiconductor layer 201 is silicon and a compound thereof, a metal silicide can be obtained.
A vacuum thermal vapor method may be used, in which a mixed powder containing metals (including but not limited to titanium, cobalt, and nickel) is placed in a vacuum furnace, heated to a metal vapor temperature, and deposited on the side walls of the semiconductor layer 201 to form a metal semiconductor compound film, and when the material used for the semiconductor layer 201 is silicon or a compound thereof, a metal silicide film may be obtained.
The metal silicide has good conductivity and resistivity, and is suitable for being used as electrode material of a capacitor.
In some embodiments, step S50, performing a metallization process on the semiconductor layer remaining on the second region to form a first connection structure, includes:
after removing at least a portion of each semiconductor layer in each initial sub-stack structure, sidewalls of the semiconductor layer 201 remaining on the second region 120 shown in fig. 12 form a first metal layer (not shown).
Then, the semiconductor layer 201 remaining on the second region 120 and a portion of the first metal layer are formed together to form a first connection structure 603 through a heat treatment process. The heat treatment process may allow the metal material used for the first metal layer and the material of the semiconductor layer (e.g., silicon) to react at high temperature to obtain a metal silicide. The metal silicide may serve as the first connection structure 603.
In some embodiments, a first metal layer (not shown) may also be formed on the upper surface of the substrate 100 over the second region 120 shown in fig. 12. Then, the substrate 100 and the first metal layer thereon are formed together into a connection layer 604 shown in fig. 13 through a heat treatment process.
In some embodiments, there is also a remaining first metal layer that does not react with the semiconductor layer 603, which is removed to form the second fill region 720 shown in fig. 13. In some embodiments, there is also a first metal layer that is not reacted with the substrate 100, and this remaining first metal layer is removed. Conductive material may be subsequently deposited in the second filling region 720 to form a first sub-electrode layer and a second sub-electrode layer located at both sides of the first connection structure 603. Fig. 13 is a schematic cross-sectional view of a semiconductor structure including a second filling region along line AA 'and a schematic cross-sectional view along line BB' according to an embodiment of the disclosure.
Referring to fig. 1, step S60 is performed to form a first electrode layer in the second filling region to form a sub-stack structure.
In some embodiments, as shown in fig. 15, the first electrode layer 600 includes a first sub-electrode layer 601 and a second sub-electrode layer 602 arranged at intervals along the Y direction, and the first electrode layer further includes a first connection structure 603 between the first sub-electrode layer 601 and the second sub-electrode layer 602, i.e., the first electrode layer 600 may be a sandwich structure of the first sub-electrode layer 601, the first connection structure 603, and the second sub-electrode layer 602.
In some embodiments, the first electrode layer 600 shown in fig. 12a and 12b may be formed by filling the first conductive material in the second filling region 720 shown in fig. 13 using a growth process or a deposition process. The first conductive material includes, but is not limited to, metallic ruthenium (Ru), metallic tungsten (W), and metallic tantalum (Ta).
A specific process of forming the first electrode layer 600 may be to first deposit a first metal material in the second filling region 720, in the first recess 210, and on the third dielectric layer 310 as shown in fig. 13, to form the first metal material layer 700 as shown in fig. 14. Then, the first metal material layer 700 deposited in the first recess 210 and on the third dielectric layer 310 is removed, leaving the first metal material layer 700 deposited in the second filling region 720, forming the first sub-electrode layer 601 and the second sub-electrode layer 602 shown in fig. 15. The first sub-electrode layer 601, the first connection structure 603, and the second sub-electrode layer 602 together constitute the first electrode layer 600. Fig. 14 is a schematic cross-sectional view of a semiconductor structure including a first metal material along line AA 'and a schematic cross-sectional view along line BB' according to an embodiment of the present disclosure, and fig. 15 is a schematic cross-sectional view of a semiconductor structure including a first electrode layer along line AA 'and a schematic cross-sectional view along line BB' according to an embodiment of the present disclosure.
By filling the first electrode layer 600 in the second filling region 720, the stability of the semiconductor structure can be improved, and shorting between electrodes can be avoided.
In some specific examples, the semiconductor layer 603 on the second region may also be removed entirely, and the first metal material layer 700 may be filled in the region where the semiconductor layer 603 is removed, to form the first electrode layer 600.
In some embodiments, as shown in fig. 16a to 16d (fig. 16a to 16d are top views of a semiconductor structure including first sub-portions and second sub-portions alternately arranged provided in embodiments of the present disclosure), the sub-stack structure 103 includes first sub-portions 221 and second sub-portions 222 alternately arranged along the X direction, and at least one of two sidewalls of the first sub-portion 221 opposite along the Y direction and two sidewalls of the second sub-portion 222 opposite along the Y direction is a curved surface.
The outer wall profile of the sub-stack 103 may be identical to the outer wall profile of the initial sub-stack, and at least one of the sidewalls of the second portion 102 of the sub-stack 103 may comprise at least curved surfaces, which may be described with reference to fig. 4a to 4e, which are not repeated here.
For example, as shown in fig. 16a, two opposite sidewalls of the first sub-portion 221 along the Y direction are both planar, one of the two opposite sidewalls of the second sub-portion 222 along the Y direction is planar, and the other sidewall is curved.
As another example, as shown in fig. 16b, one of two opposite sidewalls of the first sub-portion 221 along the Y direction is a plane, the other sidewall is a curved surface, one of two opposite sidewalls of the second sub-portion 222 along the Y direction is a plane, and the other sidewall is a curved surface.
As shown in fig. 16c, the two opposite side walls of the first sub-portion 221 along the Y direction are both planar, and the two opposite side walls of the second sub-portion 222 along the Y direction are both curved.
As also shown in fig. 16d, both sidewalls of the first sub-portion 221 opposite in the Y direction include curved surfaces, and both sidewalls of the second sub-portion 222 opposite in the Y direction include curved surfaces. It should be noted that all of the above-mentioned curved surfaces are included, and that the single-finger side wall does not include only curved surfaces, but may be a combination of curved surfaces and flat surfaces.
Referring to fig. 1, step S70 is performed to form a second dielectric layer 801 conformally covering the outer wall of the sub-stack structure and the bottom wall of the first recess shown in fig. 17 and a second electrode layer 802 conformally covering the second dielectric layer 801 using a deposition process or a growth process. Fig. 17 is a schematic cross-sectional view of a semiconductor structure including a second dielectric layer 801 and a second electrode layer 802 along line AA 'and along line BB' provided in an embodiment of the present disclosure;
Here, the conformal coverage means that the shape of the second dielectric layer 801 and the second electrode layer 802 is the same as the shape of the outer wall of the sub-stack structure 103 and the shape of the bottom wall surface of the first recess 210 between the sub-stacks structure 103.
In some embodiments, the thickness of the second dielectric layer 801 and the second electrode layer 802 on the outer walls of the sub-stacks is the same as the thickness on the bottom wall of the first recess 210 between the sub-stacks.
The material of the second dielectric layer 801 includes, but is not limited to, a high dielectric constant material, which is a material having a dielectric constant higher than that of SiO2, typically, siO2 has a dielectric constant of 3.7.
The material of the second electrode layer 802 includes a conductive material including, but not limited to, metallic ruthenium (Ru), metallic tungsten (W), and metallic tantalum (Ta).
In some embodiments, the method of forming a semiconductor structure further includes forming a bit line structure and a word line structure. The process of forming the bit line structure and the word line structure in the embodiments of the present disclosure will be specifically described with reference to fig. 18 to 21.
In some embodiments, referring to fig. 18 and fig. 19 (fig. 18 is a schematic cross-sectional view along AA 'line of a semiconductor structure including a third filling region provided in an embodiment of the disclosure; fig. 19 is a schematic cross-sectional view along AA' line of a semiconductor structure including a bit line structure provided in an embodiment of the disclosure), a method for forming a semiconductor structure further includes:
A portion of each semiconductor layer 201 of each of the initial sub-stack structures on the first region 110 is removed from one side of the initial sub-stack structure on the first region 110, which is located on the side perpendicular to the X direction, using a side etching process, forming a third filling region 410 shown in fig. 18. I.e., etching a portion of each semiconductor layer 201 of each initial sub-stack structure located on the first region 110 from the side of the initial sub-stack structure.
In some embodiments, after forming the sub-stack structure, a portion of each semiconductor layer of the stack structure located on the first region may be etched from a side of the stack structure to form a third filling region.
Then, a bit line structure 400 is formed in the third filling region 410 using a deposition process or a growth process, and the bit line structure 400 is connected with the semiconductor layer 201 remaining on the first region 110.
The material used for the bit line structure 400 includes a conductive material, such as metal tungsten.
In some embodiments, the bit line structure may include bit line 403, adhesion layer 402, and bit line contact structure 401 shown in fig. 19. The process of forming the bit line structure 400 may include performing a metallization process on the remaining semiconductor layer 201 exposed from the third fill region 410 to form the bit line contact structure 401. The bit line contact structure 401 serves to reduce the contact resistance between the bit line 403 and a transistor subsequently formed in the semiconductor layer 201.
Continuing with the deposition process or the growth process, an adhesion layer 402 is formed on the sidewalls of the third fill region 410 where the bit line contact structure 401 is formed. The material of adhesion layer 402 includes, but is not limited to, titanium nitride. The adhesion layer 402 has good adhesion and can be used to adhere the bit line 403 to the bit line contact structure 401.
It should be noted that the bit line structure 400 may be formed before forming the capacitor, or may be formed after forming the capacitor, which is not limited by the embodiments of the present disclosure.
The deposition process or the growth process is continued to form the bit line 403 in the remaining third fill region 410. The material used for bit line 403 includes a conductive material including, but not limited to, tungsten.
In some embodiments, referring to fig. 18 and 20 (fig. 20 is a schematic cross-sectional view along line AA' of a semiconductor structure including a word line structure according to an embodiment of the disclosure), a method for forming a semiconductor structure further includes:
A plurality of transistors are formed using the remaining portion of each semiconductor layer 201 on the first region 110 shown in fig. 18, where the remaining portion refers to the semiconductor layer 201 that is not removed in the first region 110.
In some embodiments, the transistor may be formed first and then the bit line structure 400 may be formed. For example, after the third filling region 410 is formed, a doping process may be performed at both ends in the X direction to form a source electrode and a drain electrode, thereby forming a plurality of transistors, the semiconductor layer 201 between the source electrode and the drain electrode constituting a channel region of the transistor, the transistor being connected to the first electrode layer 600;
In some embodiments, the bit line structure 400 may be formed first, followed by the transistor. Ion implantation may be performed on both ends of the remaining portion of each semiconductor layer 201 on the first region 110 in the Z direction, where the concentrations of ions implanted into the semiconductor layers 201 of different depths may be the same.
In some embodiments, forming a plurality of word line structures 500 may further include forming a plurality of word line structures 500, the plurality of word line structures 500 arranged in the Y-direction, each word line structure 500 extending in a thickness direction of the substrate, one word line structure 500 being connected to channel regions of a plurality of transistors in one first portion. In some specific examples, one word line structure 500 may cover two sidewalls of the channel region of each transistor in one first portion that are opposite in the Y direction.
The process of forming the word line structure 500 may be to form a word line contact structure 501 on the upper surface of the third dielectric layer 310 shown in fig. 20 and the surfaces (not shown) where the channel regions of the plurality of transistors are exposed. The material of the word line contact structure 501 may be titanium nitride. Titanium nitride has good adhesion and can be used to adhere the third dielectric layer 310 to the word line 502.
Word line 502 then continues to be formed on word line contact structure 501. The material used for the word line 502 includes a conductive material, such as metal tungsten.
In some embodiments, a mask layer 503 may be further formed on the word line structure 500, and then, as shown in fig. 21 (fig. 21 is a schematic cross-sectional view along line AA' of the semiconductor structure including the mask layer provided in the embodiment of the disclosure), a plurality of first grooves may be formed by etching the mask layer 503, where at the interface between the first portion and the second portion, the sidewalls of the second portion may be covered with the third dielectric layer 310 or may not be covered with the third dielectric layer 310.
The portion of the mask layer 503 located on the first region 110 is preserved, and the preserved mask layer 503 may protect the word line structure 500 in a subsequent process.
It will be appreciated that the order of forming the transistor, forming the bit line structure 400, and forming the word line structure 500, and forming the capacitor described above may be adjusted according to actual processes. The order of formation of the above structures is not limited herein.
The embodiments of the present disclosure also provide a semiconductor structure that can be obtained by the method of forming a semiconductor structure in any of the foregoing embodiments, based on the same concept as the method of forming a semiconductor structure in the foregoing embodiments.
As shown in fig. 22 and 23, the semiconductor structure includes:
The substrate 100 and a stacked structure on the substrate 100, wherein the stacked structure comprises a first electrode layer 600 and a first dielectric layer 320 which are alternately stacked, the stacked structure comprises a plurality of sub-stacked structures 103, each sub-stacked structure 103 extends along a first direction, the plurality of sub-stacked structures 103 are arranged along a second direction, at least one of two opposite side walls of each sub-stacked structure 103 along the second direction at least comprises a curved surface, two opposite side walls of each sub-stacked structure 103 along the thickness direction of the substrate 100 are parallel to a plane of the substrate, the first direction intersects the second direction and is perpendicular to the thickness direction of the substrate, in the embodiment of the disclosure, the first direction can be an X direction, the second direction can be a Y direction, and the thickness direction of the substrate can be a Z direction.
A second dielectric layer 801 conformally covering the outer wall of each sub-stack structure 103 and the bottom surface of a first recess formed between two adjacent sub-stacks 103;
a second electrode layer 802 conformally covers the second dielectric layer 801.
Fig. 22 is a schematic cross-sectional view of a semiconductor structure along line AA 'and a schematic cross-sectional view along line BB' according to an embodiment of the present disclosure, and fig. 23 is a top view of the semiconductor structure according to an embodiment of the present disclosure.
In the technical scheme provided by the disclosure, the first electrode layer of the stacked structure can be used as a lower electrode of the capacitor, the second dielectric layer can be used as a dielectric layer of the capacitor, and the second electrode layer can be used as an upper electrode of the capacitor. In addition, at least one of the two opposite side walls of the sub-stack structure along the second direction at least comprises a curved surface, the area of the first electrode layer is enlarged relative to the fact that the two opposite side walls of the sub-stack structure along the second direction are both plane surfaces, the second dielectric layer is conformally covered on the outer wall of each sub-stack structure and the bottom surface of a first groove formed between the two adjacent sub-stack structures, the second electrode layer is conformally covered on the second dielectric layer, the area of the second dielectric layer and the area of the second electrode layer are correspondingly enlarged, the capacity of the capacitor is increased, and the storage capacity of the capacitor is improved.
In some embodiments, referring to fig. 10 and 22, the substrate 100 includes a first region 110 and a second region 120 arranged side by side in an X-direction, each sub-stack 103 includes a first portion 101 on the first region 110 and a second portion 102 extending onto the second region 120, the second portion 102 includes alternately stacked first electrode layers 600 and first dielectric layers 320, and the first portion 101 includes the first dielectric layers 320. The second dielectric layer 801 and the second electrode layer 802 are located between the adjacent second portions 102;
at least one of the two opposite side walls of the second portion 102 along the Y direction comprises at least a curved surface, and the two opposite side walls of the first portion 101 along the Y direction are planes parallel to the X direction.
In the embodiment of the disclosure, since the second dielectric layer 801 and the second electrode layer 802 are located between the adjacent second portions 102, at least one of two opposite sidewalls of the second portions 102 in the Y direction in the sub-stack structure includes at least a curved surface, which enlarges the area of the first electrode layer relative to the two opposite sidewalls of the second portions 102 in the Y direction in the sub-stack structure, and the second dielectric layer is formed by conformally covering the outer wall of each sub-stack structure and the bottom surface of the first groove formed between the adjacent two sub-stack structures, and the second electrode layer is formed by conformally covering the second dielectric layer, thereby enlarging the area of the second dielectric layer and the area of the second electrode layer, and increasing the capacity of the capacitor and the storage capacity of the capacitor.
In some embodiments, referring to fig. 16a to 16d, the sub-stack structure 103 includes first sub-portions 221 and second sub-portions 222 alternately arranged in the X-direction, and at least one of two sidewalls of the first sub-portion 221 opposite in the Y-direction and two sidewalls of the second sub-portion 222 opposite in the Y-direction is curved.
Fig. 16a to 16d show four schematic views of the sub-stack structure 103 including the first sub-portions 221 and the second sub-portions 222 alternately arranged in the X direction. Note that the top view of the sub-stack structure 103 is not limited thereto.
In the embodiment of the disclosure, by arranging at least one of two opposite side walls of the first sub-portion 221 and two opposite side walls of the second sub-portion 222 along the Y direction to be curved, the area of the first electrode layer is enlarged compared with the situation that at least one of the two opposite side walls of the first sub-portion 221 and the two opposite side walls of the second sub-portion 222 along the Y direction is arranged to be flat, the second dielectric layer is formed to cover the outer wall of each sub-stack structure and the bottom surface of the first groove formed between the two adjacent sub-stacks, the second electrode layer is formed to cover the second dielectric layer, so that the area of the second dielectric layer and the area of the second electrode layer are correspondingly enlarged, the capacity of the capacitor is increased, the storage capacity of the capacitor is improved, and in the second aspect, as at least one of the two opposite side walls of the sub-stack structure along the second direction at least comprises the curved surface, more space is reserved for the second electrode layer and the first dielectric layer, the integration degree of the semiconductor structure can be improved, and the distance between the adjacent electrodes along the second direction can be reduced.
In some embodiments, referring to fig. 16 a-16 d, the curved surface is parallel to the thickness direction of the substrate 100, and the curved surface is concave toward the other sidewall of the sub-stack 103 opposite in the Y-direction. Compared with the other side wall of the curved surface convex sub-stack structure 103 opposite along the Y direction, in the embodiment of the disclosure, the curved surface concave sub-stack structure 103 is arranged on the other side wall opposite along the Y direction, so that the implementation in an actual process is easier, and the process difficulty is reduced. Of course, it is also optional to project the curved surface toward the other side wall opposite to the sub-stack structure 103 in the Y direction.
In some embodiments, referring to FIGS. 22 and 23, the first portion 101 further comprises a plurality of transistors 800, each transistor 800 being located between two adjacent first dielectric layers 320 in the first portion 101, each transistor 800 comprising a source and a drain at opposite ends in the X direction, a channel region located between the source and the drain;
A plurality of word line structures 500, each word line structure 500 extending in the thickness direction of the substrate 100, one word line structure 500 being connected to the channel regions of a plurality of transistors 800 in one first portion 101.
In some embodiments, referring to FIGS. 22 and 23, the first portion 101 further includes a plurality of bit line structures 400, each bit line structure 400 extending along the Y-direction, and each bit line structure 400 being located between two adjacent first dielectric layers 320 along the Z-direction, being connected to the sources or drains of a plurality of transistors 800 in one layer, the transistors 800 being connected to the first electrode layer 600.
In the embodiment of the present disclosure, the first region 110 further includes a plurality of word line structures 500, a plurality of bit line structures 400, and a plurality of transistors 800 thereon. A plurality of transistors 800 of one layer are connected to the same bit line structure 400. Here, one layer means being located on the same XY plane. A column of multiple transistors 800 is connected to the same word line structure 500, where a column refers to being in the same XZ plane.
By applying the corresponding operation voltages to the word line structure 500, the bit line structure 400, various operations such as a program operation, a read/write operation, and an erase operation to the transistor 800 and the capacitor can be realized.
In some embodiments, referring to fig. 22, each of the first electrode layers 600 in each of the sub-stack structures 103 includes first and second sub-electrode layers 601 and 602 arranged at intervals in the Y direction, and the first electrode layer 600 further includes a first connection structure 603 between the first and second sub-electrode layers 601 and 602.
The first electrode layer 600 in the embodiments of the present disclosure may be a sandwich structure of the first sub-electrode layer 601, the first connection structure 603, and the second sub-electrode layer 602. The material used for the first connection structure 603 may be a metal silicide for reducing contact resistance of the sub-electrode layers (including the first sub-electrode layer 601 and the second sub-electrode layer 602) and the active pillars.
The above semiconductor structure is described in detail on the side of the method for forming the semiconductor structure, and will not be described herein.
The methods disclosed in the several method embodiments provided in the present disclosure may be arbitrarily combined without collision to obtain a new method embodiment.
The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure.