Detailed Description
It should be noted that the following detailed description is illustrative and is intended to provide further explanation of the application. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the present application. As used herein, the singular is also intended to include the plural unless the context clearly indicates otherwise, and furthermore, it is to be understood that the terms "comprises" and/or "comprising" when used in this specification are taken to specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Furthermore, in the description and in the claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
As described in the background art, the problem that the high-efficiency heat dissipation requirement caused by the ultra-high density transistor in the chip in the prior art is difficult to meet is solved, and the embodiment of the application provides an embedded heat dissipation structure and a preparation method thereof.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.
According to an embodiment of the present application, as shown in fig. 11, an in-cell heat dissipation structure is provided, wherein the in-cell heat dissipation structure includes a base 10, a plurality of micro pillars 20, and a metal liquid 30, the base 10 includes a first substrate 101 and a second substrate 102, the first substrate 101 and the second substrate 102 enclose a cavity, the micro pillars 20 are spaced apart from each other in the cavity of the base 10, at least a portion of one end of the micro pillars 20 is in contact with the first substrate 101, the metal liquid 30 is located in the cavity, and the metal liquid 30 is in contact with the base 10 and the micro pillars 20, respectively.
The embedded heat dissipation structure comprises a substrate, a plurality of micro pillars and metal liquid, wherein the substrate comprises a first substrate and a second substrate, the first substrate and the second substrate are enclosed to form a cavity, the micro pillars are distributed in the cavity of the substrate at intervals, at least one end of each micro pillar is in contact with the first substrate, the metal liquid is located in the cavity, and the metal liquid is respectively in contact with the substrate and the micro pillars. Compared with the problem that the high-efficiency heat dissipation requirement caused by the ultra-high density transistor in the chip in the prior art is difficult to meet, the embedded heat dissipation structure comprises the substrate, the micron columns and the metal liquid, so that the heat dissipation function can be realized through the flow of the metal liquid, and the problem that the high-efficiency heat dissipation requirement caused by the ultra-high density transistor in the chip in the prior art is difficult to meet due to the fact that the motion viscosity of the metal liquid and the substrate is smaller in the flow process of the metal liquid is solved, the small resistance of the metal liquid in the flow process is further ensured, the speed of the metal liquid is ensured to be larger, and the heat dissipation effect of the embedded heat dissipation structure is ensured to be better due to the positive correlation between the heat dissipation capability and the motion speed of the metal liquid.
In the implementation process, the micrometer columns imitate lotus leaf structures in nature, namely a sparse array formed by a large number of micrometer-scale synapse structures on the surfaces.
In a specific implementation process, the coverage rate of the micro pillars on the surface of the first substrate ranges from 6% to 14%. Because the coverage rate range of the micro pillars on the surface of the first substrate is 6% -14%, the dynamic viscosity of the liquid metal can be obviously reduced within the coverage rate range, and the fluidity of the liquid metal is further enhanced to improve the overall heat dissipation performance, so that the heat dissipation effect of the embedded heat dissipation structure is further ensured to be better.
In the implementation, the coverage of the micro pillars on the first substrate surface is preferably 8.5%. Of course, in the practical application process, the micrometer columns with different coverage rates can be prepared, and the optimal coverage rate can be obtained through experimental tests.
In order to further ensure that the heat dissipation effect of the embedded heat dissipation structure is better, the material of the micro-column comprises gallium nitride, the material of the substrate comprises silicon, and the material of the metal liquid comprises gallium. Since the material of the micrometer post comprises gallium nitride and the material of the metal liquid comprises gallium, namely gallium passing through the liquid is used as flowing metal, the excellent physicochemical properties of high thermal conductivity (50.75W/(m.K)), high boiling point (2403 ℃) and low melting point (15.5 ℃), low thermal expansion coefficient (< 7.5X10-5 PPM% @ -65-350 ℃) and diamagnetism (-21.6X10-6cm3/mol@290K) are further ensured, and the radiating effect of the embedded radiating structure is better.
In the implementation process, the heat dissipation performance of the embedded heat dissipation structure is mainly influenced by the property of the heat transfer working medium and the speed of the embedded cavity, and the power source of the heat transfer working medium moving in the embedded cavity in the passive heat dissipation structure is mainly the marangoni effect, namely, the surface tension difference of the liquid metal is caused by the solid surface temperature difference, so that the liquid metal is driven to flow. However, if the micro-pillars are not arranged, that is, the high kinematic viscosity of the liquid metal gallium on the silicon interface prevents the speed of the liquid metal gallium from being increased, so that the overall heat dissipation capacity is weakened, and the general heat dissipation efficiency of the conventional liquid metal planar heat pipe passive heat dissipation structure is low. By arranging the micrometer columns, the resistance of the liquid gallium metal in the movement process is reduced, and the heat dissipation effect of the embedded heat dissipation structure is further ensured to be good.
In the prior art, two main types of heat-dissipating working media are adopted by a planar heat pipe type passive embedded liquid cooling scheme. Common substances with low boiling point and low viscosity such as water, ethanol, FC770 and the like are used as embedded liquid cooling working mediums, and although the related working mediums have the advantages of low price, mature property research and the like, the physical properties of the working mediums cannot fully meet the process compatibility test in the actual engineering processes of microsystem packaging processes (200-400 ℃), operating environments (-65-150 ℃), repairing processes (100-200 ℃), and the like. The excellent physical and chemical properties of gallium, such as high thermal conductivity (50.75W/(m.K)), high boiling point (2403 ℃), low melting point (15.5 ℃), low thermal expansion coefficient (< 7.5X10-5 PPM% @ -65-350 ℃), diamagnetism (-21.6X10-6cm3/mol@290K) and the like, ensure that the liquid metal can meet the process compatibility test in the practical engineering process.
In a specific implementation process, the section shape of the micro-column along the direction perpendicular to the extending direction comprises a regular quadrangle.
In the implementation process, the micrometer columns are regular quadrangular columns.
Of course, the cross-sectional shape of the micro-pillars along the direction perpendicular to the extending direction is not limited to a regular quadrangle, and in the practical application process, the micro-pillars with different cross-sectional shapes can be prepared, and then the cross-sectional shape with the optimal heat dissipation capability can be determined through practical test and/or theoretical test.
In a specific embodiment, the distance between two adjacent micropillars is in the range of 12 micrometers to 17.83 micrometers, the length of the micropillars is in the range of 8 micrometers to 12 micrometers, and the length of the cavities in the extension direction of the micropillars is in the range of 80 micrometers to 110 micrometers.
In the implementation process, the side length of the regular quadrangle corresponding to the micrometer column is preferably 2 micrometers, and the length of the micrometer column is preferably 10 micrometers.
Of course, the distance between the micro pillars, the length of the micro pillars, and the length of the cavities in the extending direction of the micro pillars are not limited to the above ranges, and structures with different lengths can be prepared in the practical application process, and then the length, the distance, and the height of the cavities of the micro pillars with optimal heat dissipation capability are determined through practical tests and/or theoretical tests, wherein the height of the cavities needs to be satisfied to be greater than the length of the micro pillars.
According to the embodiment of the application, a preparation method of an embedded heat dissipation structure is provided.
Fig. 12 is a flowchart of a method for manufacturing an embedded heat dissipation structure according to an embodiment of the application. As shown in fig. 12, the method includes the steps of:
Step S1201, as shown in fig. 1, providing a first substrate 101 and a preliminary substrate 103;
Specifically, the materials of the first substrate and the preparation substrate include silicon, the first substrate and the preparation substrate need to be subjected to double-sided polishing of a silicon wafer, and the processes of standard organic cleaning, acetone ultrasonic, isopropanol ultrasonic, deionized water ultrasonic, nitrogen blow-drying and the like are sequentially performed.
Step S1202, as shown in fig. 2, forming a plurality of micrometer posts 20 on the surface of the first substrate 101 at intervals;
Specifically, the coverage of the micro pillars on the first substrate surface is in the range of 6% -14%, preferably 8.5%, and the material of the micro pillars includes gallium nitride.
Step S1203, as shown in fig. 1 to 3, removing a part of the preliminary substrate 103 to form a first trench 40, and forming a second substrate 102 on the remaining preliminary substrate 103;
Specifically, by removing a portion of the preliminary substrate, not only the first trench but also a plurality of silicon pillars disposed at intervals are formed in the trench, and subsequently the second trench is formed by removing a portion of the silicon pillars in the second substrate, that is, the insulating layer, the barrier layer, and the metal layer are all located in the second trench in the silicon pillars, wherein the thickness of the preliminary substrate includes 350 micrometers, the first trench is formed by deep reactive ion etching, and the depth of the first trench includes 100 micrometers, and of course, the specific thickness is not limited and is determined according to practical situations.
Step S1204, as shown in fig. 2 to 4, bonding the first substrate 101 and the second substrate 102 such that the first trench 40 and the first substrate 101 form a cavity, the microcolumn 20 is located in the cavity, and the first substrate 101 and the second substrate 102 form a base 10;
Specifically, by bonding the first substrate and the second substrate, the silicon pillars in the second substrate are in contact with the first substrate, that is, there are a plurality of silicon pillars disposed at intervals between bottoms of the first substrate and the second substrate.
Step S1205, filling a metal liquid into the cavity, wherein the metal liquid is respectively contacted with the substrate and the micro-pillars.
Specifically, the above-mentioned metal liquid includes gallium.
The preparation method of the embedded heat dissipation structure comprises the steps of providing a first substrate and a preparation substrate, forming a plurality of micrometer posts distributed at intervals on the surface of the first substrate, removing part of the preparation substrate to form a first groove, forming the rest of the preparation substrate to form a second substrate, bonding the first substrate and the second substrate to enable the first groove and the first substrate to form a cavity, enabling the micrometer posts to be located in the cavity, enabling the first substrate and the second substrate to form a base, and finally filling metal liquid into the cavity, wherein the metal liquid is respectively in contact with the base and the micrometer posts. Compared with the problem that the high-efficiency heat dissipation requirement caused by the ultrahigh-density transistor in the chip in the prior art is difficult to meet, the preparation method of the embedded heat dissipation structure of the application comprises the steps of firstly forming the first substrate and the micron columns arranged on part of the surface of the first substrate at intervals, then forming the second substrate with grooves, forming the cavity through bonding, and enabling the micron columns to be positioned in the cavity, and finally filling the metal liquid into the cavity, so that the heat dissipation function can be realized through the flow of the metal liquid, and the problem that the high-efficiency heat dissipation requirement caused by the ultrahigh-density transistor in the chip in the prior art is difficult to meet is solved because the micron columns distributed at intervals are arranged in the cavity, the movement viscosity of the metal liquid and the substrate is smaller in the flow process of the metal liquid, so that the resistance of the metal liquid in the flow process is smaller, the speed of the embedded heat dissipation structure is ensured to be larger, and the heat dissipation effect of the embedded heat dissipation structure is better because the heat dissipation capability and the movement speed of the metal liquid are positively correlated.
In order to further ensure that the embedded heat dissipation structure has good heat dissipation effect, forming a plurality of micron posts distributed at intervals on at least part of the surface of the first substrate comprises forming a semiconductor layer on the surface of the first substrate, and removing part of the semiconductor layer to form a plurality of micron posts distributed at intervals. The semiconductor layer is formed on the surface of the first substrate, and part of the semiconductor layer is removed, so that a plurality of micro pillars distributed at intervals are formed on the rest of the semiconductor layer, namely, the coverage rate of the micro pillars on the surface of the first substrate is controlled, so that the resistance of the liquid metal in the flowing process is minimum, and the good heat dissipation effect of the embedded heat dissipation structure is further ensured.
In the implementation process, the semiconductor layer is formed by means of molecular beam epitaxy, chemical vapor phase substrate and the like, and the thickness of the semiconductor layer includes 10 micrometers, and of course, the specific thickness is not limited and is determined according to practical situations. The semiconductor layer is partially removed by processing a patterned photolithography plate arranged by gallium nitride columns, first, photoresist spin coating is used, then photolithography is performed by using a photolithography machine to form a heterogeneous graphical interface, so as to obtain a plurality of spaced micrometer columns, and in addition, a plurality of micrometer columns can be formed at a position other than the first substrate, and the method can be specifically determined according to practical situations.
In one embodiment, after bonding the first substrate and the second substrate, the method further comprises treating a surface of the first substrate remote from the micro pillars using a chemical mechanical polishing process such that a thickness of the treated first substrate is within a predetermined range. And removing part of the first substrate through a chemical mechanical mask process, so that the thickness of the rest of the first substrate is smaller, and the rest of the first substrate is ensured to meet the thickness requirement of the subsequent formation of TSVs (Through Silicon Via, through silicon vias).
In the implementation process, the thickness of the first substrate after the chemical mechanical mask is 50 micrometers, and of course, the specific thickness is not limited and is determined according to practical situations.
In the specific implementation process, before the metal liquid is filled into the cavity, the method further includes removing a portion of the first substrate 101 and a portion of the second substrate 102, as shown in fig. 4 and fig. 5, to form a plurality of second trenches 50 spaced apart from each other, where the second trenches 50 expose a portion of the second substrate 102, forming a stacked insulating layer 60, barrier layer 70, and metal layer 80 in the second trenches 50, as shown in fig. 5 to fig. 6, to obtain through-silicon-vias, where the insulating layer 60 covers the surface of the second trenches 50, removing a portion of the second substrate 102, and leaving a thickness of the remaining second substrate 102 around 150 micrometers, as shown in fig. 6 to fig. 7, where the specific thickness is not limited, and is determined according to practical situations, to expose the through-silicon-vias. And removing part of the first substrate and part of the second substrate, namely removing part of silicon pillars in the middle of the first substrate and the second substrate, forming a plurality of second grooves which are arranged at intervals, exposing part of the silicon pillars by the second grooves, and forming the laminated insulating layer, barrier layer and metal layer in the second grooves, so that the metal layer and silicon in the second substrate can be isolated by the insulating layer, direct current leakage of the metal layer is prevented, static consumption is reduced, the barrier layer can further prevent metal in the metal layer from entering the second substrate, simultaneously the barrier layer can also improve the adhesiveness between the metal layer and the insulating layer, and the connection is realized by the metal layer, thereby ensuring that the embedded heat dissipation structure can realize connection with other structures.
Of course, the embedded heat dissipation structure is not limited to be applied to the TSV, but may be applied to other structures.
In the implementation process, the material of the insulating layer includes silicon dioxide, the material of the barrier layer includes titanium or titanium nitride, and the material of the metal layer includes copper. Of course, the materials of the insulating layer, the barrier layer, and the metal layer may be other materials having the same properties according to actual conditions.
In addition, after removing part of the second substrate and before filling the cavity with the metal liquid, the method further includes forming metal connection structures 110, as shown in fig. 7 to 8, where the metal connection structures 110 are located at two ends of the through silicon via, and the metal connection structures 110 cover part of the surfaces of the first substrate 101 and the second substrate 102, that is, RDL (Re Distribution Layer ) process.
In order to further ensure the good heat dissipation effect of the embedded heat dissipation structure, the metal liquid is filled into the cavity, which includes removing a part of the first substrate 101 and a part of the micro pillars 20 as shown in fig. 8 to 9, forming a filling hole 90, wherein the filling hole 90 exposes the cavity, as shown in fig. 9 to 10, and in a predetermined gas atmosphere including nitrogen, other gases may be selected, and the metal liquid 30 is filled into the cavity through the filling hole 90, as shown in fig. 10 to 11, and the adhesive 100 is filled into the filling hole 90. The metal liquid can be filled into the cavity through the filling hole by removing part of the first substrate and part of the micron column, and the filling process is realized under the preset gas atmosphere, so that the preset gas exists between the metal liquid and the substrate, the flowing resistance of the metal liquid is further ensured to be smaller, and the radiating effect of the embedded radiating structure is further ensured to be better.
In the implementation process, the adhesive comprises a high-temperature ceramic adhesive, so that firm connection between the liquid metal and the TSV adapter plate is ensured, and then the ceramic adhesive is completely cured by curing at the curing temperature of 200 ℃ so as to ensure stable connection and encapsulation effect. Specifically, since the cavities around the TSV are communicated, the metal liquid can be poured into the whole cavity through one of the hole-filling holes, so that the number of the hole-filling holes can be one or a plurality of hole-filling holes can be provided, and the hole-filling holes can be determined according to actual situations.
In addition, the embedded heat dissipation structure disclosed by the application not only can expose the nano-scale silicon surface, but also can restrict partial nitrogen used in filling the planar heat pipe in the structural gap, so that the liquid metal can be ensured to obtain enough heat energy from the surface of the high-wettability micro-column, and meanwhile, the drag reduction efficiency of the low-wettability gap can be maintained, so that an excellent heterogeneous interface super-wettability thermal sliding effect is realized.
Examples
The process of confirming the above-described optimal coverage of the liquid metal will be described below with reference to fig. 13 to 16.
Fig. 13 is a schematic diagram illustrating the surface state of an interface, in which fig. 13 (a) and fig. b) respectively show the contact condition of a droplet and the interface when uniformly infiltrating and non-uniformly infiltrating, the contact area of the droplet and the interface is smaller, the sliding resistance of the droplet is supposedly lower in the aspect of being inductively estimated, and the direction is further provided for the subsequent calculation, fig. 14 is a graph based on a multi-body dissipation particle dynamics model, in which the sliding resistance of the interface is minimum, based on a multi-body dissipation particle dynamics model, the sliding resistance of the interface is illustrated by a graph based on a sliding-mass-particle dynamics model (Lammps) (Large-scale atomic molecule parallel Simulator), in which the sliding resistance of the droplet is greater than the sliding resistance of the interface is greater than the silicon nitride in the opposite direction, in which the sliding resistance of the droplet is greater than the silicon nitride in the aspect of the interface is greater than the longitudinal direction, and in which the sliding resistance of the droplet is greater than the silicon nitride in the aspect of being estimated by a graph based on a sliding-mass-dissipation particle dynamics model (Large scale of Lammps) (i.e., the ratio of the gallium nitride column is greater than the total area is greater than the silicon nitride) from top to bottom, and the ratio of the total area of the gallium nitride column is 0% is 0.5%, respectively seen from top to bottom. Therefore, we obtain that the optimal interval of coverage of the gallium nitride column is 6% -14% from the figure, and fig. 16 is a schematic diagram of the structure of the interposer of the embedded heat dissipation structure applied to the chip.
First, to better illustrate the principles of how the present invention achieves drag reduction gains. It should be understood that the wettability of the droplet may be in one of two states on the surface of the nanostructure, i.e., uniform or non-uniform wettability, as shown in fig. 13, and the structural relationship among the metal liquid Ga, the microcolumn GaN, and the first substrate Si is the case where the metal liquid Ga, the microcolumn GaN, and the first substrate Si are Ga. For uniform infiltration, as in (a) of fig. 13, the liquid Ga fully impregnates the nanostructures, while for non-uniform infiltration, as in (b) of fig. 13, there is gas (nitrogen) trapped in the nanostructure gap between the surface and the droplet Ga surface. These two states are referred to as the Wenzel state and the Cassie state, respectively. The contact angle of a droplet in the Wenzel state can be given by the Wenzel equation, cos θW＝rcosθY,θY is the young contact angle of droplet Ga under a smooth surface, and r is the roughness ratio, which is the ratio of the real area of the solid surface to its projected area. As can be seen from the Wenzel equation, if the surface is non-wetting (θY > 90), the roughness (r > 1) will cause the contact angle θW to be greater than the Young's contact angle θY. If the surface is wetted (θY <90 °), the roughness (r > 1) will cause the contact angle θW to be less than the young contact angle θY. For a droplet in the Cassie state, the contact angle is given by the Cassie-Baxter equation, cosθCB＝rfcosθY +f-1# (3-10), where f is the wetted portion of the projected area and rf is the roughness ratio of the wetted area;
Then, as shown in fig. 14, in the case where the metal liquid is Ga, the micro-pillars are GaN, and the first substrate is Si, in order to further explore the effect of interface roughness on the sliding resistance of the liquid droplets, an optimal hetero-interface occupation area ratio is found, that is, an optimal value of coverage of the micro-pillars GaN on the first substrate is determined, so that the moving distance of the metal liquid Ga is the farthest, and we simulate the sliding resistance of the micro-pillars gallium nitride layer on the first substrate silicon and the micro-pillars gallium nitride layer with different surface roughness nanostructures, respectively, by using a mesoscopic MDPD (Multi-PARTICLE DISSIPATIVE PARTICLE DYNAMICS, multi-body dissipative particle dynamics) model, and compare the sliding resistance of the micro-pillars gallium nitride layer with different roughness to the metal liquid gallium droplet. The simulation results are shown in fig. 14 and 15. Fig. 14 (a) shows the case where the micro-pillar gallium nitride is not provided, and in addition, when the coverage rate of the micro-pillar gallium nitride of the epitaxial nanostructure is less than 2.5%, as shown in fig. 14 (b), the metal liquid gallium droplet is in a surface slip state of the micro-pillar gallium nitride coverage density of the nanostructure, the metal liquid gallium droplet is in a Wenzel state in a low-roughness solid-liquid interface infiltration state, in this state, a large contact area exists between the metal liquid gallium droplet and the silicon surface, and a slip drag reduction effect cannot be obtained, and when the coverage density of the micro-pillar gallium nitride of the epitaxial nanostructure is more than 2.5%, the solid-liquid interface slip state of the metal liquid gallium droplet is in a Cassie state. When the nano-structure is in 6% -14% of the coverage density of the micro-pillar gallium nitride, as shown in fig. 14 (c), the metal liquid gallium drops are in a surface slip state of 8.5% of the nano-structure and in a super-infiltration slip region, the slip resistance can be reduced to 20% of the silicon surface, when the epitaxial nano-structure is in a higher coverage density, the interface of the nano-pillar gallium nitride is close to the pure gallium nitride surface, the high wettability of the micro-pillar gallium nitride to the metal liquid gallium can cause the slip resistance to be 3.5 times greater than that of the silicon surface, as shown in fig. 14 (d), as shown in fig. 14 (a), (b) and (d), the corresponding distance covering 8.5% of the metal liquid is furthest, namely the resistance is minimum, therefore, the coverage rate of the micro-pillar on the first substrate is selected to be the optimal 8.5%;
thereafter, as shown in FIG. 15, in the case where the metal liquid is Ga, the microcolumn is GaN, and the first substrate is Si, the ordinate isIn order to further verify the effectiveness of micro mesoscopic simulation results macroscopically, the sliding resistance of the nano-structure gallium nitride heterogeneous interface in the non-uniform infiltration Cassie state obtained through mesoscopic super-infiltration MDPD model simulation can be converted into a kinematic viscosity coefficient when gallium drops slide on a medium-roughness silicon substrate. Further, in the constructed macroscopic hetero-interface super-infiltration thermal slip FEM model, when the gallium drops are in a 20 ℃ per mm thermal gradient environment, the steady-state thermal slip speeds of the gallium drops on the gallium nitride, silicon and medium-roughness nano-structure gallium nitride surfaces are 0.008m/s, 0.15m/s and 1.8m/s respectively. In summary, when the proportion of the gallium nitride heterogeneous interface to the total area is 6% -14%, the sliding resistance of the liquid metal on the interface can be effectively reduced, the highest speed of the liquid metal under the driving of the marangoni effect is improved, and the overall heat transfer capacity is further enhanced;
Finally, a schematic diagram of the application of the heterogeneous interface to the passive heat dissipation structure is shown in fig. 16, which takes a high-performance CPU chip embedded cavity interposer as an example. The left diagram in fig. 16 is a schematic structural diagram of a heterogeneous interface embedded liquid-cooled heat dissipation structure, which includes a TSV part, a CPU chip, a RAM chip, the first substrate 101 and a plurality of the micro pillars 20, wherein the enlarged diagrams of the first substrate 101 and the plurality of the micro pillars 20 are shown in the right diagram, and the area is composed of a silicon substrate (the first substrate 101) and a gallium nitride pillar array (the plurality of the micro pillars 20), and the proportion of the gallium nitride pillar array in the schematic structural diagram to the total area of the silicon substrate is 8.5%.
In addition, fig. 17 shows a schematic structural diagram of the first substrate and a plurality of the micro pillars, and as can be seen from fig. 17, a plurality of the micro pillars 20 are arranged in an array on the surface of the first substrate 101. Of course, the plurality of the foregoing micro pillars are not limited to the array arrangement, and specifically, the distance between any two adjacent foregoing micro pillars may be different according to practical situations, and the shapes of the different foregoing micro pillars may also be different.
In the foregoing embodiments of the present invention, the descriptions of the embodiments are emphasized, and for a portion of this disclosure that is not described in detail in this embodiment, reference is made to the related descriptions of other embodiments.
From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:
1) The embedded heat dissipation structure comprises a substrate, a plurality of micro pillars and metal liquid, wherein the substrate comprises a first substrate and a second substrate, the first substrate and the second substrate are enclosed to form a cavity, the micro pillars are distributed in the cavity of the substrate at intervals, at least one end of each micro pillar is in contact with the first substrate, the metal liquid is located in the cavity, and the metal liquid is respectively in contact with the substrate and the micro pillars. Compared with the problem that the high-efficiency heat dissipation requirement caused by the ultra-high density transistor in the chip in the prior art is difficult to meet, the embedded heat dissipation structure comprises the substrate, the micron columns and the metal liquid, so that the heat dissipation function can be realized through the flow of the metal liquid, and the problem that the high-efficiency heat dissipation requirement caused by the ultra-high density transistor in the chip in the prior art is difficult to meet due to the fact that the motion viscosity of the metal liquid and the substrate is smaller in the flow process of the metal liquid is solved, the small resistance of the metal liquid in the flow process is further ensured, the speed of the metal liquid is ensured to be larger, and the heat dissipation effect of the embedded heat dissipation structure is ensured to be better due to the positive correlation between the heat dissipation capability and the motion speed of the metal liquid.
2) The method for manufacturing the embedded heat dissipation structure comprises the steps of providing a first substrate and a preparation substrate, forming a plurality of micrometer posts distributed at intervals on the surface of the first substrate, removing part of the preparation substrate to form a first groove, forming a second substrate by the rest of the preparation substrate, bonding the first substrate and the second substrate to enable the first groove and the first substrate to form a cavity, enabling the micrometer posts to be located in the cavity, enabling the first substrate and the second substrate to form a base, and finally filling metal liquid into the cavity, wherein the metal liquid is respectively contacted with the base and the micrometer posts. Compared with the problem that the high-efficiency heat dissipation requirement caused by the ultrahigh-density transistor in the chip in the prior art is difficult to meet, the preparation method of the embedded heat dissipation structure of the application comprises the steps of firstly forming the first substrate and the micron columns arranged on part of the surface of the first substrate at intervals, then forming the second substrate with grooves, forming the cavity through bonding, and enabling the micron columns to be positioned in the cavity, and finally filling the metal liquid into the cavity, so that the heat dissipation function can be realized through the flow of the metal liquid, and the problem that the high-efficiency heat dissipation requirement caused by the ultrahigh-density transistor in the chip in the prior art is difficult to meet is solved because the micron columns distributed at intervals are arranged in the cavity, the movement viscosity of the metal liquid and the substrate is smaller in the flow process of the metal liquid, so that the resistance of the metal liquid in the flow process is smaller, the speed of the embedded heat dissipation structure is ensured to be larger, and the heat dissipation effect of the embedded heat dissipation structure is better because the heat dissipation capability and the movement speed of the metal liquid are positively correlated.
The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.