Disclosure of Invention
In view of the above, the present application provides a sub-threshold circuit timing optimization method and related apparatus to optimize timing convergence of a sub-threshold circuit. The specific scheme is as follows:
the first aspect of the present application provides a sub-threshold circuit timing optimization method, comprising:
Performing time sequence analysis on the data input and output paths of each trigger in the sub-threshold circuit, and identifying paths which do not meet the requirement of the set-up time or the retention time;
The method comprises the steps of setting up a data input end of a trigger, and setting up a time requirement and a data input end of the trigger, wherein the data input end of the trigger is connected with a data input end of a combined circuit;
For paths which do not meet the requirement of the holding time but meet the requirement of the establishing time, carrying out time sequence optimization on the paths by adopting a mode of increasing the delay of input data between the output end of the combined circuit and the data input end of the trigger;
For paths which do not meet the requirements of the holding time and do not meet the requirements of the setting time, the paths are divided into four types of sub-paths, the first type of sub-paths are sub-paths which do not meet the requirements of the setting time but meet the requirements of the holding time, the second type of sub-paths are sub-paths which do not meet the requirements of the holding time but meet the requirements of the setting time, the third type of sub-paths are sub-paths which do not meet the requirements of the holding time and do not meet the requirements of the setting time, the fourth type of sub-paths are sub-paths which meet the requirements of the holding time and the requirements of the setting time at the same time, the first type of sub-paths are subjected to time sequence optimization in a feedback equalization mode among all logic units which only belong to the first type of sub-paths, the second type of sub-paths are subjected to time sequence optimization in a mode of increasing input data delay among all logic units which only belong to the third type of sub-paths, and the third type of sub-paths are subjected to time sequence optimization in a mode of feedback equalization and increasing input data delay.
In one possible implementation, the performing timing optimization on the path between the output terminal of the combining circuit and the data input terminal of the flip-flop by adopting a feedback equalization mode includes:
Disconnecting the output of the combining circuit from the data input of the flip-flop;
A feedback equalizer is inserted between the output of the combining circuit and the data input of the flip-flop, whereby the output of the combining circuit is connected to the data input of the feedback equalizer, the data output of the feedback equalizer is connected to the data input of the flip-flop, and the data output of the flip-flop is connected to the feedback input of the feedback equalizer.
In one possible implementation, the method for performing timing optimization on paths between the output end of the combining circuit and the data input end of the flip-flop in a feedback equalization manner further includes:
A schmitt trigger is inserted between the data output of the feedback equalizer and the data input of the trigger such that the input of the schmitt trigger is connected to the data output of the feedback equalizer and the output of the schmitt trigger is connected to the data input of the trigger.
In one possible implementation, the clock input end of the trigger adopts a clock delay mode to perform time sequence optimization on the path, and the method comprises the steps of adding a delay circuit at the clock input end of the trigger;
The delay circuit comprises a PMOS capacitor or an NMOS capacitor, wherein when the MOS capacitor is the NMOS capacitor, the grid electrode of the NMOS capacitor is connected with the clock input end of the trigger, and the semiconductor substrate of the NMOS capacitor is grounded;
Or the delay circuit comprises a logic unit with the same input signal and output signal, wherein the input end of the logic unit is connected with the clock input end of the trigger, and the output end of the logic unit is suspended;
or the output end of the delay circuit is connected with the clock input end of the trigger, and the input end of the delay circuit is used for receiving the clock signal.
In one possible implementation, the method for performing time sequence optimization on the paths between the output end of the combination circuit and the data input end of the trigger in a mode of increasing input data delay comprises the steps of disconnecting the output end of the combination circuit from the data input end of the trigger;
The method comprises the steps of setting a delay circuit at the data input end of a trigger, wherein the delay circuit comprises a PMOS capacitor or an NMOS capacitor, when the MOS capacitor is the NMOS capacitor, a grid electrode of the NMOS capacitor is connected with the data input end of the trigger, a semiconductor substrate of the NMOS capacitor is grounded, when the MOS capacitor is the PMOS capacitor, a grid electrode of the PMOS capacitor is connected with the data input end of the trigger, and a semiconductor substrate of the PMOS capacitor is connected with a power supply;
Or the time sequence optimization is carried out on the path in a mode of increasing input data delay between the output end of the combination circuit and the data input end of the trigger, and the time sequence optimization comprises the step of adding a delay circuit at the data input end of the trigger, wherein the delay circuit comprises a logic unit with the same input signal as the output signal, the input end of the logic unit is connected with the data input end of the trigger, and the output end of the logic unit is suspended.
In one possible implementation, before the time sequence analysis is performed on the data input and output paths of each trigger in the sub-threshold circuit, the method further comprises the steps of performing isomorphic analysis on each path of the sub-threshold circuit, performing time sequence analysis and time sequence optimization on only one path of all isomorphic paths, and multiplexing the time sequence optimization result of the current path into other isomorphic paths.
A second aspect of the present application provides a sub-threshold circuit timing optimization apparatus comprising:
the time sequence analysis unit is used for performing time sequence analysis on the data input and output paths of each trigger in the sub-threshold circuit and identifying paths which do not meet the requirement of the set-up time or the requirement of the hold time;
the first time sequence optimizing unit is used for performing time sequence optimization on paths which do not meet the time establishment requirement but meet the time maintenance requirement by adopting a feedback equalization mode between the output end of the combined circuit and the data input end of the trigger, or performing time sequence optimization on the paths by adopting a clock delay mode at the clock input end of the trigger, wherein the combined circuit is a digital circuit which is connected with the data input end of the trigger and is formed by connecting a plurality of logic units according to a specific logic function;
the second time sequence optimizing unit is used for performing time sequence optimization on paths which do not meet the requirement of the holding time but meet the requirement of the establishing time by adopting a mode of increasing the delay of input data between the output end of the combined circuit and the data input end of the trigger;
The third time sequence optimizing unit is used for dividing the paths which do not meet the requirement of the holding time and do not meet the requirement of the establishing time into four types of sub paths, wherein the first type of sub path is a sub path which does not meet the requirement of the establishing time and meet the requirement of the holding time, the second type of sub path is a sub path which does not meet the requirement of the holding time and meet the requirement of the establishing time, the third type of sub path is a sub path which does not meet the requirement of the holding time and does not meet the requirement of the establishing time, the fourth type of sub path is a sub path which meets the requirement of the holding time and the requirement of the establishing time at the same time, the first type of sub path is subjected to time sequence optimization in a feedback equalization mode among all logic units which only belong to the first type of sub path, the second type of sub path is subjected to time sequence optimization in a mode of increasing input data delay among all logic units which only belong to the third type of sub path, and the third type of sub path is subjected to time sequence optimization in a mode of feedback equalization and increasing input data delay.
A third aspect of the application provides a computer program product comprising computer readable instructions which, when run on an electronic device, cause the electronic device to implement the sub-threshold circuit timing optimization method of the first aspect or any implementation of the first aspect.
A fourth aspect of the application provides an electronic device comprising at least one processor and a memory coupled to the processor, wherein:
The memory is used for storing a computer program;
the processor is configured to execute the computer program to enable the electronic device to implement the sub-threshold circuit timing optimization method of the first aspect or any implementation manner of the first aspect.
A fifth aspect of the present application provides a computer storage medium carrying one or more computer programs which, when executed by an electronic device, enable the electronic device to implement the sub-threshold circuit timing optimization method of the first aspect or any implementation manner of the first aspect.
By means of the technical scheme, the sub-threshold circuit timing optimization method provided by the application classifies the situations which do not meet the timing requirements, selects a more suitable timing optimization method according to each specific situation which does not meet the timing requirements, and accordingly implements corresponding timing optimization measures, so that a more matched unit circuit layout can be generated, and the timing convergence speed of the sub-threshold circuit is accelerated.
Detailed Description
The threshold voltage is the minimum gate voltage required for a transistor to go from the cut-off region into the saturation region or the linear region. The operating region of a transistor can be divided into a super-threshold region, a near-threshold region, and a sub-threshold region according to the magnitude of the gate voltage of the transistor relative to its threshold voltage. These three regions are described in detail below:
1. Super threshold region
A super-threshold region refers to a region where the gate voltage of a transistor is significantly higher than its threshold voltage. Circuits that operate in the super-threshold region using transistors are referred to as super-threshold circuits.
2. Near threshold region
The near threshold region is located between the subthreshold region and the super-threshold region, specifically, a region where the gate voltage of the transistor is slightly higher than or near its threshold voltage. A circuit that operates in a near threshold region using a transistor is called a near threshold circuit.
3. Subthreshold region
The sub-threshold region refers to a region where the gate voltage of the transistor is lower than its threshold voltage. A circuit that operates in a subthreshold region using a transistor is called a subthreshold circuit.
In the subthreshold region, the conductive path (channel) between the source and drain of the transistor is not fully formed, so the transistor is not fully turned on, and thus the operating voltage of the transistor is relatively low. Because the operating voltage is low, the leakage current of the transistor (i.e., the weak current flowing from the source to the drain; the leakage current is also referred to as subthreshold current in the subthreshold region, which decays exponentially with the gate voltage) also decreases significantly, so that the static power consumption of the subthreshold circuit is much lower than that of the super-threshold circuit and the near-threshold circuit. The low power consumption characteristics of sub-threshold circuits make it of great potential in flip-flop designs and other digital circuit designs.
However, the low power consumption characteristics of sub-threshold circuits come at the expense of circuit speed. In a subthreshold circuit, the operating speed of the transistor is slowed down (i.e., the switching time is increased) due to the decrease in the operating voltage, resulting in an increase in the propagation delay of the signal in the circuit. The cumulative effect of such delays is particularly pronounced in complex circuits, which may cause timing convergence problems to occur in the circuit (timing convergence refers to the process of ensuring that all signals arrive at their destination within a predetermined time when the circuit is designed to meet the functional and performance requirements of the circuit). Therefore, there is a need to employ more efficient timing optimization techniques to ensure proper operation of sub-threshold circuits.
In this regard, the embodiment of the application provides a sub-threshold circuit timing optimization method. The method classifies the situations which do not meet the time sequence requirements, selects a more suitable time sequence optimizing method aiming at each specific time sequence unsatisfied situation, and accordingly implements corresponding time sequence optimizing measures, so that a more matched unit circuit layout can be generated, and the time sequence convergence speed of the sub-threshold circuit is accelerated.
The following describes a sub-threshold circuit timing optimization method according to an embodiment of the present application in detail with reference to the accompanying drawings. As one of ordinary skill in the art can know, with the development of technology and the appearance of new scenes, the technical scheme provided by the embodiment of the application is also applicable to similar technical problems.
The terms first, second and the like in the description and in the claims and in the above-described figures, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances and are merely illustrative of the manner in which embodiments of the application have been described in connection with the description of the objects having the same attributes. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
Referring to fig. 1, a sub-threshold circuit timing optimization method provided by an embodiment of the present application includes:
And step S01, carrying out time sequence analysis on the data input and output paths of each trigger in the sub-threshold circuit, and identifying paths which do not meet the requirement of the set-up time or the retention time.
Specifically, in digital circuit designs, the flip-flop is a bistable circuit element with memory function. It is capable of storing one bit of binary information (i.e. 0 and 1) and updating its state under control of a specific clock signal. In subthreshold circuit design, ensuring that the flip-flop is functioning properly is critical, involving precise control of the timing parameters, especially setup time and hold time.
The trigger edge refers to an edge (rising edge or falling edge) of the clock signal where the state of the trigger changes. For example, a D flip-flop is a clock rising edge triggered flip-flop whose triggering edge is the rising edge of the clock signal.
The setup time refers to the minimum time that the data input signal must remain stable before the trigger edge of the trigger clock signal arrives. In other words, the data-in signal must arrive and remain stable in advance of the trigger edge of the clock signal to ensure that the trigger has enough time to recognize and stably capture the data-in signal. If the data input signal changes too fast before the trigger edge of the clock signal, the flip-flop may not properly capture the data input signal, resulting in data errors or instability.
The hold time refers to the minimum time that the data input signal must continue to remain stable after the trigger edge of the clock signal of the flip-flop arrives. This is because even if the trigger edge of the clock signal has occurred, the circuitry inside the flip-flop requires a certain time to process and stabilize the new state. If the data input signal changes immediately after the trigger edge of the clock signal, such changes may be misread by the internal circuitry of the flip-flop, resulting in data errors or instability.
In the design of the subthreshold circuit, static time sequence analysis software or Monte Carlo circuit simulation software can be used for time sequence analysis on the data input and output paths of each trigger in the subthreshold circuit so as to identify all paths which do not meet the time sequence requirement in the subthreshold circuit, including paths which do not meet the time requirement of establishment but meet the time requirement of maintenance, paths which do not meet the time requirement of establishment but meet the time requirement of establishment, and paths which do not meet the time requirement of establishment but not meet the time requirement of maintenance. Aiming at different types of timing problems, the embodiment of the application adopts different optimization strategies.
And step S02, for paths which do not meet the requirement of the setup time but meet the requirement of the hold time, carrying out time sequence optimization on the paths by adopting a feedback equalization mode between the output end of the combined circuit and the data input end of the trigger, or carrying out time sequence optimization on the paths by adopting a clock delay mode at the clock input end of the trigger so as to enable the paths to meet the requirements of the setup time and the hold time at the same time, and ending the control.
Specifically, for paths which do not meet the setup time requirements but meet the hold time requirements, two optimization strategies are proposed in the embodiments of the present application, namely, performing timing optimization by adopting a feedback equalization manner or performing timing optimization by adopting a clock delay manner, so that the paths also meet the setup time requirements (i.e., ensure that data stably arrives at the trigger data input terminal before the clock edge arrives, and meet the setup time requirements).
As one of timing optimization strategies, feedback equalization, specifically, inserting a feedback equalizer at a proper position of a path, and compensating path delay by adjusting the phase and amplitude of a feedback signal, so that data is stabilized before a clock edge. The method for optimizing the paths in time sequence by adopting a feedback equalization mode between the output end of the combined circuit and the data input end of the trigger comprises the following steps Sa 1-Sa 2:
step Sa1, the connection between the output end of the combined circuit and the data input end of the trigger is disconnected, as shown in FIG. 2, and then step Sa2 is entered, as shown in FIG. 2 (DFF in FIG. 2 represents the trigger, pin D, clk, Q, Q _bar of the trigger represents the data input end, the clock input end, the data output end and the anti-phase output end respectively, and the output state of pin Q_bar is opposite to that of pin Q), wherein the combined circuit is a digital circuit which is connected with the data input end of the trigger and is formed by connecting a plurality of logic units according to specific logic functions.
Specifically, a combinational circuit, also called combinational logic circuit, is a digital circuit formed by connecting a plurality of logic units according to a specific logic function. These logic cells are typically referred to as various logic gates such as and gates, or gates, not gates, nand gates, nor gates, exclusive or gates, and the like. The output of the combining circuit depends only on the current input signal, independent of the state or history input before the circuit. In other words, the output of the combining circuit is a function of the input signal, and this function does not involve a time delay (other than propagation delay, i.e., the time required for the signal to pass through the circuit).
Step Sa2 of inserting a feedback equalizer between the output of the combining circuit and the data input of the flip-flop, i.e. connecting the output of the combining circuit to the data input of the feedback equalizer, connecting the data output of the feedback equalizer to the data input of the flip-flop, and feeding the data output of the flip-flop back to the feedback input of the feedback equalizer, as shown in fig. 3. Still referring to fig. 3, the feedback equalizer includes, for example, an inverter INV1 and four MOS transistors M1 to M4, and a data output end of the trigger is connected to gates of the MOS transistors M2 to M3 in the feedback equalizer.
Specifically, the output signal of the combined circuit is processed by the feedback equalizer and then is used as the input of the trigger, the feedback equalizer adjusts the switching threshold value of the logic gate before the trigger according to the pre-sampling output, so that the load capacitance of the critical path is charged/discharged rapidly, the propagation delay of the critical path in the combined circuit can be reduced, the opportunity is created for increasing the working frequency and/or the voltage expansion of the combined circuit, the sub-threshold circuit is more robust to time sequence errors, and the main leakage power consumption of the whole design can be obviously reduced. The design parameters of the feedback equalizer depend on the particular timing problem and the amount of adjustment required.
It should be noted that, in the embodiment of the present application, the change (disconnection, insertion, etc.) of the connection relationship of the circuit may be adjusted by using EDA (Electronic Design Automation ) software. In conventional circuit designs, the disconnection and insertion of the circuit typically requires an engineer to perform it manually, which is time consuming and error prone. The EDA software can automatically realize disconnection and insertion of the circuit, and the EDA software can automatically adjust the connection relation of the circuit according to design rules and the requirements of users, so that the correctness and stability of the circuit are ensured.
In one possible implementation, see fig. 4, a schmitt trigger may also be inserted between the data output of the feedback equalizer and the data input of the trigger, i.e. the input of the schmitt trigger is connected to the data output of the feedback equalizer and the output of the schmitt trigger is connected to the data input of the trigger.
The Schmitt trigger is used as a buffer with double thresholds, the design of the Schmitt trigger skillfully connects the output end of a feedback circuit (namely a feedback equalizer) with the input end of the Schmitt trigger, and the connection mode brings two benefits, namely, on one hand, the feedback circuit stage can effectively reduce intersymbol interference generated by voltage scaling and improve the stability of the circuit, and on the other hand, the Schmitt trigger can smoothly process any abnormal signal possibly generated by the feedback circuit, so that the circuit is prevented from generating time sequence errors during high-speed operation, and the high-speed and reliable operation of the circuit is ensured.
In addition, as another timing optimization strategy, a clock delay mode is adopted at the clock input end of the trigger (i.e. a delay circuit is additionally arranged at the clock input end of the trigger) to perform timing optimization on the path, so as to delay the arrival time of the clock signal, thereby giving more time to the data signal to meet the requirement of the set-up time. The design of the delay circuit can adopt the following three schemes:
the delay circuit added at the clock input end of the trigger can comprise an MOS capacitor, specifically, in the MOS tube, a gate electrode, a source electrode and a drain electrode are isolated by a layer of insulating layer (usually silicon dioxide), and the layer of insulating layer, the gate electrode and a semiconductor substrate form the MOS capacitor. When a MOS is used as a capacitor, a capacitor may be formed between a gate and a source (or a drain), and since the capacitor has a charge and discharge characteristic, when an input signal is changed, the capacitor needs a certain time to charge or discharge, thereby achieving a stable state, and this process generates a delay. The size of the capacitor can be changed by adjusting the size or structure of the MOS tube, so that the time of delay is controlled. The MOS capacitor used in the embodiment of the present application may be an NMOS capacitor or a PMOS capacitor, as shown in fig. 5 or fig. 6. Fig. 5 shows that when the MOS capacitor is an NMOS capacitor, the gate of the NMOS capacitor is connected to the clock input terminal of the flip-flop, and the semiconductor substrate of the NMOS capacitor is grounded, and fig. 6 shows that when the MOS capacitor is a PMOS capacitor, the gate of the PMOS capacitor is connected to the clock input terminal of the flip-flop, and the semiconductor substrate of the PMOS capacitor is connected to the power supply).
In the second scheme, the delay circuit additionally arranged at the clock input end of the trigger can also comprise a logic unit with the same input signal and output signal, wherein the input end of the logic unit is connected with the clock input end of the trigger, and the output end of the logic unit is suspended, as shown in fig. 7.
Logic cells with the same input signal as the output signal, i.e. logic cells which do not function logically, may include buffer circuits, drivers, and serial binary inverters, etc., which, although not themselves changing logic states, introduce a certain delay due to the internal circuitry, the magnitude of which depends on the internal circuitry structure and element parameters of the logic cells. The logic cell output is floating, meaning that it is not connected to a subsequent load circuit, in which case the signal propagation inside the logic cell is not disturbed by the subsequent load, resulting in a more stable delay effect.
In one possible implementation, the logic cells in FIG. 7 may be designed with low power consumption to reduce energy waste.
In one possible implementation, the logic cell in fig. 7 may be a logic cell using a wide gate long MOS device. The specific analysis is that a wide gate length MOS device has a longer gate length than the MOS devices used in conventional logic cells. An increase in gate length results in a slower switching speed of the MOS device because the carriers take longer to traverse the channel under the gate. When the output signal of the combining circuit reaches the input of the delay logic unit, the signal experiences an additional delay in passing through the delay logic unit due to the slower switching speed of the wide gate long MOS device. The time of this delay depends on the specific parameters of the wide gate long MOS device (e.g., gate length, channel width, etc.) and the characteristics of the input signal (e.g., amplitude, frequency, etc.). Eventually, the delayed signal will reach the data input of the flip-flop, thereby achieving a delay processing of the signal.
The specific structure of the delay circuit added at the clock input end of the trigger is not limited, but the output end of the delay circuit is connected with the clock input end of the trigger, and the input end of the delay circuit is used for receiving a clock signal, as shown in fig. 8.
Of course, the embodiment of the application can also combine two timing optimization strategies given in step S02 to apply, and can combine any two or three delay circuit designs under the second timing optimization strategy to apply.
And S03, for the paths which do not meet the requirement of the holding time but meet the requirement of the establishing time, carrying out time sequence optimization on the paths by adopting a mode of increasing the input data delay (namely increasing the unit delay time) between the output end of the combined circuit and the data input end of the trigger so that the paths meet the requirement of the holding time and the requirement of the establishing time at the same time, and ending the control.
Specifically, an input data delay is added between the output end of the combination circuit and the data input end of the trigger, namely, the input data of the trigger is delayed, so that the retention time of a data signal is prolonged, and the data is ensured to be retained for a long time after a clock edge so as to meet the retention time requirement of the trigger. The specific implementation mode of the method can comprise the following steps of Sb1 to Sb2:
Step Sb1, disconnecting the output end of the combined circuit and the data input end of the trigger, and then entering step Sb2;
Step Sb2 of inserting a delay circuit (as shown in fig. 9) between the output terminal of the combining circuit and the data input terminal of the flip-flop, specifically comprising connecting the input terminal of the delay circuit to the input terminal of the combining circuit and connecting the output terminal of the delay circuit to the data input terminal of the flip-flop. The delay circuit can be formed by connecting a plurality of small delay circuit units in series.
Or the specific implementation mode of carrying out delay processing on the input data of the trigger can also comprise adding a delay circuit at the data input end of the trigger, wherein the delay circuit comprises an MOS capacitor. The MOS capacitor may be an NMOS capacitor or a PMOS capacitor as shown in fig. 10 or 11. Fig. 10 shows that when the MOS capacitor is an NMOS capacitor, the gate of the NMOS capacitor is connected to the data input terminal of the flip-flop, and the semiconductor substrate of the NMOS capacitor is grounded, and fig. 11 shows that when the MOS capacitor is a PMOS capacitor, the gate of the PMOS capacitor is connected to the data input terminal of the flip-flop, and the semiconductor substrate of the PMOS capacitor is connected to the power supply.
Or the specific implementation mode of carrying out delay processing on the input data of the trigger can also comprise adding a delay circuit at the data input end of the trigger, wherein the delay circuit comprises a logic unit with the same input signal and output signal, the input end of the logic unit is connected with the data input end of the trigger, and the output end of the logic unit is suspended, as shown in fig. 12. In addition, the logic unit can adopt a low-power consumption design so as to reduce energy waste. The logic cell device in fig. 12 may be a logic cell using a wide gate long MOS device.
Of course, the above three designs of delay processing of the input data of the flip-flop can also be applied in combination.
Step S04, dividing the paths which do not meet the requirement of the holding time and do not meet the requirement of the establishing time into four types of sub-paths, wherein the first type of sub-paths are sub-paths which do not meet the requirement of the establishing time and meet the requirement of the holding time, the second type of sub-paths are sub-paths which do not meet the requirement of the holding time and meet the requirement of the establishing time, the third type of sub-paths are sub-paths which do not meet the requirement of the holding time and do not meet the requirement of the establishing time, the fourth type of sub-paths are sub-paths which meet the requirement of the holding time and the requirement of the establishing time at the same time, and then entering step S05.
Specifically, path partitioning refers to the division of paths in a circuit into different groups or classes according to certain rules or algorithms in a circuit netlist (which may be considered a graph structure).
Step S05, performing time sequence optimization on the first type of sub-paths by adopting a feedback equalization mode between all logic units belonging to the first type of sub-paths, performing time sequence optimization on the second type of sub-paths by adopting a mode of increasing input data delay between all logic units belonging to the second type of sub-paths, and performing time sequence optimization on the third type of sub-paths by adopting a mode of feedback equalization and increasing input data delay between all logic units belonging to the third type of sub-paths so that the third type of sub-paths simultaneously meet the time establishment requirement and the time maintenance requirement, and ending the control.
Specifically, in order to simplify the optimization process, avoid optimization conflicts, and improve optimization efficiency and effect, the embodiment selects and excludes the corresponding common logic units for timing optimization, which is described in detail as follows:
Searching a common logic unit between a first type sub-path and a second type sub-path, then in the first type sub-path, excluding the logic unit shared by the second type sub-path, performing time sequence optimization on the first type sub-path in a feedback balance mode between all the rest non-common logic units (namely logic units only belonging to the first type sub-path) so that the first type sub-path simultaneously meets the time establishment requirement and the time maintenance requirement, and in the second type sub-path, excluding the logic unit shared by the first type sub-path, performing time sequence optimization on the second type sub-path in a mode of increasing input data delay between the rest non-common logic units (namely logic units only belonging to the second type sub-path) so that the second type sub-path simultaneously meets the time maintenance requirement and the time establishment requirement;
And in the third type of sub-path, excluding logic units shared by the first type of sub-path and the second type of sub-path, and performing time sequence optimization on the third type of sub-path in a feedback equalization and input data delay increasing mode among all the rest non-common logic units (namely logic units only belonging to the third type of sub-path) so as to enable the third type of sub-path to simultaneously meet the requirements of establishing time and maintaining time.
For example, as shown in FIG. 13, the first type of sub-path P1 is U1-U4-U7-U9, the second type of sub-path P2 is U2-U5-U7-U9, and the third type of sub-path P3 is U3-U6-U8-U9. Searching for a common logic unit (U7, U9) which does not meet the sub-path P1 and does not meet the sub-path P2, then performing time sequence optimization between all logic units (U1, U4) before U7 on the sub-path P1 so as to enable the sub-path P1 to meet the set-up time requirement, and performing time sequence optimization between all logic units (U2, U5) before U7 on the sub-path P2 so as to enable the sub-path P2 to meet the hold time requirement. Searching a common logic unit (U9) among the first type of sub-path P1, the second type of sub-path P2 and the third type of sub-path P3, and performing time sequence optimization among all logic units (U3, U6 and U8) before U9 on the sub-path P3 so as to enable the sub-path P3 to meet the requirements of establishing time and maintaining time.
In summary, the embodiment of the application selects and implements (including precisely determining the device parameter values of the circuits such as the feedback equalizer, the delay circuit and the like) the matched time sequence optimizing method aiming at each path which is not satisfied by specific time sequences, so that the paths simultaneously satisfy the time requirement and the holding time requirement, thereby generating more matched unit circuit patterns and accelerating the time sequence convergence speed of the sub-threshold circuit.
It should be noted that, all the above-mentioned time sequence optimization processes include optimizing the device size in the path to determine the transistor size parameter values more suitable for the time sequence requirement of the path, and based on these new device size parameter values, the system will automatically fine tune the layout of the unit circuit, so as to generate the unit circuit layout under the corresponding new parameter values. Compared with the method in the prior art that only suitable units are selected from a predefined unit library, the method can generate unit circuits which are more suitable for specific requirements, further more effectively realize time sequence optimization and remarkably accelerate the convergence process.
In one possible implementation, before performing timing analysis on the data input and output paths of each flip-flop in the sub-threshold circuit, isomorphic analysis may also be performed on each path of the sub-threshold circuit first, and for all isomorphic paths, timing analysis and timing optimization are performed on only one path, and then the timing optimization result of this path is multiplexed into other isomorphic paths. The strategy not only remarkably reduces redundant calculation in the optimization process, but also greatly improves the optimization efficiency.
Corresponding to the method embodiment, the embodiment of the application also provides a sub-threshold circuit time sequence optimizing device, which comprises the following steps:
the time sequence analysis unit is used for performing time sequence analysis on the data input and output paths of each trigger in the sub-threshold circuit and identifying paths which do not meet the requirement of the set-up time or the requirement of the hold time;
the first time sequence optimizing unit is used for performing time sequence optimization on paths which do not meet the time establishment requirement but meet the time maintenance requirement by adopting a feedback equalization mode between the output end of the combined circuit and the data input end of the trigger, or performing time sequence optimization on the paths by adopting a clock delay mode at the clock input end of the trigger, wherein the combined circuit is a digital circuit which is connected with the data input end of the trigger and is formed by connecting a plurality of logic units according to a specific logic function;
the second time sequence optimizing unit is used for performing time sequence optimization on paths which do not meet the requirement of the holding time but meet the requirement of the establishing time by adopting a mode of increasing the delay of input data between the output end of the combined circuit and the data input end of the trigger;
The third time sequence optimizing unit is used for dividing the paths which do not meet the requirement of the holding time and do not meet the requirement of the establishing time into four types of sub paths, wherein the first type of sub path is a sub path which does not meet the requirement of the establishing time and meet the requirement of the holding time, the second type of sub path is a sub path which does not meet the requirement of the holding time and meet the requirement of the establishing time, the third type of sub path is a sub path which does not meet the requirement of the holding time and does not meet the requirement of the establishing time, the fourth type of sub path is a sub path which meets the requirement of the holding time and the requirement of the establishing time at the same time, the first type of sub path is subjected to time sequence optimization in a feedback equalization mode among all logic units which only belong to the first type of sub path, the second type of sub path is subjected to time sequence optimization in a mode of increasing input data delay among all logic units which only belong to the third type of sub path, and the third type of sub path is subjected to time sequence optimization in a mode of feedback equalization and increasing input data delay.
In addition, the embodiment of the application also provides a computer program product, which comprises computer readable instructions, wherein the computer readable instructions enable the electronic device to realize any sub-threshold circuit timing optimization method.
The embodiment of the application also provides electronic equipment, which comprises at least one processor and a memory connected with the processor, wherein:
The memory is used for storing a computer program;
the processor is configured to execute the computer program to enable the electronic device to implement any of the subthreshold circuit timing optimization methods described above.
The embodiment of the application also provides a computer storage medium, which carries one or more computer programs, and when the one or more computer programs are executed by electronic equipment, the electronic equipment can realize any sub-threshold circuit timing optimization method.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the embodiments of the application. Thus, the present embodiments are not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.