Disclosure of Invention
Accordingly, the present invention is directed to a data processing method, apparatus, device, medium and program product for improving soft decoding capability after hard decoding failure of a read operation. The specific scheme is as follows:
In a first aspect, the present invention provides a data processing method, applied to a memory, including:
according to a default read operation voltage, a first read offset and a second read offset, calculating to obtain the read reliability degree of the floating point type corresponding to each of the plurality of read intervals;
Normalizing the read reliability of the floating point type corresponding to each read interval according to the preset upper limit of the storage bit;
converting the read reliability of the floating point type corresponding to each read interval after normalization processing into an integer type, and recording the read reliability of the integer type corresponding to each read interval;
If the hard decoding of any read operation of the memory fails, decoding and correcting the read operation by utilizing the read reliability degree of the integer type corresponding to each read interval.
Optionally, according to a default read operation voltage, a first read offset and a second read offset, calculating a read reliability degree of a floating point type corresponding to each of the plurality of read intervals includes:
determining K read voltage axes according to the read operation voltage, the first read offset and the second read offset;
calculating the product of the interval numbers X and K corresponding to each reading voltage axis to obtain XK reading intervals;
and calculating the read reliability degree of the floating point type corresponding to the XK read intervals respectively.
Optionally, according to a preset upper limit of storage bits, normalizing the read reliability of the floating point type corresponding to each read interval, including:
determining a maximum value in read reliability of the XK floating point types;
Respectively calculating the ratio of the read reliability degree of the XK floating point types to the maximum value to obtain XK ratios;
And according to the XK ratios and the upper limit of the storage bit, calculating to obtain the read reliability degree of the floating point type corresponding to the XK read intervals after normalization processing.
Optionally, according to the XK ratios and the upper limit of the storage bits, the read reliability degrees of floating point types corresponding to the XK read intervals after normalization processing are obtained by calculation, including:
subtracting one from the upper limit of the storage bit to obtain a target value;
And calculating the product of the target value and the XK ratios to obtain the read reliability degree of the floating point type corresponding to the XK read intervals after normalization processing.
Optionally, calculating the read reliability degree of the floating point type corresponding to the XK read intervals respectively includes:
And respectively calculating the ratio of the probability of writing the character 0 to the probability of writing the character 1 in the XK reading intervals, and taking the corresponding ratio as the reading reliability of the floating point type corresponding to the XK reading intervals.
Optionally, converting the read reliability of the floating point type corresponding to each read interval after normalization processing into an integer type includes:
reading the upper limit of the storage bit from a main controller of the memory;
calculating n quantization points by using the upper limit of the storage bit;
calculating by using the upper limit of the storage bit to obtain the maximum amplitude;
Constructing and obtaining a piecewise symbol function by utilizing the n quantization points, the maximum amplitude and the read reliability of the floating point type corresponding to each read interval after normalization processing;
And solving the piecewise symbol function to obtain the read reliability degree of the integer type corresponding to each read interval.
Optionally, calculating n quantization points by using the upper limit of the storage bit includes:
calculating to obtain equidistant function values according to a first formula;
determining n quantization points unevenly distributed based on the equidistant function values;
Wherein, the first formula is:; and represents the function value corresponding to the quantization point xi, m represents the upper limit of the storage bits, i=1, 2.
Optionally, calculating the distance between two adjacent points by using the upper limit of the storage bit and n includes:
calculating according to a second formula to obtain the distance between two adjacent points;
The second formula is that D= (m-1)/n, D represents the distance, m represents the upper limit of the storage bit, and n represents the number of quantization points.
Optionally, the piecewise symbol function is:
q1,q2,…,qn represents n quantization points, i=1, 2, n,And representing the read reliability of the floating point type corresponding to each read interval after normalization processing, wherein sign () is a sign function for identifying the positive and negative of q (y), and magn represents the maximum amplitude.
Optionally, calculating the maximum amplitude by using the upper limit of the storage bit includes:
calculating according to a third formula to obtain a maximum amplitude;
Wherein the third formula is magn =m-1 -1, magn represents the maximum amplitude value, and m represents the upper limit of the storage bit.
Optionally, recording the read reliability degree of the integer type corresponding to each read interval includes:
And generating a log-likelihood ratio table comprising the read reliability degree of the integer type corresponding to each read interval.
Optionally, decoding and correcting the read operation by using the read reliability degree of the integer type corresponding to each read interval, including:
Determining a corresponding read voltage and a corresponding read offset of the memory cell read by the read operation;
Reading the preset number of the memory cells for a plurality of times by utilizing the reading voltage and the reading offset to obtain a reading result;
Inquiring the read reliability degree of the integer type corresponding to the read result;
and decoding and correcting the read operation based on the read reliability degree of the queried integer type.
Optionally, querying the read reliability degree of the integer type corresponding to the read result includes:
and taking the queried log likelihood ratio value corresponding to the reading result as the reading reliability degree of the integer type corresponding to the reading result in the log likelihood ratio table corresponding to the preset number.
Optionally, the method further comprises:
If decoding and error correction fail, the preset number is adjusted under the condition that the maximum adjustment times are not reached, and the step is executed based on the adjusted preset number, wherein the preset number of the storage units is read by utilizing the read voltage and the read offset to obtain a read result, the read reliability degree of the integer type corresponding to the read result is inquired, and decoding and error correction are carried out on the read operation based on the read reliability degree of the inquired integer type.
Optionally, the method further comprises:
And if the decoding error correction is successful, feeding the data read by the reading operation back to the corresponding client.
Optionally, the method further comprises:
if decoding error correction fails, corresponding data recovery operation is executed under the condition that the maximum adjustment times are reached.
Optionally, the method further comprises:
counting decoding error correction failure probability in a period of time;
And if the decoding error correction failure probability is greater than a preset probability threshold, adjusting the read operation voltage, the first read offset and/or the second read offset.
In a second aspect, the present invention provides a data processing apparatus for use in a memory, comprising:
The calculation module is used for calculating and obtaining the read reliability degree of the floating point type corresponding to each of the plurality of read intervals according to the default read operation voltage, the first read offset and the second read offset;
The normalization module is used for carrying out normalization processing on the read reliability degree of the floating point type corresponding to each read interval respectively according to the preset upper limit of the storage bit;
The conversion module is used for converting the read reliability of the floating point type corresponding to each read interval after normalization processing into an integer type and recording the read reliability of the integer type corresponding to each read interval;
and the read processing module is used for decoding and correcting errors of the read operation by utilizing the read reliability degree of the integer type corresponding to each read interval if the hard decoding of any read operation of the memory fails.
Optionally, the computing module is specifically configured to:
determining K read voltage axes according to the read operation voltage, the first read offset and the second read offset;
calculating the product of the interval numbers X and K corresponding to each reading voltage axis to obtain XK reading intervals;
and calculating the read reliability degree of the floating point type corresponding to the XK read intervals respectively.
Optionally, the normalization module is specifically configured to:
determining a maximum value in read reliability of the XK floating point types;
Respectively calculating the ratio of the read reliability degree of the XK floating point types to the maximum value to obtain XK ratios;
And according to the XK ratios and the upper limit of the storage bit, calculating to obtain the read reliability degree of the floating point type corresponding to the XK read intervals after normalization processing.
Optionally, the normalization module is specifically configured to:
subtracting one from the upper limit of the storage bit to obtain a target value;
And calculating the product of the target value and the XK ratios to obtain the read reliability degree of the floating point type corresponding to the XK read intervals after normalization processing.
Optionally, the computing module is specifically configured to:
And respectively calculating the ratio of the probability of writing the character 0 to the probability of writing the character 1 in the XK reading intervals, and taking the corresponding ratio as the reading reliability of the floating point type corresponding to the XK reading intervals.
Optionally, the conversion module is specifically configured to:
reading the upper limit of the storage bit from a main controller of the memory;
calculating n quantization points by using the upper limit of the storage bit;
calculating by using the upper limit of the storage bit to obtain the maximum amplitude;
Constructing and obtaining a piecewise symbol function by utilizing the n quantization points, the maximum amplitude and the read reliability of the floating point type corresponding to each read interval after normalization processing;
And solving the piecewise symbol function to obtain the read reliability degree of the integer type corresponding to each read interval.
Optionally, the conversion module is specifically configured to:
calculating to obtain equidistant function values according to a first formula;
determining n quantization points unevenly distributed based on the equidistant function values;
Wherein, the first formula is:; and represents the function value corresponding to the quantization point xi, m represents the upper limit of the storage bits, i=1, 2.
Optionally, the conversion module is specifically configured to:
calculating according to a second formula to obtain the distance between two adjacent points;
The second formula is that D= (m-1)/n, D represents the distance, m represents the upper limit of the storage bit, and n represents the number of quantization points.
Optionally, the piecewise symbol function is:
q1,q2,…,qn represents n quantization points, i=1, 2, n,And representing the read reliability of the floating point type corresponding to each read interval after normalization processing, wherein sign () is a sign function for identifying the positive and negative of q (y), and magn represents the maximum amplitude.
Optionally, the conversion module is specifically configured to:
calculating according to a third formula to obtain a maximum amplitude;
Wherein the third formula is magn =m-1 -1, magn represents the maximum amplitude value, and m represents the upper limit of the storage bit.
Optionally, the conversion module is specifically configured to:
And generating a log-likelihood ratio table comprising the read reliability degree of the integer type corresponding to each read interval.
Optionally, the read processing module is specifically configured to:
Determining a corresponding read voltage and a corresponding read offset of the memory cell read by the read operation;
Reading the preset number of the memory cells for a plurality of times by utilizing the reading voltage and the reading offset to obtain a reading result;
Inquiring the read reliability degree of the integer type corresponding to the read result;
and decoding and correcting the read operation based on the read reliability degree of the queried integer type.
Optionally, the read processing module is specifically configured to:
and taking the queried log likelihood ratio value corresponding to the reading result as the reading reliability degree of the integer type corresponding to the reading result in the log likelihood ratio table corresponding to the preset number.
Optionally, the method further comprises:
And the circulation module is used for adjusting the preset number under the condition that the maximum adjustment times are not reached if the decoding error correction fails, and executing the steps based on the adjusted preset number, namely reading the preset number of the storage units by utilizing the read voltage and the read offset to obtain a read result, inquiring the read reliability degree of the integer type corresponding to the read result, and carrying out decoding error correction on the read operation based on the read reliability degree of the inquired integer type.
Optionally, the method further comprises:
and the decoding success module is used for feeding back the data read by the reading operation to the corresponding client if the decoding error correction is successful.
Optionally, the method further comprises:
And the decoding failure module is used for executing corresponding data recovery operation under the condition that the maximum adjustment times are reached if the decoding error correction fails.
Optionally, the method further comprises:
And the adjustment module is used for counting the decoding error correction failure probability in a period of time, and adjusting the read operation voltage, the first read offset and/or the second read offset if the decoding error correction failure probability is greater than a preset probability threshold.
In a third aspect, the present invention provides an electronic device, comprising:
a memory for storing a computer program;
and a processor for executing the computer program to implement the previously disclosed data processing method.
In a fourth aspect, the present invention provides a non-volatile storage medium for storing a computer program which, when executed by a processor, implements the data processing method disclosed previously.
In a fifth aspect, the present invention provides a computer program product comprising computer programs/instructions which when executed by a processor implement the steps of the previously disclosed data processing method.
According to the scheme, the data processing method is applied to a memory and comprises the steps of calculating and obtaining read reliability degrees of floating point types corresponding to a plurality of read intervals according to default read operation voltage, first read offset and second read offset, carrying out normalization processing on the read reliability degrees of the floating point types corresponding to the read intervals according to a preset upper limit of storage bits, converting the read reliability degrees of the floating point types corresponding to the read intervals after normalization processing into integer types, recording the read reliability degrees of the integer types corresponding to the read intervals, and decoding and correcting errors by utilizing the read reliability degrees of the integer types corresponding to the read intervals if hard decoding of any read operation of the memory fails.
The method has the advantages that after the read reliability degree of the floating point type corresponding to each read interval is calculated according to the default read operation voltage, the first read offset and the second read offset, normalization processing is carried out on the read reliability degree of the floating point type corresponding to each read interval according to the preset upper limit of storage bits, so that the amplitude of the read reliability degree of the floating point type is limited to the upper limit of the storage bits, the read reliability degree of the floating point type corresponding to each read interval after normalization processing is converted into an integer type, the read reliability degree of the integer type corresponding to each read interval is recorded, and if hard decoding of any read operation of a memory fails, decoding error correction is carried out on the read operation by utilizing the read reliability degree of the integer type corresponding to each read interval. The scheme ensures that the amplitude of the reading reliability degree of the floating point type is limited to the upper limit of a storage bit set by hardware, the number of the reading intervals is calculated according to the default reading operation voltage, the first reading offset and the second reading offset, quantization points can be taken more in the area with smaller LLR amplitude, and a small number of quantization points are taken in the area with larger LLR value, so that the soft decoding capability and success rate after hard decoding failure of the reading operation are improved.
Accordingly, the data processing device, the medium and the program product provided by the invention also have the technical effects.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other examples, which a person of ordinary skill in the art would obtain without undue burden based on the embodiments of the invention, are within the scope of the invention.
Currently, an LLR table is used in a soft decoding process after a hard decoding failure in a read operation, and LLR values of integer types of a plurality of read intervals determined based on a read voltage of a memory are recorded in the LLR table, and are obtained by directly rounding or linearly changing corresponding floating point numbers, which causes amplification of all LLR values recorded in the LLR table. For example, when the difference between different floating point numbers is small, the difference of LLRs between different read intervals is eliminated through a rounding operation, which may cause soft decoding failure. Therefore, the invention provides a data processing scheme which can improve the soft decoding capability after the hard decoding failure of the read operation.
Referring to fig. 1, an embodiment of the present invention discloses a data processing method, which is applied to a memory, and includes:
S101, according to a default read operation voltage, a first read offset and a second read offset, the read reliability degree of the floating point type corresponding to each of the plurality of read intervals is calculated.
In one embodiment, according to a default read operation voltage, a first read offset and a second read offset, calculating to obtain the read reliability degree of the floating point type corresponding to each of the plurality of read intervals, wherein the method comprises the steps of determining K read voltage axes according to the read operation voltage, the first read offset and the second read offset; and calculating the product of the interval numbers X and K corresponding to each reading voltage axis to obtain XK reading intervals, and calculating the reading reliability of the floating point type corresponding to each XK reading interval.
S102, according to a preset upper limit of storage bits, normalizing the read reliability of the floating point type corresponding to each read interval.
In one embodiment, the normalization processing is performed on the read reliability of the floating point type corresponding to each read interval according to a preset upper limit of the storage bit, wherein the normalization processing comprises the steps of determining the maximum value of the read reliability of the XK floating point types, respectively calculating the ratio of the read reliability of the XK floating point types to the maximum value to obtain XK ratios, and according to the XK ratios and the upper limit of the storage bit, calculating the read reliability of the floating point types corresponding to the normalized XK read intervals.
In one embodiment, according to the XK ratios and the upper limit of the storage bit, the reading reliability degree of the floating point type corresponding to each of the XK reading intervals after normalization processing is calculated.
In one embodiment, calculating the read reliability of the floating point type corresponding to each of the XK read intervals includes calculating a ratio of probability of writing character 0 to probability of writing character 1 in each of the XK read intervals, and taking the corresponding ratio as the read reliability of the floating point type corresponding to each of the XK read intervals.
S103, converting the read reliability of the floating point type corresponding to each read interval after normalization processing into an integer type, and recording the read reliability of the integer type corresponding to each read interval.
In one embodiment, the read reliability of the floating point type corresponding to each read interval after normalization processing is converted into an integer type, wherein the method comprises the steps of reading a storage bit upper limit from a main controller of a memory, calculating to obtain n quantization points by using the storage bit upper limit, calculating to obtain a maximum amplitude by using the storage bit upper limit, constructing a segmentation symbol function by using the n quantization points, the maximum amplitude and the read reliability of the floating point type corresponding to each read interval after normalization processing, and solving the segmentation symbol function to obtain the read reliability of the integer type corresponding to each read interval.
And S104, if hard decoding of any read operation of the memory fails, decoding and correcting the read operation by utilizing the read reliability degree of the integer type corresponding to each read interval.
In one embodiment, the equidistant function value is calculated according to a first formula, n quantization points which are unevenly distributed are determined based on the equidistant function value, wherein the first formula is as follows:; And represents the function value corresponding to the quantization point xi, m represents the upper limit of the storage bits, i=1, 2. As shown in fig. 3, a plurality of function values are taken at equal intervals on the Y-axis, the corresponding X-axis values are unevenly distributed, and the larger the Y-axis value is, the denser the X-axis value distribution is, the smaller the Y-axis value is, and the thinner the X-axis value distribution is. Thus, non-uniform n quantization points are realized.
In one embodiment, the calculation of the distance between two adjacent points by using the upper limit of the storage bit and n comprises the calculation of the distance between two adjacent points according to a second formula, wherein the second formula is that D= (m-1)/n, D represents the distance, m represents the upper limit of the storage bit, and n represents the number of quantization points.
In one embodiment, the piecewise sign function is:
q1,q2,…,qn represents n quantization points, i=1, 2, n,And (3) representing the read reliability of the floating point type corresponding to each read interval after normalization processing, wherein sign () is a sign function for identifying the positive and negative of q (y), and magn represents the maximum amplitude.
In one embodiment, the maximum amplitude is calculated by using the upper limit of the storage bit, and the method comprises the step of calculating the maximum amplitude according to a third formula, wherein the third formula is magn =m-1 -1, the maximum amplitude is represented by magn, and the upper limit of the storage bit is represented by m.
In one embodiment, recording the read reliability of the integer type for each read interval includes generating a log likelihood ratio table including the read reliability of the integer type for each read interval.
In one embodiment, decoding and correcting the read operation by utilizing the read reliability degree of the integer type corresponding to each read interval respectively comprises determining the read voltage and the corresponding read offset corresponding to the memory cell read by the read operation, reading the memory cell for a preset number of times by utilizing the read voltage and the read offset to obtain a read result, inquiring the read reliability degree of the integer type corresponding to the read result, and decoding and correcting the read operation based on the read reliability degree of the inquired integer type.
In one embodiment, inquiring the read reliability of the integer type corresponding to the read result comprises taking the log likelihood ratio corresponding to the inquired read result as the read reliability of the integer type corresponding to the read result in a log likelihood ratio table corresponding to the preset number.
In one embodiment, if the decoding and error correction fail, the preset number is adjusted under the condition that the maximum adjustment times are not reached, and the step is executed based on the adjusted preset number, wherein the preset number is used for reading the storage unit for a plurality of times by using the read voltage and the read offset to obtain a read result, the read reliability degree of the integer type corresponding to the read result is inquired, and the decoding and error correction is carried out on the read operation based on the read reliability degree of the inquired integer type. Thereby, cyclic decoding error correction can be achieved. If the decoding error correction is successful, the data read by the reading operation is fed back to the corresponding client. If decoding error correction fails, corresponding data recovery operation is executed under the condition that the maximum adjustment times are reached.
In one embodiment, the method further comprises the steps of counting decoding error correction failure probability in a period of time, and adjusting the read operation voltage, the first read offset and/or the second read offset if the decoding error correction failure probability is greater than a preset probability threshold. This can reduce the decoding error correction failure probability.
It can be seen that, in this embodiment, after the read reliability degree of the floating point type corresponding to each of the plurality of read intervals is calculated according to the default read operation voltage, the first read offset and the second read offset, normalization processing is performed on the read reliability degree of the floating point type corresponding to each of the read intervals according to the preset upper limit of the storage bit, so that the magnitude of the read reliability degree of the floating point type is constrained to the upper limit of the storage bit, then the read reliability degree of the floating point type corresponding to each of the read intervals after normalization processing is converted into an integer type, and the read reliability degree of the integer type corresponding to each of the read intervals is recorded. The scheme ensures that the amplitude of the reading reliability degree of the floating point type is limited to the upper limit of a storage bit set by hardware, the number of the reading intervals is calculated according to the default reading operation voltage, the first reading offset and the second reading offset, quantization points can be taken more in the area with smaller LLR amplitude, and a small number of quantization points are taken in the area with larger LLR value, so that the soft decoding capability and success rate after hard decoding failure of the reading operation are improved.
It should be noted that, the NAND flash memory read recovery technique relies on ECC (Error Correction Code ), such as the currently mainstream LDPC (Low DENSITY PARITY CHECK, low density check code), including hard decoding and soft decoding of the LDPC code. The data is LDPC coded before being written into the flash memory, and when the data is read, the data read from the flash memory is recovered by first performing LDPC hard decoding operation. When the number of bits in which the reading error occurs is within the decoding error correction range of the LDPC code, that is, RBER is less than the error tolerance of decoding, the decoding operation can successfully decode and transmit the data to the host. However, when the overlap area between two adjacent states is increased or the original read voltage axis is not accurate enough due to the situations of shifting and widening the threshold voltage, and thus the read RBER (Raw Bit Error Rate, original error rate) exceeds the error correction capability of LDPC, the data cannot be recovered through hard decoding, and SSD (Solid STATE DRIVES, solid state disk) master control can execute the soft decoding of LDPC to recover the data.
Soft decoding requires the NAND flash memory to support the re-reading operation, performing left-right offset reading through an offset axis based on an original voltage axis, and dividing a threshold voltage axis into a plurality of sections after reading a plurality of times. Taking a voltage axis as an example, as shown in fig. 2. Performing normal reading by using the original voltage axis RL and performing left-right offset voltage axisAndThe voltage axis is divided into 4 sections, which can be represented using the results of three readings. If the three readings are identical, i.e. the non-overlapping areas (111 or 000 areas) on both sides, the reliability of the reading result of the memory cell is considered to be high, and if the three readings are different, the bit data is considered to be likely to fall into the overlapping area (101 or 001 areas). For each interval, the reliability of each interval is identified by a Log-Likelihood Ratio (LLR), expressed as:
The reliability of a zone is specifically the ratio of the probability that write 0 falls within that zone to the probability that write 1 falls within that zone. The larger the amplitude of the LLR value is, the higher the reliability of the interval is, otherwise, the smaller the amplitude of the LLR is, the closer to 0, the probability of writing 0 and writing 1 in the interval is similar, and the ambiguity is higher, namely the error probability is higher. An LLR table is maintained in the SSD master, corresponding to the LLR values for each bin. When the soft decoding is executed, the current storage unit is determined to be in which interval through the result of multiple times of reading, and then the corresponding LLR value is obtained through table lookup, so that the soft decoding of LDPC is further carried out.
The LLR configuration has great influence on the decoding result of the soft decoding, and the accurate LLR configuration can not only improve the error correction capability of the LDPC soft decoding, but also effectively reduce the decoding iteration times of the LDPC code and reduce the reading time delay. For the overlapping area of the threshold voltages of two states, since the area is the main area where the read error occurs, the accuracy of the LLR configuration in the area affects the decoding result more, and the offset valueAndThe selection of (a) also affects the calculation of LLR. Because of hardware limitation, when the LLR table is configured, the actually calculated floating point number is quantized and represented by a limited integer and stored in the LLR table for soft decoding. Quantization operations may reduce the accuracy of the LLR representation, thereby reducing the performance of LDPC soft decoding.
In the operation of converting the floating point number into the integer, the floating point number can be rounded up or down or rounded up, and when the LLR actual value is larger than the maximum value with limited representation, the clipping operation is directly executed, namely, the calculated floating point number is obtainedThe following formula is introduced:
thereby converting the floating point number to an integer,Representation pairThe upper rounding is performed so that the upper rounding is performed,Representing maximum amplitude of integer represented by limited hardware, if adopted in hardwareBit indicates that,The first bit of the bits is the sign bit.
If not directly to the above formula (2)The operation is performed, but the LLR calculated for all intervals is linearly changed first:
AndIs a parameter in the course of a linear change,It is usual to take 1 of this,Can be adjusted according to different NAND, and the parameter adjustment requirement is adjusted so as not to appearIs the case in (a). Whereby the quantization formula is modified as:
Because of the flash memory reading characteristic, the overlapping interval between two adjacent states is an error high-incidence area, and the actually calculated LLR with smaller amplitude has great influence on the decoding result. The scheme in the formula (4) firstly carries out linear change on the floating point number, amplifies all the calculated LLR values, does not carry out special treatment on smaller amplitude values of the LLR, and particularly eliminates the difference of LLR in different areas through the rounding operation when the floating point number difference is smaller.
Accordingly, the present embodiment provides a quantization scheme for LLRs corresponding to soft decoding in SSD read operations. The scheme takes the decoding characteristics of LDPC and the characteristics of the LLR values actually calculated in the flash memory into consideration, and adopts the concept of non-uniform quantization to quantize the LLR floating point numbers actually calculated, thereby constructing an LLR table. Based on the scheme, considering the characteristic of LDPC, the requirements of offset voltage configuration of offset reading left and right in soft decoding are correspondingly given.
LDPC codes are commonly used in SSD masters at present. The LDPC code is an error correction code with excellent error correction performance, and is characterized in that the check matrix has low density, and the check matrix of the LDPC code isM rows of the check matrix correspond to M check nodes and N columns correspond to N variable nodes, decoding of the LDPC code is typically iterative messaging between the variable nodes and the check nodes. Each iteration in the decoding algorithm comprises three parts, namely variable node updating, check node updating and judgment, wherein the check node updating is the most complex and is completed by the following formula:
Representing the calculated firstThe variable nodes are transferred to the firstThe LLR values given to the check nodes,Is in the last iteration, the firstVariable nodes of each are from other than the firstThe LLR values acquired by the remaining check nodes connected to itself, i.e.,,Is the firstThe set of all check nodes that the individual variable nodes connect to,Representing the retrieval of nodes from the collection. To simplify the calculation, the following will be adoptedWriting into two parts of a sign and an amplitude, so as to respectively calculate, and enabling:
Wherein the method comprises the steps of,Is a sign function, and represents positive and negative;
representing its amplitude. Therefore, update formula (5) is rewritten as:
Wherein:
in the main control implementation of the main flow of the SSD, let:
I.e. by means ofFunctional characteristics of (2)Substituting formula (9) into formula (7), updating the formula further reduces to:
The equation (10) is actually a check node update equation of the min-sum algorism (msa) which is most commonly used in the master control.
As can be seen from equation (9) in the principle of the LDPC code minimum sum decoding algorithm, the minimum sum decoding algorithm is to compare the actual sum product decodingBy usingInstead, the LLR of the minimum magnitude dominates the updating of the check node. In addition, the overlap area where the error of the NAND flash memory is easy to occur is also usually smaller in LLR value, and both points can see that the LLR value with smaller amplitude has an important influence on LDPC decoding. Therefore, the core idea of the non-uniform quantization scheme proposed in the present invention is to take more quantization points in the region with smaller LLR amplitude and take less quantization points in the region with larger LLR amplitude.
If the hardware limitation is adoptedBits to represent LLR values, then the LLR magnitudes are at most:
the most significant bit of the bits is the sign bit. Expressed in integers, all in commonThe amplitude is selectable, including amplitude 0. The present invention thus employs n-bit non-uniform quantization of the LLR,From the calculated floating point numberTo integers ofThe quantization process of (1) adopts the following scheme, which is specifically expressed as follows:
Representation ofThe number of quantization points is set to be,Is a sign function, marksIs characterized in that the positive and negative of (a),Is toThe formula of the variation is performed.
Based on the quantization formula, the quantization scheme proposed in the present embodiment is divided into two parts, one part isDetermination of quantization points, another part isIs calculated by the computer. Due to the simplification of the minimum sum algorithm is based onThe function of the function is that,The function hasThe smaller the size of the product,The larger and withIs to be used in the reduction of (1),The characteristic of sharp increase is utilized in the inventionThe function determines the quantization point.
The quantization scheme is based on the idea of equidistant linear approximation, namely, equally-spaced points are divided in the Y-axis direction, and the corresponding X-axis is the selected quantization point. In particular, for hardware limitations adoptionIn LLR configuration of bits, wherein the most significant bit is the sign bit, the significant bits of the amplitude are commonBit atTaking at equal intervalsA point of the light-emitting diode is located,The method comprises the following steps:
As in fig. 3As shown. Setting up,. Thus, correspond toThe value interval of (2) is. Due toTime of dayBut is provided withFunction edgeSymmetry and is therefore defined in this embodiment asThus corresponding toThe value point of (2) is. Furthermore, in the present embodiment, it will be calculatedIs defined as a quantization interval. As shown in fig. 3, a plurality of function values are taken at equal intervals on the Y-axis, the corresponding X-axis values are unevenly distributed, and the larger the Y-axis value is, the denser the X-axis value distribution is, the smaller the Y-axis value is, and the thinner the X-axis value distribution is. Thus, non-uniform quantization is achieved.
Based on the quantization point determination scheme set forth above, in the present embodiment, in formula (12)The calculation is as follows:
Is a vector of all actually calculated floating point values,Is to take the maximum value of the amplitude of all floating point values, thusIs the actual calculatedThe value is in the amplitudeNormalization processing was performed in the range. For the normalized productUsing the calculated quantization points, the quantization of LLR floating points to finite integers can be performed using equation (12).
In LDPC code decoding, if llr=0, this means that the initial probability of writing 0 and writing 1 at that point is the same, and in encoding, this variable node is referred to as "erasure". As seen from the updating formulas of the check nodes in the minimum and decoding, the amplitude is the minimum amplitude of all variable nodes connected with the minimum amplitude, if one variable node connected with the minimum amplitude is erased, the LLR value of the other check nodes is updated to be 0 in the iteration, LLR information of the other variable nodes of the check nodes cannot be quickly and directly transmitted, and the decoding failure probability is increased. In addition, according to the concept of the stop set in the LDPC code, the erasure node in the stop set can affect the correct decoding of the variable node on the whole stop set. Thus, the occurrence of a 0 value in the initial configuration of the LLR should be avoided. Can be shifted by an offsetAndTo avoid this problem.
From equation (12), whenIn the time-course of which the first and second contact surfaces,By the following constitutionAndAnd equation (15) it can be seen that to avoid 0 after LLR quantization, it is necessary to satisfy:
i.e. adjusting the offsetAndThe actually calculated floating point LLR values are required to satisfy:
Is thatAnd has mathematical properties: the calculation may be performed by a look-up table.
In one example, a specific implementation step may include:
1) Determining voltage axis offset value by testing to obtain NAND threshold voltage distribution, and adjusting offsetAndSo that at the current offset setting, all floating point values actually calculated satisfy equation (17), thereby determiningAnd. Each voltage axis contains a pair of offset values, which can be stored in the master control.
2) According to the actual test result, calculating LLR value based on the settingAndAnd calculating LLR floating point values of each interval on the threshold voltage axis according to the threshold voltage distribution. As shown in FIG. 2, after each voltage axis is shifted and read, 4 sections are divided, if the flash page currently read containsThe voltage axis is divided into the threshold voltage axisEach interval, calculating LLR value of each interval according to formula (1), and recording as。
3) According to the hardware limit requirement, the main control provides the value of m, calculates the quantization point in the quantization scheme, if the LLR storage bit isThe first bit is a sign bit, and the sign is positive and negative. Then for the followingThe function is atShaftTaking at equal intervalsA point of the light-emitting diode is located,Every two points have a spacing of. Namely:
Based onDetermining to obtainCheck function table acquisitionThe quantization point can be obtained according to the formula (14)。
4) Normalization to obtainFor the floating point LLR vector calculated in step2The quantized result is calculated using equation (15):。
5) And (3) quantizing the floating points into integers, namely calculating quantized integer LLR values by using the quantized points calculated in the step (3) and normalized LLR floating point values calculated in the step (4), and storing the quantized integer LLR values into an LLR table maintained in a main control by using a formula (12).
6) When SSD reads data, after normal reading and re-reading, hard decoding is failed, soft decoding is entered. The soft decoding performs multiple read operations such as normal read and left-right offset, which is obtained from the master control relative to the voltage axis during normal readAndObtaining a new voltage axisAnd) And performing multiple readings, and indicating which interval of the threshold voltage axis the voltage of the currently-read memory cell is located by utilizing the reading result, namely acquiring an interval index value. LLR values are correspondingly obtained from the LLR table by using the index values for LDPC soft decoding. See fig. 4 in detail.
7) The LLR calculation is performed off-line outside the SSD, and based on the result of pre-measuring the threshold voltage distribution, an LLR table is constructed after calculation and stored in the DDR of the main control, so that the calculation operation does not increase the calculation complexity and time delay of SSD reading operation.
In another example, if the hardware is limitedAnd the amplitude can only be represented using 3 bits,Then calculate the right side of inequality (17) by looking up a tableI.e. voltage axis offsetAndIs set so that the calculated actual floating point value deviation cannot be excessive, the maximum value of all calculated floating point values does not exceed 20 times the minimum value, the LLR value of each interval is calculated according to the actual NAND test result, and four interval LLRs in the LLR floating point number vector are assumed to beWherein the maximum of all interval values is 13.5. Calculating quantization points according to equation 3) and equation (18), i.e. from7 Points were inserted, respectively: CheckingThe function table is limited by the read voltage axis offset, and aims to reasonably configure and eliminate the occurrence of erasure.
A data processing apparatus according to an embodiment of the present invention is described below, and a data processing apparatus described below and other embodiments described herein may be referred to with reference to each other.
The embodiment of the invention discloses a data processing device, which is applied to a memory and comprises:
The calculation module is used for calculating and obtaining the read reliability degree of the floating point type corresponding to each of the plurality of read intervals according to the default read operation voltage, the first read offset and the second read offset;
The normalization module is used for carrying out normalization processing on the read reliability degree of the floating point type corresponding to each read interval respectively according to the preset upper limit of the storage bit;
The conversion module is used for converting the read reliability of the floating point type corresponding to each read interval after normalization processing into an integer type and recording the read reliability of the integer type corresponding to each read interval;
And the read processing module is used for decoding and correcting the read operation by utilizing the read reliability degree of the integer type corresponding to each read interval if the hard decoding of any read operation of the memory fails.
In one embodiment, the computing module is specifically configured to:
determining K read voltage axes according to the read operation voltage, the first read offset and the second read offset;
calculating the product of the interval numbers X and K corresponding to each reading voltage axis to obtain XK reading intervals;
and calculating the read reliability degree of the floating point type corresponding to the XK read intervals respectively.
In one embodiment, the normalization module is specifically configured to:
determining a maximum value in read reliability of the XK floating point types;
respectively calculating the ratio of the read reliability degree to the maximum value of the XK floating point types to obtain XK ratios;
And according to the XK ratios and the upper limit of the storage bit, calculating to obtain the read reliability degree of the floating point type corresponding to the XK read intervals after normalization processing.
In one embodiment, the normalization module is specifically configured to:
subtracting one from the upper limit of the storage bit to obtain a target value;
And calculating the product of the target value and the XK ratios to obtain the read reliability degree of the floating point type corresponding to the XK read intervals after normalization processing.
In one embodiment, the computing module is specifically configured to:
And respectively calculating the ratio of the probability of writing the character 0 to the probability of writing the character 1 in the XK reading intervals, and taking the corresponding ratio as the reading reliability of the floating point type corresponding to the XK reading intervals.
In one embodiment, the conversion module is specifically configured to:
reading from a main controller of a memory to obtain an upper limit of memory bits;
Calculating n quantization points by using the upper limit of the storage bit;
calculating by using the upper limit of the storage bit to obtain the maximum amplitude;
Constructing and obtaining a piecewise symbol function by utilizing the read reliability of the floating point type corresponding to each read interval after n quantization points, the maximum amplitude and the normalization processing;
and solving the piecewise symbol function to obtain the read reliability of the integer types corresponding to each read interval.
In one embodiment, the conversion module is specifically configured to:
calculating to obtain equidistant function values according to a first formula;
determining n quantization points unevenly distributed based on the equidistant function values;
Wherein, the first formula is:; and represents the function value corresponding to the quantization point xi, m represents the upper limit of the storage bits, i=1, 2.
In one embodiment, the conversion module is specifically configured to:
calculating according to a second formula to obtain the distance between two adjacent points;
Wherein, the second formula is D= (m-1)/n, D represents the distance, m represents the upper limit of the storage bit, and n represents the number of quantization points.
In one embodiment, the piecewise sign function is:
q1,q2,…,qn represents n quantization points, i=1, 2, n,And (3) representing the read reliability of the floating point type corresponding to each read interval after normalization processing, wherein sign () is a sign function for identifying the positive and negative of q (y), and magn represents the maximum amplitude.
In one embodiment, the conversion module is specifically configured to:
calculating according to a third formula to obtain a maximum amplitude;
wherein the third formula is magn =m-1 -1, magn represents the maximum amplitude, and m represents the upper limit of the storage bits.
In one embodiment, the conversion module is specifically configured to:
And generating a log-likelihood ratio table comprising the read reliability degree of the integer type corresponding to each read interval.
In one embodiment, the read processing module is specifically configured to:
Determining a read voltage and a corresponding read offset corresponding to a memory cell read by a read operation;
Reading the preset number of the memory cells for a plurality of times by using the read voltage and the read offset to obtain a read result;
Inquiring the read reliability degree of the integer type corresponding to the read result;
and decoding and correcting the read operation based on the read reliability degree of the queried integer type.
In one embodiment, the read processing module is specifically configured to:
and taking the log likelihood ratio value corresponding to the queried reading result as the reading reliability degree of the integer type corresponding to the reading result in the log likelihood ratio table corresponding to the preset number.
In one embodiment, the method further comprises:
And the circulation module is used for adjusting the preset number under the condition that the maximum adjustment times are not reached if the decoding error correction fails, and executing the steps based on the adjusted preset number, namely reading the preset number of the storage units by utilizing the read voltage and the read offset to obtain a read result, inquiring the read reliability degree of the integer type corresponding to the read result, and decoding and correcting the error of the read operation based on the read reliability degree of the inquired integer type.
In one embodiment, the method further comprises:
and the decoding success module is used for feeding back the data read by the reading operation to the corresponding client if the decoding error correction is successful.
In one embodiment, the method further comprises:
And the decoding failure module is used for executing corresponding data recovery operation under the condition that the maximum adjustment times are reached if the decoding error correction fails.
In one embodiment, the method further comprises:
and the adjusting module is used for counting the decoding error correction failure probability in a period of time, and adjusting the read operation voltage, the first read offset and/or the second read offset if the decoding error correction failure probability is greater than a preset probability threshold.
The more specific working process of each module and unit in this embodiment may refer to the corresponding content disclosed in the foregoing embodiment, and will not be described herein.
Therefore, the embodiment provides a data processing device, the amplitude of the read reliability degree of the floating point type is constrained to the upper limit of the storage bit set by hardware by the scheme, the number of the read intervals is calculated according to the default read operation voltage, the first read offset and the second read offset, quantization points can be taken more in the area with smaller LLR amplitude, and a small number of quantization points can be taken in the area with larger LLR value, so that the soft decoding capability and success rate after hard decoding failure of the read operation are improved.
An electronic device provided in the embodiments of the present invention is described below, and an electronic device described below may refer to other embodiments described herein.
Referring to fig. 5, an embodiment of the present invention discloses an electronic device, including:
A memory 501 for storing a computer program;
a processor 502 for executing the computer program to implement the method disclosed in any of the embodiments above.
In this embodiment, when executing the computer program stored in the memory, the processor may specifically implement the steps of calculating, according to a default read operation voltage, a first read offset, and a second read offset, a read reliability degree of a floating point type corresponding to each of a plurality of read intervals, performing normalization processing on the read reliability degree of the floating point type corresponding to each of the read intervals according to a preset upper limit of storage bits, converting the read reliability degree of the floating point type corresponding to each of the read intervals after normalization processing into an integer type, and recording the read reliability degree of the integer type corresponding to each of the read intervals, and if hard decoding for any read operation of the memory fails, performing decoding error correction on the read operation by using the read reliability degree of the integer type corresponding to each of the read intervals.
In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented, where K read voltage axes are determined according to the read operation voltage, the first read offset, and the second read offset, products of the interval numbers X and K corresponding to the read voltage axes are calculated to obtain XK read intervals, and read reliability degrees of floating point types corresponding to the XK read intervals are calculated.
In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented, where a maximum value of the read reliability degrees of XK floating point types is determined, ratios of the read reliability degrees of XK floating point types to the maximum value are calculated respectively to obtain XK ratios, and the read reliability degrees of the floating point types corresponding to the XK read intervals after normalization processing are calculated according to the XK ratios and the upper limit of the memory bits.
In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented, where the upper limit of the storage bit is subtracted by one to obtain a target value, and the product of the target value and XK ratios is calculated to obtain the read reliability of the floating point type corresponding to XK read intervals after normalization processing.
In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented, where the ratio of the probability of writing character 0 to the probability of writing character 1 in XK read intervals is calculated, and the corresponding ratio is used as the read reliability of the floating point type corresponding to the XK read intervals.
In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented, where the upper limit of the storage bit is read from the main controller of the memory, n quantization points are obtained by using the calculation of the upper limit of the storage bit, the maximum amplitude is obtained by using the calculation of the upper limit of the storage bit, the piecewise symbol function is constructed by using the n quantization points, the maximum amplitude and the read reliability of the floating point type corresponding to each read interval after normalization processing, and the piecewise symbol function is solved to obtain the read reliability of the integer type corresponding to each read interval.
In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented, where the distance between two adjacent points is calculated according to a second formula, where the second formula is d= (m-1)/n, D represents the distance, m represents the upper limit of the storage bits, and n represents the number of quantization points.
In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented, where the maximum amplitude is calculated according to a third formula, where the third formula is magn =m-1 -1, where magn represents the maximum amplitude, and where m represents the upper limit of the storage bits.
In this embodiment, the processor may be configured to generate a log likelihood ratio table including read reliability levels of integer types corresponding to the respective read intervals when executing the computer program stored in the memory.
In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented, where the read voltage and the corresponding read offset corresponding to the storage unit read by the read operation are determined, the preset number of times of the storage unit are read by using the read voltage and the read offset to obtain a read result, the read reliability degree of the integer type corresponding to the read result is queried, and decoding and error correction are performed on the read operation based on the queried read reliability degree of the integer type.
In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented, where in the log likelihood ratio table corresponding to the preset number, the log likelihood ratio corresponding to the queried reading result is used as the reading reliability degree of the integer type corresponding to the reading result.
In this embodiment, when executing the computer program stored in the memory, the processor may specifically implement the steps of adjusting the preset number if the decoding error correction fails, and executing the steps based on the adjusted preset number, by reading the preset number of storage units by using the read voltage and the read offset to obtain a read result, querying the read reliability of the integer type corresponding to the read result, and decoding the read operation based on the queried read reliability of the integer type.
In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented, where if decoding error correction is successful, the data read by the read operation is fed back to the corresponding client.
In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented, where if decoding error correction fails, the corresponding data recovery operation is executed if the maximum adjustment number is reached.
In this embodiment, when the processor executes the computer program stored in the memory, the method may specifically include counting decoding error correction failure probabilities within a period of time, and if the decoding error correction failure probabilities are greater than a preset probability threshold, adjusting a read operation voltage, a first read offset, and/or a second read offset.
Further, the embodiment of the invention also provides electronic equipment. The electronic device may be a server as shown in fig. 6 or a terminal as shown in fig. 7. Fig. 6 and 7 are structural diagrams of electronic devices according to an exemplary embodiment, and the contents of the drawings should not be construed as any limitation on the scope of use of the present invention.
Fig. 6 is a schematic structural diagram of a server according to an embodiment of the present invention. The server may include at least one processor, at least one memory, a power supply, a communication interface, an input-output interface, and a communication bus. Wherein the memory is configured to store a computer program that is loaded and executed by the processor to implement the relevant steps in the data processing disclosed in any of the foregoing embodiments.
In this embodiment, the power supply is configured to provide working voltages for each hardware device on the server, the communication interface is capable of creating a data transmission channel with an external device for the server, a communication protocol to which the communication interface conforms is any communication protocol applicable to the technical scheme of the present invention, and is not specifically limited herein, and the input/output interface is configured to obtain external input data or output data to the outside, where a specific interface type of the input/output interface may be selected according to a specific application requirement, and is not specifically limited herein.
In addition, the memory may be a read-only memory, a random access memory, a magnetic disk, an optical disk, or the like as a carrier for storing resources, where the resources stored include an operating system, a computer program, data, and the like, and the storage mode may be transient storage or permanent storage.
The operating system is used for managing and controlling each hardware device and computer program on the Server to realize the operation and processing of the processor on the data in the memory, and the operation and processing can be Windows Server, netware, unix, linux and the like. The computer program may further comprise a computer program capable of being used to perform other specific tasks in addition to the computer program capable of being used to perform the data processing method disclosed in any of the embodiments described above. The data may include data such as information on a developer of the application program in addition to data such as update information of the application program.
Fig. 7 is a schematic structural diagram of a terminal according to an embodiment of the present invention, where the terminal may specifically include, but is not limited to, a smart phone, a tablet computer, a notebook computer, a desktop computer, or the like.
In general, the terminal in this embodiment includes a processor and a memory.
The processor may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor may be implemented in at least one hardware form of DSP (DIGITAL SIGNAL Processing), FPGA (Field-Programmable gate array), PLA (Programmable Logic Array ). The processor may also include a main processor, which is a processor for processing data in a wake-up state, also called a CPU (Central Processing Unit ), and a coprocessor, which is a low-power processor for processing data in a standby state. In some embodiments, the processor may incorporate a GPU (Graphics Processing Unit, image processor) for rendering and rendering of content to be displayed by the display screen. In some embodiments, the processor may also include an AI (ARTIFICIAL INTELLIGENCE ) processor for processing computing operations related to machine learning.
The memory may include one or more computer non-volatile storage media, which may be non-transitory. The memory may also include high-speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In this embodiment, the memory is at least used to store a computer program, where the computer program, after being loaded and executed by the processor, can implement relevant steps in the data processing method performed by the terminal side disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory can also comprise an operating system, data and the like, and the storage mode can be short-term storage or permanent storage. The operating system may include Windows, unix, linux, among other things. The data may include, but is not limited to, update information for the application.
In some embodiments, the terminal may further include a display screen, an input-output interface, a communication interface, a sensor, a power supply, and a communication bus.
Those skilled in the art will appreciate that the structure shown in fig. 7 is not limiting of the terminal and may include more or fewer components than shown.
A non-volatile storage medium according to an embodiment of the present invention is described below, and the non-volatile storage medium described below and other embodiments described herein may be referred to with reference to each other.
A non-volatile storage medium for storing a computer program which, when executed by a processor, implements the data processing method disclosed in the foregoing embodiments. The nonvolatile storage medium is a computer readable nonvolatile storage medium, and can be read-only memory, random access memory, magnetic disk or optical disk, etc. as a carrier for storing resources, and the resources stored on the nonvolatile storage medium include an operating system, a computer program, data, etc., and the storage mode can be transient storage or permanent storage.
A computer program product provided by embodiments of the present invention is described below, and the computer program product described below may be referred to with respect to other embodiments described herein.
A computer program product comprising computer programs/instructions which when executed by a processor implement the steps of the previously disclosed data processing method.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, so that the same or similar parts between the embodiments are referred to each other.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software modules may be disposed in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of non-volatile storage medium known in the art.
While the principles and embodiments of the present invention have been described in detail in this application, the foregoing embodiments are provided to facilitate understanding of the principles and concepts of the invention and are further provided by one of ordinary skill in the art to which the invention pertains.