Detailed Description
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
It should be understood that the described embodiments are merely some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The following describes the technical scheme of the present invention in detail through examples.
Example 1
The present embodiment provides a wafer test result generation method, which may be performed by a corresponding wafer test result generation apparatus, which may be integrated in a wafer test device. Referring to fig. 1, the method specifically includes the following steps 101-103.
Step 101, obtaining a plurality of test files generated by performing a plurality of tests on the same wafer.
In a specific process of wafer testing, a wafer to be tested may be first selected and placed on a test platform. Test platforms are often equipped with a variety of test equipment, such as probe stations and test instruments. Subsequently, various tests such as an electrical characteristic test, a functional test, a performance test, and the like are performed on the semiconductor chips distributed on the wafer using the test apparatus. After each wafer test is completed, the test equipment generates a test file for recording the test results of all the semiconductor chips tested at the time. In order to ensure the integrity and accuracy of the data, the test files are also compressed and encrypted in some cases. Test files typically include extensive test details and result information, not just simple pass/fail flags, for example, which may contain the following categories of information:
1. Basic information such as:
Wafer number, namely, the number of each wafer is uniquely identified;
chip position: the specific coordinates (e.g., X, Y coordinates) of the semiconductor chip on the wafer;
test date and time, time record of each test;
Operator information, name or ID of the person performing the test;
2. test scenarios, such as:
Environmental conditions, namely environmental parameters such as temperature, humidity and the like during testing;
the power supply condition is information such as voltage, frequency and the like of a power supply;
test equipment, namely the model, brand and version of the used test equipment;
3. Test item
(1) Verifying whether the function of each semiconductor chip is normal;
(2) Electrical property testing, for example:
Measuring the input/output current and voltage of the chip;
Power consumption test, namely power consumption under different working states;
(3) Performance testing, for example:
Time sequence analysis, namely measuring delay time and rising/falling time of a signal;
Frequency response, namely testing the performance of the chip under different frequencies;
(4) Reliability tests, for example:
thermal testing, namely testing stability under different temperature conditions;
aging test, namely performance after long-time operation;
4. Test results, for example:
test data, namely specific electrical parameters and performance indexes;
a pass/fail determination as to whether each semiconductor chip meets an expected standard;
abnormal recording, namely any abnormal condition and specific parameter found in the test process;
5. Data analysis, for example:
Yield statistics, namely, the proportion of qualified chips to the total number of chips;
failure analysis, namely deeply analyzing the reasons of the unqualified chips;
trend analysis, analyzing potential problems in the production process based on historical data.
In practical applications, to verify the performance of semiconductor chips under different conditions (e.g., at different temperatures, voltages or signal frequencies), it is necessary to perform repeated tests on the same wafer to ensure the accuracy and reliability of the test. The repeated test strategy may be a full-coverage method, i.e. all semiconductor chips on the wafer are tested at each time, or a partial spot test, i.e. only a selected part of the semiconductor chips on the wafer are tested at each time, but the whole flow needs to ensure that each semiconductor chip is tested at least once, so as to realize the effective verification of the whole batch of chips.
The method comprises the steps of carrying out initial test on all semiconductor chips on a wafer, recording test results in one test file, and circularly retesting semiconductor chips which are not up to standard in the previous test on the wafer until preset stop conditions are met, wherein each retest result is independently recorded in one test file. The stop condition may be that the number of retests reaches a set threshold. In the preferred mode, the resource is concentrated in the problem chip, the test link is optimized, the test time and the resource can be saved, the test cost is reduced, the test result of the problem chip can be ensured to be more accurate and reliable, and the method is beneficial to identifying and correcting potential manufacturing defects or test errors.
The multiple test files generated by testing the same wafer for multiple times have various formats, and particularly can depend on manufacturers and industry standards of the test equipment, for example, the test files can be in STDF, JSON or proprietary formats, and can be stored in a designated storage area of the test equipment, for example, under a monitoring catalog in a configuration file. In performing this step 101, these test files stored on the test equipment are read.
Step 102, integrating the plurality of test files, wherein only the optimal test results are reserved for the plurality of test results of the same semiconductor chip on the wafer.
In this step 102, each test file obtained in step 101 may be read and compared one by one, and redundancy removal and updating of the semiconductor chip test result may be performed. The optimal test result refers to a test result which is screened out and has the best performance according to a preset chip quality evaluation standard in multiple tests on the same semiconductor chip. In specific implementation, the redundancy removal and updating of the test result of the semiconductor chip can be realized by adopting any one of the following mechanisms.
1. Optimal result screening mechanism
① And preprocessing all the test files to be integrated, and extracting the test result of each semiconductor chip.
② The test results for each semiconductor chip are scored according to predefined chip quality metrics (e.g., test accuracy, performance parameters, consistency, etc.).
③ And (5) for each semiconductor chip, reserving the test result with the highest score, and deleting the rest test records.
2. Incremental update mechanism
① A baseline test file is set as a test file blue book.
② Processing the remaining test files one by one, and for the test results in each file:
Comparing the semiconductor chip test result with the test result of the corresponding chip in the blue book, and if the new result is better, updating the test record in the blue book.
After the iteration processing of all the test files, the optimal test information of each semiconductor chip is reserved in the blue book.
3. Differential contrast mechanism
① An empty test file blue book is created.
② Processing all test files to be integrated one by one, and for each file:
Comparing the test records in the blue book, finding out the newly added or updated test result, updating the corresponding original test result in the blue book if the new test result is better, and skipping if the test results are identical, thereby avoiding repetition.
In this way, the blue book will gradually accumulate optimal test results while eliminating duplicate and inferior results.
In addition, to enhance maintainability, extensibility and reusability of the code, the present embodiment may construct a module chain structure to implement the multiple test file integration function in step 102. The method comprises the steps of integrating a task, namely, a plurality of independent subtasks, namely, disassembling the integrating task into a plurality of independent subtasks, designing a special module for each subtask, initializing a chain structure, and accessing each module into the chain structure as a node string according to the logic sequence of an integrating process in the process, so as to obtain a complete module chain. Illustratively, each module in the chain of modules may inherit an abstract base class that encapsulates the task implementation interfaces of the modules and pointers to the next nodes in the chain to ensure smooth collaboration between the modules.
Further, a pre-built module chain is called, and each test file obtained in step 101 is integrated. Once the module chain is constructed, operation of the module chain may be initiated by an initiation signal or program entry point. The front-most module in the chain is activated first, receiving as input the first test file. After each module completes its own task, the next module is found by the pointer of the next node, and the next module is called to continue processing based on the task realization interface of the next module until all modules complete their own tasks. For processing multiple test files, the module chain supports a loop call mechanism, which means that for each test file to be integrated, a complete link flow will be performed, thereby ensuring that all test data is unified, comprehensive and thorough integrated regardless of the number of files.
By means of the modular and chain structure dual advantages of the modular and chain structure, convenience in file integration function maintenance and expansion is remarkably improved. The independent module design ensures that the updating of a single component does not prevent the whole operation, improves the stability of the system, and the chain architecture is flexibly assembled and rapidly responds to the function change so as to meet the diversified requirements.
Optionally, if a plurality of test files generated by performing multiple tests on the same wafer are in a non-text format, the text format of the test files is converted, and then the step 102 is performed. When multiple tests are performed on the same wafer, multiple types of test files may be generated, which may be in a non-text format, such as binary, proprietary formats of specific hardware or software, and so forth. Before file integration, the conversion of these test files in non-text format into text format is a key step to ensure accurate and efficient data integration. Through this conversion process, the reliable access, management and processing efficiency of data can be improved.
And 103, obtaining a final test result of the wafer based on the integrated test file.
In this step, the integrated test file can be directly used as the final test result of the wafer. If the integrated test file is in a text format and the original test file is in a non-text format, the conversion operation of the non-text format is also required to be executed. Or clearing abnormal data and error data in the integrated test file, filling or removing missing data and the like, and ensuring the accuracy and the completeness of a final test result. Of course, the integrated data can be further subjected to statistical analysis, and the analysis results are summarized together with the integrated test file to be used as the final test result of the wafer.
Example two
The present embodiment optimizes the steps of integrating the test file on the basis of the above embodiment. Referring to fig. 2, a wafer test result generating method includes the following steps 201-204.
Step 201, a plurality of test files generated by performing a plurality of tests on the same wafer are obtained.
This step 201 is the same as step 101 in the first embodiment, and will not be described here again.
Step 202, selecting a test file from the plurality of test files as a test file blue book.
The test file blue book can be selected by selecting the earliest test file or the latest test file as the blue book based on time sequence, selecting the test file with the highest yield as the blue book based on the quality of the test result, and randomly selecting one test file as the blue book based on random sampling. As a preferred embodiment, all the test files obtained in step 201 are sorted by size, and the first (largest) test file is selected as the test file blue book. This approach has the following benefits:
The method has the advantages that the integration flow is simplified, namely the maximum file is taken as the blue book, which means that the file already contains the most comprehensive test result, when other files are integrated, only the test result missing in the blue book is needed to be supplemented, or the test record with the better result is updated, so that the complexity of data integration is simplified;
The data redundancy is reduced, namely the maximum file usually covers all or most of test scenes, so that repeated data input can be avoided in the integration process, the data redundancy is reduced, and the cleanliness and efficiency of a data set are improved;
the larger the file used as the blue book, the more comprehensive the test result is theoretically contained, and the final data set can be ensured to be as complete as possible in the integration process, so that the omission of important test data is avoided;
The method is convenient for difference identification, namely based on the maximum file, the newly added or different test results compared with the blue book in other files can be more easily identified, the difference can be processed in a targeted manner, and the accuracy and timeliness of integrated data are ensured;
optimizing storage and processing in subsequent data analysis and processing, an optimally integrated blueprint file may reduce the time and consumption of storage resources for data processing, as most of the necessary data is already effectively integrated.
Step 203, based on each remaining test file in turn, executing the following blue book modification process:
And replacing the corresponding original test result in the test file blue book with the new test result of the same semiconductor chip which is better in the current based test file, and adding the test result of the new semiconductor chip in the current based test file into the test file blue book.
The test file records wafer test results in a tree-like data structure, including information such as test point coordinates, test results, test equipment parameters, and test scenes of the semiconductor chip. The structure distinguishes the test results of different semiconductor chips in a branched mode, and the test result details of each semiconductor chip are described in detail through the hierarchical structures of the child nodes and the offspring nodes of the test units. Each node in the tree structure has its own unique identifier and set of attributes in a test file. Typically, identifiers of nodes in all test files generated by testing the same wafer multiple times are different to ensure accurate tracking and distinguishing of data. Thus, the identifiers of the test cell nodes and their descendants representing the test result details of the same semiconductor chip are different in different test files, e.g., for a particular semiconductor chip on the wafer, test cell node NodeA and child nodes SubNodeA and SubNodeA in test file 1 describe test result details for that chip at the time of the first test, and test cell node NodeB and child nodes SubNodeB1 and SubNodeB2 in test file 2 describe test result details for that chip at the time of the second test. Then the identifiers of nodes NodeA, subNodeA, subNodeA2, nodeB, subNodeB1, and SubNodeB2 are different. Wherein the identifiers may be distinguished by a serial number, for example the identifiers may be embodied as serial numbers.
In addition, the tree structure may further include a basic data definition node for storing specific data items related to specific test attributes, and establishing a reference relationship with the test unit node and its descendant nodes. In particular, the base data definition node may be linked to an attribute of the test element node or its descendant nodes such that the latter can directly reference the stored contents of the former. Under this mechanism, the value of a certain attribute of a test element node and/or its descendant nodes can be reduced to a unique identifier of the referenced underlying data definition node, thereby building an efficient data referencing relationship. Under normal conditions, the basic data definition node is usually used as an end node of the tree data structure, and is not provided with child nodes, and the child nodes, the test unit child nodes and the descendant nodes thereof are respectively positioned on different branches of the tree data structure, so that the independence and the definition of the data are ensured.
The basic data definition nodes are introduced into the tree data structure, and the advantages are that:
1. Data consistency
The basic data definition node provides a centralized management mode for storing specific data items related to the test attribute, so that the consistency and accuracy of data can be ensured to be maintained when the same data item is referenced in a plurality of test unit nodes;
2. Redundancy reduction
By defining the nodes by using the basic data, the same data can be prevented from being repeatedly stored in different test unit nodes and descendant nodes thereof, redundancy is reduced, storage space is saved, and potential errors are reduced;
3. easy maintenance
When the basic data is required to be updated, only one modification is needed in the basic data definition node, and all test unit nodes and descendant nodes referring to the node automatically reflect the change, so that the data maintenance efficiency is greatly improved;
4. Improving scalability
The user can easily add new data items without modifying the whole structure in a large scale, thereby being beneficial to adapting to future demand change;
5. Clear structure
The reference relation between the basic data definition node and the test unit node and the descendant nodes thereof clearly shows the logic association between the data, and is helpful for understanding and managing the complex data structure.
For example, fig. 3 shows a part of nodes in a tree data structure of a test file, specifically as follows:
the Info is a root node which is a starting point of the description of the wafer test result;
Lot is a batch node, a child node of Info, which represents a set of Die on a wafer and is used for tracking production and test progress;
unit, test Unit node, child node of Lot, represent a Die in a wafer;
Bin is a test result classification node, and is a child node of a Unit, and represents the grade or classification of the test result, such as good products, defective products and the like;
SerialNumber is a Die sequence number node, a child node of Unit;
flow, testing scene nodes and child nodes of Unit;
Test, namely testing item nodes and child nodes of the Flow;
BitString binary bit nodes, child nodes of Test, for representing pass/fail status of Test points in Test items;
PinMeasure pin measurement nodes, test sub-nodes, representing chip pin measurement data including but not limited to current, voltage, resistance and other electrical parameters;
evaluation, namely evaluating the child nodes of the node and Test, and describing the Evaluation information of the Test item result;
PatternResult a mode result node and a child node of a Test describe Test item results after a specific Test mode is executed;
StructureMeasure structural measurement nodes, child nodes of Test, measurement data describing the internal structure of the chip, such as the size of circuit layout, layer spacing and the like;
mfg, a test basic information node, a child node of Info, which describes the basic background and context of the test and can contain the following attributes of equipmentId, test equipment number information, equipmentType, test equipment type, MFGAREANAME, test site, MFGSTEPNAME, test station, operatorId, tester number, testCode, test program code number;
Component, component node, child node of Mfg, describes Component information directly related to the wafer fabrication process;
BinDesc child nodes of the Info, basic data defining nodes, describing detailed information of the test result;
ParamRef child nodes of the Info, basic data defining nodes, describing test parameter detailed information;
pattern, child node of Info, basic data definition node, describing logical relation between test condition and expected result;
PinRef child nodes of Info, basic data defining nodes, describing pin details related to test;
TestDesc child nodes of the Info, basic data defining nodes, describing test item details;
Wafer, child node of Info, basic data defining node, describing Wafer details.
Based on the test file framework of the tree data structure, the implementation of step 203 may be refined to perform the following operations:
identifying a target node in a test file based on the current, wherein the target node comprises a different-standard identical-core test unit node and a descendant node thereof with better chip quality attribute, and a different-standard identical-core test unit node and a descendant node thereof compared with a blue book of the test file;
And updating the target node and the association relation between the target node and the basic data definition node in the test file based on the current test file in the test file blue book.
The updating in the test file blue book may specifically include:
1. merging different-standard and different-efficiency basic data definition nodes
Different standard and different effect basic data definition nodes in a test file based on the current data definition nodes are added into a test file blue book, and a new identifier is given to the different standard and different effect basic data definition nodes in the test file blue book;
2. migration different-standard different-core test unit node and descendant node thereof
Aiming at the different-standard and different-core test unit nodes and the descendant nodes thereof in the test file based at present, firstly, the attribute values of the attributes of the basic data definition nodes are intensively referenced, updated into identifiers of the corresponding basic data definition nodes in the test file blue book, and then, the whole is migrated to the test file blue book, and a new identifier in the test file blue book is given to the test file blue book.
3. Optimizing different standard concentric test unit node
If the chip quality attribute of the different standard concentric test unit node in the current based test file is superior to the corresponding node in the test file blue book, aiming at the different standard concentric test unit node and its descendant node in the current based test file, firstly, the attribute of the basic data definition node is intensively referenced to the value of the attribute of the basic data definition node, and updated to the identifier of the corresponding basic data definition node in the test file blue book, and then, the different standard concentric test unit node and its descendant node in the current based test file are substituted for the corresponding node in the test file blue book, but the original identifier of the corresponding node in the test file blue book is kept unchanged.
The standard deviation identical basic data definition node refers to a basic data definition node which has different identifiers in a current test file and a test file blue book and the same key attribute name and value thereof, wherein the key attribute does not contain the identifier of the node, and the attribute can be preset by a person skilled in the art;
Different standard and different effect basic data definition nodes refer to basic data definition nodes which do not have the same identifier, key attribute name and value thereof with any basic data definition node in a test file blue book in the current test file;
Different standard concentric test unit nodes refer to nodes which have different identifiers in the current test file and the test file blue book and represent the same semiconductor chip;
The different-standard and different-core test unit nodes refer to nodes which do not have the same identifier as any test unit node in the blue book of the test file and do not represent the same semiconductor chip in the current test file.
Those skilled in the art will appreciate that other ways of updating may also be employed. For example, for the test unit node and its descendant node in the test file currently based on, the association relation with the basic data definition node in the test file blue book may be updated first, the attribute set of the association relation is referred to the value of the attribute of the alien standard identical basic data definition node, the value of the attribute of the alien standard identical basic data definition node in the test file blue book is updated to the identifier of the corresponding alien standard identical basic data definition node in the test file blue book, then the alien standard identical core and the alien standard identical core are distinguished and migrated or optimized to the test file blue book according to different modes, or the alien standard identical core and the alien standard identical core are distinguished and migrated or optimized to the test file blue book according to different modes, then the association relation with the basic data definition node in the test file blue book is updated, the attribute set of the attribute of the alien standard identical basic data definition node in the test file currently based on is referred to the value of the attribute of the alien standard identical basic data definition node, and the identifier of the alien standard identical basic data definition node in the test file blue book is updated. The present embodiment is not particularly limited thereto.
And 204, obtaining a final test result of the wafer based on the modified test file blue book.
Step 204 is the same as step 103 in the first embodiment, and will not be described here again.
Example III
This embodiment provides a preferred embodiment based on all of the embodiments described above. Referring to fig. 4, a wafer test result generating method includes the following steps 401-406.
Step 401, accessing a configuration file monitoring directory.
Step 402, judging whether a test file exists under the catalog.
Initially, a plurality of test files generated by testing the same wafer for a plurality of times are stored in the configuration file monitoring catalog. If so, steps 403-405 are performed. If not, step 406 is skipped.
Step 403, reading a test file according to the order of the files from big to small.
And 404, taking the read test file as a current test file, and sending the current test file into a module chain for modifying the blue book of the test file.
In this step 404, referring to fig. 5, the module chain includes a format conversion module 501, an information recording module 502, and a blue book modification module 503, which are sequentially connected.
The current test file fed into the module chain records the wafer test results in a tree-like data structure, and is encrypted and compressed. After decryption and decompression, the format conversion module 501 reads the current test file in a stream, the file contains node names and attribute names and byte lengths contained in each node, the bytes in the stream are traversed circularly, and the text format file is written according to the node names and the structures of the attribute names and values contained in the node names. The data structure of a text format file can be seen in the example of fig. 6, in which:
Unit, test Unit, representing a Die in a wafer, comprising following attributes of serialID, die sequence number, siteIndex, null value, nonsensical for wafer test, seqNumber, unit sequence number, STARTTIMESTAMP/ENDTIMESTAMP, start time and end time, recording test time stamp, chuckId, chuck ID, for representing chuck position on test machine;
Flow, test scene, including sequence, test scene serial number, context, test scene name, result, test result in test scene, STARTTIMESTAMP/ENDTIMESTAMP, and time stamp of start and end of test;
Test, test item, including following attributes, isBinnable, whether the Test item performs a binding operation, TESTDESCID, test item description ID for pointing to Test item detail description, result, test item overall result, componentHash, hash value, each bit value representing a switch of a specific physical meaning, alarm flag, lowSpecLimit/HIGHSPECLIMIT, low specification limit and high specification limit, defining Test range, PARAMREFPTR, parameter reference pointer for pointing to Test parameter detail description, STARTTIMESTAMP/ENDTIMESTAMP, and time stamp of start and end of Test.
Then, the information recording module 502 reads the current test file in text format, records the node type and the reference relation thereof in the current test file, and outputs the recording result and the current test file in text format to the blueprint modification module 503. The recording process specifically comprises the following steps:
Judging whether the current test file is the first test file in the chain;
If yes, the information recording module 502 records the following contents in the current test file, namely a, all basic data definition nodes, b, all test unit nodes and descendant nodes thereof, c, the maximum serial numbers of all test unit nodes, d, the maximum serial numbers of all similar basic data definition nodes;
if not, the information recording module 502 records the following contents in the current test file, namely a, different standard identical-efficiency basic data definition nodes and different standard different-efficiency basic data definition nodes, b, different standard identical-core test unit nodes and different standard different-core test unit nodes, and c, all test unit nodes and the reference relation between the descendant nodes and the basic data definition nodes.
Then, the blueprint modification module 503 determines whether the current test file is the first in-link test file. If so, the blueprint modification module 503 sets the current test file as the blueprint of the test file to be saved. If not, the blueprint modification module 503 performs the following steps:
(1) Merging different-standard and different-efficiency basic data definition nodes
Adding different standard and different effect basic data definition nodes in the current test file into the test file blue book, and resetting the serial numbers of the different standard and different effect basic data definition nodes to be the maximum serial numbers of all the current similar basic data definition nodes in the test file blue book plus 1;
(2) Migration different-standard different-core test unit node and descendant node thereof
① Updating the value of the attribute of the different-standard different-core test unit node and the descendant node of the different-standard different-core test unit node which refers to the basic data definition node in the current test file into the serial number of the corresponding basic data definition node in the blue book of the test file;
② Adding different-standard different-core test unit nodes and descendant nodes thereof in the current test file to corresponding nodes in the test file blue book, wherein the serial numbers of the different-standard different-core test unit nodes are reset to be that the maximum serial numbers of all test unit nodes in the test file blue book are added with 1;
(3) Optimized different-standard concentric test unit node and offspring node thereof
Comparing the chip quality attribute of the different standard concentric test unit in the current test file and the test file blue book, and judging whether the current test file and the test file are better;
if the former is better, the following file modification operations are sequentially carried out:
① Updating the values of the attributes of the different standard concentric test unit nodes and the descendant nodes of the basic data definition nodes in the current test file into serial numbers of the corresponding basic data definition nodes in the blue book of the test file;
② Replacing corresponding nodes in the blueprint of the test file by different standard concentric test unit nodes and offspring nodes in the current test file, and keeping the serial numbers of the different standard concentric test unit nodes unchanged;
If the latter is more preferable, the file modification operations ① and ② in (3) above are not performed.
Fig. 7 shows a specific example of the integration of the test file blue book with the current test file.
And step 405, deleting the test file which is input to the module chain at this time under the configuration file monitoring directory. Execution continues back to step 402.
And step 406, converting the test file blue book into a set non-text format, and outputting.
The module chain will output a duplicate and complete test file blue book. In this step 406, each node in the text format of the test file blue book may be converted into a set non-text format according to bytes, one by one, according to the data structure and type defined by the spec. Typically, the non-text format is a test file format stored under the initial configuration file monitor directory. The spec.xml specification file defines the complete structure of the test file, including data structure and type information for each node, indicating which attributes are necessary and which are optional. In the process of generating the test file in the non-text format, the definition in the spec.xml specification file is read, and the data is converted and stored according to the specified structure and data type. For example, the test file blueprint converted to a non-text format may be output to a profile monitor directory.
Example IV
The embodiment provides a wafer test result generating device, which can be used for executing the wafer test result generating method according to the embodiment of the invention, can be realized by software and/or hardware, and is integrated in wafer test equipment. Referring to fig. 8, the apparatus specifically includes the following units:
a test file obtaining unit 801, configured to obtain a plurality of test files generated by performing multiple tests on the same wafer;
a test file integrating unit 802, configured to integrate the plurality of test files, wherein only optimal test results are reserved for a plurality of test results of the same semiconductor chip on the wafer;
and the test result generating unit 803 is configured to obtain a final test result of the wafer based on the integrated test file.
The wafer test result generating device of the present embodiment can implement the wafer test result generating method of any one of the foregoing embodiments, and the implementation principle and the corresponding technical effects are basically the same, which is not described herein in detail.
In implementation, the test file integration unit 802 may include:
A blue book determination subunit 8021, configured to select one test file from the plurality of test files as a test file blue book;
the blue-ray modification subunit 8022 is configured to perform, based on each remaining test file in turn, the following blue-ray modification processing:
And replacing the corresponding original test result in the test file blue book with the new test result of the same semiconductor chip which is better in the current based test file, and adding the test result of the new semiconductor chip in the current based test file into the test file blue book.
Illustratively, the blue book modification subunit 8022 is specifically configured to:
Identifying a target node in a test file based on the current, wherein the target node comprises a different-standard identical-core test unit node and a descendant node thereof, and a different-standard identical-core test unit node and a descendant node thereof, wherein the different-standard identical-core test unit node and the descendant node thereof have better chip quality attribute compared with a blue book of the test file;
And updating the target node and the association relation between the target node and the basic data definition node in the test file based on the current test file in the test file blue book.
Further, the wafer test result generating apparatus provided in this embodiment further includes a test file sorting unit 804, configured to sort the plurality of test files according to a size;
the blue book determination subunit 8021 is specifically configured to select a first-ranked test file as a blue book of the test file.
As a preferred embodiment, the test file integration unit 802 is specifically configured to invoke a pre-built module chain to integrate the plurality of test files.
The wafer test result generating device provided in this embodiment further includes:
A format conversion unit 805 configured to perform text format conversion on the plurality of test files before the test file integration unit 802 integrates the plurality of test files;
and a test file generating unit 806, configured to perform a primary test on all the semiconductor chips on the wafer, record the test results in one test file, and repeatedly test the semiconductor chips on the wafer that have not reached the standard for the previous test until a preset stop condition is met, where the test results are recorded in one test file independently.
Fig. 9 is a schematic structural diagram of an embodiment of an electronic device according to the present invention, where the electronic device may include a housing 91, a processor 92, a memory 93, a circuit board 94 and a power circuit 95, where the circuit board 94 is disposed inside a space enclosed by the housing 91, the processor 92 and the memory 93 are disposed on the circuit board 94, the power circuit 95 is used to supply power to each circuit or device of the electronic device, the memory 93 is used to store executable program codes, and the processor 92 executes a program corresponding to the executable program codes by reading the executable program codes stored in the memory 93, so as to execute the wafer test result generating method according to any one of the foregoing embodiments.
The specific implementation of the above steps by the processor 92 and the further implementation of the steps by the processor 92 through the execution of executable program codes may be referred to in the description of the method embodiments of the present invention, and will not be repeated herein.
The electronic device exists in a variety of forms including, but not limited to:
(1) The server is similar to a general computer architecture in that the server is required to provide highly reliable service, and therefore, the server has higher requirements on processing capacity, stability, reliability, safety, expandability, manageability and the like;
(2) Other electronic devices having data processing and communication functions.
Furthermore, an embodiment of the present invention provides a computer readable storage medium, where one or more programs are stored, where the one or more programs may be executed by one or more processors, so as to implement the wafer test result generating method described in the foregoing embodiment.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.
In the embodiment of the invention, the term "and/or" describes the association relation of the association objects, which means that three relations can exist, for example, A and/or B, and can mean that A exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship.
In this specification, each embodiment is described in a related manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments.
In particular, for the device embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference is made to the description of the method embodiments in part.
For convenience of description, the above apparatus is described as being functionally divided into various units/modules, respectively. Of course, the functions of the various elements/modules may be implemented in the same piece or pieces of software and/or hardware when implementing the present invention.
Those skilled in the art will appreciate that implementing all or part of the above-described methods in accordance with the embodiments may be accomplished by way of a computer program stored on a computer readable storage medium, which when executed may comprise the steps of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a random-access Memory (Random Access Memory, RAM), or the like.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the present invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.