Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, well-known functions and constructions are not described in detail to avoid obscuring the present disclosure, i.e., not all features of an actual embodiment are described herein.
In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present in the present disclosure.
Spatial relationship terms such as "under", "above", "over" and the like may be used herein for convenience of description to describe one element or feature as illustrated in the figures in relation to another element or feature. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
With the continuous progress of technology in recent years, the performance and the preparation process of a semiconductor structure have been greatly developed, and in order to meet the use requirement of the semiconductor structure, a power supply structure is generally arranged on a substrate of the semiconductor structure.
However, when the power supply structure, the device structure, and the like are disposed on the front surface of the substrate, there are generally phenomena such as large power loss and interference between signals.
Based on this, the following technical solutions of the embodiments of the present disclosure are provided:
the embodiment of the disclosure provides a method for preparing a semiconductor structure, as shown in fig. 1, the method comprises the following steps:
Step S101, providing a substrate, and sequentially forming a buried power rail and a device structure on a first surface of the substrate;
step S102, forming a first dielectric layer on a second surface of a substrate, and performing an etching process on at least the first dielectric layer to form a through hole structure and an opening structure, wherein the opening structure is positioned around the through hole structure, and the through hole structure exposes a buried power rail;
step S103, performing a filling process to form a stress absorbing structure in the opening structure and a conductive structure in the via structure.
Thus, in the embodiment of the disclosure, the power supply structure (including but not limited to the conductive structure) originally arranged together with the transistors is directly transferred to the back of the transistors for rearrangement, so that signal interference between the transistors and the power supply structure is avoided while the arrangement density of the transistors in a unit area is increased, wiring congestion at the rear end of a circuit is reduced, power performance advantages are provided, and the reliability of a chip is enhanced. At the same time, further shortening of the process nodes is also facilitated. In addition, in the embodiment of the disclosure, due to the provision of the stress absorbing structure, even if the process step of thinning the substrate is performed in the process of forming the plurality of structures included in the power supply structure, the thermal stress generated in the process of forming the plurality of structures is effectively absorbed by the stress absorbing structure, so that the occurrence of defects such as structural delamination, cracks, warpage and the like caused by poor heat dissipation and thermal stress accumulation is reduced, which is helpful for improving various performances of the finally obtained semiconductor structure.
It should be understood that, although the steps in fig. 1 are shown in sequence as indicated by arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in fig. 1 may include multiple sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, nor do the order in which the sub-steps or stages are performed necessarily performed in sequence, but may be performed alternately or alternately with at least a portion of other steps or sub-steps of other steps.
In order that the above-recited objects, features and advantages of the present disclosure will become more readily apparent, a more particular description of the disclosure will be rendered by reference to the appended drawings. In describing embodiments of the present disclosure in detail, the schematic drawings are not necessarily to scale and are merely illustrative and should not be taken as limiting the scope of the disclosure.
Fig. 2 to 12 are process flow diagrams of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure, fig. 13 is a schematic structural diagram of a positional relationship among a buried power rail, a metal line structure, a conductive structure, and a stress absorbing structure according to an embodiment of the present disclosure, fig. 14 is a schematic structural diagram of a positional relationship among a buried power rail, a metal line structure, a conductive structure, and a stress absorbing structure according to another embodiment of the present disclosure, fig. 15 is a schematic structural diagram of a cross-sectional shape of a stress absorbing structure according to an embodiment of the present disclosure, and fig. 16 is a schematic structural diagram of a stress absorbing structure according to a different embodiment of the present disclosure.
The method for manufacturing the semiconductor structure provided by the embodiment of the disclosure is further described in detail below with reference to the accompanying drawings.
First, step S101 is performed, and as shown in fig. 2 to 5, a substrate 10 is provided, and a buried power rail 11 and a device structure 12 are sequentially formed on a first surface S1 of the substrate 10.
In some embodiments, as shown in fig. 2 and 3, providing the substrate 10 includes:
Providing a substrate 101;
Forming an etch stop layer 102 on a substrate 101;
A semiconductor layer 103 is formed on the etch stop layer 102.
Here, the substrate 101 may be a semiconductor material, and specifically may include an elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), or a III-V compound semiconductor material (e.g., a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), or a II-VI compound semiconductor material, or an organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the substrate is a silicon material. In some embodiments, the substrate 101 may comprise a wafer.
In some embodiments, the material of etch stop layer 102 may comprise any suitable material that may perform a time etch stop function during a thinning operation of substrate 10, including, but not limited to, a silicon germanium layer, etc.
In some embodiments, the semiconductor layer may include, but is not limited to, at least one of silicon, germanium, and the like, or a combination thereof.
In some embodiments, the first surface S1 of the substrate 10 may be the front surface of the substrate 10, but is not limited thereto, and in some other embodiments, the first surface S1 of the substrate 10 may also be the back surface of the substrate 10, which is not specifically limited herein, and may be flexibly selected according to practical situations.
In some embodiments, forming the buried power rail 11 and the device structure 12 in sequence on the first surface S1 of the substrate 10 includes:
Forming a second dielectric layer L2 on the semiconductor layer 103;
forming a trench structure (not shown) extending in a first direction in the second dielectric layer L2 and the semiconductor layer 103, the trench structure (not shown) not exposing the etch stop layer 102;
a filling process is performed to form buried power rails 11 in the trench structure (not identified in the figures);
Device structure 12 is formed.
Here, the material of the second dielectric layer L2 may include, but is not limited to, an insulating material of oxide, nitride, oxynitride, or the like. In some specific embodiments, the material of the second dielectric layer L2 may include, but is not limited to, silicon oxide (SiOx) or the like.
In some embodiments, the material of the buried power rail 11 may be a conductive material, and in particular may include, but is not limited to, a metallic material, such as one or more of Cu, co, W, ni and Ru. By selecting these materials, the resistivity of the buried power rail 11 is made low, which is advantageous for improving RC delay, processing speed of the chip, and power supply efficiency.
In some embodiments, device structure 12 may include, but is not limited to, a transistor or the like. The buried power rail 11 can be used for supplying power to the device structure 12, and the wider buried power rail 11 is beneficial to increasing the volume of the power rail, so that the resistance of the buried power rail 11 is reduced, the power supply resistance is correspondingly reduced, and the power supply efficiency of the device structure 12 is further improved, and the voltage drop is improved.
In some embodiments, after the semiconductor layer 103 is formed, the second dielectric layer L2 having a thinner thickness may be formed first, and then a process of forming a trench structure (not shown) is performed, and then a process of filling material to form the buried power rail 11 is performed.
Then, after the buried power rail 11 is formed, a step of forming the device structures 12 may be performed, and a process of forming the second dielectric layer L2 between the device structures 12 may be performed again during, before, or after the formation of the device structures 12 to achieve an effect of electrical insulation between the adjacent device structures 12.
In some embodiments, after forming device structure 12, the method of fabrication further includes forming conductive metal line structure 15, and the material of conductive metal line structure 15 may include a conductive metal, such as tungsten, or the like.
Then, step S102 is performed, as shown in fig. 8 and fig. 9, a first dielectric layer L1 is formed on the second surface S2 of the substrate 10, and an etching process is performed on at least the first dielectric layer L1 to form a via structure T and an opening structure H, where the opening structure H is located around the via structure T, and the via structure T exposes the buried power rail 11, where the first surface S1 and the second surface S2 are two surfaces disposed opposite to the substrate 10.
In some embodiments, the material of the first dielectric layer L1 may include, but is not limited to, an insulating material such as oxide, nitride, or oxynitride. In some specific embodiments, the material of the first dielectric layer L1 may include, but is not limited to, silicon oxide, and the like.
In some embodiments, the via structure T and the opening structure H may be formed in the same process step, but not limited thereto, and may be formed in different process steps to facilitate improvement of production efficiency. The design method of the opening structure H is compatible with the current fab process flow, and has the characteristics of simple structure and strong matching universality.
In some embodiments, the via structure T and the opening structure H may be obtained using a photolithography process to deepen a reactive ion etching process.
In some embodiments, as shown in fig. 7 and 8, before forming the first dielectric layer L1 on the second surface S2 of the substrate 10, the preparation method further includes:
thinning the substrate 10 from the second surface S2 to expose the etch stop layer 102;
The etch stop layer 102 is removed.
In some embodiments, the second surface S2 of the substrate 10 may be a back surface of the substrate 10, but is not limited thereto, and in some other embodiments, the second surface S2 of the substrate 10 may also be a front surface of the substrate 10, which is not specifically limited herein, and may be flexibly selected according to practical situations.
It should be noted that, in the embodiment of the disclosure, the first surface S1 and the second surface S2 are two surfaces disposed opposite to each other, for example, when the first surface S1 is a front surface, the second surface S2 may be a back surface, whereas when the first surface S1 is a back surface, the second surface S2 may be a front surface.
In some specific embodiments, the first surface S1 of the substrate 10 may be a front surface of the substrate 10, and the second surface S2 of the substrate 10 may be a back surface of the substrate 10.
In some embodiments, as shown in fig. 6, before thinning the substrate 10 from the second surface S2 to expose the etch stop layer 102, the method of preparing further comprises:
bonding the surface of the substrate 10 provided with the device structure 12 with the carrier plate 20;
the semiconductor structure is flipped 180 deg. so that the second surface S2 of the substrate 10 is facing upwards.
Here, before the semiconductor structure is flipped, the bonding operation is performed between the surface of the substrate 10 on which the device structure 12 is disposed and the carrier 20, so that the carrier 20 may perform an effective supporting function and may protect the structure located on the first surface S1 of the substrate 10 from being scratched or damaged during the subsequent process steps.
In some embodiments, performing an etching process on at least the first dielectric layer L1 to form a via structure T and an opening structure H includes:
an etching process is performed on the first dielectric layer L1 and the semiconductor layer 103 to form a via structure T and an opening structure H, wherein the via structure T and the opening structure H each expose the buried power rail 11 (refer to fig. 9 in detail).
Or alternatively
In other embodiments, an etching process is performed on the first dielectric layer L1 and the semiconductor layer 103 to form a via structure T and an opening structure H, wherein the via structure H exposes the buried power rail 11 and the opening structure H does not expose the buried power rail 11.
In the disclosed embodiments, the opening structure H may have various positions and forms, such as:
In some cases, the opening structure H may be located directly above the buried power rail 11, or a portion of the opening structure H in the same opening structure H may be located directly above the buried power rail 11, and the remaining portion of the opening structure H may be located around the buried power rail 11, and in structures at different positions, the opening structure H may have different depths, for example, when the opening structure H has a greater depth, the opening structure H may expose the buried power rail 11 located therebelow, and when the opening structure H has a smaller depth, the opening structure H may not expose the buried power rail 11 located therebelow. Specifically, the depth of the opening structure H and whether the buried power rail 11 needs to be exposed can be determined according to practical requirements, which is not limited herein.
In other cases, the relationship between the opening structure H and the buried power rail 11 may be other, for example, any portion of the same opening structure H may not be located directly above the buried power rail 11 but on the surrounding area of the buried power rail 11, and in this case, the dimension of the opening structure H on the second surface S2 perpendicular to the substrate 10 may not necessarily be limited to the distance between the surface of the buried power rail S1 and the top of the first dielectric layer, but may be a depth of a larger dimension than this distance in scope, that is, the embodiment is advantageous in better achieving the absorption effect of the finally obtained stress absorbing structure 13 on the thermal stress as compared with the previous embodiment. Specifically, the numerical range of the opening structure H may be flexibly selected according to practical situations, which is not specifically limited herein.
In some embodiments, in order to meet the requirement that the stress absorbing structure 13 formed by filling the material in the subsequent step S103 of the opening structure H better exerts the thermal stress, which may include the thermal stress generated during the preparation of the second surface of the substrate 10 and during other processes, the ratio of the dimension of the opening structure H in the direction perpendicular to the second surface S2 of the substrate 10 to the dimension of the via structure T in the direction perpendicular to the second surface S2 of the substrate 10 may be greater than 0 and less than or equal to 1.
In some embodiments, the ratio of the dimension of the opening structure H in the direction parallel to the second surface S2 to the dimension of the via structure T in the direction parallel to the second surface S2 may be greater than 0 and less than or equal to 1.
In the conventional structure, the through hole structure, the material filled in the through hole structure, the buried power supply rail, the device structure and the like are usually positioned on the same surface of the substrate, at this time, the area occupied on the plane of the substrate is more, the problems of signal interference and the like are often generated between the structures due to the closer distance, in addition, the layout mode also causes the wiring congestion phenomenon in the subsequent process, and the electric energy loss is increased.
In addition, the structures are arranged on the same surface of the substrate, so that the operation space reserved for the subsequent process is seriously reduced after the previous process is finished, the convenience of process operation is not facilitated, and the further shortening of process nodes is also not facilitated.
In the embodiment of the disclosure, the conductive structure obtained after the filling process of the subsequent step S103 is performed by the through hole structure can be used as a power supply structure of the semiconductor structure, so that the power supply structure which is originally arranged on the same surface with the transistors is transferred to the back of the transistors for rearrangement, which is beneficial to increasing the arrangement density of the transistors in a unit area, avoiding signal interference between the transistors and the power supply structure, reducing wiring congestion at the rear end of a circuit, providing power performance advantages, and enhancing the reliability of a chip. Meanwhile, in the embodiment of the disclosure, the structural layout can also release more space for the realization of the subsequent process, so that the occupation of the area of the interconnection line on the surface of the substrate provided with the device structure is reduced, and the further shortening of the process node is facilitated.
It will be appreciated that in preparing the plurality of structures on the second surface S2 of the substrate 10, it is generally necessary to perform a process that thins the substrate 10 (e.g., in some structures, the substrate may be thinned by 300nm, but is not limited thereto, and other thicknesses are possible) so that the resulting semiconductor structure has a lighter weight and a smaller volume. In addition, since these structures are usually made of materials involving different systems, such as but not limited to metal materials, semiconductor materials, and dielectric materials, the materials of different systems need to undergo different heat treatment conditions, so that the semiconductor structure undergoes a relatively complex heat treatment process during the preparation process, which easily causes the thermal stress to be continuously accumulated in the structure, and further affects the thermal stability of the structure, resulting in a reduction of the product yield.
In the embodiment of the present disclosure, the opening structure H is filled with a material having a preset thermal expansion coefficient in the subsequent process step S103 due to the opening structure H disposed around the via structure T, so that thermal stress generated during the preparation of multiple structures on the back surface of the substrate 10 can be effectively absorbed, thereby effectively reducing the occurrence of defects such as delamination, cracks, warpage, and the like, and contributing to improving various performances of the finally obtained semiconductor structure.
Finally, step S103 is performed, as shown in fig. 10 and 11, to perform a filling process to form the stress absorbing structure 13 in the opening structure H and to form the conductive structure 14 in the via structure T.
Here, the conductive structure 14 may be a through silicon via structure ((Through Silicon Via, TSV)
In some embodiments, a filling process is performed to form the stress absorbing structure 13 in the opening structure H and the conductive structure 14 in the via structure T, including:
filling a material having a predetermined thermal expansion coefficient into the opening structure H to form a stress absorbing structure 13;
A conductive material is filled into the via structure T to form the conductive structure 14.
In some embodiments, the material used to form the stress absorbing structure 13 may include, but is not limited to, a material having a lower coefficient of thermal expansion. The material used to form the conductive structure 14 may include, but is not limited to, a conductive metal, such as tungsten or the like.
In some specific embodiments, a chemical vapor deposition process may be used to deposit a high-toughness low-coefficient of thermal expansion organic polymer, such as a high-temperature resistant bismaleimide resin, or the like, in the open structure H to obtain the stress absorbing structure 13.
In some embodiments, the predetermined coefficient of thermal expansion of the material filled in the opening structure H ranges from greater than 0 and less than or equal to 3ppm/K.
It will be appreciated that in embodiments of the present disclosure, the via structure T and the opening structure H may be formed in the same process step to facilitate an improvement in production efficiency. Meanwhile, although the stress absorbing structure 13 is added in the embodiment of the disclosure, the structure can have better compatibility with the process of forming the conductive structure 14 in the forming process, that is, the design method provided in the embodiment of the disclosure can be compatible with the process of preparing the current semiconductor structure, and the obtained stress absorbing structure 13 has the characteristics of simple structure and strong matching universality.
In some embodiments, the cross-sectional shape of the stress absorbing structure 13 in a direction parallel to the second surface S2 of the substrate 10 includes at least one of a circle, an ellipse, a triangle, a quadrilateral, a regular hexagon, a polygon, and an irregular shape, or a combination thereof.
In some embodiments, the step S103 may be performed in the order of forming the stress absorbing structure 13 by filling the opening structure H first and then forming the conductive structure 14 by refilling the via structure T, but not limited thereto, and the step S103 may be performed in the order of forming the stress absorbing structure 13 by refilling the opening structure H after forming the conductive structure 14 by filling the via structure T first, and whatever the order, the thermal stress generated during the structure preparation process of the second surface S2 of the substrate 10 is effectively absorbed due to the stress absorbing structure 13, so that the occurrence of defects such as delamination, cracks, warpage of the structure may be effectively alleviated.
It will be appreciated that, in the embodiment in which step S103 may be performed by using the order in which the opening structure H is filled first to form the stress absorbing structure 13 and then the via structure T is refilled to form the conductive structure, the thermal stress generated during the formation of the conductive structure 14 is effectively absorbed due to the structure capable of absorbing the thermal stress formed in advance of the formation of the conductive structure 14, so that the thermal mechanical strain generated due to the mismatch of the thermal expansion coefficients of the materials is more effectively reduced, which is more helpful for finally achieving the effects of improving the wafer warpage and reducing the thermal mechanical stress of the structure.
In some embodiments, as shown in fig. 12 and fig. 13 and 14, after forming the stress absorbing structure 13 and the conductive structure 14, the method of preparing further includes:
A metallization process is performed to form a metal line structure 16 over the conductive structure, defining a region formed after the orthographic projections of the buried power rail 11 and the metal line structure 16 on the second surface S2 of the substrate 10 cross each other as a crossing region a, the conductive structure 14 being located on a portion of the crossing region a, and the stress absorbing structure 13 being located around the conductive structure 14.
In some embodiments, the material of the metal line structure 16 may include any suitable conductive metal, such as copper, tungsten, and the like.
In some embodiments, as shown in fig. 13, the intersection area a includes a first area A1 and a second area A2, the conductive structure 14 is located on the first area A1, the stress absorbing structure 13 is located at least on the second area A2, and the conductive structure 14 is spaced apart from the stress absorbing structure 13 along the direction in which the metal line structure 16 extends.
In other embodiments, as shown in fig. 14, the intersection region a includes a first region A1 provided with the conductive structure 14 and a second region A2 not provided with the conductive structure 14, and the stress absorbing structure 13 is located at least between the first region A1 and the second region A2 in the direction in which the buried power rail 11 extends.
In still other embodiments, the stress absorbing structure 13 may be located around the conductive structure 14, but not within the range defined by the orthographic projection of the buried power rail 11 and the metal line structure 16 on the substrate, but at least in part outside the range defined by the orthographic projection of the buried power rail 11 and the metal line structure 16 on the substrate.
But not limited thereto, in some embodiments, the location where the stress absorbing structure 13 is disposed may also be a combination of at least two of the locations provided by any of the above embodiments, for example, the stress absorbing structure 13 may include a structure located on the second area A2 of the intersection area a and between the first area A1 and the second area A2 of the intersection area a, or the stress absorbing structure 13 may also include a structure located on the second area A2 of the intersection area a and at least a portion of the structure located at a location outside the range defined by the front projection of the buried power rail 11 and the metal line structure 16 on the substrate, or the stress absorbing structure 13 may also include a structure located between the first area A1 and the second area A2 of the intersection area a and a structure located at a location outside the range defined by the front projection of the buried power rail 11 and the metal line structure 16 on the substrate. Specifically, in actual operation, the selection may be flexibly performed according to actual situations, which is not specifically limited herein.
In any of the above embodiments, the number of stress absorbing structures 13 located at the same position includes 1 or more, for example, 2, 3, 4, 5 or more, and the like, and meanwhile, the number of stress absorbing structures 13 located at different positions may be the same or different, and likewise, the dimensions of the stress absorbing structures 13 located at different positions on the second surface S2 parallel (or perpendicular) to the substrate 10 may be the same or different. Specifically, the number of the stress absorbing structures 13 to be increased or decreased at this position and the size of the stress absorbing structures 13 to be increased or decreased may be flexibly selected according to the actual situation, for example, whether thermal stress accumulation is likely to occur, and are not particularly limited herein.
It can be appreciated that in actual operation, the number and size of the stress absorbing structures can be flexibly selected according to actual conditions and design manuals to balance the relationship between thermal stress absorption and area occupation.
The embodiment of the disclosure further provides a semiconductor structure, as shown in fig. 12, including:
A substrate 10;
a buried power rail 11 and a device structure 12 disposed on the first surface S1 of the substrate 10 from bottom to top;
A first dielectric layer L1 on the second surface S2 of the substrate 10;
The stress absorbing structure 13 and the conductive structure 14, wherein part of the conductive structure 14 and at least part of the stress absorbing structure 13 are located in the first dielectric layer L1, and the stress absorbing structure 13 is located around the conductive structure 14, and the conductive structure 14 penetrates through the first dielectric layer L1 and is connected with the buried power rail 11.
In the embodiment of the disclosure, the first surface S1 and the second surface S2 are two surfaces disposed opposite to each other, for example, when the first surface S1 is a front surface, the second surface S2 may be a back surface, whereas when the first surface S1 is a back surface, the second surface S2 may be a front surface.
In some specific embodiments, the first surface S1 of the substrate 10 may be a front surface of the substrate 10, and the second surface S2 of the substrate 10 may be a back surface of the substrate 10.
Here, the conductive structure may be used as a power supply structure of the semiconductor structure.
In the embodiment of the disclosure, the power supply structure which is originally distributed together with the transistors is directly transferred to the back of the transistors for rearrangement, so that signal interference between the transistors and the power supply structure is avoided while the arrangement density of the transistors in a unit area is increased, wiring congestion at the rear end of a circuit is reduced, the power performance advantage is provided, and the reliability of a chip is enhanced. At the same time, further shortening of the process nodes is also facilitated. In addition, in the embodiment of the disclosure, due to the provision of the stress absorbing structure, even if the process step of thinning the substrate is performed in the process of forming the plurality of structures included in the power supply structure, the thermal stress generated in the process of forming the plurality of structures is effectively absorbed by the stress absorbing structure, so that the occurrence of defects such as structural delamination, cracks, warpage and the like caused by poor heat dissipation and thermal stress accumulation is reduced, which is helpful for improving various performances of the finally obtained semiconductor structure.
In some embodiments, the material used to form the conductive structure 14 may include, but is not limited to, a conductive metal, such as tungsten, or the like.
In some embodiments, the stress absorbing structure comprises a material having a predetermined coefficient of thermal expansion.
In some embodiments, the predetermined coefficient of thermal expansion of the material filled in the opening structure H ranges from greater than 0 and less than or equal to 3ppm/K.
In some specific embodiments, a chemical vapor deposition process may be used to deposit a high-toughness low-coefficient of thermal expansion organic polymer, such as a high-temperature resistant bismaleimide resin, or the like, in the open structure H to obtain the stress absorbing structure 13.
In some embodiments, as shown in fig. 15, the cross-sectional shape of the stress absorbing structure 13 in a direction parallel to the second surface S2 of the substrate 10 includes at least one of a circle, an ellipse, a triangle, a quadrilateral, a regular hexagon, a polygon, and an irregular shape, or a combination thereof.
In some embodiments, as shown in fig. 12 and 16, along the direction in which the first surface S1 points to the second surface S2, the stress absorbing structure 13 includes a first sub-portion 131 and a second sub-portion 132, and the thermal expansion coefficients of the first sub-portion 131 and the second sub-portion 132 are different (refer to (1) in fig. 16 in particular);
And/or the number of the groups of groups,
In a direction parallel to the second surface S2, the stress absorbing structure 13 includes a first sub-layer 13a and a second sub-layer 13b from inside to outside, and the coefficients of thermal expansion of the first sub-layer 13a and the second sub-layer 13b are different (refer to fig. 16 (2)).
It can be appreciated that when the stress absorbing structure 13 is provided with the first sub-portion 131 and the second sub-portion with different thermal expansion coefficients, and/or the first sub-layer 13a and the second sub-layer 13b with different thermal expansion coefficients are provided, the effect of providing a plurality of stress absorbing structures 13 at a single location is equivalent to that of providing a plurality of stress absorbing structures 13, and different thermal stress absorbing effects can be achieved at the location by the stress absorbing structures 13 located at different areas, which is helpful for a designer to perform a targeted design according to the distribution situation of the thermal stress, so as to meet the requirement situation of the semiconductor structure for thermal stress absorption in the preparation process, thereby reducing the thermo-mechanical strain generated by the non-adaptation of the thermal expansion coefficients of the materials, and being helpful for finally achieving the effects of improving the wafer warpage and reducing the thermal mechanical stress of the structure.
In some embodiments, as shown in fig. 13, the intersection area a includes a first area A1 and a second area A2, the conductive structure 14 is located on the first area A1, the stress absorbing structure 13 is located at least on the second area A2, and the conductive structure 14 is spaced apart from the stress absorbing structure 13 along the direction in which the metal line structure 16 extends.
In other embodiments, as shown in fig. 14, the intersection region a includes a first region A1 provided with the conductive structure 14 and a second region A2 not provided with the conductive structure 14, and the stress absorbing structure 13 is located at least between the first region A1 and the second region A2 in the direction in which the buried power rail 11 extends.
In still other embodiments, the stress absorbing structure 13 may be located around the conductive structure 14, but not within the range defined by the orthographic projection of the buried power rail 11 and the metal line structure 16 on the substrate, but at least in part outside the range defined by the orthographic projection of the buried power rail 11 and the metal line structure 16 on the substrate.
But not limited thereto, in some embodiments, the location where the stress absorbing structure 13 is disposed may also be a combination of at least two of the locations provided by any of the above embodiments, for example, the stress absorbing structure 13 may include a structure located on the second area A2 of the intersection area a and between the first area A1 and the second area A2 of the intersection area a, or the stress absorbing structure 13 may also include a structure located on the second area A2 of the intersection area a and at least a portion of the structure located at a location outside the range defined by the front projection of the buried power rail 11 and the metal line structure 16 on the substrate, or the stress absorbing structure 13 may also include a structure located between the first area A1 and the second area A2 of the intersection area a and a structure located at a location outside the range defined by the front projection of the buried power rail 11 and the metal line structure 16 on the substrate. Specifically, in actual operation, the selection may be flexibly performed according to actual situations, which is not specifically limited herein.
In any of the above embodiments, the number of stress absorbing structures 13 located at the same position includes 1 or more, for example, 2, 3, 4, 5 or more, and the like, and meanwhile, the number of stress absorbing structures 13 located at different positions may be the same or different, and likewise, the dimensions of the stress absorbing structures 13 located at different positions on the second surface S2 parallel (or perpendicular) to the substrate 10 may be the same or different. Specifically, the number of the stress absorbing structures 13 to be increased or decreased at this position and the size of the stress absorbing structures 13 to be increased or decreased may be flexibly selected according to the actual situation, for example, whether thermal stress accumulation is likely to occur, and are not particularly limited herein.
It can be appreciated that in actual operation, the number and size of the stress absorbing structures can be flexibly selected according to actual conditions and design manuals to balance the relationship between thermal stress absorption and area occupation.
It should be noted that the semiconductor structure and the method for manufacturing the same provided in the embodiments of the present disclosure may be applied to any semiconductor device including the structure, and are not limited herein. The embodiment of the semiconductor device manufacturing method and the embodiment of the semiconductor device provided by the disclosure belong to the same conception, and the technical features in the technical scheme recorded in each embodiment can be arbitrarily combined under the condition of no conflict.
The foregoing description of the preferred embodiments of the present disclosure is not intended to limit the scope of the present disclosure, but is intended to cover any modifications, equivalents, and improvements within the spirit and principles of the present disclosure.