Method for improving QoS of storage device in response to influence of consistency of storage mediumTechnical Field
The application relates to the technical field of storage, in particular to a method for improving QoS (quality of service) of storage equipment in response to the influence of consistency of storage media.
Background
FIG. 1A illustrates a block diagram of a storage device. The storage device 102 is coupled to a host for providing storage capability for the host. The host and storage device 102 may be coupled by a variety of means including, but not limited to, interfacing the host and storage device 102 via a variety of storage protocols such as SATA (SERIAL ADVANCED Technology Attachment ), SCSI (Small Computer system interface), SAS (SERIAL ATTACHED SCSI ), IDE (INTEGRATED DRIVE Electronics), USB (Universal Serial Bus ), PCIE (PERIPHERAL COMPONENT INTERCONNECT EXPRESS, PCIE, peripheral component interconnect), NVMe (NVM Express, high speed nonvolatile storage), ethernet, fibre channel, wireless communication network, etc. The host may be an information processing device capable of communicating with the storage device in the manner described above, such as a personal computer, tablet, server, portable computer, network switch, router, cellular telephone, personal digital assistant, or the like. The memory device 102 includes an interface 103, a control unit 104, one or more NVM chips 105, and a DRAM (Dynamic Random Access Memory ) 110.
NAND flash memory, phase change memory, feRAM (Ferroelectric RAM, ferroelectric memory), MRAM (Magnetic Random Access Memory, magnetoresistive memory), RRAM (RESISTIVE RANDOM ACCESS MEMORY, resistive memory), XPoint memory, and the like are common NVM.
The interface 103 may be adapted to exchange data with a host by means of, for example SATA, IDE, USB, PCIE, NVMe, SAS, ethernet, fibre channel, etc.
The control unit 104 is used to control data transfer among the interface 103, NVM chip 105, and DRAM 110, and also for memory management, host logical address to flash physical address mapping, erase balancing, bad block management, etc. The control component 104 can be implemented in a variety of ways, such as software, hardware, firmware, or a combination thereof, for example, the control component 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application SPECIFIC INTEGRATED Circuit), or a combination thereof. The control component 104 may also include a processor or controller in which software is executed to manipulate the hardware of the control component 104 to process IO (Input/Output) commands. Control unit 104 may also be coupled to DRAM 110 and may access data of DRAM 110. FTL tables and/or cached data of IO commands may be stored in the DRAM.
The control section 104 includes a flash interface controller (or referred to as a media interface controller, a flash channel controller) that is coupled to the NVM chip 105 and issues commands to the NVM chip 105 in a manner conforming to an interface protocol of the NVM chip 105 to operate the NVM chip 105 and receive a command execution result output from the NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI", and the like.
Fig. 1B shows a detailed block diagram of the control components of the storage device.
The host accesses the storage device in IO commands that follow the storage protocol. The control component generates one or more media interface commands based on the IO commands from the host and provides the media interface commands to the media interface controller. The media interface controller generates storage media access commands (e.g., program commands, read commands, erase commands) that follow the interface protocol of the NVM chip according to the media interface commands. The control unit also keeps track of all media interface commands generated from one IO command being executed and indicates to the host the result of processing the IO command.
Referring to fig. 1B, the control part includes, for example, a host interface, a host command processing unit, a storage command processing unit, a media interface controller, and a storage media management unit. The host interface acquires an IO command provided by the host and generates a storage command to be provided to the storage command processing unit. The storage commands, for example, access the same size of storage space, e.g., 4KB. The data unit of the data accessed by the corresponding one of the storage commands recorded in the NVM chip is referred to as a data frame. The physical page records one or more frames of data. For example, if the physical page size is 17664 bytes and the data frame size is 4KB, then one physical page can store 4 data frames.
The storage medium management unit maintains a logical address to physical address translation for each storage command. For example, the storage medium management unit includes FTL tables. For a read command, the storage medium management unit outputs a physical address corresponding to a logical address accessed by the storage command, for a write command, the storage medium management unit allocates an available physical address to the storage medium management unit, and records a mapping relationship between the logical address accessed by the storage medium management unit and the allocated physical address. The storage medium management unit also maintains functions required to manage the NVM chip, such as garbage collection, wear leveling, etc.
The storage command processing unit operates the medium interface controller to issue a storage medium access command to the NVM chip according to the physical address provided by the storage medium management unit. For purposes of clarity, commands sent by the host to the storage device are referred to as IO commands, commands sent by the host command processing unit to the storage command processing unit are referred to as storage commands, commands sent by the storage command processing unit to the media interface controller are referred to as media interface commands, and commands sent by the media interface controller to the NVM chip are referred to as storage media access commands. The storage medium access command follows the interface protocol of the NVM chip. SSD (Solid STATE DRIVES, solid state disk) includes multiple NVM chips. Each NVM chip includes one or more LUNs (Logical UNit, logical units), each logical unit including a plurality of physical blocks (blocks). As the storage capacity increases, the number of NVM chips/LUNs/blocks increases, as does the probability of storage media failure. To ensure reliability of delivery of stored data to users, RAID (Redundant Arrays of INDEPENDENT DISKS, disk array) like technology (simply RAID technology) is used in enterprise-level SSDs to construct data protection units across NVM chips/logic units, thereby ensuring that data is not lost even if a single NVM chip/logic unit fails. This also can cope with sporadic data errors that occur in SSD operation.
The page stripe is a data protection unit within the SSD that is constructed based on RAID technology, the page stripe being constructed in large blocks. A chunk includes a physical block from a plurality of logical units, and the plurality of logical units that provide the physical block to the chunk are referred to as a logical unit group. Each logical unit in the set of logical units may provide a physical block for a large block. For example, in the schematic diagram of a chunk shown in FIG. 2A, the chunk is constructed on n+1 logical units. Each chunk includes n+1 physical blocks from n+1 logical units, respectively. The chunk stores user data and verification data. And calculating to obtain the large-block check data according to the large-block stored user data. By way of example, the check data is stored in the last physical block of the large block. Other physical blocks of the large block may also be selected to store the check data. Other configurations may also be used to construct the large blocks, as shown with reference to FIG. 2B, which is an implementation of constructing the large blocks in a multi-planar logic cell.
Large blocks, which are used as allocation and reclamation units of SSDs to storage medium resources. When allocating storage medium resources to carry write data, free chunks are selected. Inside the selected chunk, data is written in sequence. When the storage medium resource is recovered, the whole block is recovered, and after the valid data is recovered, all physical blocks of the block are erased (Erase). Thus, within an SSD, all physical blocks within a large block typically always have the same number of erasures.
Referring to fig. 3A and 3B, a large block includes a plurality of page stripes including a plurality of physical pages from, for example, different physical blocks of the same large block. For example, among a plurality of physical pages of a page stripe, P pages are used to store user data, and Q pages are used to store check data (q=1 in fig. 3A and 3B). The data written to page i is denoted as D (i). The check data D (Q) is generated from P pages of user data according to a specified error correction algorithm. For example, the check data is determined based on an exclusive-or operation, then D (Q) =d (0) XOR D (1) XOR. Thus, in writing data to a page stripe, D (Q) can only be calculated if D (0) through D (P-1) are known. The size of D (i) is typically, for example, 2KB, 4KB, 16KB, etc.
In TLC (Triple-LEVEL CELL, three-tier storage) flash memory, one-Shot programming mode is typically used, requiring that 3 physical pages on the same word line be programmed in One ONFI command, which causes a single programming command to operate 3 physical pages. Accordingly, to improve write performance, page stripes are constructed in groups of 1 for 3 physical pages, such that the size of D (Q) is typically 48KB. In a multi-plane TLB (Translation Lookaside Buffer, translation detect buffer) flash, a multi-plane programming mode may be used to improve write performance. This results in a single program command to operate on, for example, 12 physical pages (including 4 planes per logical unit). Accordingly, the size of D (Q) is typically 192KB.
In order to use RAID techniques, it is necessary to calculate the parity data D (Q) for the data written to the page stripe. Calculating the verification data involves a large number of XOR operations, and to accelerate this process, the calculation of D (Q) =d (0) XOR D (1) xor..xor D (P-1) is typically done using a dedicated hardware unit (called XOR calculation unit). The XOR computation unit further comprises an XOR buffer for buffering the data D (i), and intermediate results of each XOR computation, e.g. the result of D (0) XOR D (1), the result of D (0) XOR D (1) XOR D (2), until a final D (Q) is obtained, and then D (Q) is written to the page stripe. The XOR buffer thus needs to be sized to accommodate the entire D (i) and to be occupied to service the write of data to a page stripe before it is allocated from the beginning of the write of data to the page stripe to the full page stripe.
To improve the performance of SSDs, data may be written to multiple page stripes of multiple large blocks simultaneously, with each page stripe written concurrently correspondingly requiring its exclusive XOR cache to be allocated. As mentioned earlier, D (Q) may be up to 192KB in size (and also include some out-of-band data), so that a single XOR cache requires around 200KB of capacity. While on-chip cache resources are quite expensive, the number of XOR caches of the XOR computation unit is typically small (e.g. 1-4).
In chinese patent applications such as 201610861793.5, 2016108365313, 201720947480.1, 2020106151782, 2020106130343, media interface controllers are provided. In the prior art, the XOR calculation unit is located in the media interface controller, as shown in fig. 4A and 4B. Page stripes with different data protection capabilities are adapted by operating the XOR calculation unit. The data protection level of the page stripe is determined by the size relationship of the check data and the user data, i.e. the values of P and Q represent the data protection capability of the page stripe. And, the XOR computation is completed during the process of the media interface controller providing data (e.g., D (0)) to the NVM chip (e.g., physical pages P0-0) through (Program) programming commands. For example, assuming that page stripe 0 is assigned XOR buffer 0 (initialized to all 0), during the move of D (0) to physical page P0-0 of page stripe 0, 0XOR D (0) is calculated, the result is D (0) and stored in XOR buffer 0, then D (1) is moved to physical page P0-1 of page stripe 0, D (0) XOR D (1) is calculated, where D (0) is internal to XOR buffer 0, D (1) is obtained in the data move, then the result of D (0) XOR D (1) is recorded in XOR buffer 0, then D (2) is moved to physical page P0-2 of page stripe 0, the result of D (0) XOR D (1) recorded in XOR buffer 0 is XOR-ed with the moved D (2), and the result is still stored in XOR buffer 0. With this push, D (Q) is obtained in XOR buffer 0 after D (P-1) is moved to physical page P0- (P-1) of page stripe 0, which in turn moves D (Q) to physical page P0-P of page stripe 0. To this point page stripe 0 is written full and XOR cache 0 is released.
As an optimization, the media interface command received by the media interface controller may include only the indication of the physical address of each page of the page stripe to which D (0) to D (P-1) are written, and not the indication of the page stripe to which D (Q) is written. D (Q) is automatically calculated by the media interface controller and written to the page stripe.
For a media interface controller, it needs to manage multiple Logical Units (LUNs), see fig. 5. And for the purpose of, for example, performance, it is necessary to fully exploit the capability of parallel processing of commands between a plurality of logic units, and to control the cost of the media interface controller, reducing its circuit scale. In the prior art (e.g., chinese patent application 201610861793.5), a media interface controller is provided that includes multiple threads. The thread is used as a task processing unit capable of being scheduled, can be dynamically bound with the logic unit, and processes commands to the logic unit bound with the thread through the thread. In the chinese patent application No. 2022117373066, the co-program is used as a task processing unit corresponding to a logic unit, and the micro instruction sequence is executed by the co-program to operate the access to the logic unit, for example, see fig. 5. In fig. 5, the host interface acquires an IO command provided by the host and generates a storage command to be provided to the storage command processing unit. The storage commands, for example, access the same size of storage space, e.g., 4KB. There is also a prior art in which a corresponding Flash Controller (Flash Controller) is provided for each Flash channel or logical unit, and the logical unit bound thereto is operated by providing commands to the Flash Controller.
Whether a software or firmware based thread, coroutine, or hardware based flash controller, acts as a task processing unit that is operable to access the logic units to which it is bound. Multiple task processing units can work in parallel, operating multiple logic units simultaneously. For clarity purposes, it is referred to as a LUN controller. Implementations include prior art threads, coroutines, flash memory controllers, and other similarly functioning implementations of media interface controllers, as well as future implementations of media interface controllers that bind to logical units for operation access to logical units. Thus, among media interface commands provided to the media interface controller, the LUN controller is specified to process the media interface commands and access the logical units by describing the logical units to be accessed.
In the existing scheme, besides completing XOR calculation in the process that the media interface controller provides data (e.g., D (0)) to the NVM chip through a programming command, a function is added to the media interface controller, for example, the media interface controller provided in chinese patent application No. 201911367405.8 can perform XOR operation on specified data in the DRAM, but does not necessarily write the specified data to the NVM chip. Thus, when operating a page stripe where P takes a large value, the computation of D (Q) is divided into multiple segments. For example, in section 1, D (0) XOR D (1) XOR (D2). XOR D (m) (which results in temp), and in section 2, temp XOR D (m+1) XOR. Wherein temp transferred to the XOR computation unit in paragraph 2 is not written to the NVM chip.
The operation in which the XOR calculation unit performs XOR calculation on the specified data in the DRAM, but does not write the specified data to the NVM chip is referred to as a check data calculation operation (abbreviated as R operation). Two of the R operations that participate in the XOR computation, one from the XOR cache and one from the DRAM, require the DRAM address to be described in the media interface command that instructs the media interface controller to perform the R operation, and also require the XOR cache to be designated for use in operation. In the R operation, the result of the XOR calculation remains in the XOR buffer.
And a media interface command instructing the media interface controller to perform a programming operation, in the sense that specified data in the DRAM is written to a specified physical address of the NVM chip through the Program command, and the XOR calculation is performed with the specified data and data in the XOR buffer, with the calculation result remaining in the XOR buffer, the operation being simply referred to as a P operation.
The specified data in the DRAM is used to generate the parity data and write the page stripe, typically in a manner that cooperates with the P operation and the write of the data in the XOR cache to the NVM chip.
Disclosure of Invention
When erasing a physical block in a large block, a preceding erasing operation needs to occupy an NVM chip for a long time, which further causes a subsequent programming (Program) command on the NVM chip to be delayed, and further causes that an XOR buffer corresponding to a page stripe to which a physical page operated by the programming command belongs cannot be released in time, so that the XOR buffer occupation time becomes longer, and the utilization rate of the XOR buffer is reduced.
Moreover, when the storage medium resource is recovered, the whole block is recovered, and after the valid data is recovered, all physical blocks of the block are erased. The power consumption required when the NVM chip performs an erase operation is large, and the simultaneous erasure of all physical blocks of a large block further increases the instantaneous power consumption of the memory device, possibly even beyond the power capability of the receiving memory device. Fluctuations in power consumption also pose challenges to the power supply capability of the data center. It is therefore desirable to be able to suppress fluctuations in power consumption during operation of the memory device.
On the other hand, XOR cache resources within the storage device are limited, and it is desirable to complete processing performed using the XOR cache resources as soon as possible to release the XOR cache as early as possible to improve resource utilization. However, when there is an erase operation, the LUN controller performing the erase operation is also occupied, so that the processing of the subsequent programming operation and/or operation using XOR caching by the LUN controller is deferred. This problem can be alleviated to a certain extent by scheduling the LUN controllers, however, when a large block is reclaimed and all physical blocks of the large block are erased, all LUN controllers are occupied by the erase operation, so that an idle LUN controller cannot be found to handle the operation using the XOR buffer, further, the occupied time of the XOR buffer is increased, the utilization efficiency is reduced, and the read/write performance of the storage device is reduced or fluctuates.
By trying to distribute IO commands from the host evenly to each NVM chip or Logical Unit (LUN) of the storage device, the parallel IO command processing capability of the storage device is fully utilized, which helps to improve the performance of the storage device. However, as NVM chips increase on storage devices, consistency issues have also been found for each NVM chip, each LUN, and/or each physical block. In addition to the data reliability index represented by the bit error rate, accesses to some physical blocks have a faster or slower response speed than other physical blocks. Such storage medium performance inconsistencies may further accumulate, resulting in the blocking of one or more LUN controllers or the stacking of their processed tasks (medium interface commands), resulting in host-perceived QoS issues for IO command processing (e.g., fluctuations in processing delays of different IO commands), and also resulting in some internal resources of the control unit (e.g., XOR buffers) being occupied for a long period of time, affecting the performance of the control unit (e.g., bandwidth).
The present application seeks to provide a method to address one or more of the above mentioned technical problems.
In a first aspect, an embodiment of the present application provides a command allocation method, including obtaining an operation type indicated by a media interface command in response to the received media interface command, determining a LUN controller associated with the media interface command and the operation type, allocating the media interface command to the LUN controller, and processing the media interface command by the LUN controller, where the operation type includes a P1 operation or an R operation, the P1 operation indicates that specified data in a memory is moved to an NVM chip, and the R operation indicates that XOR computation is performed on the specified data in the memory and a calculation result is reserved in an XOR cache.
Optionally, the operation type further includes a P2 operation, the P2 operation indicating to move data in the XOR cache to the NVM chip.
Optionally, the obtaining the operation type indicated by the media interface command includes determining, based on an operation type field included in the media interface command, an operation type corresponding to the media interface command.
Optionally, in the case that the operation type is a P1 operation or a P2 operation, the media interface command includes a field indicating a physical address of the NVM chip to be accessed and a field indicating data to be moved, and the determining the LUN controller associated with the media interface command and the operation type includes determining the accessed logical unit based on the physical address indicated by the media interface command, and determining the LUN controller corresponding to the accessed logical unit based on a mapping relationship between the logical unit and the LUN controller.
Optionally, in the case that the operation type is P1 operation, in response to the accessed physical page and the specified data in the memory, the LUN controller generates a storage medium access command and sends the storage medium access command to a corresponding logic unit to write the specified data to the corresponding physical page to perform the P1 operation, where the accessed physical page is determined based on the physical address indicated by the medium interface command, and the specified data is the data to be moved in the memory indicated by the medium interface command.
Optionally, in the case that the operation type is a P2 operation, in response to the accessed physical page and check data in the XOR cache, the LUN controller generates a storage medium access command and sends the storage medium access command to a corresponding logical unit to write the check data to the corresponding physical page to perform the P2 operation, where the accessed physical page is determined based on a physical address indicated by the medium interface command, the check data is data to be moved in the XOR cache indicated by the medium interface command, and the check data is determined based on a plurality of specified data to be moved in the memory, and the plurality of specified data are written to a same page stripe.
Optionally, in the case where the operation type is an R operation, the determining the LUN controller associated with the media interface command and the operation type includes determining a LUN controller determined from a plurality of LUN controllers that has no pending erase operation as the LUN controller associated with the media interface command and the operation type.
Optionally, in the case that the media interface command includes a field indicating a LUN controller, determining that there is no unprocessed completed erasure operation as the LUN controller associated with the media interface command and the operation type includes determining a first LUN controller based on the LUN controller indicated by the media interface command, determining that there is no unprocessed completed erasure operation as the LUN controller associated with the media interface command and the operation type if the first LUN controller does not have an unprocessed completed erasure operation, and determining that there is no unprocessed completed erasure operation determined from a plurality of LUN controllers as the LUN controller associated with the media interface command and the operation type if the first LUN controller has an unprocessed completed erasure operation.
Optionally, the field indicating the LUN controller is a field indicating a logical unit to be accessed.
Optionally, the media interface command includes a source address field and a destination address field indicating data to be operated, the method further includes applying for an XOR buffer based on the destination address indicated by the media interface command, and in case of successful application, performing an XOR operation on the data to be operated indicated by the source address field and the data in the applied XOR buffer by the determined LUN controller, and reserving a calculation result in the applied XOR buffer.
Optionally, the method further comprises repeatedly applying for the XOR buffer based on the destination address indicated by the media interface command until the application is successful in case of application failure.
Optionally, the method further comprises releasing the applied XOR cache in response to the determined LUN controller completing the R operation.
Optionally, if the LUN controller has an erase operation that is not processed, the LUN controller processes the media interface command with the operation type of P1 operation or P2 operation after the LUN controller processes the erase operation.
Optionally, if the operation type indicates an erase operation, acquiring the number of erase operations being processed by one or more LUN controllers, if the number of erase operations being processed by one or more LUN controllers is greater than a threshold, suspending processing the media interface command whose operation type is an erase operation, and if the number of erase operations being processed by all LUN controllers is not greater than the threshold, determining an accessed logical unit based on a physical address indicated by the media interface command, and determining a LUN controller corresponding to the accessed logical unit based on a mapping relationship between the logical unit and the LUN controllers.
In a second aspect, an embodiment of the present application provides a media interface controller, including a command allocation unit and a plurality of LUN controllers, where the command allocation unit responds to a received media interface command, obtains an operation type indicated by the media interface command, determines LUN controllers associated with the media interface command and the operation type among the plurality of LUN controllers, allocates the media interface command to the LUN controllers, and processes the media interface command by the LUN controllers, where the operation type is a P1 operation or an R operation, where the P1 operation indicates that specified data in a memory is moved to an NVM chip, and the R operation indicates that XOR calculation is performed on the specified data in the memory, and a calculation result is reserved in an XOR cache.
Optionally, the operation type further includes a P2 operation, the P2 operation indicating to move data in the XOR cache to the NVM chip.
Optionally, the command allocation unit determines an operation type corresponding to the media interface command based on an operation type field included in the media interface command.
Optionally, in the case that the operation type is a P1 operation or a P2 operation, the media interface command includes a field indicating a physical address of the NVM chip to be accessed and a field indicating data to be moved, the command allocation unit determines the accessed logical unit based on the physical address indicated by the media interface command, and determines the LUN controller corresponding to the accessed logical unit based on a mapping relationship between the logical unit and the LUN controller.
Optionally, in the case that the operation type is P1 operation, in response to the accessed physical page and the specified data in the memory, the LUN controller generates a storage medium access command and sends the storage medium access command to a corresponding logic unit to write the specified data to the corresponding physical page to perform the P1 operation, where the accessed physical page is determined based on the physical address indicated by the medium interface command, and the specified data is the data to be moved in the memory indicated by the medium interface command.
Optionally, in the case that the operation type is a P2 operation, in response to the accessed physical page and check data in the XOR cache, the LUN controller generates a storage medium access command and sends the storage medium access command to a corresponding logical unit to write the check data to the corresponding physical page to perform the P2 operation, where the accessed physical page is determined based on a physical address indicated by the medium interface command, the check data is data to be moved in the XOR cache indicated by the medium interface command, and the check data is determined based on a plurality of specified data to be moved in the memory, and the plurality of specified data are written to a same page stripe.
Optionally, in the case where the operation type is R operation, the command assigning unit determines a LUN controller, determined from among the plurality of LUN controllers, for which there is no unprocessed completed erase operation as a LUN controller associated with the media interface command and the operation type.
Optionally, in the case that the media interface command includes a field indicating a LUN controller, the command assigning unit determines a first LUN controller based on the LUN controller indicated by the media interface command, determines the first LUN controller as a LUN controller associated with the media interface command and the operation type if there is no unprocessed erase operation on the first LUN controller, and
If the first LUN controller has an unprocessed erasing operation, the command distribution unit determines a second LUN controller which is determined from a plurality of LUN controllers and has no unprocessed erasing operation as the LUN controller associated with the medium interface command and the operation type.
Optionally, the field indicating the LUN controller is a field indicating a logical unit to be accessed.
Optionally, the media interface command includes a source address field and a destination address field indicating data to be operated, the determined LUN controller applies for an XOR buffer based on the destination address indicated by the media interface command, and in case of successful application, the determined LUN controller performs an XOR operation on the data to be operated indicated by the source address field and the data in the applied XOR buffer, and retains a calculation result in the applied XOR buffer.
Optionally, in case of application failure, repeatedly applying for XOR buffering based on the destination address indicated by the media interface command until application is successful.
Optionally, releasing the applied XOR cache in response to the determined LUN controller completing the R operation.
Optionally, if the LUN controller has an erase operation that is not processed, the LUN controller processes the media interface command with the operation type of P1 operation or P2 operation after the LUN controller processes the erase operation.
Optionally, if the operation type indicates an erase operation, the command allocation unit obtains the number of erase operations being processed by one or more LUN controllers, if the number of erase operations being processed by one or more LUN controllers is greater than a threshold, the command allocation unit suspends processing the media interface command whose operation type is an erase operation, and if the number of erase operations being processed by all LUN controllers is not greater than the threshold, the command allocation unit determines the logical unit being accessed based on the physical address indicated by the media interface command, and determines the LUN controller corresponding to the logical unit being accessed based on a mapping relationship between the logical unit and the LUN controller.
In a third aspect, an embodiment of the present application provides a data access method, including generating, in response to writing specified data to each first physical page of a first page stripe, a pair of P1 operations and R operations, where the P1 operations indicate to move the specified data in a memory to an NVM chip, and the R operations indicate to perform XOR computation on the specified data in the memory and to reserve a computation result in a first XOR cache corresponding to the first page stripe, where the first page stripe includes a second physical page and a plurality of first physical pages, and generating, in response to writing data to the second physical page of the first page stripe, a P2 operation, where the P2 operations indicate to write check data in the first XOR cache to the second physical page of the first page stripe.
Optionally, after determining the check data corresponding to the first page stripe according to the R operations respectively corresponding to the plurality of first physical pages, processing the P2 operation.
Optionally, the method further comprises allocating the first XOR buffer for the first page stripe of specified data to be written into the memory.
Optionally, when processing the generated P1 operation and the R operation, the method comprises the steps of determining a corresponding first LUN controller according to a logic unit to which a first physical page indicated by the P1 operation belongs when processing each P1 operation, processing the P1 operation through the first LUN controller to write the specified data in the memory indicated by the P1 operation into the first physical page indicated by the P1 operation, determining a second LUN controller for processing the R operation when processing each R operation, processing the R operation through the second LUN controller, performing an XOR operation on the specified data indicated by the R operation, and storing an operation result in the first XOR cache.
Optionally, the determining a second LUN controller that handles the R operation includes determining a LUN controller from among a plurality of LUN controllers that does not have an unprocessed completed erase operation as the second LUN controller.
Optionally, if the first LUN controller has an unprocessed and completed erase operation, determining a LUN controller without an unprocessed and completed erase operation from a plurality of LUN controllers, determining the LUN controller as the second LUN controller, and if the first LUN controller has no unprocessed and completed erase operation, determining the first LUN controller as the second LUN controller.
Optionally, the first XOR buffer is applied before the R operation is processed by the second LUN controller, and if the first XOR buffer is applied, the second LUN controller moves the specified data to be operated to the first XOR buffer and performs an XOR operation with the data in the first XOR buffer.
Optionally, the method further comprises repeatedly applying the first XOR buffer until the application is successful if the first XOR buffer is not applied.
Optionally, the method further comprises releasing the first XOR buffer if the R operation is completed.
Optionally, if the first LUN controller has an erase operation that is not processed, the first LUN controller processes the P1 operation after the first LUN controller completes the erase operation.
Optionally, if the second LUN controller is allocated with the P1 operation during the process of processing the R operation by the second LUN controller, the second LUN controller reprocesss the P1 operation after the second LUN controller processes the R operation.
Optionally, the relationship between the first LUN controller and the second LUN controller is one of the following cases that the logic units corresponding to the first LUN controller and the second LUN controller belong to the same logic unit group, the logic units corresponding to the first LUN controller and the second LUN controller belong to different logic unit groups, each logic unit group comprises a plurality of logic units, each logic unit corresponds to one LUN controller, and the logic units belonging to the same logic unit group correspond to the same large block.
Optionally, when the pair of the P1 operation and the R operation is generated, the method further comprises the steps of obtaining whether an unprocessed erasure operation exists in a first LUN controller corresponding to the P1 operation, indicating the first LUN controller in the generated R operation if the first LUN controller does not have the unprocessed erasure operation, and indicating the LUN controller which is different from the first LUN controller and has no unprocessed erasure operation in the generated R operation if the first LUN controller does have the unprocessed erasure operation.
Optionally, after generating the P2 operation, the method further includes determining a corresponding third LUN controller according to a logical unit to which the second physical page belongs, the third LUN controller processing the P2 operation to write the check data into the second physical page.
Optionally, in the case that the third LUN controller has an erasure operation being processed, the method further comprises moving the check data in the first XOR buffer indicated by the P2 operation to an external memory and releasing the first XOR buffer, applying for the first XOR buffer after the third LUN controller completes the erasure operation, moving the check data to the first XOR buffer, and writing the check data in the first XOR buffer to the second physical page.
Optionally, multiple LUN controllers process multiple pairs of P1 operations, R operations, and 1P 2 operation in parallel.
Optionally, when a LUN controller is allocated for the P1 operation, if a first LUN controller is determined based on a logical unit corresponding to the P1 operation and at least one pending operation exists in the first LUN controller, continuing to allocate the P1 operation to the first LUN controller, and when a LUN controller is allocated for the P2 operation, if a third LUN controller is determined based on a logical unit corresponding to the P2 operation and at least one pending operation exists in the third LUN controller, continuing to allocate the P2 operation to the third LUN controller.
Optionally, when the LUN controller is allocated to the R operation, determining, from among the plurality of LUN controllers, that the LUN controller without the unprocessed completed erase operation is the second LUN controller, and continuing to allocate the R operation to the second LUN controller if at least one pending operation is present in the second LUN controller.
Optionally, when writing the specified data to the plurality of first physical pages of the first page stripe, a plurality of pairs of P1 operations and R operations are generated and allocated to corresponding LUN controllers, wherein the LUN controllers are allocated for the plurality of pairs of P1 operations and R operations in parallel.
Optionally, each of the plurality of LUN controllers independently processes the allocated P1 operation regardless of the operating state of the other LUN controllers, and each of the plurality of LUN controllers independently processes the allocated R operation regardless of the operating state of the other LUN controllers in the case of applying to the first XOR buffer.
Optionally, if the first page stripe is not allocated to the first XOR buffer, suspending generating the P1 operation and the R operation, and after being allocated to the first XOR buffer, continuing generating the P1 operation and the R operation.
Optionally, after the P2 operation is completed, the first XOR buffer is set to an allocable state.
Optionally, in the case of writing data to multiple page stripes, both P1 and R operations corresponding to the multiple page stripes are generated and allocated and processed in parallel by multiple LUN controllers, where the LUN controllers only process one operation at a time, multiple page stripes correspond to multiple XOR caches, and R operations corresponding to the same page stripe use the same XOR cache.
In a fourth aspect, embodiments of the present application provide a control unit including a storage command processing unit and a media interface controller, the storage command processing unit generating a media interface command indicating a pair of P1 operations and R operations in response to writing of specified data to each first physical page of a first page stripe and providing the media interface command to the media interface controller, the P1 operations indicating that specified data in a memory is moved to an NVM chip, the R operations indicating that XOR computation is performed on the specified data in the memory and a result of the computation is retained in a first XOR cache corresponding to the first page stripe, wherein the first page stripe includes a second physical page and a plurality of first physical pages, the storage command processing unit generating a media interface command indicating a P2 operation and providing the media interface command to the second physical page of the first page stripe in response to writing of data to the second physical page of the first page stripe, the P2 operations indicating that check data in the first XOR cache is written to the second physical page of the first page stripe.
Optionally, the media interface controller processes the P2 operation after determining the check data corresponding to the first page stripe according to the R operations respectively corresponding to the plurality of first physical pages.
Optionally, the storage command processing unit allocates the first XOR buffer for the first page stripe of specified data to be written into the memory.
Optionally, the media interface controller determines a corresponding first LUN controller according to a logical unit to which a first physical page indicated by the P1 operation belongs when processing the generated P1 operation and the R operation, processes the P1 operation by the first LUN controller to write specified data in the memory indicated by the P1 operation into the first physical page indicated by the P1 operation, determines a second LUN controller to process the R operation by the second LUN controller when processing each R operation, processes the R operation by the second LUN controller, and stores an operation result in the first XOR cache.
Optionally, the media interface controller determines a LUN controller from among a plurality of LUN controllers for which an unprocessed completed erase operation is not present as the second LUN controller.
Optionally, if the first LUN controller has an unprocessed erasing operation, the medium interface controller determines that the LUN controller with no unprocessed erasing operation is the second LUN controller from the plurality of LUN controllers, and if the first LUN controller has no unprocessed erasing operation, the medium interface controller determines the first LUN controller as the second LUN controller.
Optionally, the media interface controller applies for the first XOR buffer before the R operation is processed by the second LUN controller, and if applied for the first XOR buffer, the second LUN controller moves the specified data to be operated to the first XOR buffer and performs an XOR operation with the data in the first XOR buffer.
Optionally, if the first XOR buffer is not applied, the media interface controller repeatedly applies for the first XOR buffer until the application is successful.
Optionally, the media interface controller releases the first XOR buffer upon completion of the R operation.
Optionally, if the first LUN controller has an erase operation that is not processed, the first LUN controller processes the P1 operation after the first LUN controller completes the erase operation.
Optionally, if the media interface controller assigns the P1 operation to the second LUN controller during the process of processing the R operation by the second LUN controller, the second LUN controller reprocesss the P1 operation after the second LUN controller processes the R operation.
Optionally, the relationship between the first LUN controller and the second LUN controller is one of the following cases that the logic units corresponding to the first LUN controller and the second LUN controller belong to the same logic unit group, the logic units corresponding to the first LUN controller and the second LUN controller belong to different logic unit groups, each logic unit group comprises a plurality of logic units, each logic unit corresponds to one LUN controller, and the logic units belonging to the same logic unit group correspond to the same large block.
Optionally, the storage command processing unit acquires whether an unprocessed erasure operation exists in a first LUN controller corresponding to the P1 operation when generating the P1 operation and the R operation in pairs, if the first LUN controller does not have an unprocessed erasure operation, indicates the first LUN controller in the generated R operation, and if the first LUN controller does have an unprocessed erasure operation, indicates a LUN controller different from the first LUN controller and having no unprocessed erasure operation in the generated R operation.
Optionally, the media interface controller determines a corresponding third LUN controller according to the logical unit to which the second physical page belongs, where the third LUN controller processes the P2 operation to write the check data into the second physical page.
Optionally, when the third LUN controller has an erasure operation being processed, the media interface controller moves the check data in the first XOR buffer indicated by the P2 operation to an external memory and releases the first XOR buffer, and after the third LUN controller completes the erasure operation, the media interface controller applies for the first XOR buffer, moves the check data to the first XOR buffer, and writes the check data in the first XOR buffer to the second physical page.
Optionally, multiple LUN controllers process multiple pairs of P1 operations, R operations, and 1P 2 operation in parallel.
Optionally, when the LUN controller is allocated to the P1 operation, if a first LUN controller is determined based on a logic unit corresponding to the P1 operation and at least one operation to be processed exists in the first LUN controller, the media interface controller continues to allocate the P1 operation to the first LUN controller, and when the LUN controller is allocated to the P2 operation, if a third LUN controller is determined based on a logic unit corresponding to the P2 operation and at least one operation to be processed exists in the third LUN controller, the media interface controller continues to allocate the P2 operation to the third LUN controller.
Optionally, when the media interface controller allocates a LUN controller to the R operation, the media interface controller determines that a LUN controller with no unprocessed completed erase operation is the second LUN controller from the plurality of LUN controllers, and if the second LUN controller has at least one pending operation, the media interface controller continues to allocate the R operation to the second LUN controller.
Optionally, when writing the specified data to the plurality of first physical pages of the first page stripe, the storage command processing unit generates and allocates the plurality of pairs of P1 operations and R operations to corresponding LUN controllers, wherein the LUN controllers are allocated for the plurality of pairs of P1 operations and R operations in parallel.
Optionally, each of the plurality of LUN controllers independently processes the allocated P1 operation regardless of the operating state of the other LUN controllers, and each of the plurality of LUN controllers independently processes the allocated R operation regardless of the operating state of the other LUN controllers in the case of applying to the first XOR buffer.
Optionally, if the first page stripe is not allocated to the first XOR buffer, the storage command processing unit pauses generation of the P1 operation and the R operation, and after allocation to the first XOR buffer, the storage command processing unit continues generation of the P1 operation and the R operation.
Optionally, after completing the P2 operation, the media interface controller sets the first XOR buffer to an allocable state.
Optionally, in the case of writing data to multiple page stripes, both P1 and R operations corresponding to the multiple page stripes are generated and allocated and processed in parallel by multiple LUN controllers, where the LUN controllers only process one operation at a time, multiple page stripes correspond to multiple XOR caches, and R operations corresponding to the same page stripe use the same XOR cache.
In a fifth aspect, an embodiment of the present application provides an erasure control method, including determining, in response to a received media interface command, that the media interface command indicates an erasure operation, determining a first LUN controller associated with the media interface command and the erasure operation, and if the number of unprocessed erasure operations satisfies a first preset condition and the first LUN controller does not have an unprocessed erasure operation, assigning the media interface command to the first LUN controller, and processing, by the first LUN controller, the erasure operation based on the media interface command.
Optionally, the determining that the media interface command indicates an erase operation in response to the received media interface command includes determining that the media interface command indicates an erase operation based on an operation type field included in the media interface command.
Optionally, the media interface command includes a field indicating an erased physical block address, and the determining the first LUN controller associated with the media interface command and the erase operation includes determining a logical unit corresponding to the erase operation based on the physical block address indicated by the media interface command, and determining a first LUN controller matching the logical unit corresponding to the erase operation based on a mapping relationship between the logical unit and the LUN controller.
Optionally, the method further comprises receiving the media interface command if the number of unprocessed completed erase operations meets a second preset condition.
Optionally, the receiving the media interface command when the number of unprocessed completed erase operations meets a second preset condition includes one of receiving the media interface command when there are no unprocessed completed erase operations, and receiving the media interface command when the number of unprocessed completed erase operations is less than or equal to a second threshold.
Optionally, before or after determining the first LUN controller, the method further includes obtaining a number of unprocessed completed erase operations, suspending processing the media interface command if the obtained number of unprocessed completed erase operations does not meet the first preset condition, and continuing processing the media interface command if the obtained number of unprocessed completed erase operations meets the first preset condition.
Optionally, if the number of the obtained unprocessed completed erase operations does not meet the first preset condition, suspending processing the media interface command includes suspending processing the media interface command if the number of the obtained unprocessed completed erase operations is greater than a first threshold.
Optionally, after suspending processing the media interface command, resuming processing the media interface command when the number of unprocessed completed erase operations is monitored to be less than or equal to a first threshold.
Optionally, if the number of the obtained erase operations meets the first preset condition, continuing to process the media interface command, wherein the method comprises the steps of continuing to process the media interface command if no unprocessed erase operation exists, and continuing to process the media interface command if the number of the obtained unprocessed erase operations is smaller than or equal to a first threshold.
Optionally, if the number of obtained erase operations is determined to satisfy the first preset condition before determining the first LUN controller, and if the first LUN controller does not have an erase operation that is not processed, processing the media interface command by the first LUN controller to complete the erase operation.
Optionally, if, after determining the first LUN controller, it is determined that the number of acquired erase operations meets the first preset condition, the first LUN controller processes the media interface command to complete the erase operation without an unprocessed completed erase operation.
Optionally, under the condition that a plurality of medium interface commands indicating the erasing operation are received, the method further comprises determining N logic unit groups corresponding to a plurality of LUN controllers corresponding to the plurality of medium interface commands, wherein each logic unit group corresponds to a large block, N is an integer greater than or equal to 2, and controlling the quantity of the erasing commands corresponding to the N logic unit groups at the same time to meet a third preset condition.
Optionally, the controlling the number of the erase commands corresponding to the N logic cell groups at the same time satisfies a third preset condition includes at least one of controlling the total number of the erase commands corresponding to the N logic cell groups at the same time to be less than or equal to a third threshold value and controlling the number of the erase commands corresponding to each logic cell group at the same time to be less than or equal to a fourth threshold value.
Optionally, the method further comprises determining a fifth LUN controller associated with the P1 operation in response to receiving a media interface command indicating the P1 operation, distributing the media interface command indicating the P1 operation to the fifth LUN controller, processing the media interface command indicating the P1 operation by the fifth LUN controller, acquiring a sixth LUN controller without unprocessed completed erasure operation in response to receiving a media interface command indicating the R operation, distributing the media interface command indicating the R operation to the sixth LUN controller, and processing the media interface command indicating the R operation by the sixth LUN controller, wherein the P1 operation indicates that specified data in a memory is moved to an NVM chip, and the R operation indicates that the specified data in the memory is subjected to XOR calculation and a calculation result is reserved in an XOR cache.
In a sixth aspect, an embodiment of the present application further provides a media interface controller, including a command allocation unit and a plurality of LUN controllers, where the command allocation unit determines, in response to a received media interface command, that the media interface command indicates an erase operation, determines, among the plurality of LUN controllers, a first LUN controller associated with the media interface command and the erase operation, and where the number of unprocessed completed erase operations satisfies a first preset condition and where the first LUN controller does not have an unprocessed completed erase operation, the command allocation unit allocates the media interface command to the first LUN controller, and where the first LUN controller processes the erase operation based on the media interface command.
Optionally, the command allocation unit determines that the media interface command indicates an erase operation based on an operation type field included in the media interface command.
Optionally, the media interface command includes a field indicating an erased physical block address, the command allocation unit determines a logical unit corresponding to the erase operation based on the physical block address indicated by the media interface command, and determines a first LUN controller matching the logical unit corresponding to the erase operation based on a mapping relationship between the logical unit and the LUN controller.
Optionally, the command distribution unit receives the media interface command sent by the storage command processing unit in a case where the number of unprocessed completed erase operations satisfies a second preset condition.
Optionally, the command distribution unit receives the media interface command in the absence of an unprocessed completed erase operation, or the command distribution unit receives the media interface command in the event that the number of unprocessed completed erase operations is less than or equal to a second threshold.
Optionally, before or after determining the first LUN controller, the command distribution unit obtains the number of unprocessed completed erase operations, if the obtained number of unprocessed completed erase operations does not meet the first preset condition, the command distribution unit suspends processing the media interface command, and if the obtained number of unprocessed completed erase operations meets the first preset condition, the command distribution unit continues processing the media interface command.
Optionally, in a case where the number of acquired unprocessed completed erase operations is greater than a first threshold, the command distribution unit suspends processing the media interface command.
Optionally, after suspending processing the media interface command, the command distribution unit resumes processing the media interface command when the number of erase operations detected as unprocessed completed is less than or equal to a first threshold.
Optionally, the command distribution unit continues to process the media interface command in the absence of an unprocessed completed erase operation, or in the event that the number of acquired unprocessed completed erase operations is less than or equal to a first threshold.
Optionally, if the number of acquired erase operations is determined to satisfy the first preset condition before determining the first LUN controller, the command allocating unit determines the first LUN controller, and if the first LUN controller does not have an erase operation that is not processed, the first LUN controller processes the media interface command to complete the erase operation.
Optionally, if, after determining the first LUN controller, it is determined that the number of acquired erase operations meets the first preset condition, the first LUN controller processes the media interface command to complete the erase operation without an unprocessed completed erase operation.
Optionally, under the condition that a plurality of media interface commands indicating the erasing operation are received, the command distribution unit determines N logic unit groups corresponding to a plurality of LUN controllers corresponding to the plurality of media interface commands, each logic unit group corresponds to a large block, N is an integer greater than or equal to 2, and the command distribution unit controls the number of the erasing commands corresponding to the N logic unit groups at the same time to meet a third preset condition.
Optionally, the command distribution unit controls the total number of the erase commands corresponding to the N logic unit groups at the same time to be smaller than or equal to a third threshold value, or the command distribution unit controls the number of the erase commands corresponding to each logic unit group at the same time to be smaller than or equal to a fourth threshold value.
Optionally, the command distribution unit determines a fifth LUN controller associated with the P1 operation in response to receiving a media interface command indicating the P1 operation, distributes the media interface command indicating the P1 operation to the fifth LUN controller, processes the media interface command indicating the P1 operation by the fifth LUN controller, acquires a sixth LUN controller without unprocessed completed erase operation in response to receiving the media interface command indicating the R operation, distributes the media interface command indicating the R operation to the sixth LUN controller, processes the media interface command indicating the R operation by the sixth LUN controller, wherein the P1 operation indicates that specified data in a memory is moved to an NVM chip, and the R operation indicates that XOR calculation is performed on the specified data in the memory and a calculation result is reserved in an XOR buffer.
In a seventh aspect, an embodiment of the present application provides a method performed by a storage device, including, in response to a large block to be erased, the large block including a plurality of physical blocks from a plurality of logical units, providing a media interface command indicating an erase operation to a media interface controller if a number of unprocessed erase operations corresponding to a plurality of LUN controllers is less than a specified threshold, and repeatedly performing the step of providing the media interface command indicating an erase operation to the media interface controller until all physical blocks of the large block are erased.
Optionally, the method further comprises the steps of generating a pair of P1 operation and R operation in response to the fact that the specified data are to be written into each first physical page of a first page stripe, wherein the P1 operation indicates that the specified data in a memory are moved to an NVM chip, the R operation indicates that the specified data in the memory are subjected to XOR calculation, and calculation results are reserved in a first XOR cache corresponding to the first page stripe, the first page stripe comprises a second physical page and a plurality of first physical pages, and the P2 operation is generated in response to the fact that the data are to be written into the second physical page of the first page stripe, and the P2 operation indicates that the check data in the first XOR cache are written into the second physical page of the first page stripe.
Optionally, the method further comprises the steps of determining a second LUN controller according to a logic unit indicated by the P1 operation for processing the P1 operation, processing the P1 operation through the second LUN controller, obtaining a third LUN controller without an unprocessed and completed erasing operation for processing the R operation, processing the R operation through the third LUN controller, determining a fourth LUN controller according to the logic unit indicated by the P2 operation for processing the P2 operation, and processing the P2 operation through the fourth LUN controller.
Optionally, the method further comprises obtaining a third LUN controller in which there is no pending erase operation for generating the R operation in which the use of the third LUN controller to process the R operation is indicated.
Optionally, the method further comprises determining a second LUN controller according to a logic unit to which a first physical page to be accessed by the P1 operation belongs for generating the pair of the P1 operation and the R operation, indicating to use the second LUN controller to process the R operation in the R operation if the second LUN controller does not have an unprocessed completed erase operation, and acquiring a third LUN controller without an unprocessed completed erase operation if the second LUN controller does have an unprocessed completed erase operation, and indicating to use the third LUN controller to process the R operation in the R operation.
In an eighth aspect, an embodiment of the present application further provides a control unit, including a storage command processing unit and a media interface controller, where the storage command processing unit is responsive to a large block to be erased, the large block including a plurality of physical blocks from a plurality of logic units, where if a number of unprocessed erase operations corresponding to a plurality of LUN controllers is less than a specified threshold, the storage command processing unit provides a media interface command indicating an erase operation to the media interface controller, and where repeatedly executing the number of unprocessed erase operations corresponding to the plurality of LUN controllers is less than the specified threshold, the storage command processing unit provides a media interface command indicating an erase operation to the media interface controller until all physical blocks of the large block are erased.
Optionally, the storage command processing unit generates a pair of P1 operation and R operation in response to writing the specified data to each first physical page of a first page stripe, the P1 operation indicating to move the specified data in the memory to the NVM chip, the R operation indicating to perform XOR computation on the specified data in the memory and to reserve the computation result in a first XOR cache corresponding to the first page stripe, wherein the first page stripe includes a second physical page and a plurality of first physical pages, and the storage command processing unit generates a P2 operation in response to writing the data to the second physical page of the first page stripe, the P2 operation indicating to write the check data in the first XOR cache to the second physical page of the first page stripe.
Optionally, in order to process the P1 operation, the media interface controller determines a second LUN controller according to the logic unit indicated by the P1 operation, processes the P1 operation through the second LUN controller, acquires a third LUN controller without an unprocessed and completed erase operation, processes the R operation through the third LUN controller, determines a fourth LUN controller according to the logic unit indicated by the P2 operation, and processes the P2 operation through the fourth LUN controller.
Optionally, to generate the R operation, the storage command processing unit acquires a third LUN controller in which an unprocessed completed erase operation does not exist, and instructs the R operation to be processed using the third LUN controller in the R operation.
Optionally, to generate the pair of P1 operation and R operation, the storage command processing unit determines a second LUN controller according to a logical unit to which the first physical page to be accessed by the P1 operation belongs, if the second LUN controller does not have an unprocessed completed erase operation, the storage command processing unit instructs to use the second LUN controller to process the R operation in the R operation, and if the second LUN controller does have an unprocessed completed erase operation, the storage command processing unit acquires a third LUN controller having no unprocessed completed erase operation, and instructs to use the third LUN controller to process the R operation in the R operation.
In a ninth aspect, an embodiment of the present application further provides a command allocation method, including obtaining an operation type indicated by a media interface command in response to the received media interface command, determining a LUN controller associated with the media interface command and the operation type, allocating the media interface command to the LUN controller, processing the media interface command by the LUN controller, and recording the media interface command in a command queue of the LUN controller in response to the media interface command being allocated to the LUN controller, where the operation type includes a P1 operation or an R operation, the P1 operation indicates that specified data in a memory is moved to an NVM chip, and the R operation indicates that XOR calculation is performed on the specified data in the memory and a calculation result is reserved in an XOR cache.
Optionally, in response to the operation type being R operation, determining a load condition of a first LUN controller or a media interface controller corresponding to a logic unit to be accessed by the media interface command, and allocating the LUN controller to the media interface command based on the load condition of the first LUN controller or the media interface controller.
Optionally, the load condition of the first LUN controller or the media interface controller includes the number of unprocessed media interface commands stored in the command queue in the LUN controller or the proportion of the occupied XOR buffer in the XOR calculation unit.
Optionally, determining a state of the first LUN controller based on a load condition of the first LUN controller or the medium interface controller, or determining a state of the medium interface controller based on a load condition of the first LUN controller or the medium interface controller, wherein the states comprise a first state and a second state, and responding to the first LUN controller or the medium interface controller in the second state, and using the first LUN controller as the LUN controller associated with the medium interface command and the operation type.
Optionally, in response to the first LUN controller or the media interface controller being in a first state, selecting a second LUN controller from a plurality of LUN controllers, and using the second LUN controller as a LUN controller associated with the media interface command and the operation type, wherein the second LUN controller is in the second state.
Optionally, the method further comprises identifying whether the first LUN controller has an unprocessed completed erase operation, selecting the second LUN controller from a plurality of LUN controllers if the first LUN controller has an unprocessed completed erase operation, and using the second LUN controller as the LUN controller associated with the media interface command and the operation type.
Optionally, if the first LUN controller does not have an erase operation which is not processed, determining a state of the first LUN controller corresponding to a logic unit to be accessed by the media interface command, and allocating the LUN controller to the media interface command based on the state of the first LUN controller.
Optionally, determining the type of one or more media interface commands recorded in the command queue of the first LUN controller, and identifying whether the first LUN controller has an unprocessed erase operation based on the type of the media interface commands.
Optionally, a LUN controller having no unprocessed erasing operation is selected from the plurality of LUN controllers, and the LUN controller is used as the second LUN controller, or a LUN controller having a second state is selected from the plurality of LUN controllers, and the LUN controller is used as the second LUN controller.
Optionally, in the first state, at least one condition is included that a depth of a command queue in the LUN controller is greater than a first threshold, wherein the depth of the command queue characterizes a number of media interface commands in the command queue, a number of media interface commands of a specified type stored in the command queue of the LUN controller is greater than a second threshold, and an occupied XOR buffer ratio in the XOR computation unit is greater than a third threshold.
Optionally, in response to receiving a plurality of first media interface commands indicating P1 operations, determining a logical unit to be accessed by each first media interface command, where each first media interface command is to access the same logical unit, and allocating the plurality of first media interface commands to a third LUN controller corresponding to the logical unit, where physical pages corresponding to physical addresses indicated by the plurality of first media interface commands belong to different page stripes.
Optionally, the method further comprises the steps of responding to the received multiple second media interface commands indicating R operation, determining a logic unit to be accessed by each second media interface command, wherein the second media interface commands are in one-to-one correspondence with the first media interface commands, and distributing the LUN controllers to the second media interface commands based on the load condition of the third LUN controllers or the media interface controllers.
In a tenth aspect, the embodiment of the application further provides a medium interface controller, which comprises a command distribution unit and a plurality of LUN controllers, wherein the command distribution unit responds to a received medium interface command, acquires an operation type indicated by the medium interface command, determines LUN controllers associated with the medium interface command and the operation type in the plurality of LUN controllers, distributes the medium interface command to the LUN controllers, processes the medium interface command by the LUN controllers, and records the medium interface command in a command queue of the LUN controllers in response to the distribution of the medium interface command to the LUN controllers, wherein the operation type is a P1 operation or an R operation, the P1 operation indicates that specified data in a memory is moved to an NVM chip, and the R operation indicates that XOR calculation is performed on the specified data in the memory and a calculation result is reserved in an XOR buffer.
Optionally, the command allocation unit determines a load condition of a first LUN controller or a media interface controller corresponding to a logical unit to be accessed by the media interface command in response to the operation type being an R operation, and allocates the LUN controller to the media interface command based on the load condition of the first LUN controller or the media interface controller.
Optionally, the command allocation unit determines a load condition of a first LUN controller or a media interface controller corresponding to a logical unit to be accessed by the media interface command in response to the operation type being an R operation, and allocates the LUN controller to the media interface command based on the load condition of the first LUN controller or the media interface controller.
Optionally, the load condition of the first LUN controller or the media interface controller includes the number of unprocessed media interface commands stored in the command queue in the LUN controller or the proportion of the occupied XOR buffer in the XOR calculation unit.
Optionally, the command distribution unit determines a state in which a first LUN controller is based on a load condition of the first LUN controller or the media interface controller, or determines a state in which the media interface controller is based on a load condition of the first LUN controller or the media interface controller, wherein the states include a first state and a second state, and in response to the first LUN controller or the media interface controller being in the second state, the first LUN controller is used as the LUN controller associated with the media interface command and the operation type.
Optionally, the command distribution unit responds to the first LUN controller or the medium interface controller being in a first state, selects a second LUN controller from a plurality of LUN controllers, and uses the second LUN controller as the LUN controller associated with the medium interface command and the operation type, wherein the second LUN controller is in the second state.
Optionally, the method further comprises the steps that the command distribution unit identifies whether the first LUN controller has an unprocessed and completed erasing operation or not, and if the first LUN controller has the unprocessed and completed erasing operation, the second LUN controller is selected from a plurality of LUN controllers, and the second LUN controller is used as the LUN controller associated with the medium interface command and the operation type.
Optionally, if the first LUN controller does not have an unprocessed erase operation, the command distribution unit determines a state of the first LUN controller corresponding to a logical unit to be accessed by the media interface command, and distributes the LUN controller to the media interface command based on the state of the first LUN controller.
Optionally, the command allocation unit determines a type of one or more media interface commands recorded in a command queue of the first LUN controller, and identifies whether an unprocessed erase operation exists for the first LUN controller based on the type of the media interface command.
Optionally, the command distribution unit selects a LUN controller having no unprocessed erasing operation from the plurality of LUN controllers, and uses the LUN controller as the second LUN controller, or the command distribution unit selects a LUN controller having a second state from the plurality of LUN controllers, and uses the LUN controller as the second LUN controller.
Optionally, in the first state, at least one condition is included that a depth of a command queue in the LUN controller is greater than a first threshold, wherein the depth of the command queue characterizes a number of media interface commands in the command queue, a number of media interface commands of a specified type stored in the command queue of the LUN controller is greater than a second threshold, and an occupied XOR buffer ratio in the XOR computation unit is greater than a third threshold.
According to the embodiment of the application, the P1 operation for indicating to move the specified data in the memory to the NVM chip but not performing the XOR operation and the P2 operation for indicating to move the data in the XOR buffer to the NVM chip are introduced, the R operation for executing the XOR calculation on the specified data in the memory and keeping the result in the XOR buffer is supported, the specified data in the memory and the corresponding check data can be written into the NVM chip through three stages based on the cooperation of the P1 operation, the P2 operation and the R operation, the operations of the three stages are mutually independent and do not affect each other, the XOR buffer can be released in time after the XOR calculation and the data movement in the XOR buffer are completed, the occupation time of the XOR buffer is reduced, and the utilization efficiency of the XOR buffer is improved. The application can limit the number of the simultaneously processed erasing operations, and avoid the problem that the power consumption of the storage device fluctuates caused by the erasing operations generated by the large-block recycling and/or the XOR cache cannot be released in time because the erasing operations occupy a plurality of or all LUN controllers and the R operation cannot be scheduled in time.
Drawings
FIG. 1A shows a block diagram of a storage device;
FIG. 1B illustrates a detailed block diagram of the control components of the storage device;
FIG. 2A shows a schematic diagram of a chunk one;
FIG. 2B shows a schematic diagram II of a large block;
FIG. 3A shows a schematic diagram of a page stripe;
FIG. 3B shows a second schematic diagram of a page stripe;
FIG. 4A shows a schematic diagram of interactions between a media interface controller, DRAM and NVM chips;
FIG. 4B shows a second schematic interaction diagram of the media interface controller, DRAM, and NVM chip;
FIG. 5 shows a schematic diagram of the interaction of a media interface controller with a host, logic unit;
FIG. 6 is a schematic diagram of a media interface controller accessing a logic unit based on media interface commands according to an embodiment of the present application;
FIG. 7 is a schematic diagram showing a media interface controller allocating a LUN controller to a media interface command according to an embodiment of the application;
FIG. 8 is a schematic diagram II of a media interface controller for allocating a LUN controller for a media interface command according to an embodiment of the application;
FIG. 9 illustrates a third exemplary embodiment of a media interface controller for allocating a LUN controller for a media interface command;
FIG. 10 is a schematic diagram of LUN controllers for P1 and R operations in pairs corresponding to different logical unit groups according to an embodiment of the application;
FIG. 11 is a schematic diagram of a method for writing user data to a designated page stripe of an NVM chip according to an embodiment of the present application;
FIG. 12 shows a specific example of writing data to page stripe PS0 according to an embodiment of the application;
FIG. 13A is a schematic diagram I of a bulk block including physical blocks provided by logical units according to an embodiment of the application;
FIG. 13B is a schematic diagram II of a large block including physical blocks provided by logical units according to an embodiment of the present application;
FIG. 13C illustrates an example of an embodiment of the present application erasing a physical block in a large block;
FIG. 14 illustrates an example of different groups of logic cells corresponding to different erase commands at the same time in accordance with an embodiment of the present application;
FIG. 15 is a schematic diagram of a media interface controller according to another embodiment of the present application accessing a logical unit based on media interface commands;
FIG. 16 illustrates a flowchart of a method for writing user data and parity data to a page stripe based on P1, R, and P2 operations, provided by yet another embodiment of the present application;
FIG. 17 illustrates a flowchart of a method for writing user data and parity data to a page stripe based on P1 operation, R operation, and P2 operation, according to yet another embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
According to an embodiment of the present application, P1 operations and P2 operations processed by a media interface controller are introduced. The P1 operation instructs the media interface controller to move the specified data in the memory (e.g., DRAM) to the NVM chip, but does not perform an XOR operation, which is equivalent to forming a data channel between the memory and the NVM chip. The P2 operation instructs the media interface controller to move the data in the XOR buffer to the NVM chip. The media interface controller also supports R operations (performing XOR computations on specified data in memory, keeping the results in XOR caches). The same function or effect as the P operation of the related art is achieved by the paired P1 operation and R operation. By coordinating the P1 operation, the P2 operation, and the R operation, writing of the specified data and the corresponding verification data in the memory to the NVM chip may be accomplished based on three phases. The three stages of operations are mutually independent and do not affect each other, and after the XOR calculation is completed and the data in the XOR buffer is moved, the XOR buffer can be released in time, so that the occupied time of the XOR buffer is reduced, and the utilization efficiency of the XOR buffer is improved.
According to an embodiment of the present application, the media interface controller includes a plurality of LUN controllers, each of which may correspond to a logical unit. When P1 operation is executed, a corresponding LUN controller is determined based on the physical address of the NVM chip accessed by the P1 operation, so that the media interface controller processes the P1 operation by using the LUN controller to write specified data in the memory into the specified physical address of the NVM chip.
According to an embodiment of the present application, the status of whether it is processing an erase command is recorded for each logical unit. Since the logical units are in one-to-one correspondence with the LUN controllers, the corresponding states (whether or not an erase operation is being processed) can be carried by the LUN controllers. The state is set after the LUN controller issues an erase command to the corresponding logical unit, and is cleared after the erase command is processed.
According to an embodiment of the present application, an appropriate LUN controller (whose state indicates a LUN controller for which an erase operation is not currently being processed) is selected for an R operation based on the state of whether or not there is an erase operation being processed recorded by the LUN controller, so as to avoid a situation in which the R operation is blocked by the erase command.
During the writing of data to the page stripes, the P1 and R operations received by the media interface controller occur in pairs, with the P2 operation being used to move the data in the XOR cache to the NVM chip only once for each page stripe. Data in the DRAM is written to the page stripe by one or more pairs of P1 and R operations, and check data for the page stripe is generated in the XOR buffer. And writing the data in the XOR cache to the page stripe via a P2 operation. The paired P1 operation is identical to the data D (i) for which the R operation is directed, i.e., in the paired P1 and R operations, the P1 operation directs the data D (i) to be written to the NVM chip, while the corresponding R operation directs the same data D (i) to be moved to the XOR cache for the XOR computation. And according to the embodiment of the application, the P1 operation and the R operation can be respectively scheduled and executed, so that the processing sequence of the paired P1 operation and R operation is not limited, and the paired P1 operation and R operation can be processed simultaneously or sequentially. Although the LUN controller handling the P1 operation is limited in the P1 operation, the corresponding R operation is not limited to the LUN controller, but can be handled by any LUN controller in the media interface controller, and the pair of P1 operation and R operation can be handled by the same LUN processor. Preferably, R operations are handled by a LUN controller that is not currently having an erase operation being handled, to avoid blocking R operations.
Still alternatively or further, all R operations (each operating on a different data D (i)) used when writing data to the same page stripe use the same XOR cache. So that even though all R operations used when writing data to the same page stripe are handled by different LUN controllers, respectively, since the XOR caches used are the same, they are not handled simultaneously, but rather are handled sequentially to use the same XOR caches.
After the R operation exclusive-ors the specified data in the DRAM and stores it in the XOR buffer, the verification data also needs to be written to the specified location in the NVM chip. According to the embodiment of the present application, the order in which a plurality of P1 operations and one P2 operation each of writing data to the same page stripe are performed is not limited, and it is possible that the P2 operations are processed even before all the P1 operations (e.g., the P1 operations are blocked by the erase operation). Therefore, the writing of the check data corresponding to the page stripe to the NVM chip may occur before the writing of the specified data (user data) in the DRAM to the NVM chip (the writing operation of the user data is blocked), and the releasing of the XOR buffer may also occur before the writing of the user data to the NVM chip, thereby reducing the occupation time of the XOR buffer, further reducing the time of waiting for the allocation of the XOR buffer by the subsequent write command, and improving the utilization rate of the XOR buffer. The time waiting for the allocation of the XOR buffer when processing the write command is also reduced, so that the user experiences that the write command processing performance of the SSD is stable, and the performance of the write command processing is not dithered due to the occurrence of the erase operation.
The media interface controller provided by the embodiment of the application can process three media interface commands corresponding to P1 operation, P2 operation and R operation. The media interface controller receives the media interface command, assigns the media interface command to a corresponding LUN controller based on the operation type indicated by the media interface command, and executes a P1 operation, a P2 operation, or an R operation by the LUN controller.
Referring to fig. 6, the media interface controller includes a command distribution unit, a plurality of LUN controllers, and an XOR calculation unit. The command distribution unit receives media interface commands, each of which includes a plurality of fields. The field indicates the type of operation to which the media interface command corresponds and other related information.
When the media interface controller receives the media interface command, it is determined whether the media interface command corresponds to a P1 operation, a P2 operation, or an R operation according to the operation type field.
The media interface command indicating P1 operation includes, in addition to the operation type field, a field indicating the physical address of the NVM chip to be accessed and a field indicating the data to be moved. The logical units to be accessed may also be determined based on the physical address indicated by the media interface command, and the physical pages to be accessed may also be determined based on the physical address field, the field indicating the data to be moved indicating, for example, a DRAM index.
By way of example, the media interface command corresponding to the P1 operation is denoted as: < OPCODE, LUN, PPA, data >. The OPCODE field is an operation type field whose contents are used to indicate a P1 operation, the LUN field indicates a logical unit to be accessed, the PPA field indicates a physical address to be accessed (e.g., a physical page to be accessed), and the Data field corresponds to Data to be written to the physical address PPA, such as a pointer to a DRAM or the Data itself to be written. Alternatively, the LUN field and the PPA field are represented as a single field indicating the physical address of the NVM chip to be accessed.
The media interface controller, in response to the received media interface command, after recognizing the P1 operation, determines the LUN controller to process the P1 operation according to the contents of the LUN field. For example, a corresponding logical unit is determined according to the contents of the LUN field, and the P1 operation is allocated to the LUN controller corresponding to the determined logical unit. Next, the LUN controller may perform a P1 operation, generate a storage medium access command (program command) according to the Data field and the PPA field, and send the storage medium access command to a corresponding logical unit, so as to implement writing Data in the DRAM to a corresponding physical page of the logical unit.
The media interface command indicating P2 operation includes an operation type field, a field indicating the physical address of the NVM chip to be accessed, and a field indicating the data to be moved. The difference with the P1 operation is that it indicates that the data indicated by the field of the data to be moved is in the XOR buffer.
For example, the media interface command corresponding to the P2 operation is represented as < OPCODE, LUN, PPA, XOR Buffer Index >, the OPCODE field is an operation type field whose contents are used to indicate that the operation is a P2 operation, the LUN field corresponds to a logical unit to be accessed, the PPA field corresponds to a physical address to be accessed (i.e., a physical page to which the check data is to be written), and the XOR Buffer Index field corresponds to an Index of the XOR Buffer. For example, XOR Buffer 0 is allocated to page stripe PS1, and in the case where Parity data of page stripe PS1 is calculated to be Parity (PS 1) and Parity data Parity (PS 1) is stored in XOR Buffer 0, it is necessary to move Parity data Parity (PS 1) from XOR Buffer 0 to the corresponding physical page of page stripe PS1, and the XOR Buffer Index field is an Index of XOR Buffer 0.
The media interface controller, in response to receiving the media interface command, after recognizing the P2 operation, determines the LUN controller to process the P2 operation according to the contents of the LUN field. The LUN controller performs a P2 operation, generates a storage medium access command (program command) according to the XOR Buffer Index field and the PPA field, and sends the storage medium access command (program command) to a corresponding logical unit to write data in the XOR Buffer to a corresponding physical page of the logical unit.
A media interface command indicating an R operation includes an operation type field, a source address field indicating data to be operated on, and a destination address field indicating data to be operated on. Optionally, a field indicating the logical unit or LUN controller is also included. The source address of the data in the R operation is, for example, DRAM, and the destination address is an XOR buffer.
For example, the media interface command corresponding to the R operation is expressed as < OPCODE, LUN, XOR Buffer Index, data >, the OPCODE field is an operation type field, the content of the OPCODE field is used for indicating that the operation is the R operation, the LUN field indicates a logic unit, the LUN controller for processing the R operation is determined according to the LUN field, the XOR Buffer Index field is an Index of an XOR Buffer as a destination address, and the Data field is a source address. Alternatively, the R operation may not include a LUN field, but the command distribution unit selects the appropriate LUN controller to handle the R operation, e.g., selects the LUN controller whose corresponding logical unit is not executing the erase command. Still alternatively, the R operation indicates a LUN field that is the same as the LUN field of its paired P1 operation (thereby indicating paired P1 operation and R operation), but the command assigning unit assigns R operations to other LUN controllers for processing based on the LUN controller corresponding to the LUN field is processing an erase operation.
The media interface controller, in response to the received media interface command, after recognizing the R operation, determines the LUN controller to process the R operation, and the media interface controller applies for the XOR buffer. The XOR buffer is the XOR buffer indicated by the destination address field in the R operation indicating the data to be operated on. In case of applying to the XOR buffer, the LUN controller processing the R operation moves the data to be operated, indicated by the source address field of the data to be operated, of the R operation to the XOR buffer, and performs the XOR operation with the data in the XOR buffer, and the calculation result is retained in the XOR buffer. The XOR buffer has a state to flag whether the XOR buffer is occupied. The states of the XOR cache include, for example, "occupied" (denoted as O) and "free" (denoted as F).
The R operation indicates the XOR buffer to be used. When the LUN controller processes an R operation, the state of the XOR buffer to be used (also referred to as the application XOR buffer) is checked. When the XOR buffer to be used is idle, the XOR buffer is applied to be successful, and the subsequent processing of the R operation is continued. When the XOR buffer to be applied is occupied, the application of the XOR buffer fails, and the LUN controller repeatedly applies for the XOR buffer until the application of the XOR buffer is successful.
When a LUN controller is allocated for an R operation, it may be detected whether or not there is an unprocessed erase operation for the LUN controller corresponding to the logical unit to be accessed indicated by the R operation. If not, R operation can be allocated to the LUN controller corresponding to the logic unit to be accessed, or can be allocated to other idle LUN controllers without unprocessed erasing operation. When there is an unprocessed erase operation for the LUN controller corresponding to the logical unit to be accessed indicated by the R operation, the R operation is allocated to other LUN controllers in order to avoid long-time occupation of the XOR buffer.
The command distribution unit distributes the received media interface command to one of the LUN controllers for processing. For P1 and P2 operations, the command distribution unit always distributes it to the LUN controllers corresponding to the logical units it is to access. For R operations, the command distribution unit distributes LUN controllers for R operations according to one or more embodiments provided by the present application.
To write data to the page stripe (PS 1), one or more pairs of P1 and R operations, and a single P2 operation, are provided to the media interface controller, in accordance with an embodiment of the present application. For example, if page stripe PS1 holds N pages of user data and 1 page of parity data, writing data to page stripe PS1 requires N pairs of P1 and R operations, and 1P 2 operation. The N pairs of P1 operations and R operations are denoted as P1 (i) and R (i), where 0< =i < =n-1. Alternatively, all N R operations herein use the same XOR buffer (e.g., XOR buffer 0).
Referring to fig. 6, the media interface controller receives a media interface command 1 and a media interface command 2. For example, media interface command 1 indicates to perform a P1 (0) operation, and media interface command 2 indicates to perform an R (0) operation. The P1 (0) operation indicates that data D0 is written into physical page P0-0 of logical unit 0, and the R (0) operation indicates that D0 is exclusive-ORed with the data in XOR cache 0.
Since the P1 (0) operation indicates that the user data D0 is written to the physical page of the logical unit 0, the LUN controller 0 corresponding to the logical unit 0 is allocated for the medium interface command 1, and the LUN controller 1 is allocated for the medium interface command 2.
In the example of FIG. 6, LUN controller 0 has an erase operation that is not processed, and therefore, media interface command 2 is assigned a different LUN controller than LUN controller 0, as an example, LUN controller 1 is selected to process media interface command 2. Accordingly, LUN controller 0 processes the P1 (0) operation after processing the erase operation to write D0 into physical page P0-0. The LUN controller 1 performs an R (0) operation to exclusive-or the specified value D0 with the data in the XOR buffer 0 to obtain the check data (denoted as Parity (0)).
Still by way of example, the media interface controller assigns a LUN controller to media interface command 3 and media interface command 4 upon receiving media interface command 3 indicating to perform P1 (1) operations and media interface command 4 indicating to perform R1 operations.
Wherein the P1 (1) operation indicates writing data D1 into physical page P0-1 of logical unit 1, and the R (1) operation indicates exclusive-ORing data (currently Party (0)) in XOR cache 0 with data D1, thus allocating LUN controller 1 corresponding to logical unit 1 for media interface command 3. In the example of fig. 6, the P1 (1) operation indicates that the data D1 is written to the physical page of the logical unit 1, and the LUN controller 1 corresponding to the logical unit 1 does not have an unprocessed completed erase operation, so that the LUN controller 1 is also allocated to the media interface command 4 (even when the LUN controller 1 has not processed the completed media interface command 3).
When the LUN controller 1 executes R (1) operation, performing exclusive OR operation on the check data Party (0) in the XOR buffer 0 and D1 to obtain the check data Party (1) (still positioned in the XOR buffer 0), wherein the LUN controller 1 requests to allocate the resource of the XOR buffer 0 before executing the R (1) operation, and if the R (0) operation is not completed, pausing executing the R (1) operation. Since LUN controller 1 does not have an erase operation that is not processed, LUN controller 1 can directly perform P1 (1) operation to write D1 into physical page P0-1. Alternatively, during the processing of the P1 (1) operation by the LUN controller 1, the R (1) operation is processed concurrently, for example, during a period of waiting for programming to be completed after transmitting data to the logic unit 1, the LUN controller 1 processes the R (1) operation.
The process of writing D2 to D (P-1) is similar to the above process, and a description thereof will not be repeated here. After the Parity data (PS 0) corresponding to the page stripe PS0 is generated through a series of processes, a LUN controller P is allocated to the media interface command corresponding to the P2 operation based on the media interface command, and the Parity (PS 0) is written to the physical pages P0-P in the logical unit P by the LUN controller P performing the P2 operation. In embodiments of the present application, the paired P1 and R operations may be handled by the same or different LUN controllers. The LUN controller corresponding to the P1 operation is determined based on the logical unit corresponding to the P1 operation. In order to reduce the occupancy of the XOR caches, an erase operation that is not in process is typically required on the LUN controller to which the R operation corresponds. By way of example, the following description will be made of the case where the paired P1 operation and R operation correspond to the same LUN controller and different LUN controllers, respectively.
The media interface controller receives a media interface command 1 indicating to perform a P1 operation, and a media interface command 2 indicating to perform an R operation. The P1 operation and the R operation are operations corresponding to the user data D0 in the DRAM. The LUN controller (e.g., LUN controller 0 corresponding to logical unit 0) that is to handle the P1 operation is determined based on the content indicated by the LUN field included in media interface command 1 (e.g., the identification of logical unit 0).
The LUN controller 0 is checked for an unprocessed completed erase operation to determine how to process the media interface command 2. Referring to FIG. 7, if LUN controller 0 does not have an unprocessed completed erase operation, R (D0) operations may also be assigned to LUN controller 0 processing.
If there is an unprocessed erase operation for LUN controller 0, an R (D0) operation may be assigned to LUN controller 1 in an idle state (LUN controller 1 does not have an unprocessed erase operation). LUN controller 0 and LUN controller 1 may process P1 (D0) operations in parallel with R (D0) operations.
Note that, in the case where there is no unprocessed completed erase operation for the LUN controller 0, R (D0) operation may be allocated to another LUN controller in an idle state (where there is no unprocessed completed erase operation) other than the LUN controller 0.
In the above example, the P1 (D0) operation must be allocated to LUN controller 0 (because the P1 (D0) operation corresponds to logical unit 0 with LUN controller 0), and the R (D0) operation can be allocated to any LUN controller that does not have an outstanding erase operation in order to reduce the time taken for the XOR cache. Because the LUN controller applies for the XOR buffer when processing the R operation, releases the XOR buffer after the R operation is processed, if there is an erase operation that is not processed, the R operation cannot be processed later, so that the XOR buffer is occupied for a long time, and the check data of the page stripe cannot be calculated later, so that the XOR buffer allocated for the current page stripe is occupied for a long time.
In the embodiment of the present application, if an unprocessed erasure operation exists on a LUN controller executing a P1 operation, a corresponding R operation needs to be allocated to other LUN controllers. And for a LUN controller with an unprocessed erase operation, the LUN controller needs to execute a P1 operation after the erase operation is completed.
As an example, the media interface controller receives a media interface command 1 indicating to perform a P1 operation, a media interface command 2 indicating to perform an R operation, the P1 operation and the R operation being operations corresponding to D0 data in the DRAM. The LUN controller (e.g., LUN controller 0 corresponding to logical unit 0) that is to handle the P1 operation is determined based on the content indicated by the LUN field included in media interface command 1 (e.g., the identification of logical unit 0). It is detected whether or not the LUN controller 0 has an erase operation which has not been completed yet. Referring to fig. 8, a logical unit 0 corresponds to a LUN controller 0 that has an erase operation (e.g., an operation for handling an erase command erase 0) that has not been completed. Since the P1 (D0) operation corresponds to the logical unit 0, the P1 (D0) operation is allocated to the LUN controller 0, the R (D0) operation is allocated to the LUN controller 2 in an idle state (there is no erase operation which is not processed completely), and the R (D0) operation is performed by the LUN controller 2. After the erase operation is processed, the LUN controller 0 may perform a P1 (D0) operation, i.e., the P1 (D0) operation and the operation of processing the erase command erase0 are queued on the LUN controller 0, and the LUN controller 0 first processes the erase operation in order and then performs the P1 (D0) operation.
Since there is an unprocessed completed erase operation on the LUN controller 0 corresponding to the logical unit 0, by assigning an R (D0) operation to the LUN controller 2 in the idle state (there is no unprocessed completed erase operation), it is possible to avoid the erase operation from blocking the R (D0) operation. Furthermore, before the erasure command erase0 is processed, the calculation of the check data corresponding to the page stripe (e.g., page stripe PS 1) may be completed and the matched physical page may be written, so that the XOR buffer is released, thereby avoiding the situation that the XOR buffer 0 allocated to the page stripe PS1 is occupied for a long period due to the existence of the erasure command erase 0.
In the embodiment of FIG. 9, LUN controller 0 is processing P1 (D0) operations and LUN controller 2 is processing R (D0) operations, at which point in turn media interface commands are received that indicate P1 (D2) operations and R (D2) operations. D0 and D2 are both data located in the DRAM and are to be written to the same page stripe. Both the R (D0) operation and the R (D2) operation use XOR buffer 0. The P1 (D2) operation is to write data to the logic unit 2.
Although the LUN controller 2 has been assigned the R (D0) operation, since the logical unit 2 matches the LUN controller 2, the media interface controller still assigns the P1 (D2) operation to the LUN controller 2, whereas the R (D2) operation is assigned to the LUN controller 6 in the idle state (there is no erase operation that is not processed, completed), the R (D2) operation is performed by the LUN controller 6. The R (D0) operations handled by LUN controller 2 are concurrent with the R (D2) operations handled by LUN controller 6 and both use XOR buffer 0. Thus, when a LUN controller processes an R operation, it needs to apply for the allocated XOR buffer (XOR buffer 0), and the LUN controller applying for XOR buffer 0 has authority to use XOR buffer 0 and process the R operation, and after it finishes processing the R operation and releases XOR buffer 0, another LUN controller can apply for XOR buffer 0 again. Thus, the respective R operations of LUN controller 2 and LUN controller 6 will be queued based on the application of XOR buffer 0, but the processing time of the R operation is relatively short (compared to the P1 operation) and thus will not significantly affect the processing delay in writing data to the page stripe.
According to embodiments of the present application, multiple logical units of a storage device may be grouped, referred to as a logical unit group. Each logic cell group includes a plurality of logic cells. The large blocks are constructed from logical units within the logical unit group. While the LUN controllers remain in one-to-one correspondence with the logical units. These LUN controllers share XOR cache resources.
For P1 operations, the LUN controller handling the P1 operation is a fixed LUN controller corresponding to the logical unit accessed by the P1 operation, while for R operations, the LUN controller handling the R operation may be any LUN controller of the media interface controller. For paired P1 and R operations, the LUN controllers that handle both operations may be the same LUN controller or different LUN controllers, and are LUN controllers that may correspond to logical units of different logical unit groups.
When the LUN controller corresponding to the R operation corresponds to a different logical unit group from the LUN controller corresponding to the P1 operation, the LUN controller corresponding to the R operation corresponds to a different big block, that is, the LUN controller corresponding to the other big block can be adopted for processing the R operation on a certain big block, so that the situation that the R operation is delayed due to the insufficient LUN controller corresponding to the current big block can be avoided, and resource sharing can be realized by utilizing the LUN controllers corresponding to the other big blocks.
As an example, referring to fig. 10, the memory device includes 16 logic units (logic unit 0 to logic unit 15). Every 8 logic cells are grouped (e.g., logic cell 0 through logic cell 7 are grouped, and logic cell 8 through logic cell 15 are grouped). Block 0 is constructed in the group of logic units 0 through 7, and block 1 is constructed in the group of logic units 8 through 15. Each logic unit corresponds to one LUN controller, the logic units 0-7 correspond to the LUN controllers 0-7, and the logic units 8-15 correspond to the LUN controllers 8-15.
In the example of fig. 10, the control section processes a media interface command 1 indicating a P1 operation corresponding to writing D0 data to the NVM chip, and processes a media interface command 2 indicating an R operation to be performed on the D0 data. The media interface controller assigns a P1 (D0) operation to LUN controller 0, and the P1 (D0) operation is performed by LUN controller 0. And an R (D0) operation is assigned to the LUN controller 15, and the R (D0) operation is performed by the LUN controller 15.
The following describes the process of writing user data and check data to a specified page stripe of an NVM chip based on P1 operation, R operation, and P2 operation in detail. Referring to fig. 11, the steps may be included as follows:
Step 1101, allocate a stripe of pages, allocate an XOR buffer for the stripe of pages.
The allocated page stripe is a free page stripe in the storage device and the allocated XOR cache is an XOR cache that is not currently allocated to any page stripe. By way of example, a page stripe includes P pages to store user data and Q pages to store parity data. The process of writing data to a page stripe requires that P pairs of P1 operations and R operations, and Q P2 operations be provided to the media interface controller. The media interface controller processes these operations to complete the process of writing data to the page stripe. Here P1 operations each write user data to P pages of a page stripe, P R operations each use the allocated XOR buffers to calculate the parity data for the page stripe from the user data, and Q P2 operations each write parity data to Q pages of the page stripe.
Step 1102, when user data is written to a physical page in a page stripe, a pair of P1 operation and R operation is generated.
Step 1103, determining a LUN controller corresponding to the P1 operation according to the logical unit to which the physical address indicated in the media interface command representing the P1 operation belongs, allocating the P1 operation to the LUN controller, and processing the P1 operation by the LUN controller.
The physical address to be accessed is indicated in a media interface command representing the P1 operation, and a corresponding LUN controller (e.g., LUN controller 1) is determined based on the logical unit to which the physical address belongs. P1 operations are assigned to LUN controllers 1.
Step 1104, the R operation is allocated to the LUN controller X on which the erasure operation is not being processed, and the R operation is processed by the LUN controller.
The R operation may be allocated to the LUN controller X, where the selection condition of the LUN controller X is that there is no erase operation being processed thereon, and the LUN controller X may be the LUN controller 1 or may be different from the LUN controller 1, and the XOR buffer corresponding to the R operation is the XOR buffer pre-allocated in step 1101.
The XOR buffer allocated for the page stripe (e.g., XOR buffer 0) is indicated in the media interface command representing the R operation. When the LUN controller X processes the R operation, the LUN controller applies for XOR buffer 0 indicated in the R operation. If the XOR cache 0 is not available, then the LUN controller pauses processing the R operation and attempts to continue with the application of XOR cache 0. After applying for XOR buffer 0, LUN controller X uses this XOR buffer 0 to exclusive or and leave the result in XOR buffer 0, and then releases XOR buffer 0.
Step 1105, after determining the check data corresponding to the page stripe according to the plurality of R operations, moving the check data to the physical page storing the check data through the P2 operation, and completing writing of the check data.
Wherein one or more media interface commands representing P pairs of P1 operations and R operations and Q P2 operations are provided to the media interface controller for processing. The media interface controller assigns each P1 operation, P2 operation, and/or R operation to an appropriate LUN controller. Each LUN controller processes the received operations in parallel according to the processing manner provided by the embodiments of the present application.
It will be appreciated that in writing data to the page stripe (PS 1), media interface commands to access other page stripes may also be provided to the media interface controller. So that the same LUN controller may be handling, for example, multiple P1 operations, multiple P2 operations, and/or multiple R operations at a time. The LUN controller may process the plurality of operations assigned to it sequentially, alternately, or in other ways.
By way of example, PS0 is a stripe of pages in chunk 0, and writing data to page stripe PS0 includes writing user data D0, D1, D2, D3, D4, D5, and D6 to corresponding physical pages (involving 7P 1 operations), calculating Parity data Party (PS 0), and writing Party (PS 0) to corresponding physical pages (involving 7R operations and 1P 2 operation). According to an embodiment of the present application, to write data D0 to a physical page of page stripe PS0, a media interface command representing a pair of P1 operations and R operations is generated and provided to a media interface controller for processing. So that 7 pairs of media interface commands representing P1 operations and R operations are co-generated for the user data D0, D1, D2, D3, D4, D5, and D6 to be written to the page stripe. And to write the check data Parity (PS 0) to the physical page of the page stripe, generate 1 media interface command representing a P2 operation, when no R operation is generated.
The following describes a specific procedure for writing data to page stripe PS 0:
Writing D0 to the NVM chip includes a P1 (D0) operation and an R (D0) operation. Referring to FIG. 12, the P1 (D0) operation is used to indicate that D0 is written to physical page P0-0, and the R (D0) operation is used to indicate that the data in XOR cache 0 is XORed with D0. XOR buffer 0 is the XOR buffer resource allocated for page stripe PS 0. When D0 is the first data written to page stripe PS0, the initial value of XOR buffer 0 may be 0 when performing the R (D0) operation.
P1 (D0) operations are assigned to LUN controller 0 corresponding to logical unit 0, and D0 data is written to physical pages P0-0 by LUN controller 0. The R (D0) operation may be assigned to the LUN controller X, which is selected on the condition that there is no erase operation being processed thereon, by which the R (D0) operation is processed. XOR buffer 0 is required when LUN controller X is to handle R (D0) operations. When the LUN controller X processes R (D0) operations, the media interface controller needs to apply for an XOR buffer (here, XOR buffer 0 is determined when page stripe PS0 is allocated and is carried in the media interface command indicating R (0) operations), and does not go down if not applied. After applying for XOR buffer 0 and generating Parity data (D0), LUN controller X processing R (0) operation releases XOR buffer 0, i.e. releases LUN controller X's control right for XOR buffer 0. Parity data (D0) = (data in XOR buffer 0) XOR (D0), i.e. by xoring the data in XOR buffer 0 with D0, the Parity data associated with D0 is obtained.
The process of writing D1, D2, D3, D4, D5, and D6 to the NVM chip is similar to the process of writing D0 to the NVM chip described above, and will not be described here.
After generating the Parity data (PS 0) of the page stripe PS0 based on D0, D1, D2, D3, D4, D5, and D6, the data in the XOR buffer 0 is moved to the physical page of the page stripe PS0 storing the Parity data by the P2 operation, and the XOR buffer 0 is released, wherein the Parity (PS 0) =d0 XOR D1 XOR D2 XOR D3 XOR D4 XOR D5 XOR D6.
According to an embodiment of the present application, to write data to a page stripe, a storage command processing unit (see also FIG. 1B) generates one or more pairs of media interface commands carrying P1 operations and R operations, respectively, and 1 media interface command carrying P2 operations, and provides them to a media interface controller. And also allocates an XOR buffer for the page stripe. The allocated XOR buffers are not occupied for processing write operations for other page stripes. Optionally, after the R operation is processed, the XOR buffer carried by the R operation is released, so that the released XOR buffer may be allocated again. All R operations generated by the store command processing unit to write data to the same page stripe indicate the same allocated XOR cache as in the P2 operation.
Still alternatively, the paired P1 operation and R operation indicate the same logical unit. The media interface controller allocates LUN controllers for handling P1 operations and R operations according to the logical units indicated by the P1 operations and R operations. And when the LUN controller corresponding to the logic unit indicated by the R operation has an erasure operation which is being processed, the R operation is distributed to other LUN controllers.
In yet another embodiment, to generate a pair of P1 and R operations, the storage command processing unit obtains the status of the erase operation being processed on one or more LUN controllers of the media interface controller. And selecting, by the storage command processing unit, an idle LUN controller for the generated R operation, and indicating the selected LUN controller in the R operation. Further, even if the storage command processing unit selects an idle LUN controller, the command allocation unit of the media interface controller may still allocate another LUN controller for the R operation to process. Because the state of whether there is an erase operation on the LUN controller may change as the command distribution unit processes the R operation.
Alternatively, the pair of P1 operations and R operations generated by the storage command processing unit always indicate the same logical unit, regardless of the state on the LUN controller in which the erase operation is being processed. While the command assignment unit recognizes the state on the LUN controller that the erase operation is being processed and assigns the R operation to the appropriate LUN controller.
In yet another embodiment, the logical unit is not indicated in the R operation generated by the storage command processing unit, so that the LUN controller that processes the R operation is selected entirely by the command distribution unit.
It will be appreciated that the storage command processing unit may write data to a plurality of page stripes simultaneously, and generate a plurality of media interface commands carrying P1 operations, P2 operations, and R operations, respectively, for writing data to the plurality of page stripes to be processed by the media interface controller. The store command processing unit ensures that no one XOR buffer is allocated to multiple page stripes at any time. If there is no XOR buffer currently available (e.g., XOR buffers are all allocated to page stripes), the store command processing unit waits for the XOR buffer to be released while suspending generation of media interface commands for writing to new page stripes.
According to an embodiment of the present application, LUN controllers 0 through 6 handle P1 operations of writing D0, D1, D2, D3, D4, D5, and D6 to the NVM chip, respectively. The timing at which each of these P1 operations is processed is not limited. There may be erase operations on some LUN controllers that are being processed, so that processing of the corresponding P1 operation is deferred. It is also possible that all R operations and P2 operations of the page stripe are processed to completion before the processing of one or more P1 operations begins, at which point the XOR caches allocated for the page stripe have been freed and may be allocated to other page stripes. Thereby avoiding the XOR buffers being occupied for a long time.
Still by way of example, there may be an erase operation on LUN controller N that is processing a P2 operation of a page stripe, and cause the processing of the P2 operation to be deferred. Alternatively, the P2 operation is suspended at this time, or the P2 operation is not allocated to the LUN controller N, but the data in the XOR buffer indicated by the P2 operation is temporarily moved to an external memory such as DRAM. And releasing the XOR buffer indicated by the P2 operation so that the XOR buffer may be allocated to other page stripes. After the erase operation of LUN controller N is completed, the XOR cache is reapplied for processing the suspended P2 operation and the subsequent processing continues.
Referring back to FIG. 11, when step 1104 is performed, LUN controller X is allocated for R operations, and LUN controller X needs to be found on which there is no erase operation being processed. However, in some cases, it is possible that all LUN controllers are handling erase operations and result in an inability to allocate R operations to the available LUN controllers and result in the handling of R operations being deferred.
For a storage device, the storage device needs to erase all physical blocks of a chunk when reclaiming the chunk. To erase a large physical block, a media interface command is provided to the media interface controller indicating an erase operation. The erase operation includes, in addition to the operation type field, a field indicating the address of the physical block to be erased, and a logical unit to which the physical block to be erased belongs based on this field.
According to the embodiment of the application, in order to avoid the fluctuation of power consumption of the storage device caused by the erasure operation generated by the large-block reclamation and/or to avoid the problem that the XOR cache cannot be released in time caused by the fact that the R operation cannot be scheduled in time due to the fact that the erasure operation occupies a plurality of or all LUN controllers, the number of the erasure operations which are processed simultaneously is limited. For example, the memory device includes M logic cells, while the number of erase operations that are simultaneously processed is less than M. For another example, the number of erase operations that can be processed simultaneously is limited to 1 or 2.
In one example, when a media interface command is provided to a media interface controller, it is identified whether there is an unprocessed erase operation. Only when there is no erase operation that has not been completed, a media interface command indicating the erase operation is provided to the media interface controller. Or only when the number of unprocessed completed erase operations is less than a specified threshold (e.g., 2 or 3), providing a media interface command to the media interface controller indicating an erase operation.
In one example, the command allocation unit of the media interface controller identifies whether there is an unprocessed erase operation when allocating media interface commands to the LUN controller. When a media interface command indicating an erase operation is to be allocated, only when there is no unprocessed erase operation on all the LUN controllers, the media interface command indicating the erase operation is allocated to one of the LUN controllers. Since the medium interface command indicating an erase operation is to be processed by the LUN controller corresponding to the logical unit to which the physical block to be erased belongs, the command assigning unit not only recognizes whether or not the LUN controller has an incomplete erase operation but also checks whether or not other LUN controllers have an incomplete erase operation. Alternatively, the command assigning unit assigns a media interface command indicating an erase operation to the LUN controller only when the number of unprocessed completed erase operations is less than a specified threshold (e.g., 2 or 3).
Since each LUN controller has recorded thereon the status of whether it has an unprocessed completed erase operation, an appropriate LUN controller (LUN controller without an unprocessed completed erase operation) can be selected for the R operation based on the recorded status of the LUN controllers, so as to avoid the occurrence of blocking of the R operation by the erase operation. The method for processing the erasure command can reduce the number of LUN controllers occupied by the erasure command at the same time, and further can provide more choices when selecting a proper LUN controller for R operation.
As an example, referring to fig. 13A and 13B, the large block 0 includes physical blocks B1 provided by (logical unit) LUN0 to LUN N, respectively, and the large block 1 includes physical blocks B3 provided by (logical unit) LUN0 to LUN N, respectively. In FIGS. 13A and 13B, physical block y of logical unit x is indicated by "LUNx-y" with a border. When all physical blocks in the large block 0 are erased, each physical block in the large block 0 is erased respectively. In the case of performing an erase operation on all physical blocks in the large block 0 and the large block 1, each physical block is erased separately. For n+1 physical blocks included in big block 0 and n+1 physical blocks included in big block 1, n+1 erase operations need to be performed, respectively, only for one physical block each. The n+1 erase operations are performed separately and not simultaneously. As shown in fig. 13A and 13C, first, an erase operation (operation of processing the erase command erase 0) is performed on a physical block B1 (LUN 0-B1) from the logical unit 0 in the large block 0, and at this time, the LUN controller 0 corresponding to the logical unit 0 is processing the erase operation. At this time, if the media interface controller receives a P1 operation of writing data to the physical block B2 of the logical unit 0 and an R operation corresponding thereto, the command distribution unit distributes the P1 operation to the LUN controller 0 and distributes the R operation to any LUN controller (e.g., the LUN controller 2) in an idle state (there is no erase operation that is not processed). So that the P1 operation is blocked by the erase command, but the R operation can be immediately processed. Also, since embodiments of the present application limit the number of erase operations that are simultaneously processed at the same time, it is ensured that there must be a conditional LUN controller (no erase operations that have not been processed) to process an R operation when it is allocated.
Referring to fig. 13A, after the erase operation (operation of processing the erase command erase 0) on the physical block B1 (LUN 0-B1) from the logical unit 0 in the large block 0 is completed, the erase operation (operation of processing the erase command erase 1) on the physical block B1 (LUN 1-B1) from the logical unit 1 in the large block 0 is allowed, and then the erase operation (operation of processing the erase command erase 2) on the physical block B1 (LUN 2-B1) from the logical unit 2 in the large block 0 is sequentially performed, the erase operation (operation of processing the erase command erase 3) on the physical block B1 (LUN 3-B1) from the logical unit 3 in the large block 0 is performed, and the erase operation (operation of processing the erase command erase N) on the physical block B1 (LUN N-B1) from the logical unit N in the large block 0 is performed.
Although in fig. 13A, the erasing operation is processed in the order of LUN numbers (LUN 0, LUN 1. Other sequences of erase operations for individual physical blocks of a large block may be employed, only to ensure that the number of erase operations that are simultaneously processed is 1 or less than a specified threshold.
Still alternatively, when 2 or more large blocks are erased, it is also ensured that the number of erase operations that are simultaneously processed is 1 or less than a specified threshold according to an embodiment of the present application. So that while the erase operation of a physical block of one large block is handled, the erase operation of the other large block is blocked. For example, after all physical blocks of big block 0 are erased, an erase operation is scheduled for a physical block of another big block.
For example, referring to fig. 13A to 13C, when an erase operation (operation of handling the erase command erase 0) is performed on the physical block B1 (LUN 0-B1) from the logical unit 0 in the bulk 0, the erase operation is performed on the LUN0-B1 without affecting the physical blocks of other logical units in the bulk 0 or the physical blocks of the logical units in the bulk 1. At this time, the LUN controller corresponding to the physical block LUN0-B1 has an unprocessed completed erase operation (an operation of processing the erase command erase 0), when the media interface controller receives the P1 operation and the R operation for the logical unit 0, the command distribution unit distributes the P1 operation to the LUN controller 0 corresponding to the logical unit 0, and the LUN controller 0 executes the P1 operation after executing the erase operation corresponding to the erase0, because the LUN controller 0 has the unprocessed completed erase operation, if the R operation is distributed to the LUN controller 0 and the R operation is processed, the waiting is needed, and the XOR cache resource is occupied for a long time. When the LUN0-B1 is erased, only the LUN controller 0 corresponding to the logic unit 0 is occupied, other LUN controllers are not occupied, and R operation can be allocated to other idle LUN controllers except the LUN controller 0 in order to avoid that the XOR cache resource is occupied for a long time.
Alternatively, the scheduling of the erase operation is performed by a command distribution unit (see also fig. 6). After reclamation of the large block, the storage command processing unit issues to the media interface controller a plurality of media interface commands indicating erase operations to erase all physical blocks of the large block, while the command assigning unit is instructed to ensure that the erase operations assigned to the LUN controller process do not exceed 1 or a specified number at any time. Still alternatively, the command processing unit is stored to ensure that the media interface commands provided to the media interface controller indicating an erase operation do not exceed 1 or a specified number at any time.
According to the embodiment of the application, the probability that the subsequent programming operation/reading operation accessing the same logic unit is blocked by the erasing operation is reduced to 1/K by limiting the number of the erasing operations processed simultaneously to 1 for example, wherein K is the number of the logic units in the storage device. Since there may be hundreds, or even thousands, of IO commands from the host simultaneously in the storage device, by reducing the chance that the program/read operations will be blocked by the erase operations, the jitter in the processing delay of the host IO commands is correspondingly reduced, thereby reducing the impact of the erase operations on the QoS (Quality of Service ) of the storage device.
In the above example, since the erase operation corresponding to the erase command erase0 is being processed. Suppose that a program operation (P1 operation or P2 operation) of a certain page stripe (e.g., page stripe PS 1) is to be processed at the same time. Assume that page stripe PS1 comprises N physical pages, where logical unit 0 contributes 1 physical page. At this time, in the Program operation on the page stripe PS1, the Program operation of the physical page of the logic unit 0 is blocked by the previous erase operation (the operation of processing the erase command erase 0), and the Program command of the physical page of the logic unit 1 to the logic unit (N-1) can be normally completed. If the scheme of the present application is not employed, in the programming operation for page stripe PS1, all of the N physical pages of the N logical units are blocked. After the scheme of the application is adopted, the number of blocked programming operations is 1/N of the previous programming operations.
By way of example only, the memory device includes multiple groups of logic cells (e.g., G groups of logic cells), allowing a specified number of erase operations to be handled at most within each group of logic cells simultaneously. For example, G logical unit groups process G erase operations at most at the same time (the number of erase operations processed simultaneously within each logical unit group is not more than 1), and erase commands in different logical unit groups do not affect each other.
As an example, referring to fig. 14, the memory device includes, for example, 16 logic units, the 16 logic units are divided into 2 groups, the logic units 0 to 7 are group1 (logic unit group 1), and the logic units 8 to 15 are group2 (logic unit group 2). At a certain moment, group1 corresponds to one erase command (erase 0) and group2 corresponds to one erase command (erase 8), specifically, an erase operation (operation for handling erase command erase 0) exists for the LUN controller 0 corresponding to the logical unit 0 in group1, and an erase operation (operation for handling erase command erase 8) exists for the LUN controller 8 corresponding to the logical unit 8 in group 2. At this time, group1 and group2 correspond to two erase commands at the same time.
For a logical unit group, only one erasure command is corresponding to the logical unit group at the same time, so that only one LUN controller has erasure operation, the power consumption consumed by the erasure operation can be reduced, the number of LUN controllers occupied by the erasure operation can be reduced, more choices can be provided when proper LUN controllers are selected for R operation, and meanwhile, as only one logical unit is blocked by the erasure operation, the long-time occupation of an XOR buffer can be avoided.
The embodiment of the application provides a medium interface controller which comprises a command distribution unit and a plurality of LUN controllers, wherein the command distribution unit responds to a received medium interface command, acquires an operation type indicated by the medium interface command, determines the LUN controllers associated with the medium interface command and the operation type in the plurality of LUN controllers, distributes the medium interface command to the LUN controllers, and processes the medium interface command by the LUN controllers, wherein the operation type is P1 operation or R operation, the P1 operation indicates to move specified data in a memory to an NVM chip, and the R operation indicates to execute XOR calculation on the specified data in the memory and reserve a calculation result in an XOR cache. And the media interface controller is further configured to perform other embodiments of the command distribution method, which are not described herein.
When the media interface controller executes the erasure control method, the command distribution unit responds to the received media interface command, determines that the media interface command indicates an erasure operation, determines a first LUN controller associated with the media interface command and the erasure operation in a plurality of LUN controllers, and distributes the media interface command to the first LUN controller when the number of the erasure operations which are not processed are met by the first LUN controller and the first LUN controller does not have the erasure operation which is not processed and completed, and processes the erasure operation based on the media interface command by the first LUN controller. And the media interface controller is further configured to perform other embodiments of the erase control method, which are not described herein.
The embodiment of the application provides a control part, which comprises a storage command processing unit and a medium interface controller, wherein the storage command processing unit responds to writing specified data to each first physical page of a first page stripe, generates a medium interface command indicating paired P1 operation and R operation and provides the medium interface command to the medium interface controller, the P1 operation indicates to move the specified data in a memory to an NVM chip, the R operation indicates to execute XOR calculation on the specified data in the memory and reserve calculation results in a first XOR cache corresponding to the first page stripe, the first page stripe comprises a second physical page and a plurality of first physical pages, the storage command processing unit responds to writing data to the second physical page of the first page stripe, generates a medium interface command indicating P2 operation and provides the medium interface command to the medium interface controller, and the P2 operation indicates to write check data in the first XOR cache to the second physical page of the first page stripe. And the control unit is further configured to perform other embodiments of the data access method, which are not described herein.
The control unit responds to the large block to be erased, the large block comprises a plurality of physical blocks from a plurality of logic units, if the number of unprocessed erasing operations corresponding to the plurality of LUN controllers is smaller than a specified threshold, the storage command processing unit provides a medium interface command indicating the erasing operation for the medium interface controller, and if the number of unprocessed erasing operations corresponding to the plurality of LUN controllers is smaller than the specified threshold, the storage command processing unit provides a medium interface command indicating the erasing operation for the medium interface controller repeatedly until all the physical blocks of the large block are erased. And the control unit is further configured to perform other embodiments of the method performed by the storage device, which are not described herein.
FIG. 15 is a schematic diagram of a media interface controller according to another embodiment of the present application for accessing a logical unit based on media interface commands.
As an example, as shown in fig. 15, the media interface controller includes a command distribution unit, a plurality of LUN controllers, and an XOR calculation unit. The LUN controller corresponding to each logical unit LUN includes a command queue for caching media interface commands. Each LUN controller stores media interface commands that the LUN controller did not process completion through a command queue. The unprocessed completed media interface commands include, for example, media interface commands that are being processed or are to be processed. Corresponding command information is obtained from unprocessed media interface commands stored in the command queues of the respective LUN controllers. For example, the command information includes a type of a media interface command (e.g., P1 operation, R operation, P2 operation, erase operation, program (Program) operation, read operation, etc.), the number of unprocessed completed media interface commands, and the like. When the medium interface controller receives the medium interface command, the medium interface command is distributed to the corresponding LUN controllers according to the LUNs accessed by the medium interface command, and the received medium interface command is distributed to one of the LUN controllers in the medium interface controller for processing according to the current load condition of each LUN controller. For example, the received media interface command is allocated to one of the other LUN controllers other than the LUN controller corresponding to the LUN accessed by the media interface command according to the current load condition of the LUN controller. The current load situation of the LUN controller includes, for example, the number of outstanding media interface commands stored in the command queue in the LUN controller or the occupied XOR buffer in the XOR calculation unit, etc. The case of unprocessed completed media interface commands stored in the command queue in the LUN controller may in turn include, for example, the total number of unprocessed completed media interface commands stored in the command queue in the LUN controller or the number of specified types of media interface commands (e.g., media interface commands indicating a programming operation) stored in the command queue in the LUN controller.
When the media interface controller allocates the media interface command, a part of the media interface command needs to be allocated to the LUN controller corresponding to the logic unit to be accessed, such as P1 operation command, P2 operation, erase operation or programming operation. While some media interface commands may be assigned to other LUN controllers than the LUN controller to which the logical unit to be accessed is indicated, e.g., R operations. The scheme of allocating the LUN controller for the P1 operation, the P2 operation, the erase operation, the program operation, and the like is similar to that of the embodiment shown in fig. 6, and is not described herein. Since the P1 operation and the R operation appear in pairs, the following briefly describes the process of allocating LUN controllers for the P1 operation and the R operation.
The media interface controller is responsive to receiving the media interface command and identifies a type of the media interface command. For P1 operation, indicating a logic unit to be accessed according to a LUN field in a media interface command corresponding to the P1 operation, taking a LUN controller corresponding to the logic unit to be accessed as the LUN controller for processing the P1 operation, and recording the media interface command corresponding to the P1 operation in a command queue of the LUN controller. The LUN controller performs a P1 operation, generates a storage medium access command (program command), and transmits the storage medium access command to a corresponding logical unit to write data (user data) to a corresponding physical page of the logical unit.
For an R operation, the R operation is processed by selecting one of a plurality of LUN controllers according to the current load condition of the LUN controller corresponding to the LUN accessed by the media interface command corresponding to the R operation or the load condition of the media interface controller. For example, P1 and R operations occurring in pairs may be assigned to the same LUN controller for processing, e.g
The LUN controller processing the P1 operation is used as the LUN controller processing the R operation. For another example, paired P1 and R operations may also be assigned to different LUN controllers for processing, such as assigning R operations to LUN controllers that are different from processing their corresponding P1 operations. For example, if an unprocessed erase operation exists in the command queue of the LUN controller corresponding to the logical unit to be accessed by the P1 operation corresponding to the R operation, the R operation is allocated to another LUN controller that is idle and has no unprocessed erase operation. In addition, in fig. 15, the LUN controllers record the types of outstanding media interface commands through the command queue, so that it is not necessary to record in each LUN controller whether there is an status of an unprocessed and completed Erase operation, and it can be directly determined whether the LUN controller has an Erase operation to be processed according to the command queue.
For example, when a LUN controller is allocated for an R operation, determining a current load condition of the LUN controller or a current overall load condition of a media interface controller corresponding to a logic unit to be accessed indicated by the R operation, and judging whether the LUN controller or the media interface controller corresponding to the logic unit to be accessed indicated by the R operation is in a state M1 according to the current load condition of the LUN controller or the current overall load condition of the media interface controller, wherein when the LUN controller or the media interface controller is in the state M1, the LUN controller or the media interface controller is in a relatively high load state, and the so-called relatively high load state may, for example, have situations of insufficient processing resources or processing congestion. The state M1 includes, for example, the proportion occupied in the XOR cache in the XOR compute unit being greater than a threshold A, the depth of the command queue in the LUN controller corresponding to the logical unit to be accessed by the R operation (or the P1 operation corresponding thereto) being greater than a threshold B, where the depth of the command queue indicates the total number of commands it records, or the number of unprocessed programming operations recorded by the command queue of the LUN controller corresponding to the logical unit to be accessed by the R operation (or the P1 operation corresponding thereto) being greater than a threshold C.
If the LUN controller or the media interface controller corresponding to the logical unit to be accessed indicated by the R operation is in the state M1, the R operation is allocated to other idle LUN controllers. If the LUN controller or the media interface controller corresponding to the logical unit to be accessed by the R operation is in the state M2, the R operation may be allocated to the LUN controller corresponding to the logical unit to be accessed by the R operation or the LUN controller corresponding to the P1 operation, where the state M2 is opposite to the state M1. The state M2 includes, for example, the proportion occupied in the XOR cache in the XOR compute unit not being greater than a threshold A (e.g., 50% for threshold A), the depth of the command queue in the LUN controller corresponding to the logical unit to be accessed by the R operation (or the P1 operation corresponding thereto) not being greater than a threshold B, where the depth of the command queue indicates the total number of commands it records, or the number of outstanding programming operations recorded by the command queue of the LUN controller corresponding to the logical unit to be accessed by the R operation (or the P1 operation corresponding thereto) not being greater than a threshold C. Therefore, in the embodiment of the application, when the LUN controller or the media interface controller corresponding to the logic unit to be accessed by the R operation is in the state M1, the R operation is allocated to other idle LUN controllers to be processed, so as to share the pressure of the LUN controller corresponding to the logic unit to be accessed by the R operation, reduce the burden of the LUN controller corresponding to the logic unit to be accessed by the R operation, and enable the R operation to be processed as soon as possible so as to shorten the occupation time of the XOR cache.
With continued reference to FIG. 15, for example, the media interface controller receives a media interface command A1 and a media interface command A2, where the media interface command A1 indicates a P1 (0) operation, the media interface command A2 indicates an R (0) operation, the P1 (0) operation and the R (0) operation are a pair, and the P1 (0) operation and the R (0) operation indicate that the LUN0 is to be accessed. The media interface controller allocates the media interface command A1 to the LUN controller 0 corresponding to the LUN0, and records the media interface command A1 into the command queue of the LUN controller 0. Since in fig. 15, the command queue of the LUN controller 0 also records a media interface command (E0 for short) indicating an erase operation, that is, the LUN controller 0 has an erase operation that has not been completed yet. Since there is an unprocessed erase operation for LUN controller 0, media interface command A2 is assigned to other LUN controllers than LUN controller 0, e.g., media interface command A2 is assigned to an idle LUN controller P-1 that does not have an unprocessed erase operation, where LUN controller P-1 corresponds to LUN P-1.
When the media interface controller receives the media interface command A1 and the media interface command A2 before or after the processing is completed, the media interface controller receives the media interface command A3 and the media interface command A4 again. The media interface command A3 indicates P1 (2 ') operation, and the media interface command A4 indicates R (2') operation, the P1 (2 ') operation and the R (2') operation being a pair. The P1 (2 ') operation and the R (2') operation indicate that LUN2 is to be accessed, the media interface controller assigns media interface command A3 to the LUN controller 2 corresponding to LUN2, and records media interface command A3 into the command queue of LUN controller 2. In response to identifying that the LUN controller 2 is in the state M2, the media interface command A4 corresponding to the R (2') operation is also allocated to the LUN controller 2 corresponding to the LUN2, and the media interface command A4 is recorded in the command queue of the LUN controller 2.
The media interface controller may receive multiple pairs of media interface commands representing P1 operations and R operations to access the same logical unit.
By way of example only, the media interface controller also receives media interface command A5 and media interface command A6 before receiving media interface command A3 and media interface command A4. Wherein the media interface command A5 indicates a P1 (2 ") operation and the media interface command A6 indicates an R (2") operation. The P1 (2 ") operation and the R (2") operation are a pair, and the P1 (2 ") operation and the R (2") operation indicate that LUN2 is to be accessed. Wherein P1 (2 ") operations are used to access different physical pages in LUN2 than P1 (2 '), e.g., P1 (2') operations are used to access physical page 1 on LUN2 with physical address PPA_1, and P1 (2") operations are used to access physical page 2 on LUN2 with physical address PPA_2. Although P1 (2 ") already exists on the LUN controller 2, the media interface controller still allocates the media interface command A5 to the LUN controller 2 corresponding to the LUN2, and records the media interface command A5 into the command queue of the LUN controller 2. At this time, the media interface commands assigned to the LUN controller 2 and not processed to be completed include media interface commands corresponding to P1 (2 ') operation, R (2') operation, and P1 (2 ") operation. Recognizing that the LUN controller 2 is in the state M2, the medium interface command A6 corresponding to the R (2 ") operation is also allocated to the LUN controller 2 corresponding to the LUN2, and the medium interface command A6 is recorded in the command queue of the LUN controller 2. By way of example, R1 (2') operates with XOR buffer 1, and accordingly, in FIG. 15, XOR buffer 1 is marked as "occupied". R1 (2 ") operation is to use XOR buffer 0, and accordingly, in FIG. 15, XOR buffer 0 is marked as" occupied ".
Before the media interface commands A1, A2, A3, A4, A5, and A6 are not processed, the media interface controller receives the media interface command B1 and the media interface command B2 again, where the media interface command B1 indicates a P1 (2) operation, the media interface command B2 indicates an R (2) operation, the P1 (2) operation and the R (2) operation are a pair, and the P1 (2) operation and the R (2) operation indicate that the LUN2 is to be accessed, as an example. The media interface controller allocates the media interface command B1 to the LUN controller 2 corresponding to the LUN2, and records the media interface command B1 into a command queue of the LUN controller 2. At this time, the command queue of the LUN controller 2 records, in addition to the media interface commands corresponding to the P1 (2) operation, the media interface commands corresponding to the paired P1 (2 ') operation and R (2') operation, and the media interface commands corresponding to the paired P1 (2 ") operation and R (2") operation. In one example, if the depth threshold B of the command queue of the LUN controller is 4. At this time, the depth of the command queue of the LUN controller 2 is greater than the threshold B, so that the LUN controller 2 corresponding to the logical unit to be accessed by the R (2) operation is in the state M1, and the R (2) operation is allocated to other idle LUN controllers, for example, in fig. 15, the R (2) operation is allocated to the LUN controller P-1. As also seen in FIG. 15, in LUN controller P-1, there is already an R (0) operation pending, but the load of LUN controller P-1 is relatively low with respect to the other LUN controllers, thus assigning an R (2) operation to LUN controller P-1. By way of example, R1 (2) operation is to use XOR buffer 3, and accordingly, in FIG. 15, XOR buffer 3 is marked as "occupied".
The storage command processing unit may issue media interface commands for processing multiple page stripes simultaneously. For example, in the example of FIG. 15, the media interface commands corresponding to the pairs of P1 (2) and R (2) operations, P1 (2 ") and R (2") operations, and P1 (2 ') and R (2') operations are used to access physical pages belonging to different page stripes in LUN2, and the media interface controller may concurrently process page stripes corresponding to the P1 (2) and R (2) operations, P1 (2 ") and R (2") operations, and P1 (2 ') and R (2') operations. So that R (2), R (2') and R (2 ") operations correspond to different page stripes and require the use of different XOR cache units. The XOR buffers (XOR Buffer Index) to be used are indicated in the media interface command representing the R operation, and the media interface controller knows the status of whether each XOR Buffer is occupied. According to an embodiment of the present application, when a LUN controller is allocated for an R operation, the LUN controller is also allocated for the R operation according to the use condition of the XOR buffer. The allocation XOR caches are allocated in terms of page stripes, which may span at least one NVM chip, each NVM chip in turn including a plurality of LUNs. Thus, the XOR caches to be used by multiple R operations accessing different LUNs may be the same XOR cache. Taking R (2'), and R (2) operations accessing different physical pages on the same LUN as an example, the process of allocating LUN controllers for each R operation according to the use of the XOR buffer will be briefly described. To simplify the scheme for a clearer introduction of the process of assigning LUN controllers for R (2 '), R (2 ') and R (2) operations, in this example only for R (2 '), R (2 ') and R (2) operations, the LUN controller 2 to which it corresponds defaults to have no outstanding media interface commands before receiving a media interface command indicating R (2 ') operation.
In one example, if the threshold a is 40%, the XOR calculation unit includes 4 XOR buffers, namely XOR buffer 0, XOR buffer 1, XOR buffer 2, and XOR buffer 3. The media interface controller receives R operations of 3 corresponding different page strips in sequence according to R (2 '), R (2 ') and R (2 '). The media interface controller determines that 4 XOR buffers in the XOR calculation unit are all unused in response to receiving the media interface command indicating the R (2 ") operation, and the proportion of the XOR buffers occupied is less than a threshold value a. Alternatively, if the R (2 ") operation is to use XOR buffer 0, XOR buffer 0 is marked as" occupied "accordingly. Still alternatively, the allocation of the XOR buffers is done outside the media interface controller. The media interface controller takes the LUN controller 2 corresponding to the LUN2 accessed by the media interface command indicating the R (2 ") operation as the LUN controller handling the R (2") operation. Next, the media interface controller receives a media interface command indicating the R (2') operation, and determines that only XOR buffer 0 is occupied in 4 XOR buffers in the current XOR calculation unit, where the proportion of occupied XOR buffers is 25% less than the threshold a. If the R1 (2') operation is to use XOR buffer 1, XOR buffer 1 is accordingly marked as "occupied". The media interface controller assigns the LUN controller 2 to the R (2') operation. The media interface controller receives the media interface command indicating the operation of R (2), and determines that XOR buffer 0 and XOR buffer 1 are occupied in 4 XOR buffers in the current XOR calculation unit, where the proportion of occupied XOR buffers is 50% greater than the threshold a. Since the ratio of occupied XOR buffers is greater than the threshold a when a media interface command indicating an operation of R (2) is received, the LUN controller 2 or the whole media interface controller corresponding to the media interface command indicating the operation of R (2) is currently in the state M1. To allocate a LUN controller for a media interface command indicating an R (2) operation, one of the other LUN controllers other than the LUN controller 2 among the media interface controllers is processed to indicate the R (2) operation. For example, R (2) operations are assigned to a relatively idle LUN controller P-1. XOR buffer 3 is marked as "occupied" state.
In the embodiment according to FIG. 15, by way of example, the page stripe includes physical pages from LUNs 0 through LUNP, so that when writing data to the page stripe, the number of programming operations (represented by P1 operations and P2 operations) distributed to LUNs 0 through P is uniform. Even if data is written to multiple page stripes simultaneously, each LUN from LUN0 to LUN P should receive the same number of programming operations (represented by P1 operations and P2 operations). However, due to the storage medium consistency differences of the LUNs, a stack of medium interface commands occurs in the command queue of the LUN controller 2 corresponding to LUN 2, with more medium interface commands than in the command queues of other LUN controllers. According to the embodiment of fig. 15, the M1 state can reflect the media interface command stack in the command queue of the LUN controller 2, and by allocating the R (2) operation to other relatively idle LUN controllers, the burden of the LUN controller 2 is reduced, and the R (2) operation can be processed earlier on the relatively idle LUN controllers, so as to shorten the occupation time of the XOR buffer 3 corresponding to the R (2) operation, accelerate the release of the XOR buffer 3, and improve the overall utilization of the XOR buffer. Also, according to embodiments of the present application, without knowing the specific case of storage medium consistency differences, the effects of identifying storage medium consistency differences by differences between command queue depths of multiple LUN controllers, and/or utilization of XOR buffers, etc. have been accumulated and negative effects thereof are eliminated by allocation of R operations to other LUN controllers.
FIG. 16 illustrates a flowchart of a method for writing user data and parity data to a page stripe based on P1, R, and P2 operations, according to yet another embodiment of the present application.
Through the flow chart illustrated in fig. 16, a plurality of media interface commands for writing data to a page stripe are generated.
Referring to fig. 16, the steps may be included as follows:
step 1601, allocate a page stripe, allocate XOR caches for the page stripe.
The allocated page stripe is a free page stripe in the storage device and the allocated XOR cache is an XOR cache that is not currently allocated to any page stripe. By way of example, a page stripe includes P pages to store user data and Q pages to store parity data. The process of writing data to a page stripe requires that P pairs of P1 operations and R operations, and Q P2 operations be provided to the media interface controller. The media interface controller processes these operations to complete the process of writing data to the page stripe. Here P1 operations each write user data to P pages of a page stripe, P R operations each use the allocated XOR buffers to calculate the parity data for the page stripe from the user data, and Q P2 operations each write parity data to Q pages of the page stripe.
Step 1602, when writing user data to a physical page in a page stripe, generates, for example, P pairs of P1 operations and R operations.
In step 1603, when processing the media interface command representing the P1 operation, determining the LUN controller corresponding to the P1 operation according to the logical unit to which the physical address indicated in the media interface command representing the P1 operation belongs, and allocating the P1 operation to the LUN controller, where the LUN controller processes the P1 operation.
The physical address to be accessed is indicated in a media interface command representing the P1 operation, and a corresponding LUN controller (e.g., LUN controller 1) is determined based on the logical unit to which the physical address belongs. P1 operations are assigned to LUN controllers 1.
In step 1604, when a media interface command representing an R operation is processed, if the LUN controller or the media interface controller corresponding to the R operation is in the state M1 as a whole, the R operation is allocated to the free LUN controller X. Optionally, if the LUN controller or the media interface controller corresponding to the R operation is in the state M2 as a whole, the media interface command representing the R operation is allocated to the LUN controller indicated by the media interface command or the LUN controller indicated by the P1 operation paired with the R operation.
R operations are handled by LUN controller X, which is the LUN controller corresponding to the operations different from P1 in the media interface controller. The selection condition of the LUN controller X is that the LUN controller is idle. While here free is relative, e.g., no erase operation on LUN controller X is processed, the command queue depth for LUN controller X is less than threshold B, LUN the number of write operations recorded in the command queue for controller X is less than threshold C, the number of XOR buffers occupied in the media interface controller is less than a specified threshold, etc. LUN controller X may not be completely devoid of outstanding media interface commands, which may have at least outstanding media interface commands, so long as LUN controller X does not handle the completed media interface commands, for example, to satisfy no erase operations, LUN controller X's command queue depth is less than threshold B, LUN the number of write operations recorded in controller X's command queue is less than threshold C, the number of XOR buffers occupied in the media interface controller is less than a specified threshold, and so on. LUN controller X needs to use the XOR buffer allocated in step 1601 when handling R operations. To use the XOR buffer, LUN controller X applies for the XOR buffer indicated in the R operation when processing the R operation. If the XOR buffer is not available, the LUN controller pauses processing the R operation and attempts to continue to apply for the XOR buffer. After applying for the XOR buffer, LUN controller X uses the XOR buffer to exclusive-or and leave the result in the XOR buffer, and then releases the XOR buffer.
Step 1605, after determining the parity data corresponding to the page stripe according to the plurality of R operations, generating a media interface command representing the P2 operation, and moving the parity data in the XOR buffer to the physical page storing the parity data on the page stripe through the P2 operation, thereby completing writing of the parity data. Optionally, writing the parity data to the page stripe requires generating multiple P2 operations. P2 operations are assigned to the LUN controllers corresponding to the LUNs accessed by the P2 operations to process the P2 operations.
When the unprocessed media interface command is recorded through the command queue in the LUN controller, whether the LUN controller has an erasure operation to be processed currently can be identified through the unprocessed media interface command recorded by the command queue. The LUN controller may be allocated for R operations in one implementation in combination with the erase operation and the current load conditions of the LUN controller (e.g., state M1 or state M2).
FIG. 17 illustrates a flowchart of a method for writing user data and parity data to a specified page stripe based on P1, R, and P2 operations, according to yet another embodiment of the present application. Referring to fig. 17, the steps may be included as follows:
step 1710 allocates a stripe of pages, allocates an XOR buffer for the stripe of pages.
Step 1720, when writing user data to a physical page in the page stripe, generates a pair of P1 operation and R operation. Pairs of P1 and R operations may include multiple pairs. The pairs of P1 and R operations may be provided simultaneously with the media interface controller, and the media interface controller processes the pairs of P1 and R operations in parallel without being limited by the order in which the P1 and R operations are received. For paired P1 and R operations, the corresponding R operation may be processed first, even though the P1 operation has not yet been processed, and vice versa.
Step 1730, for each P1 operation, determining a LUN controller a corresponding to the P1 operation according to a logical unit to which a physical address indicated in a media interface command representing the P1 operation belongs, allocating the P1 operation to the LUN controller a, and processing the P1 operation by the LUN controller a.
Step 1740, when processing the R operation of the pair of P1 operation and R operation, identifying whether the LUN controller A processing the P1 operation has a pending erase operation.
All media interface commands which are distributed to the LUN controller A and are not processed are recorded in a command queue of the LUN controller A, and whether the media interface commands recorded in the command queue of the LUN controller A have media interface commands corresponding to erasure operation or not is identified. If so, then LUN controller A has an erase operation to be processed.
In step 1740, if there is an erase operation pending on LUN controller A for processing P1 operation, go to step 1745, otherwise, go to step 1750.
Step 1745, if there is an erasure operation to be processed in the LUN controller a, assigning an R operation to the free LUN controller X, and processing the R operation by the LUN controller X.
LUN controller X is a different LUN controller from LUN controller a in the media interface controller.
Step 1750, if the LUN controller a does not have the pending erase operation, identifying whether the LUN controller a or the media interface controller corresponding to the R operation is in the state M1.
For example, the number of media interface commands recorded in the command queue of LUN controller a or the number of specified media interface commands (e.g., media interface commands corresponding to write operations) is counted. If the number of media interface commands recorded in the command queue of the LUN controller a is greater than the threshold B, the LUN controller a or the media interface controller corresponding to the R operation is in the state M1. Or if the number of the designated media interface commands recorded in the command queue of the LUN controller a is greater than the threshold C, the LUN controller a or the media interface controller corresponding to the R operation is in the state M1. Or the occupied proportion of the XOR buffer in the current XOR calculation unit is greater than the threshold value A, and the LUN controller A or the medium interface controller corresponding to the R operation is in the state M1.
If the LUN controller a or the media interface controller corresponding to the R operation is in state M1, the process goes to step 1755, otherwise, the process goes to step 1760.
Step 1755, if the LUN controller a or the media interface controller is in the state M1, assigning R operation to the free LUN controller X.
Step 1760, if LUN controller A or media interface controller is not in state M1, assigning R operation to LUN controller A.
Step 1770, after determining the parity data corresponding to the page stripe according to the plurality of R operations, generating one or more P2 operations to move the parity data to the physical page storing the parity data. P2 operations are assigned to the LUN controllers corresponding to the LUNs accessed by the P2 operations to process the P2 operations. After the P2 operation is processed, the XOR cache indicated by the P2 operation is optionally also released.
Alternatively, the P2 operation needs to be processed after all R operations that generate check data for the page stripe it accesses are processed. But the execution or absence of a P1 operation accessing the same page stripe does not affect the processing of a P2 operation. So that a P2 operation may be generated and processed before 1 or more P1 operations with which it accesses the same page stripe are processed.
While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the application. It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.