Disclosure of Invention
The invention aims to provide a photovoltaic cell and a preparation method thereof, which are used for solving the technical problem of high silicon substrate loss in the preparation method of the photovoltaic cell.
In order to achieve the above object, the present invention provides the following technical solutions:
in a first aspect, the present invention provides a method for preparing a photovoltaic cell, comprising:
Providing a substrate, wherein the substrate is provided with a first surface and a second surface which are opposite, and the first surface comprises a first area, a second area and a third area positioned between the first area and the second area;
sequentially stacking a first tunneling oxide layer, an intrinsic polysilicon layer and a first doping layer on the first surface;
removing the first tunneling oxide layer, the intrinsic polysilicon layer and the first doped layer on the second region and the third region to form a third surface of the substrate;
Diffusing a first doping element of the first doping layer to the intrinsic polycrystalline silicon layer to form a first doping polycrystalline silicon layer opposite to the first region;
Sequentially stacking a second tunneling oxide layer and a second doped polysilicon layer on a portion of the third surface corresponding to the second region;
And removing a portion of the first doped layer opposite to the first region.
According to at least one embodiment of the present invention, before stacking the first tunneling oxide layer, the intrinsic polysilicon layer, and the first doping layer in order on the first surface, the preparation method further includes:
Forming a first pile on the first surface, and/or,
A second pile is formed on the second surface.
According to at least one embodiment of the present invention, after stacking a second tunneling oxide layer and a second doped polysilicon layer in order on a portion of the third surface corresponding to the second region, before removing a portion of the first doped layer opposite to the first region, the preparation method further includes:
A third pile surface is formed on a portion of the third surface corresponding to the third region.
According to at least one embodiment of the present invention, when a second tunneling oxide layer and a second doped polysilicon layer are sequentially stacked on a portion of the third surface corresponding to the second region, the preparation method includes:
sequentially stacking the second tunneling oxide layer and the second doped polysilicon layer on one side, away from the substrate, of the first doped layer and on the third surface;
And removing the parts of the second tunneling oxide layer opposite to the first region and the third region and the parts of the second doped polysilicon layer opposite to the first region and the third region.
According to at least one embodiment of the invention, a second doped layer is further formed on the side of the second doped polysilicon layer facing away from the substrate;
Before removing the portion of the second tunneling oxide layer opposite to the first region and the third region and the portion of the second doped polysilicon layer opposite to the first region and the third region, the preparation method further includes:
and removing a portion of the second doped layer opposite to the first region and the third region.
According to at least one embodiment of the present invention, when removing a portion of the first doped layer opposite to the first region, the preparation method further includes:
And removing a portion of the second doped layer opposite to the second region.
According to at least one embodiment of the present invention, after removing the portion of the first doped layer opposite to the first region, the preparation method further includes:
Stacking a first passivation anti-reflection layer on the first doped polysilicon layer, the second doped polysilicon layer and the portion of the third surface corresponding to the third region;
along the stacking direction, a first electrode penetrates through the part of the first passivation anti-reflection layer, which is positioned on the first doped polysilicon layer, and is connected with the first doped polysilicon layer;
And arranging a second electrode penetrating through the part of the first passivation anti-reflection layer, which is positioned on the second doped polysilicon layer, and forming connection with the second doped polysilicon layer.
According to at least one embodiment of the present invention, when a first passivation and anti-reflection layer is stacked on each of the first doped polysilicon layer, the second doped polysilicon layer, and a portion of the third surface corresponding to the third region, the preparation method further includes:
And stacking a second passivation anti-reflection layer on the second surface or the second suede.
According to at least one embodiment of the present invention, the first doped layer is a borosilicate glass layer, and the step of diffusing the first doping element of the first doped layer into the intrinsic polysilicon layer to form a first doped polysilicon layer opposite to the first region includes:
diffusing the borosilicate glass layer as a boron source into the intrinsic polysilicon layer to form a boron doped first doped polysilicon layer, or
The first doped layer is a phosphosilicate glass layer, and the step of diffusing the first doping element of the first doped layer into the intrinsic polysilicon layer to form a first doped polysilicon layer opposite to the first region includes:
and diffusing the phosphorosilicate glass layer as a phosphorus source to the intrinsic polycrystalline silicon layer to form a phosphorus doped first doped polycrystalline silicon layer.
According to at least one embodiment of the present invention, the second doped polysilicon layer includes one of a phosphorus doped second doped polysilicon layer or a boron doped second doped polysilicon layer.
In a second aspect, the present invention also provides a photovoltaic cell manufactured by the manufacturing method according to the first aspect.
In one or more of the technical solutions provided in the exemplary embodiments of the present invention, at least one of the following advantages may be achieved.
In the method for manufacturing the photovoltaic cell according to the exemplary embodiment of the present invention, the first tunneling oxide layer, the intrinsic polysilicon layer, and the first doped layer are sequentially stacked on the first surface of the substrate, and then the above-mentioned three-layer structures of the second region and the third region are removed, and the above-mentioned three-layer structure on the first region is maintained. The first doped polysilicon layer is formed on the first region by diffusing the first doping element of the first doped layer into the intrinsic polysilicon layer, and the second doped polysilicon layer on the third region is formed in a subsequent process. In the prior art, a first tunneling oxide layer, a first doped polysilicon layer and a first doped layer are sequentially formed on all areas of a first surface of a substrate, and then the first tunneling oxide layer, the first doped polysilicon layer and the first doped layer on a second area and a third area are removed, and the first tunneling oxide layer and the first doped polysilicon layer on the first area are reserved, so that a layer of shallow doped matrix layer is inevitably formed on all areas of the first surface of the substrate, and parts of the doped matrix layer, which are positioned in the second area and the third area, need to be removed in subsequent procedures, thereby increasing the loss of the substrate.
Compared with the prior art, in the preparation method of the exemplary embodiment of the invention, after the steps of removing the first tunneling oxide layer, the intrinsic polysilicon layer and the first doped layer of the second region and the third region, the first doped polysilicon layer on the first region is formed, so that the formation of the doped matrix layer on the second region and the third region is avoided, and the removal of the part of the doped matrix layer in the subsequent process is avoided. Based on the above, the manufacturing method of the exemplary embodiment of the present invention can reduce the loss of the substrate as much as possible, and for the same substrate, compared with the manufacturing method of the prior art, the power generation efficiency of the substrate can be improved.
Meanwhile, in the photovoltaic cell manufactured by the manufacturing method according to the exemplary embodiment of the present invention, the second region and the third region are removed by one less doped base layer compared with the prior art, and thus, the height difference between the second region and the first region is reduced. In the process of forming the grid line in the second area of the subsequent process, the dosage of the grid line slurry can be reduced, and the situation of poor grid line type is not easy to occur.
Further, a laser etching process is generally used in the process of removing the second region and the third region, and the preparation method of the exemplary embodiment of the present invention needs to remove the intrinsic polysilicon layer of the region, whereas in the prior art, the first doped polysilicon layer of the region needs to be removed, and the laser energy required for removing the intrinsic polysilicon layer is lower than that of the first doped polysilicon layer, so that the laser etching difficulty can be effectively reduced, and the cost is lower.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Before describing the embodiments of the present invention, the following definitions are first given for the relative terms involved in the embodiments of the present invention:
Fill Factor (FF) in photovoltaic cells and other photovoltaic devices can be used to measure the effect of internal resistance and electron loss of a photovoltaic device on its performance. The fill factor is a characteristic of the current-voltage (I-V) curve, and represents the ratio of maximum output power ImVm to limit output power IscVoc, i.e., ff= ImVm/IscVoc.
The value of the filling factor ranges from 0 to 1, and the closer to 1 is the better the performance of the photoelectric device. The fill factor is mainly determined by the series resistance, shunt resistance and PN junction characteristics. The FF becomes smaller when the series resistance increases, the shunt resistance decreases, and defects such as defects and impurities are present in the PN junction. In addition, the fill factor increases with increasing forbidden bandwidth of the battery material.
The short-circuit current density (Short Circuit Current Density, jsc) refers to the current density per unit area generated by the photovoltaic cell in a short-circuit condition. In the short-circuit state, the two electrodes of the photovoltaic cell are directly connected together, without an external load, the magnitude of which is expressed as the vertical axis intercept in the graph of the J-V curve, in mA/cm2. Jsc is primarily affected by the intensity of incident light and the size of the material's absorption band gap, with smaller band gaps being more capable of converting photons into electrical energy. In addition, the device thickness, the quality of each layer of film, and the carrier transport capability all affect the Jsc size.
The open circuit voltage (Open Circuit Voltage, voc) refers to the voltage difference between the two electrodes when the photovoltaic cell is not connected to any load. Specific values of open circuit voltage are represented in the J-V curve diagram as intercept lengths in the transverse axes, typically in mV or V.
Calculation of the conversion efficiency ETA (ETA) is typically used to measure the ability of a photovoltaic cell to convert solar energy into electrical energy, photovoltaic cell conversion efficiency eta= (electrical energy produced by the cell/solar radiation energy impinging on the cell) ×100%.
The IBC battery structure has good compatibility with other high efficiency battery structures. The tunneling oxidation passivation contact technology of TOPCon photovoltaic cells can solve the problem of high recombination of the metal contact area on the back surface of the N-type cell, and separates the N-type crystalline silicon substrate from the doped polysilicon layer through an ultrathin tunneling oxide layer. The tunneling oxide layer is thin, so that the tunneling oxide layer does not obstruct the transmission of majority carriers, but can prevent minority carriers from reaching an interface, the recombination of the interface can be obviously reduced, and the high doped polysilicon layer can form good ohmic contact with the metal electrode.
Applying TOPCon technology to IBC cells can further improve solar cell efficiency, for example TBC photovoltaic cells prepared using the above technology are a current research hotspot. In the TBC production process, a plurality of cleaning processes such as laser etching, alkali cleaning, acid cleaning and the like are required, so that the loss of the silicon substrate can be increased.
Fig. 1 is a schematic flow chart of a preparation method of a photovoltaic cell according to an embodiment of the present invention, and fig. 2 to 11 are schematic cross-sectional views of corresponding process structures after each step in the preparation method of a photovoltaic cell according to an embodiment of the present invention is completed. As shown in fig. 1, an exemplary embodiment of the present invention provides a method for manufacturing a photovoltaic cell, which may include the steps of:
Step 101, providing a substrate 10, wherein the substrate 10 has a first surface 11 and a second surface 12 opposite to each other, and the first surface 11 includes a first area E1, a second area E2, and a third area E3 located between the first area E1 and the second area E2, as shown in fig. 2.
Illustratively, the substrate 10 may be a silicon substrate, such as a p-type silicon substrate or an n-type silicon substrate. The front surface (light receiving surface) of the substrate 10 is a second surface 12, and the back surface is a first surface 11.
It should be noted that the substrate 10 of fig. 2 does not have only one set of the first region E1, the second region E2, and the third region E3, but may have multiple sets of the above regions.
For example, the first surface 11 may have the first area E1, the third area E3, the second area E2, the third area E3, the first area E1, the third area E3, and the second area E2 sequentially arranged thereon, or the first surface 11 may have the first area E1, the third area E3, the second area E2, the third area E3, and the first area E1 sequentially arranged thereon, that is, the third area E3 is provided between each group of areas.
Step 102, sequentially stacking a first tunneling oxide layer 21, an intrinsic polysilicon layer 22 and a first doped layer 23 on the first surface 11, as shown in fig. 3.
A first tunnel oxide layer 21, an intrinsic polysilicon layer 22, and a first doped layer 23 may be sequentially deposited on the substrate 10 by deposition over the entire area of the first surface 11. The Deposition process can be sequentially prepared by adopting any one Deposition mode or a combination of multiple Deposition modes of vacuum evaporation, a low-pressure chemical Vapor Deposition method (Low Pressure Chemical Vapor Deposition, LPCVD), a plasma enhanced chemical Vapor Deposition method (PLASMA ENHANCED CHEMICAL Vapor Deposition, PECVD), a physical Vapor Deposition method (Physical Vapour Deposition, PVD) and monoatomic layer Deposition (atomic layer Deposition, ALD).
A p region (positive electrode region) is formed in the first region E1, an n region (negative electrode region) is formed in the second region E2, and a spacer region between the p region and the n region is formed in the third region E3.
The first tunneling oxide layer 21 is a silicon oxide layer with a thickness of 0.5 nn-3.0 nm, for example, 0.7nm, 1nm, 1.5nm, 2nm, 2.5nm, etc., and the thickness of the first tunneling oxide layer 21 is reasonably controlled to increase the collection probability of majority carriers and further improve the photoelectric conversion efficiency of the battery, the first doped layer 23 is a borosilicate glass layer (Boron Silicon Glass, BSG), the process and cost for using the borosilicate glass layer are lower, and the intrinsic polysilicon layer 22 is an undoped polysilicon layer.
Step 103 is to remove the first tunneling oxide layer 21, the intrinsic polysilicon layer 22 and the first doped layer 23 on the second region E2 and the third region E3 to form the third surface 13 of the substrate 10, as shown in fig. 4.
Illustratively, a method of one or more combinations of laser lift-off or chemical clean etching may be employed to remove the first tunneling oxide layer 21, the intrinsic polysilicon layer 22, and the first doped layer 23 on the second region E2 and on the third region E3.
For example, the laser lift-off is performed by irradiating a laser beam with a laser beam to remove the first doped layer 23 on the second region E2 and the third region E3, then removing the intrinsic polysilicon layer 22 and the first tunnel oxide layer 21 on the second region E2 and the third region E3 by chemical cleaning etching, specifically, printing an alkali cleaning solution such as sodium hydroxide on the second region E2 and the third region E3 by a roller, removing the intrinsic polysilicon layer 22 by etching, and printing an acid cleaning solution such as hydrofluoric acid on the region, and removing the first tunnel oxide layer 21 by etching.
In the above-described process of removing the stacked structure on the second region E2 and the third region E3, there is a possibility that etching of a certain depth is formed on the substrate 10, thereby forming the third surface 13 of the substrate 10, and a certain height difference H1 is formed between the third surface 13 and the portion of the first surface 11 located in the first region E1, as shown in fig. 4. It will be appreciated that H1 may also be 0, i.e. the third surface 13 may be flush with the first surface 11.
It should be noted that, in the process of depositing the stacked structure on the first surface 11 in step 102, a portion of the materials of the first tunneling oxide layer 21, the intrinsic polysilicon layer 22, and the first doped layer 23 may be coated around the second surface 12 of the substrate 10 due to process reasons. Therefore, in this step 103, the above three materials on the second surface 12 are removed by chemical cleaning and etching.
Step 104, diffusing the first doping element of the first doped layer 23 into the intrinsic polysilicon layer 22 to form a first doped polysilicon layer 22a opposite to the first region E1, as shown in fig. 5.
And performing diffusion treatment on the intrinsic polycrystalline silicon layer 22 by taking the borosilicate glass layer as a boron source in a high-temperature annealing mode, so as to obtain the boron doped polycrystalline silicon layer on the first region E1.
Illustratively, the annealing temperature in this step is 850-1100 ℃, e.g., 900 ℃, 950 ℃, 1000 ℃, 1050 ℃, etc. Under the above annealing temperature conditions, the doping concentration of the first doped polysilicon layer 22a may be optimized. Illustratively, the first doped polysilicon layer 22a may have a thickness of 50 nm-300 nm, such as 60nm, 70nm, 80nm, 100nm, 150nm, 200nm, 250nm, etc.
In step 105, a second tunneling oxide layer 31 and a second doped polysilicon layer 32 are sequentially stacked on a portion of the third surface 13 corresponding to the second region E2, forming a structure as shown in fig. 9.
In step 1051, a second tunneling oxide layer 31 and a second doped polysilicon layer 32 are sequentially stacked on the side of the first doped layer 23 facing away from the substrate 10 and on the third surface 13, so as to form a structure as shown in fig. 6.
The side of the first doped layer 23 facing away from the substrate 10, i.e. the portion of the back surface of the substrate 10 located in the first region E1, and the third surface 13, i.e. the portion of the back surface of the substrate 10 located in the third region E3 and the second region E2, are each stacked with a second tunnel oxide layer 31 and a second doped polysilicon layer 32, or a second tunnel oxide layer 31 is deposited by deposition over the entire back surface of the substrate 10, and then a second doped polysilicon layer 32 is deposited. The implementation mode can avoid using a mask process, and the preparation process is simple and effective.
The second tunneling oxide layer 31 may be a silicon oxide layer, and the thickness thereof may be 0.5 nm-3.0 nm, for example, 0.7nm, 1nm, 1.5nm, 2nm, 2.5nm, etc., and by reasonably controlling the thickness of the second tunneling oxide layer 31, the collection probability of majority carriers may be increased, thereby improving the photoelectric conversion efficiency of the battery.
The thickness of the second doped polysilicon layer 32 may be 50nm to 300nm, for example 60nm, 70nm, 80nm, 100nm, 150nm, 200nm, 250nm, etc. Illustratively, the thickness of the second doped polysilicon layer 32 may or may not be consistent with the thickness of the first doped polysilicon layer 22 a.
The second doping element of the second doped polysilicon layer 32 is different from the first doping element, and when the first doping element is boron, the second doping element is phosphorus, that is, the second doped polysilicon layer 32 is the phosphorus doped second doped polysilicon layer 32, and in the finally formed cell, the first region E1 forms a p region, and the second region E2 forms an n region.
When the first doping element is phosphorus, the second doping element is boron, that is, the second doped polysilicon layer 32 is a boron doped second doped polysilicon layer 32, and in the finally formed cell, the first region E1 forms an n region, and the second region E2 forms a p region. In this embodiment, since the temperature of boron diffusion is higher than the temperature of phosphorus diffusion, phosphorus diffusion is performed first to form an n region in the first region E1, and then boron diffusion is performed to form a p region in the second region E2, which affects the active layer concentration of the n region and is further detrimental to the photoelectric conversion efficiency of the battery.
Illustratively, in step 1051, the deposition process may be sequentially performed using any one or a combination of deposition methods of vacuum evaporation, low pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, physical vapor deposition, and monoatomic layer deposition.
In an alternative embodiment, in step 1051, the corresponding portions of the first region E1 and the third region E3 on the back surface of the substrate 10 are masked by using a mask, and then the second tunnel oxide layer 31 and the second doped polysilicon layer 32 are sequentially stacked on the portion of the third surface 13 corresponding to the second region E2 through a deposition process.
Illustratively, in this step 1051, a second doped polysilicon layer 33 is also formed on a side of the second doped polysilicon layer 32 facing away from the substrate 10.
During the formation of the second doped polysilicon layer 32 on the second tunnel oxide layer 31, the second doped layer 33 is naturally formed. Taking the second doped polysilicon layer 32 as an example of the second doped polysilicon layer 32 doped with phosphorus, a phosphosilicate glass layer (Phospho SILICATE GLASS, PSG) is naturally formed on the second doped polysilicon layer 32, as shown in fig. 6.
Step 1052 is to remove the portions of the second tunnel oxide layer 31 opposite the first and third regions E1 and E3 and the portions of the second doped polysilicon layer 32 opposite the first and third regions E1 and E3 to form the structure shown in fig. 7.
Illustratively, a method of one or more of laser lift-off or chemical clean etching may be employed to remove portions of the second tunnel oxide layer 31 opposite the first and third regions E1 and E3, portions of the second doped polysilicon layer 32 opposite the first and third regions E1 and E3.
For example, the specific process of laser lift-off is that the laser emits laser light, and the laser bombards the surface to remove the portion of the second doped polysilicon layer 32 opposite to the first region E1 and the third region E3, the portion of the second tunnel oxide layer 31 opposite to the first region E1 and the third region E3, so as to expose the first doped layer 23 opposite to the first region E1, and the portion of the third surface 13 located in the third region E3.
When the second doped layer 33 is formed during the formation of the second doped polysilicon layer 32. In this step 1052, the photovoltaic cell manufacturing method further includes removing portions of the second doped layer 33 opposite to the first region E1 and the third region E3.
Since the second doped layer 33 is located at a side of the second doped polysilicon layer 32 facing away from the substrate 10, the second doped layer 33 needs to be removed first in order to remove portions of the second doped polysilicon layer 32 opposite the first and third regions E1 and E3 and portions of the second tunnel oxide layer 31 opposite the first and third regions E1 and E3.
Illustratively, portions of the second doped layer 33 opposite the first and third regions E1 and E3 may be etched away by laser lift-off.
Illustratively, the portions of the second doped layer 33 opposite the first and third regions E1 and E3 may also be removed by etching the second doped layer 33 using, for example, a hydrofluoric acid solution, specifically, a hydrofluoric acid solution is printed on the first and third regions E1 and E3 by a roller to etch the second doped layer 33 on the two regions.
Step 1053, forming a third pile surface 43 on a portion of the third surface 13 corresponding to the third region E3, as shown in fig. 8.
Illustratively, when the third pile face 43 is formed on the portion of the third surface 13 corresponding to the third region E3, the second pile face 42 is also formed on the second surface 12.
For example, a textured surface is formed on the second surface 12 and on a portion of the third surface 13 corresponding to the third region E3 by etching by alkali washing, for example, by reacting a sodium hydroxide solution with the surface of the substrate 10.
It should be noted that, before this step 1053, the second surface 12 of the substrate 10 may be coated with the second doped layer 33, the second doped polysilicon layer 32 and the second tunnel oxide layer 31, so before the second surface 12 forms the textured surface, the layers of the second surface 12 need to be removed by acid washing or alkali washing to expose the silicon substrate of the substrate 10.
Step 106, removing the portion of the first doped layer 23 opposite to the first region E1 to form the structure shown in fig. 9.
After step 1052, the portion of the first doped layer 23 opposite to the first region E1 is exposed, and the portion of the first doped layer 23 needs to be removed to expose the first doped polysilicon layer 22a for subsequent formation of the cell structure.
When the second doped layer 33 is formed during the formation of the second doped polysilicon layer 32, the photovoltaic cell fabrication method further includes removing a portion of the second doped layer 33 opposite the second region E2 in this step 106. For example, the portion of the second doped layer 33 opposite to the second region E2 may be etched away by a laser lift-off method or an acid cleaning method, where the specific etching method is consistent with the removal of the corresponding portion of the second doped layer 33 in step 105, which is not described herein.
Step 107 the method of manufacturing a photovoltaic cell further comprises stacking a first passivation anti-reflection layer 51 on the back side and forming an electrode after removing the portion of the first doped layer 23 opposite to the first region E1.
At step 1071, a first passivation anti-reflection layer 51 is stacked on each of the first doped polysilicon layer 22a, the second doped polysilicon layer 32, and the portion of the third surface corresponding to the third region E3.
A first passivation and anti-reflection layer 51 is deposited on the entire back surface of the substrate 10, i.e., the first passivation and anti-reflection layer 51 covers the first doped polysilicon layer 22a, the second doped polysilicon layer 32, and the portion of the third surface corresponding to the third region E3.
Illustratively, the material of the first passivation anti-reflection layer 51 may be one or more of aluminum oxide, silicon nitride, silicon oxynitride or silicon oxide.
In step 1072, when the first passivation and anti-reflection layer 51 is stacked on the first doped polysilicon layer 22a and the second doped polysilicon layer 32, the method further includes stacking the second passivation and anti-reflection layer 52 on the second surface 12 or the second pile face 42 to form the structure shown in fig. 10.
The method for stacking the second passivation and anti-reflection layer 52 is the same as that for stacking the first passivation and anti-reflection layer 51 in step 1071, and will not be described here again. The material of the second passivation anti-reflection layer 52 may be identical or inconsistent with the material of the first passivation anti-reflection layer 51.
Step 1073, disposing the first electrode 61 through the portion of the first passivation and anti-reflection layer 51 located on the first doped polysilicon layer 22a and forming connection with the first doped polysilicon layer 22a along the stacking direction, and disposing the second electrode 62 through the portion of the first passivation and anti-reflection layer 51 located on the second doped polysilicon layer 32 and forming connection with the second doped polysilicon layer 32 to form the structure shown in fig. 11.
The above stacking direction is a direction perpendicular to the first surface 11 of the substrate 10, and corresponding metal electrodes are prepared on the first and second regions E1 and E2 by printing electrode paste. For example, the first electrode 61 has one end located outside the first passivation and anti-reflection layer 51 and the other end penetrating the first passivation and anti-reflection layer 51 and extending to the first doped polysilicon layer 22a to form an electrical connection therewith, and the second electrode 62 has one end located outside the first passivation and anti-reflection layer 51 and the other end penetrating the first passivation and anti-reflection layer 51 and extending to the second doped polysilicon layer 32 to form an electrical connection therewith, thereby forming a photovoltaic cell.
Illustratively, when the first doped polysilicon layer 22a is a boron doped first doped polysilicon layer 22a, the first electrode 61 is a positive electrode and, correspondingly, the second electrode 62 is a negative electrode.
In some embodiments, when the first doped polysilicon layer 22a is a phosphorus doped first doped polysilicon layer 22a, the first electrode 61 is a negative electrode and, correspondingly, the second electrode 62 is a positive electrode.
In some embodiments, the photovoltaic cell manufacturing method of the present exemplary embodiment further comprises a texturing step, a polishing step, before step 102, after step 101.
Illustratively, a first textured surface (not shown) is formed on the first surface 11 of the substrate 10, and optionally a second textured surface 42 is formed on the second surface 12, before the first tunneling oxide layer 21, the intrinsic polysilicon layer 22, and the first doped layer 23 are sequentially stacked on the first surface 11.
For example, a suede may be formed on both the first surface 11 and the second surface 12 of the substrate 10 by alkali washing, while removing dirt, impurities, metal ions, etc. on the surface of the substrate 10 by alkali washing or acid washing, and performing a polishing process.
The surface of the substrate 10 is textured before step 102, so that the stacked structure formed subsequently on the first area E1, the first tunneling oxide layer 21, the first doped polysilicon layer 22a and the first passivation anti-reflection layer 51 all have a textured effect, and the light trapping effect is utilized to improve the photoelectric conversion efficiency. If the pile is formed in the subsequent process, for example, in step 1053, the pile cannot be formed on the first region E1 of the substrate 10 because the first region E1 is already covered with the stacked structure, and the photoelectric conversion efficiency is reduced.
Examples and comparative examples are given below to illustrate the technical effects of the preparation method of the exemplary embodiment of the present invention.
Example 1
As shown in fig. 2-11, a method for preparing a TBC photovoltaic cell includes the steps of:
Step 201, double-sided texturing is performed on the first surface 11 and the second surface 12 of the silicon substrate 10, wherein the first surface 11 is provided with at least one group of areas, and each group of areas is divided into a first area E1, a second area E2 and a third area E3 which is arranged between the first area E1 and the second area E2 as a space. The silicon substrate 10 is an n-type silicon base.
Step 202, sequentially depositing a first tunneling oxide layer 21, an intrinsic polysilicon layer 22 and a borosilicate glass layer on the first surface 11, wherein the first tunneling oxide layer 21 is silicon oxide, and the thickness of the first tunneling oxide layer is 1.8nm.
Step 203, removing borosilicate glass layers, a first tunneling oxide layer 21 and an intrinsic polysilicon layer 22 of the second region E2 and the third region E3 by laser, wherein the height difference between the first region E1 and the second region E2 is H1, H1 = 0.5 μm, and the laser wavelength is 355nm, the output power is 3W, and the scanning speed is 2000mm/s.
The borosilicate glass layer on the second surface 12, the first tunneling oxide layer 21, and the intrinsic polysilicon layer 22 are removed by acid cleaning.
And 204, performing high-temperature 1000 ℃ annealing, and performing diffusion treatment on the intrinsic polycrystalline silicon layer 22 by taking the borosilicate glass layer as a boron source to obtain a p-type first doped polycrystalline silicon layer 22a with the thickness of 120 nm.
Step 205, sequentially depositing a second tunneling oxide layer 31 (silicon oxide) with a thickness of 1.8nm and an n-type second doped polysilicon layer 32 (phosphorus doped) with a thickness of 120nm on the back surface of the silicon substrate 10 to naturally form a phosphosilicate glass layer.
Step 206, removing the second tunneling oxide layer 31, the second doped polysilicon layer 32 and the phosphosilicate glass layer of the first region E1 and the third region E3 by laser.
Step 207 is to remove the phosphosilicate glass layer, the second tunnel oxide layer 31 and the second doped polysilicon layer 32 on the second surface 12. A pile surface is formed on the second surface 12 and the third surface 13 at a portion corresponding to the third region E3.
Step 208, acid cleaning, wherein the borosilicate glass layer of the first area E1 and the phosphosilicate glass layer of the second area E2 are removed by using hydrofluoric acid solution.
Step 209, depositing a second passivation and anti-reflection layer 52 and a first passivation and anti-reflection layer 51 on the second surface 12 and the back surface of the substrate 10, wherein the second passivation and anti-reflection layer 52 and the first passivation and anti-reflection layer 51 are aluminum oxide layers respectively.
Step 210 of preparing a first electrode 61 on the first region E1, which is electrically connected to the first doped polysilicon layer 22a through the first passivation anti-reflection layer 51;
A second electrode 62 is fabricated on the second region E2 and electrically connected to the second doped polysilicon layer 32 through the first passivation anti-reflective layer 51 to produce a TBC photovoltaic cell.
Example 2
This embodiment differs from embodiment 1 only in that:
In step 203, the difference in height between the first region E1 and the second region E2 is 1.0 μm.
Example 3
This embodiment differs from embodiment 1 only in that:
in step 203, the difference in height between the first region E1 and the second region E2 is 1.5 μm.
Comparative example
Fig. 12-19 are schematic cross-sectional views of corresponding process structures after completion of each step in the method for manufacturing a photovoltaic cell in the comparative example. A method of preparing a TBC photovoltaic cell comprising the steps of:
Step 301, double-sided texturing is performed on the first surface 11 and the second surface 12 of the silicon substrate 10, wherein the first surface 11 has at least one group of areas, and each group of areas is divided into a first area E1, a second area E2 and a third area E3 which is located between the first area E1 and the second area E2 as a space. The silicon substrate 10 is an n-type silicon base.
Step 302, sequentially depositing a first tunneling oxide layer 21, a first doped polysilicon layer 22a and a first doped layer 23 on the first surface 11, wherein the first doped layer 23 is a borosilicate glass layer naturally formed when the first doped polysilicon layer 22a is formed, and the first tunneling oxide layer 21 is silicon oxide with a thickness of 1.8nm, as shown in fig. 12.
Step 303, removing borosilicate glass layers of the second area E2 and the third area E3, the first tunneling oxide layer 21, the first doped polysilicon layer 22a and the doped matrix layer 22b by laser, wherein the height difference between the first area E1 and the second area E2 is H2, and the doped matrix layer 22b has to be removed, at this time, h2=3μm, H2> H1, and the damage amount of the silicon substrate 10 is more than that of the embodiment, as shown in fig. 13, wherein the laser wavelength is 355nm, the output power is 3W, and the scanning speed is 2000mm/s.
The borosilicate glass layer on the second surface 12, the first tunneling oxide layer 21, and the first doped polysilicon layer 22a are removed by acid cleaning and alkali cleaning.
Step 304, a second tunneling oxide layer 31 (silicon oxide) with a thickness of 1.8nm and an n-type second doped polysilicon layer 32 (phosphorus doped) with a thickness of 120nm are sequentially deposited on the back surface of the silicon substrate 10, and a phosphosilicate glass layer is naturally formed, as shown in fig. 14.
Step 305, laser removing the second tunneling oxide layer 31, the second doped polysilicon layer 32 and the phosphosilicate glass layer of the first region E1 and the third region E3, as shown in fig. 15.
Step 306 is to remove the phosphosilicate glass layer, the second tunneling oxide layer 31 and the second doped polysilicon layer 32 on the second surface 12. A pile is formed on the second surface 12 and the third surface 13 at a portion corresponding to the third region E3, as shown in fig. 16.
Step 307, acid cleaning, removing the borosilicate glass layer of the first region E1 and the phosphosilicate glass layer of the second region E2 by using hydrofluoric acid solution, as shown in FIG. 17.
Step 308, depositing a second passivation and anti-reflection layer 52 and a first passivation and anti-reflection layer 51 on the second surface 12 and the back surface of the substrate 10, respectively, wherein the second passivation and anti-reflection layer 52 and the first passivation and anti-reflection layer 51 are aluminum oxide layers, respectively, as shown in fig. 18.
Step 309, preparing a first electrode 61 on the first region E1, which is electrically connected with the first doped polysilicon layer 22a through the first passivation anti-reflection layer 51;
a second electrode 62 is fabricated on the second region E2 and electrically connected to the second doped polysilicon layer 32 through the first passivation anti-reflective layer 51, producing a TBC photovoltaic cell, as shown in fig. 19.
Table 1 electrical performance data for TBC photovoltaic cells
| Jsc(mA/cm2) | Voc(mV) | FF(%) | Eta(%) |
| Example 1 | 43.27 | 734.6 | 81.38 | 25.87 |
| Example 2 | 43.25 | 734.7 | 81.29 | 25.83 |
| Example 3 | 43.27 | 734.8 | 81.21 | 25.82 |
| Comparative example | 43.26 | 734.6 | 80.67 | 25.64 |
Table 2 fine grid paste consumption for TBC photovoltaic cells
As shown in table 1, among the photovoltaic cells prepared by the TBC photovoltaic cell preparation methods of examples 1 to 3, the short-circuit current densities of examples 1 and 3 were increased by 0.01mA/cm2, the fill factors of examples 1 to 3 were increased by 0.71% at the maximum, and the photoelectric conversion efficiencies of examples 1 to 3 were increased by 0.23% at the maximum, relative to the photovoltaic cells prepared by the comparative examples. Therefore, the photovoltaic cell preparation method of the embodiment of the invention improves the conversion efficiency of the cell on the basis of reducing the silicon substrate loss.
As shown in table 2, the photovoltaic cell prepared by the TBC photovoltaic cell preparation method of the example reduced the amount of the N-zone (second zone) fine-grid paste by 14% and the P-zone (first zone) fine-grid paste by 3.5% relative to the photovoltaic cell prepared by the comparative example. Therefore, the photovoltaic cell preparation method of the exemplary embodiment of the invention reduces the silicon substrate loss, that is, reduces the height difference (H2 > H1) between the first region E1 and the second region E2, avoids the problem of excessive usage of thin gate paste in the N region with lower height as much as possible, and simultaneously reduces the height difference to avoid the poor line type of the gate line as much as possible.
As can be seen from the above, in the comparative example, the first tunnel oxide layer 21, the first doped polysilicon layer 22a and the borosilicate glass layer are sequentially formed on the entire area of the first surface 11 of the substrate 10, so that the first tunnel oxide layer 21, the first doped polysilicon layer 22a and the borosilicate glass layer on the second area E2 and the third area E3 are removed, and the first tunnel oxide layer 21 and the first doped polysilicon layer 22a on the first area E1 are remained, so that a lightly doped base layer 22b is inevitably formed on the entire area of the first surface 11 on the substrate 10, and the portions of the doped base layer 22b located in the second area E2 and the third area E3 need to be removed in the subsequent process, thereby increasing the loss of the substrate 10, that is, the height difference H2 between the first area E1 and the second area E2 is larger.
In the preparation method of embodiment 1-embodiment 3 of the present invention, after the steps of removing the first tunneling oxide layer 21, the intrinsic polysilicon layer 22 and the borosilicate glass layer of the second region E2 and the third region E3, the first doped polysilicon layer 22a on the first region E1 is formed again, so that the formation of the doped base layer 22b on the second region E2 and the third region E3 is avoided, and the removal of the doped base layer 22b in the subsequent process, that is, the height difference H1 between the first region E1 and the second region E2 is reduced compared with H2 in the prior art, is avoided. Based on the above, the manufacturing method of the exemplary embodiment of the present invention can reduce the loss of the substrate as much as possible, and for the same substrate, compared with the manufacturing method of the prior art, the power generation efficiency of the substrate can be improved.
The invention further provides a photovoltaic cell, which is manufactured by the photovoltaic cell manufacturing method of the embodiment.
The exemplary embodiment of the invention also provides a photovoltaic cell assembly comprising the photovoltaic cell of the embodiment.
The technical advantages of the photovoltaic cell and the photovoltaic cell assembly compared with the prior art are the same as those of the photovoltaic cell preparation method, and are not repeated here.
It will be appreciated by persons skilled in the art that the above embodiments are provided for clarity of illustration only and are not intended to limit the scope of the invention. Other variations or modifications will be apparent to persons skilled in the art from the foregoing disclosure, and such variations or modifications are intended to be within the scope of the present invention.