Micro-channel heat dissipation packaging structure of chipTechnical Field
The invention relates to the technical field of semiconductor packaging, in particular to a micro-channel heat dissipation packaging structure of a chip.
Background
In the rapidly evolving semiconductor industry today, chip designs are evolving towards higher integration, higher performance, and lower power consumption. However, with the increasing power consumption and increasing power consumption of the chip, the problem of heat dissipation has become a key factor for restricting the further improvement of the chip performance. Although the conventional heat dissipation methods, such as active heat dissipation devices such as fan heat dissipation and heat dissipation fins, alleviate the heat dissipation pressure of the chip to some extent, when facing a multi-chip system with large power consumption and high density integration, the heat dissipation efficiency of the multi-chip system is difficult to meet the requirements, and even the chip may be overheated due to heat accumulation, which affects the stability and reliability of the device.
Therefore, it is necessary to provide a micro-fluidic channel heat dissipation package structure of a chip to solve the above-mentioned problems in the related art.
Disclosure of Invention
The micro-channel heat dissipation packaging structure comprises a substrate, wherein an insulating layer I is arranged on the substrate, a micro-channel II is arranged in the insulating layer I, a heat dissipation layer is arranged on the insulating layer I, the heat dissipation layer comprises a heat dissipation plate arranged on the upper surface and the lower surface of a rewiring layer, a micro-channel I is arranged in the heat dissipation plate, through holes I which are respectively communicated with the micro-channel I in the upper heat dissipation plate and the lower heat dissipation plate are arranged in the rewiring layer, the micro-channel I in the lower heat dissipation plate is communicated with the micro-channel II, an insulating layer II is arranged on the heat dissipation layer, a through hole seven which is communicated with the micro-channel I in the upper heat dissipation plate is arranged in the insulating layer II, a plastic sealing layer is arranged on the insulating layer II, a chip is arranged in the plastic sealing layer, a micro-channel III which is communicated with the through hole seven is also arranged in the plastic sealing layer, a heat equalizing plate is arranged on the plastic sealing layer, a micro-channel IV which is communicated with the micro-channel III is arranged in the heat equalizing plate, the output end of the micro-channel II is communicated with the micro-channel II, and the chip is connected with the substrate through the rewiring layer.
Further, the first orifice is arranged in the heat dissipation plate, the second micro flow channel is connected with the first micro flow channel in the lower heat dissipation plate through the first orifice in the lower heat dissipation plate, and the seventh through hole is connected with the first micro flow channel in the upper heat dissipation plate through the first orifice in the upper heat dissipation plate.
Further, the first through holes are provided in plurality.
Further, a through hole six for connecting with the substrate is formed in the first insulating layer, a conductor II is arranged in the through hole six, a through hole eight for connecting with the chip is formed in the second insulating layer, a conductor III is arranged in the through hole eight, a through hole IV is formed in the heat dissipation plate, a conductor I is arranged in the through hole IV, the conductor III is connected with the upper surface of the rewiring layer through the conductor I in the upper heat dissipation plate, and the conductor II is connected with the lower surface of the rewiring layer through the conductor I in the lower heat dissipation plate.
Further, the micro-channel III is arranged on the periphery of the chip, an orifice II is arranged in the vapor chamber, and the micro-channel IV is connected with the micro-channel III through the orifice II.
Furthermore, grid bars which are S-shaped are distributed in the fourth micro-channel, the grid bars divide the fourth micro-channel into S-shaped channels, the second orifice is arranged on the vapor chamber, the S-shaped channels are connected with the third micro-channel through the second orifice, and an inlet connected with the S-shaped channels is further arranged on the vapor chamber.
Further, an insulating outer frame is arranged on the periphery of the rewiring layer.
Further, a through hole III is formed in the insulating outer frame, a through hole five connected with the through hole III is formed in the heat dissipation plate, a through hole five in the lower heat dissipation plate is connected with the micro-channel II, a through hole nine connected with the through hole five in the upper heat dissipation plate is formed in the insulating layer II, a through hole ten connected with the through hole nine is formed in the plastic sealing layer, an outlet connected with the through hole ten is formed in the vapor chamber, and the through hole III, the through hole five, the through hole ten and the outlet form a return channel.
Further, a heat conducting wall is formed on the inner wall of the micro-channel III.
Compared with the prior art, the invention provides a micro-channel heat dissipation packaging structure of a chip, which has the following beneficial effects:
According to the invention, through the structural design of the heat dissipation layer, the first insulating layer, the second insulating layer, the plastic sealing layer, the vapor chamber and the reflow channel, the micro-channel heat dissipation packaging structure for the chip is more precise, through the design that the inlet is used as a heat dissipation fluid, the micro-channel IV, the micro-channel III, the micro-channel I and the micro-channel II are sequentially formed, and flow out of the reflow channel, the chip, the rewiring layer and the substrate can be fully dissipated, the heat exchange area is greatly increased, the transfer path of heat from the chip to the cooling liquid is shortened, the heat resistance is effectively reduced, the heat dissipation efficiency and the heat dissipation effect are further improved, and especially for the design of the heat dissipation layer, the heat dissipation fluid can fully absorb the heat between the chip and the substrate, and the design of the micro-channel III can fully absorb the heat of the periphery of the chip, so that the efficient heat dissipation effect of the chip is achieved.
Drawings
FIG. 1 is a schematic diagram of a micro-fluidic channel heat dissipation package structure according to the present invention;
FIG. 2 is a schematic diagram of a micro-fluidic channel heat dissipation package structure according to the present invention;
FIG. 3 is a schematic view of a soaking plate structure according to the present invention;
FIG. 4 is a schematic illustration of the preparation of a plastic sealing layer according to the present invention;
FIG. 5 is a schematic diagram of a second embodiment of an insulating layer;
FIG. 6 is a schematic diagram of a heat spreader plate of the present invention;
FIG. 7 is a schematic diagram of a heat dissipation layer according to the present invention;
FIG. 8 is a schematic diagram of an insulation layer according to the present invention;
The heat dissipation layer (3), the insulating layer (4), the insulating layer (5), the insulating layer (6), the plastic sealing layer (7), the chip (8), the soaking plate (9), the reflow channel (10), the carrier plate (21), the through hole (first), the insulating frame (23), the through hole (second), the convex cover (24), the insulating wall (25), the through hole (221), the through hole (third), the heat dissipation plate (31), the heat dissipation plate (32), the conductor (first), the through hole (33), the through hole (fourth), the 34, the through hole (fifth), the 35, the orifice (first), the 311, the micro-channel (first), the 41, the micro-channel (second), the conductor (43), the through hole (sixth), the 51, the through hole (seventh), the 52, the conductor (third), the through hole (eighth), the through hole (ninth), the 61, the micro-channel (third), the 62, the through hole (tenth), the 64, the heat conductor (65), the heat conducting wall (81), the micro-channel (fourth), the 82, the grating bars (83), the outlet (84, the orifice (second, the 85 and the inlet.
Detailed Description
Referring to fig. 1-8, the invention provides a micro-channel heat dissipation packaging structure of a chip, which comprises a substrate 1, wherein an insulating layer I4 is arranged on the substrate 1, a micro-channel II 41 is arranged in the insulating layer I4, a heat dissipation layer 3 is arranged on the insulating layer I4, the heat dissipation layer 3 comprises a heat dissipation plate 31 arranged on the upper surface and the lower surface of a rewiring layer 2, a micro-channel I311 is arranged in the heat dissipation plate 31, through holes 21 which are respectively communicated with the micro-channel I311 in the upper and lower heat dissipation plates 31 are arranged in the rewiring layer 2, the micro-channel I311 in the lower heat dissipation plate 31 is communicated with the micro-channel II 41, an insulating layer II 5 is arranged on the upper surface of the heat dissipation layer 3, a through hole III 51 which is communicated with the micro-channel I311 in the upper heat dissipation plate 31 is arranged in the insulating layer II 5, a plastic layer 6 is arranged on the upper surface of the insulating layer II 5, the chip 7 is arranged in the plastic layer 6, a micro-channel III 61 which is communicated with the through hole III 51 is also arranged in the plastic layer 6, a heat equalizing plate 8 is arranged on the plastic layer 6, the micro-channel I311 is respectively communicated with the micro-channel III which is communicated with the micro-channel I41 in the upper surface of the plastic layer 6, the micro-channel 8 is communicated with the micro-channel I1, the micro-channel I is communicated with the micro-channel I1 through the micro-channel I through the micro-channel 9, and the micro-channel 81 is communicated with the micro-channel I through the micro-channel I2;
In this embodiment, referring to fig. 5, the second insulating layer 5 is processed by forming the second insulating layer 5 on the carrier plate 10 by a chemical vapor deposition process or a physical vapor deposition process, etching the second insulating layer 5 by a deep reactive ion etching process, forming a corresponding eighth through hole 53 on the second insulating layer 5, forming a third conductor 52 in the eighth through hole 53 by a chemical vapor deposition process or a physical vapor deposition process, etching the second insulating layer 5 by a deep reactive ion etching process, and forming a corresponding ninth through hole 54 and a seventh through hole 51 on the second insulating layer 5;
In this embodiment, as shown in fig. 4, the processing steps of the molding layer 6 include molding the chip 7 to form the molding layer 6, etching the molding layer 6 by a deep reactive ion etching process, forming a corresponding micro-channel III 61 on the molding layer 6, forming a heat conductor 64 in the micro-channel III 61 by a chemical vapor deposition process or a physical vapor deposition process, and etching the molding layer 6 and the heat conductor 64 by a deep reactive ion etching process to form a through hole ten 62 and a heat conducting wall 65.
In this embodiment, the first opening 35 is disposed in the heat dissipation plate 31, the second micro-channel 41 is connected with the first micro-channel 311 in the lower heat dissipation plate 31 through the first opening 35 in the lower heat dissipation plate 31, the seventh through-hole 51 is connected with the first micro-channel 311 in the upper heat dissipation plate 31 through the first opening 35 in the upper heat dissipation plate 31, wherein, in combination with fig. 6, the heat dissipation plate 31 is combined with the carrier plate 10, the heat dissipation plate 31 is etched by a deep reactive ion etching process, the fourth corresponding through-hole 33 is formed on the heat dissipation plate 31, the first conductor 32 is formed in the fourth through-hole 33 by a chemical vapor deposition process or a physical vapor deposition process, the heat dissipation plate 31 is etched by a deep reactive ion etching process, and the fifth through-hole 34, the first micro-channel 311 and the first opening 35 are respectively formed on the heat dissipation plate 31, wherein, the first through-hole 35 is provided.
In this embodiment, the first through holes 21 are provided with a plurality of through holes, wherein, as shown in fig. 7 and 1, the re-wiring layer 2, the insulating outer frame 22 and the heat dissipation plate 31 are processed by combining the re-wiring layer 2 with the carrier plate 10, forming the insulating outer frame 22 on the outer periphery of the re-wiring layer 2 through a chemical vapor deposition process or a physical vapor deposition process, etching the re-wiring layer 2 through a deep reactive ion etching process, forming the corresponding second through holes 23 on the re-wiring layer 2, sequentially forming the convex covers 24 matched with the first micro-channels 311 and the filling second through holes 23 on the re-wiring layer 2 through a chemical vapor deposition process or a physical vapor deposition process or a deep reactive ion etching process, combining the re-wiring layer 2 with one surface of the convex covers 24 with the first micro-channels 311, sequentially forming the convex covers 24 matched with the first micro-channels 311, the third through holes 211 matched with the fifth through holes 34 on the re-wiring layer 2 through a chemical vapor deposition process or a physical vapor deposition process, sequentially forming the second through holes 25 in the second through holes, and combining the insulating walls 31 with the other surface of the re-wiring layer 2.
In this embodiment, a through hole six 43 for connecting with the substrate 1 is provided in the insulating layer one 4, a conductor two 42 is provided in the through hole six 43, a through hole eight 53 for connecting with the chip 7 is provided in the insulating layer two 5, a conductor three 52 is provided in the through hole eight 53, a through hole four 33 is provided in the heat dissipation plate 31, a conductor one 32 is provided in the through hole four 33, the conductor three 52 is connected with the upper surface of the rewiring layer 2 through the conductor one 32 in the upper heat dissipation plate 31, the conductor two 42 is connected with the lower surface of the rewiring layer 2 through the conductor one 32 in the lower heat dissipation plate 31, wherein, in combination with the process shown in fig. 8, the insulating layer one 4 is processed by sequentially forming the insulating layer one 4 on the carrier plate 10 through a chemical vapor deposition process or a physical vapor deposition process, etching the insulating layer one 4 is then forming a corresponding through hole six 43 on the insulating layer one 4, then forming the conductor two 42 in the through hole six 43 through a chemical vapor deposition process or a physical vapor deposition process, and then etching the insulating layer one 4 through a deep reaction ion etching process, forming the micro-runner two 41 on the insulating layer one 4.
In this embodiment, the third micro flow channel 61 is disposed on the outer periphery of the chip 7, the soaking plate 8 is provided with the second orifice 84, and the fourth micro flow channel 81 is connected with the third micro flow channel 61 through the second orifice 84, that is, the number of the second orifices 84 is one.
In this embodiment, the fourth micro-runner 81 is provided with an S-shaped barrier rib 82, the fourth micro-runner 81 is separated by the barrier rib 82 to form an S-shaped runner, the soaking plate 81 is provided with a second orifice 84, the S-shaped runner is connected with the third micro-runner 61 through the second orifice 84, and the soaking plate 81 is further provided with an inlet 85 connected with the S-shaped runner.
In this embodiment, an insulating outer frame 22 is provided on the outer periphery of the rewiring layer 2.
In this embodiment, the insulating outer frame 22 is provided with a third through hole 221, the heat dissipation plate 31 is provided with a fifth through hole 34 connected with the third through hole 221, the fifth through hole 34 in the lower heat dissipation plate 31 is connected with the second micro-channel 41, the insulating layer two 5 is provided with a ninth through hole 54 connected with the fifth through hole 34 in the upper heat dissipation plate 31, the plastic layer 6 is provided with a tenth through hole 62 connected with the ninth through hole 54, the soaking plate 8 is provided with an outlet 83 connected with the tenth through hole 62, and the third through hole 221, the fifth through hole 34, the tenth through hole 62 and the outlet 83 form the back flow channel 9.
In this embodiment, the inner wall of the third microchannel 61 is formed with a heat conducting wall 65.
In specific implementation, the method comprises the following steps:
Step 1, prefabricating a soaking plate 8;
Step 2, plastic packaging is carried out on the chip 7 to form a plastic packaging layer 6;
step 3, prefabricating the insulating layer II 5;
Step 4, prefabricating the rewiring layer 2 and the combination of the upper surface and the lower surface of the rewiring layer 2 and the radiating plate 31 to form a radiating layer 3;
step 5, prefabricating the first insulating layer 4;
And 6, preparing and packaging the first insulating layer 4 and the substrate 1, packaging the heat dissipation layer 3 on the first insulating layer 4, packaging the second insulating layer 5 on the heat dissipation layer 3, packaging the plastic layer 6 on the second insulating layer 5, packaging the vapor chamber 8 on the plastic layer 6, forming an inlet which is taken as a heat dissipation fluid, sequentially passing through the fourth micro-channel 81, the third micro-channel 61, the first micro-channel 311 and the second micro-channel 41, and flowing out from the reflow channel 9, thereby fully dissipating heat of the chip 7, the rewiring layer 2 and the substrate 1.
The above description is only of the preferred embodiments of the invention, but the protection scope of the invention is not limited thereto, and any person skilled in the art who is skilled in the art to which the invention pertains should make equivalent substitutions or modifications according to the technical solution of the invention and its inventive concept within the scope of the invention.