Disclosure of Invention
In view of the above, it is an object of the present application to provide a device interconnection system, method, device, medium and program product for simplifying the complexity and layout of device interconnection. The specific scheme is as follows:
in a first aspect, the present application provides an equipment interconnection system, comprising:
at least two resource pools, each resource pool comprising at least one switching chip;
the hardware resource devices in the same resource pool are memory devices, hardware acceleration devices or computing devices, and the hardware resource devices in different resource pools are different;
the at least one upstream port of the at least one switching chip is used for connecting the upstream port of the at least one switching chip in the other resource pool;
the at least one switching chip is used for forwarding the upstream data to the corresponding downstream port according to the destination address of the upstream data sent by any one upstream port and/or forwarding the downstream data to the corresponding upstream port according to the destination address of the downstream data sent by any one downstream port.
Optionally, the at least one switching chip comprises a route forwarding engine module;
The route forwarding engine module is used for determining the destination address of the upstream data sent by any upstream port in the current exchange chip and/or the destination address of the downstream data sent by any downstream port in the current exchange chip according to the routing table.
Optionally, the at least one switching chip comprises a memory module;
the storage module is used for storing the routing table, the upstream data sent by any upstream port in the current exchange chip and the downstream data sent by any downstream port in the current exchange chip.
Optionally, the at least one switching chip comprises a direct memory access engine module;
the direct memory access engine module is used for realizing communication between other resource pools connected with any one upstream port in the current exchange chip and hardware resource equipment connected with any one downstream port in the current exchange chip by using a direct memory access technology.
Optionally, the at least one switching chip comprises a control logic module;
the control logic module comprises a data packet conversion unit, a register unit and a resource sensing module;
the data packet conversion unit is used for converting data format of upstream data sent by any upstream port in the current exchange chip and/or downstream data sent by any downstream port in the current exchange chip;
The register unit is used for configuring port information of any upstream port and/or any downstream port in the current exchange chip, wherein the port information comprises port parameters, port attributes and port states;
the resource sensing unit is used for monitoring whether each downstream port in the current switching chip is connected with hardware resource equipment or not and/or monitoring resource use information of the hardware resource equipment connected with the downstream port in the current switching chip, and generating a corresponding resource sensing table.
Optionally, each downstream port of the at least one switch chip supports a first protocol, and each upstream port of the at least one switch chip supports a second protocol;
Correspondingly, the data packet conversion unit is used for converting the upstream data sent by any upstream port in the current exchange chip into the first protocol format by the second protocol format and/or converting the upstream data sent by any downstream port in the current exchange chip into the second protocol format by the first protocol format.
Optionally, the register unit is configured to configure a routing table and a resource awareness table.
Optionally, the resource sensing unit is configured to update the resource sensing table in real time according to whether each downstream port obtained by real-time monitoring is connected with a hardware resource device and/or resource usage information of the hardware resource device.
Optionally, any hardware resource device is used for sending the idle resource information in the device to the resource sensing unit according to a preset period;
correspondingly, the resource sensing unit updates the resource sensing table according to the information sent by the hardware resource equipment.
Optionally, the resource sensing unit is used for periodically detecting whether the communication links between each upstream port of the current switching chip and the connected resource pool are connected or not, and periodically detecting whether the communication links between each downstream port of the current switching chip and the connected hardware resource equipment are connected or not.
Optionally, each upstream port of the at least one switching chip is provided with a decoder;
The decoder is used for determining the address mapping relation between the memory of the computing device connected with the upstream port where the current decoder is positioned and the hardware resource device connected with the downstream port in the current exchange chip.
Optionally, the decoder is configured to store memory capacity information of a computing device connected to an upstream port where the current decoder is located.
Optionally, the at least one exchange chip comprises a cache consistency interface module;
The cache consistency interface module is used for providing a cache consistency transmission channel for the hardware resource devices connected with each downstream port in the current exchange chip.
Optionally, the at least one switching chip comprises a clock and reset module;
the clock and reset module is used for keeping clock synchronization among devices in the system.
Optionally, the at least one switching chip further comprises a switching function module.
Optionally, the at least one switching chip comprises a power management module;
the power management module is used for providing power for the exchange function module and the exchange chips in each resource pool and managing the power consumption of the exchange function module and the exchange chips in each resource pool.
Optionally, each hardware resource device in each resource pool supports a CLOS topology and/or a full interconnect topology.
In a second aspect, the present application provides a device interconnection method, applied to the device interconnection system described in any one of the foregoing, including:
Aiming at any resource pool in the equipment interconnection system, at least one upstream port of at least one exchange chip in the current resource pool is connected with upstream ports of at least one exchange chip in other resource pools; connecting at least one downstream port of at least one switching chip in the current resource pool with hardware resource equipment; connecting at least one upstream port of at least one switching chip in the current resource pool with upstream ports of other switching chips in the current resource pool;
the device interconnection system comprises at least two resource pools, wherein each resource pool comprises at least one exchange chip, and hardware resource devices in the same resource pool are memory devices, hardware acceleration devices or computing devices, and the hardware resource devices in different resource pools are different;
the at least one switching chip is used for forwarding upstream data to a corresponding downstream port according to a destination address of the upstream data sent by any one upstream port and/or forwarding downstream data to the corresponding upstream port according to a destination address of the downstream data sent by any one downstream port.
In a third aspect, the present application provides an electronic device, comprising:
a memory for storing a computer program;
and a processor for executing the computer program to implement the device interconnection method disclosed above.
In a fourth aspect, the present application provides a non-volatile storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the device interconnection method disclosed above.
In a fifth aspect, the present application provides a computer program product comprising computer programs/instructions which when executed by a processor implement the steps of the device interconnection method disclosed previously.
According to the scheme, the equipment interconnection system comprises at least two resource pools, wherein each resource pool comprises at least one switching chip, at least one downstream port of the at least one switching chip is used for being connected with hardware resource equipment, the hardware resource equipment in the same resource pool is memory equipment, hardware acceleration equipment or computing equipment, the hardware resource equipment in different resource pools is different, at least one upstream port of the at least one switching chip is used for being connected with an upstream port of at least one switching chip in other resource pools, and the at least one switching chip is used for forwarding upstream data to a corresponding downstream port according to a destination address of the upstream data sent by any one upstream port and/or forwarding downstream data to a corresponding upstream port according to a destination address of the downstream data sent by any one downstream port.
The method has the advantages that different hardware resource devices such as memory devices, hardware acceleration devices or computing devices are incorporated into different resource pools, at least one upstream port of at least one switching chip in each resource pool is connected with the upstream port of at least one switching chip in other resource pools, interconnection among different resource pools is achieved, at least one downstream port of at least one switching chip in each resource pool is connected with the hardware resource devices, the switching chips forward upstream data to corresponding downstream ports according to destination addresses of upstream data sent by any one upstream port, and/or forward downstream data to corresponding upstream ports according to destination addresses of downstream data sent by any one downstream port, and intra-system communication is achieved. According to the scheme, the interconnection of devices in the system is realized by the number of ports as small as possible, the downstream devices do not need to be connected in pairs, the number of connecting wires and the wiring layout complexity are reduced, the communication delay can be correspondingly reduced, and the communication requirement of low-delay requirement service is met.
Correspondingly, the device interconnection method, the device, the medium and the program product provided by the application also have the technical effects.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other examples, which a person of ordinary skill in the art would obtain without undue burden based on the embodiments of the application, are within the scope of the application.
Currently, the bus topology architecture is mostly based on PCIe bus and PCIE SWITCH chip tree structures. In this configuration, PCIE SWITCH ports are limited in number. As the system scale increases, the number of levels increases, and PCIE SWITCH is enormous, resulting in complicated wiring and configuration. In addition, the increase of the hop count in the multi-level topology also causes an increase of communication delay, which cannot meet the service requirement with strict requirements for low delay. Therefore, the application provides a device interconnection scheme which can simplify the complexity and wiring layout of device interconnection.
Referring to fig. 1, the embodiment of the application discloses a device interconnection system, which comprises at least two resource pools, wherein each resource pool comprises at least one switching chip, at least one downstream port of the at least one switching chip is used for connecting hardware resource devices, the hardware resource devices in the same resource pool are memory devices, hardware acceleration devices or computing devices, the hardware resource devices in different resource pools are different, and at least one upstream port of the at least one switching chip is used for connecting with an upstream port of the at least one switching chip in other resource pools. And the at least one upstream port of the at least one switching chip is used for connecting the upstream ports of other switching chips in the resource pool where the current switching chip is positioned.
In FIG. 1, each switch chip has ports P1-PN, where P1-P5 are upstream ports and P6-PN are downstream ports. Of course, the number of upstream ports can be extended according to actual requirements.
It should be noted that the memory device may be a DRAM (Dynamic Random Access Memory ) or the like, the hardware acceleration device may be a GPU (Graphics Processing Unit, graphics processor), an FPGA (Field-Programmable gate array) or the like, and the computing device may include a CPU (Central Processing Unit ), a NIC (Network Interface Controller, network interface controller), a DRAM or the like. In one embodiment, each hardware resource device in each resource pool supports a CLOS topology and/or a full interconnect topology.
The at least one switching chip is used for forwarding the upstream data to the corresponding downstream port according to the destination address of the upstream data sent by any one upstream port and/or forwarding the downstream data to the corresponding upstream port according to the destination address of the downstream data sent by any one downstream port.
In one embodiment, at least one of the switch chips comprises a routing forwarding engine module, wherein the routing forwarding engine module is used for determining a destination address of upstream data sent by any upstream port in the current switch chip and/or a destination address of downstream data sent by any downstream port in the current switch chip according to a routing table.
In one embodiment, at least one switch chip comprises a storage module for storing a routing table, upstream data sent by any upstream port in the current switch chip, and downstream data sent by any downstream port in the current switch chip.
In one embodiment, at least one of the switch chips includes a direct memory access engine module for implementing communication between other resource pools connected to any one of the upstream ports of the current switch chip and hardware resource devices connected to any one of the downstream ports of the current switch chip using a direct memory access (Data Memory Access, also referred to as direct memory access) technique.
In one example, at least one switching chip includes a control logic module including a packet conversion unit, a register unit, and a resource awareness module.
The data packet conversion unit is used for carrying out data format conversion on upstream data sent by any one upstream port in the current exchange chip and/or downstream data sent by any one downstream port in the current exchange chip.
The register unit is used for configuring port information of any upstream port and/or any downstream port in the current exchange chip, wherein the port information comprises port parameters, port attributes and port states.
The resource sensing unit is used for monitoring whether each downstream port in the current switching chip is connected with hardware resource equipment or not and/or monitoring resource use information of the hardware resource equipment connected with the downstream port in the current switching chip, and generating a corresponding resource sensing table.
The data packet conversion unit is used for converting the upstream data sent by any one of the upstream ports in the current exchange chip into a first protocol format and/or converting the upstream data sent by any one of the downstream ports in the current exchange chip into a second protocol format. For example, each downstream port of at least one switch chip supports CCIX protocol (cache consistent interconnection protocol for accelerator), each upstream port of at least one switch chip supports CXL protocol (Compute Express Link, an open interconnection technical standard), and accordingly, the data packet conversion unit is used for converting the upstream data sent by any upstream port in the current switch chip from CXL protocol format to CCIX protocol format, and/or converting the upstream data sent by any downstream port in the current switch chip from CCIX protocol format to CXL protocol format.
Accordingly, the register unit is used for configuring the routing table and the resource perception table. The resource perception table is recorded with parameters such as the residual memory, the maximum bandwidth, the residual computing power and the like of the hardware resource equipment.
Correspondingly, the resource sensing unit is used for updating the resource sensing table in real time according to whether each downstream port obtained by real-time monitoring is connected with the hardware resource equipment and/or the resource use information of the hardware resource equipment.
In one embodiment, any hardware resource device is configured to send idle resource information in itself to the resource sensing unit according to a preset period, and correspondingly, the resource sensing unit updates the resource sensing table according to the information sent by the hardware resource device.
And the resource sensing unit is used for periodically detecting whether the communication links between each upstream port of the current switching chip and the connected resource pool are connected or not, and periodically detecting whether the communication links between each downstream port of the current switching chip and the connected hardware resource equipment are connected or not.
In one embodiment, each upstream port of at least one switch chip is provided with a decoder, and the decoder is used for determining the address mapping relation between the memory of the computing device connected with the upstream port where the current decoder is located and the hardware resource device connected with the downstream port in the current switch chip. In one example, the decoder is configured to store memory capacity information for a computing device to which an upstream port at which the decoder is currently connected.
In one embodiment, at least one of the switch chips includes a cache coherence interface module for providing a cache coherence transport channel between hardware resource devices connected to each of the downstream ports in the current switch chip.
In one embodiment, at least one of the switching chips includes a clock and reset module for maintaining clock synchronization between devices within the system.
In one embodiment, the at least one switching chip further comprises a switching function module. The power management module is used for providing power for the exchange function module and the exchange chips in each resource pool and managing the power consumption of the exchange function module and the exchange chips in each resource pool.
It can be seen that, in this embodiment, different hardware resource devices, such as a memory device, a hardware acceleration device, or a computing device, are incorporated into different resource pools, and at least one upstream port of at least one switch chip in each resource pool is connected to an upstream port of at least one switch chip in another resource pool, so as to implement interconnection between different resource pools, and at least one downstream port of at least one switch chip in each resource pool is connected to a hardware resource device, so that the switch chip forwards upstream data to a corresponding downstream port according to a destination address of upstream data sent by any one upstream port, and/or forwards downstream data to a corresponding upstream port according to a destination address of downstream data sent by any one downstream port, so as to implement intra-system communication. According to the scheme, the interconnection of devices in the system is realized by the number of ports as small as possible, the downstream devices do not need to be connected in pairs, the number of connecting wires and the wiring layout complexity are reduced, the communication delay can be correspondingly reduced, and the communication requirement of low-delay requirement service is met.
The switching chip in the application is a CXL switch chip (hereinafter referred to as a switch for short) of a bus level in a rack, and has a cache consistency maintenance function of CXL in addition to a switching forwarding function. In addition, the connection between any two CXL switch chips is CXL bus.
Referring to fig. 2, the present embodiment adopts a direct connection mode with reference to Dragonfly network (a network topology structure) topology, and divides the whole system into three layers, namely a system layer, a group layer (resource pool layer) and a switch layer. The system layer comprises 4 resource pools, full connection is realized among the 4 resource pools, network interconnectivity and redundancy can be improved, and efficient and reliable data transmission in the whole system is ensured. And the whole system supports resource expansibility, is suitable for the construction of a pooling system, has the maximum number of switch forwarding hops of 3 hops, has the transmission path and the node number superior to the CLOS topology, and has superior time delay performance. The connection lines illustrated in fig. 3 are significantly reduced in routing and deployment difficulties and costs compared to device full interconnect topologies or switch full interconnect topologies.
Fig. 2 shows heterogeneous acceleration resource pools of GPUs and FPGAs, CXL extended memory resource pools of DRAM-based, NVMe SSDs. In practical application, according to the application acceleration scene, the number and the types of the resource pools can be increased appropriately, for example, NPU acceleration calculation resource pools can be added.
The system shown in fig. 2 realizes full interconnection of pooled resources by using limited links, greatly reduces consumption of a plurality of devices, improves energy efficiency ratio and reduces transmission delay, and secondly, deploys resource pools of different types, facilitates management and scheduling of resources, can reasonably layout application calculation force according to the characteristics of different resources, improves acceleration efficiency and improves resource utilization rate.
Specifically, in this embodiment, 3 CXL 3.1 switch chips are configured for each resource pool, supporting switch-to-switch connection. The 1 upstream port in each switch chip is used for interconnection of different resource pools, and 6 PCIe links are totally arranged, and the bidirectional bandwidths are PCIE 4.0 192GB/s and PCIE 5.0 384GB/s. In the resource pool, 2 upstream ports of each switch are used for interconnection of resource devices connected on different switch chips in the same resource pool, and 3 PCIe links can realize full connection of the devices in the resource pool. In FIG. 2, there are 10 interfaces per CXL switch, and in practice there may be more interfaces.
In this embodiment, the number X-Y-Z is used to indicate that the X-th resource pool and the Z-th port on the Y-th switch correspond to the values of 1-4, 1-3 and 1-10 in FIG. 2. The port number 1 of each switch is used for interconnection among resource pools, and a specific port interconnection table is shown in table 1, so as to realize interconnection between 4 pools in pairs. The 3, 4 ports of each switch are used for every two interconnections between 3 switches in the resource pool.
TABLE 1 interconnection between resource pools table
Denoted by X as intra-resource pool links, then the intra-resource pool interconnections are as shown in table 2.
TABLE 2 interconnection table in resource pools
In this example, a total of 6+3×4=18 connection lines are required for the full connection of 12 CXL switch chips, each occupying 3 interfaces. If a full interconnect topology is used for the 12 CXL switch chips, 12×11/2=66 connection lines are required to directly interconnect the 12 switch chips two by two, and the interfaces of each CXL switch are 11. According to the present embodiment, the number of occupied interfaces is relatively small, which also means that a larger-scale system interconnection can be realized in the case where the switch expansion capability is limited. On the basis of the intercommunication and interconnection of all the devices, the scheme greatly reduces the use of connecting wires and the occupation of switch port resources and reduces the wiring difficulty.
In addition, the number of hardware devices connected with the switches, the number of switches in each resource pool and the number of resource pools can be correspondingly expanded according to actual calculation requirements, and the expansion cost of three layers is sequentially increased. By utilizing the memory expansion function of CXL protocol, the device supporting multiple storage media such as DRAM, NVMe SSD is expanded into system memory by CXL bus, and the access delay is far lower than the delay required by RDMA technology accessed by network in traditional separated memory pool.
On the switches in the FPGA and the GPU acceleration computing resource pool, corresponding interfaces are reserved for connecting the NIC network card, so that connection with an Ethernet can be realized, communication across a rack range can be realized, and further expansion of the system scale can be supported.
In addition, the topology of various hardware equipment resources is supported in the resource pool, so that the topology can be compatible with a CLOS topology and a full interconnection topology scheme of DPUs (Data Processing Unit, data processors), and more possibilities are provided for performance improvement and innovation application of the system.
If a link between two resource pools fails to meet the bandwidth requirements, then ports # 2 and # 3 on each switch may be further interconnected to obtain a greater parallel bandwidth. Each switch is guaranteed to have links up to an additional 3 resource pools, as shown in fig. 3. At this time, the maximum hop count of the system is reduced to 2, and the average delay of the system is further reduced while the bandwidth is increased. Accordingly, port connections are as in table 3, requiring a total of 18 links.
TABLE 3 inter-resource pool interconnect table in Bandwidth extended mode
In one example, a switch may be implemented based on a reconfigurable FPAG and enable it to support CXL and PCIe protocols. As shown in fig. 4, the switch includes the following functional modules:
and the routing forwarding engine module is responsible for realizing the routing and forwarding of the data packet, controlling the distribution of traffic and the arbitration management of bus and interface resources, and ensuring the high efficiency and stability of data transmission. The ternary content addressing memory TCAM (ternary content addressable memory) is used for storing and quickly searching entries such as routing table (the effect is that the route searching is quick, the port is stored with communication connection), has high searching efficiency, and can quickly match the destination address of the data packet and determine the next hop path.
An HDM Decoder (Host-MANAGED DEVICE Memory Decoder) is present at each upstream port of the Switch, which maintains the volatile and persistent Memory capacity of the extended Memory, and determines the mapping between Host physical addresses and device physical addresses, and the HDM Decoder in the upstream port determines which downstream port is the target of the Memory access. Resolving an address mapping relationship between a host address and a downstream device address,
The on-chip memory module can adopt an on-chip SRAM memory, has rapid read-write speed and low access delay, and can be used as a memory space for buffering important information such as data packets, forwarding tables, transfer buffers and the like.
And the direct memory access (DMA, direct Memory Access) engine module is used for supporting the DMA high-speed data transmission function and reducing the load of the CPU by directly accessing the memory.
The control logic module is responsible for controlling, managing and configuring the resources and functions of the switch, and specifically comprises the following steps:
1) The data packet conversion unit is responsible for converting the format of the received data packet, for example, converting the data packet from CXL protocol format to CCIX protocol format, or editing and modifying the header information of the data packet, and realizing the functions of cache consistency maintenance and the like. The CCIX protocol is used between acceleration computing devices in the group.
2) The register unit is responsible for realizing the configuration space of the switch equipment and is used for configuring the parameters, the attributes and the states of the ports, the functions of configuring the routing table, the resource perception table parameters and the like.
3) And the resource sensing table is used for monitoring the use condition of the system resources. The resource utilization table can be stored in SDRAM cache on the module, and can read, write and update data quickly, so that the resource utilization condition can be acquired quickly when needed. For example, the memory/computing device sends the idle memory capacity/idle computing unit number to the control logic module in a certain period, and the control logic module configures the resource sensing table after receiving the port resource information, so as to be convenient for dynamically sensing the resource utilization rate. The control logic module can also send signals to the port module according to a preset period, detect whether the links between the port and the external equipment are normal or not, and control whether the physical links are connected or not through the port so as to realize the dynamic conversion of the system connection topology and the monitoring isolation of faults.
And the cache consistency interface module can be connected to a PCIe interface of the main board to provide a data transmission channel with devices such as an accelerator. The system comprises a protocol transmission layer, a link layer and a physical layer, wherein the physical layer is responsible for the initialization and control related functions of a physical link, the link layer is responsible for the control and management of the state of a data link, and the transmission layer is responsible for the encapsulation and decapsulation of a message.
Other supporting modules, such as a clock and reset module, are needed on the switch equipment to provide clock synchronization and reset functions between the equipment and ensure the accuracy of data transmission, and a power management module is responsible for supplying power to each module of the switch and managing the power consumption of the switch equipment.
Meanwhile, the resources of the same type in the pooling belong to redundant equipment, even if one or a plurality of equipment malfunctions, the tasks can be born by the equipment of the same type through the scheduling in the system, and the reliability of the pooling platform is improved.
In summary, the embodiment proposes a hierarchical pooling server system interconnection topology scheme based on CXL 3.1 protocol specification, wherein the first layer is a pooling server, the second layer is a plurality of resource pools, the pools are interconnected and intercommunicated two by two, the third layer is a single switch layer, and is connected with a plurality of heterogeneous acceleration and storage devices, and a plurality of interconnection modes are supported between the devices, for example, the devices are interconnected through CCIX and other protocols. The interconnection topology not only reduces the complexity of system connection, but also can realize interconnection and intercommunication among devices in all resource pools only by small hops. The interconnection architecture can realize low-delay consistent access of CPU and accelerator heterogeneous computing resources to host memory and extended memory resources in the whole server system, and support large-scale extension of pooled resources and management and maintenance of resource pooling. The scheme also supports a bandwidth expansion mode, realizes a scheme of interconnection with more links and higher bandwidth between resource pools, has good system flexibility, can flexibly configure and adjust the links according to specific requirements, and ensures that each switch is directly connected with other resource pools by links, so that the interconnection between the resource pools has redundant paths, and the reliability and fault tolerance of the server system are improved. In addition, the switch equipment is internally provided with a resource sensing unit and related control logic to support dynamic sensing of pooled resource utilization conditions, and the control logic module supports dynamic configuration of port links, so that dynamic adjustment of system topology can be realized, and fault isolation can be supported while the system topology flexibility is improved.
The pooling server interconnection topology scheme provided by the embodiment can realize high-bandwidth low-delay interconnection in a high-power server system, and further can be connected to a network through devices such as a network card and the like to support interconnection with a larger range and a higher level. The topology interconnection scheme not only simplifies the system deployment, but also reduces the cost and the power consumption, and is suitable for being applied to a data center.
The following describes a device interconnection method provided in an embodiment of the present application, and the device interconnection method described below may refer to other embodiments described herein.
The embodiment of the application discloses a device interconnection method which is applied to the device interconnection system in any embodiment, and comprises the steps of enabling at least one upstream port of at least one switching chip in a current resource pool to be connected with the upstream port of at least one switching chip in other resource pools, enabling at least one downstream port of at least one switching chip in the current resource pool to be connected with hardware resource equipment, and enabling at least one upstream port of at least one switching chip in the current resource pool to be connected with the upstream port of other switching chips in the current resource pool.
The device interconnection system comprises at least two resource pools, wherein each resource pool comprises at least one exchange chip, and hardware resource devices in the same resource pool are memory devices, hardware acceleration devices or computing devices, and the hardware resource devices in different resource pools are different;
The at least one switching chip is used for forwarding the upstream data to the corresponding downstream port according to the destination address of the upstream data sent by any one upstream port and/or forwarding the downstream data to the corresponding upstream port according to the destination address of the downstream data sent by any one downstream port.
In one embodiment, at least one of the switch chips comprises a routing forwarding engine module, wherein the routing forwarding engine module is used for determining a destination address of upstream data sent by any upstream port in the current switch chip and/or a destination address of downstream data sent by any downstream port in the current switch chip according to a routing table.
In one embodiment, at least one switch chip comprises a storage module for storing a routing table, upstream data sent by any upstream port in the current switch chip, and downstream data sent by any downstream port in the current switch chip.
In one embodiment, at least one switching chip comprises a direct memory access engine module, wherein the direct memory access engine module is used for realizing communication between other resource pools connected with any one upstream port in the current switching chip and hardware resource devices connected with any one downstream port in the current switching chip by using a direct memory access technology.
In one embodiment, at least one switching chip comprises a control logic module, wherein the control logic module comprises a data packet conversion unit, a register unit and a resource sensing module.
The data packet conversion unit is used for carrying out data format conversion on upstream data sent by any one upstream port in the current exchange chip and/or downstream data sent by any one downstream port in the current exchange chip.
The register unit is used for configuring port information of any upstream port and/or any downstream port in the current exchange chip, wherein the port information comprises port parameters, port attributes and port states.
The resource sensing unit is used for monitoring whether each downstream port in the current switching chip is connected with hardware resource equipment or not and/or monitoring resource use information of the hardware resource equipment connected with the downstream port in the current switching chip, and generating a corresponding resource sensing table.
In one embodiment, each downstream port of at least one switch chip supports CCIX protocol, each upstream port of at least one switch chip supports CXL protocol, and correspondingly, the data packet conversion unit is used for converting the upstream data sent by any upstream port in the current switch chip from CXL protocol format to CCIX protocol format and/or converting the upstream data sent by any downstream port in the current switch chip from CCIX protocol format to CXL protocol format.
In one embodiment, the register unit is used to configure a routing table and a resource aware table.
In one embodiment, the resource sensing unit is configured to update the resource sensing table in real time according to whether each downstream port obtained by real-time monitoring is connected with a hardware resource device and/or resource usage information of the hardware resource device.
In one embodiment, any hardware resource device is configured to send idle resource information in itself to the resource sensing unit according to a preset period, and correspondingly, the resource sensing unit updates the resource sensing table according to the information sent by the hardware resource device.
In one embodiment, the resource sensing unit is used for periodically detecting whether the communication links between each upstream port of the current switching chip and the connected resource pool are connected or not, and periodically detecting whether the communication links between each downstream port of the current switching chip and the connected hardware resource device are connected or not.
In one embodiment, each upstream port of at least one switch chip is provided with a decoder, and the decoder is used for determining the address mapping relation between the memory of the computing device connected with the upstream port where the current decoder is located and the hardware resource device connected with the downstream port in the current switch chip.
In one embodiment, the decoder is configured to store memory capacity information for a computing device to which the upstream port at which the decoder is currently connected.
In one embodiment, at least one of the switch chips includes a cache coherence interface module for providing a cache coherence transport channel between hardware resource devices connected to each of the downstream ports in the current switch chip.
In one embodiment, at least one of the switching chips includes a clock and reset module for maintaining clock synchronization between devices within the system.
In one embodiment, the at least one switching chip further comprises a switching function module.
In one embodiment, at least one of the switch chips includes a power management module for providing power to the switch and the switch chips in each of the resource pools and for managing power consumption of the switch and the switch chips in each of the resource pools.
In one embodiment, each hardware resource device in each resource pool supports a CLOS topology and/or a full interconnect topology.
The more specific working process of each module and unit in this embodiment may refer to the corresponding content disclosed in the foregoing embodiment, and will not be described herein.
It can be seen that this embodiment provides a device interconnection method, which implements interconnection of devices in a system with the smallest possible number of ports, and the downstream devices do not need to be connected two by two, so that the number of connection lines and the complexity of wiring layout are reduced, the communication delay can be correspondingly reduced, and the communication requirement of low-delay requirement service is satisfied.
An electronic device provided in the embodiments of the present application is described below, and an electronic device described below may refer to other embodiments described herein. The electronic device may be any functional module of the aforementioned system.
Referring to fig. 5, an embodiment of the present application discloses an electronic device, including:
A memory 501 for storing a computer program;
A processor 502 for executing the computer program to implement the method disclosed in any of the embodiments above.
In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented, where the upstream data is forwarded to the corresponding downstream port according to the destination address of the upstream data sent by any one of the upstream ports, and/or the downstream data is forwarded to the corresponding upstream port according to the destination address of the downstream data sent by any one of the downstream ports.
In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented, where the destination address of the upstream data sent by any upstream port in the current switch chip and/or the destination address of the downstream data sent by any downstream port in the current switch chip are determined according to the routing table.
In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented, where the routing table, the upstream data sent by any upstream port in the current switch chip, and the downstream data sent by any downstream port in the current switch chip are stored.
In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented, where the direct memory access technology is used to implement communications between any one of the upstream ports in the current switch chip and any one of the downstream ports in the current switch chip connected to the hardware resource devices.
In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented, where data format conversion is performed on upstream data sent by any one of the upstream ports in the current switch chip and/or downstream data sent by any one of the downstream ports in the current switch chip.
In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented, where the port information includes a port parameter, a port attribute, and a port state, and the port information configures any upstream port and/or any downstream port in the current switch chip.
In this embodiment, when the processor executes the computer program stored in the memory, the steps of monitoring whether each downstream port in the current switch chip is connected with a hardware resource device and/or monitoring resource usage information of the hardware resource device connected to the downstream port in the current switch chip, and generating a corresponding resource awareness table may be specifically implemented.
In this embodiment, when executing the computer program stored in the memory, the processor may specifically implement the steps of converting the upstream data sent by any one of the upstream ports in the current switch chip from the CXL protocol format to the CCIX protocol format, and/or converting the upstream data sent by any one of the downstream ports in the current switch chip from the CCIX protocol format to the CXL protocol format.
In this embodiment, the processor may implement the steps of configuring the routing table and the resource awareness table when executing the computer program stored in the memory.
In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented, where the resource awareness table is updated in real time according to whether each downstream port obtained by real-time monitoring is connected with a hardware resource device and/or resource usage information of the hardware resource device.
In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented, where the idle resource information in the processor is sent to the resource sensing unit according to a preset period, and correspondingly, the following steps may also be specifically implemented, where the resource sensing table is updated according to the information sent by the hardware resource device.
In this embodiment, when the processor executes the computer program stored in the memory, the steps of periodically detecting whether the communication link between each upstream port of the current switching chip and the connected resource pool is connected, and periodically detecting whether the communication link between each downstream port of the current switching chip and the connected hardware resource device is connected may be specifically implemented.
In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented, where the address mapping relationship between the memory of the computing device connected to the upstream port where the current decoder is located and the hardware resource device connected to the downstream port in the current switch chip is determined.
In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented to store memory capacity information of the computing device connected to the upstream port where the current decoder is located.
In this embodiment, when the processor executes the computer program stored in the memory, the steps of providing a cache consistency transmission channel between the hardware resource devices connected to each downstream port in the current switch chip may be specifically implemented.
In this embodiment, the processor, when executing the computer program stored in the memory, may specifically implement the step of maintaining clock synchronization between devices within the system.
In this embodiment, when the processor executes the computer program stored in the memory, the steps of providing power to the switch and the switch chips in each resource pool and managing power consumption of the switch and the switch chips in each resource pool may be specifically implemented.
Further, the embodiment of the application also provides electronic equipment. The electronic device may be a server as shown in fig. 6 or a terminal as shown in fig. 7. Fig. 6 and 7 are structural diagrams of electronic devices according to an exemplary embodiment, and the contents of the drawings should not be construed as any limitation on the scope of use of the present application.
Fig. 6 is a schematic structural diagram of a server according to an embodiment of the present application. The server may include at least one processor, at least one memory, a power supply, a communication interface, an input-output interface, and a communication bus. The memory is used for storing a computer program, and the computer program is loaded and executed by the processor to implement relevant steps in the device interconnection disclosed in any of the foregoing embodiments.
In this embodiment, the power supply is configured to provide working voltages for each hardware device on the server, the communication interface is capable of creating a data transmission channel with an external device for the server, a communication protocol to which the communication interface conforms is any communication protocol applicable to the technical scheme of the present application, and is not specifically limited herein, and the input/output interface is configured to obtain external input data or output data to the outside, where a specific interface type of the input/output interface may be selected according to a specific application requirement, and is not specifically limited herein.
In addition, the memory may be a read-only memory, a random access memory, a magnetic disk, an optical disk, or the like as a carrier for storing resources, where the resources stored include an operating system, a computer program, data, and the like, and the storage mode may be transient storage or permanent storage.
The operating system is used for managing and controlling each hardware device and computer program on the Server to realize the operation and processing of the processor on the data in the memory, and the operation and processing can be Windows Server, netware, unix, linux and the like. The computer program may further comprise a computer program capable of performing other specific tasks in addition to the computer program capable of performing the device interconnection method disclosed in any of the foregoing embodiments. The data may include data such as information on a developer of the application program in addition to data such as update information of the application program.
Fig. 7 is a schematic structural diagram of a terminal according to an embodiment of the present application, where the terminal may specifically include, but is not limited to, a smart phone, a tablet computer, a notebook computer, a desktop computer, or the like.
In general, the terminal in this embodiment includes a processor and a memory.
The processor may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor may be implemented in at least one hardware form of DSP (DIGITAL SIGNAL Processing), FPGA (Field-Programmable gate array), PLA (Programmable Logic Array ). The processor may also include a main processor, which is a processor for processing data in a wake-up state, also called a CPU (Central Processing Unit ), and a coprocessor, which is a low-power processor for processing data in a standby state. In some embodiments, the processor may incorporate a GPU (Graphics Processing Unit, image processor) for rendering and rendering of content to be displayed by the display screen. In some embodiments, the processor may also include an AI (ARTIFICIAL INTELLIGENCE ) processor for processing computing operations related to machine learning.
The memory may include one or more computer non-volatile storage media, which may be non-transitory. The memory may also include high-speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In this embodiment, the memory is at least configured to store a computer program, where the computer program, when loaded and executed by the processor, is capable of implementing relevant steps in the device interconnection method performed by the terminal side as disclosed in any one of the foregoing embodiments. In addition, the resources stored in the memory can also comprise an operating system, data and the like, and the storage mode can be short-term storage or permanent storage. The operating system may include Windows, unix, linux, among other things. The data may include, but is not limited to, update information for the application.
In some embodiments, the terminal may further include a display screen, an input-output interface, a communication interface, a sensor, a power supply, and a communication bus.
Those skilled in the art will appreciate that the structure shown in fig. 7 is not limiting of the terminal and may include more or fewer components than shown.
A non-volatile storage medium according to an embodiment of the present application is described below, and the non-volatile storage medium described below and other embodiments described herein may be referred to with reference to each other.
A non-volatile storage medium for storing a computer program which, when executed by a processor, implements the device interconnection method disclosed in the foregoing embodiments. The nonvolatile storage medium is a computer readable nonvolatile storage medium, and can be read-only memory, random access memory, magnetic disk or optical disk, etc. as a carrier for storing resources, and the resources stored on the nonvolatile storage medium include an operating system, a computer program, data, etc., and the storage mode can be transient storage or permanent storage.
A computer program product provided by embodiments of the present application is described below, and the computer program product described below may be referred to with respect to other embodiments described herein.
A computer program product comprising computer programs/instructions which when executed by a processor implement the steps of the device interconnection method disclosed previously.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, so that the same or similar parts between the embodiments are referred to each other.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software modules may be disposed in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of non-volatile storage medium known in the art.
While the principles and embodiments of the present application have been described in detail in this application, the foregoing embodiments are provided to facilitate understanding of the principles and concepts of the application and are further provided by one of ordinary skill in the art to which the application pertains.