Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Electronic fuses (eFuses) are a programmable fuse technology commonly used in integrated circuit design and can be used for storing information and protecting chips, and electronic fuses have wide application in integrated circuits, including chip protection, power management, circuit calibration, and storing key information. The repair information of the memory, the chip identification, the security identity authentication information and the like need to be stored in the electronic fuse, wherein the repair information of the memory is stored in the electronic fuse in the test stage of the ATE (Automatic Test Equipment ), and the identity authentication information may need to be written by a user to access the electronic fuse. The data storage of the electronic fuse in different scenes may need to be realized through different types of bus interfaces, and when multiple scenes exist, efficient data storage from the multiple interfaces is a problem to be solved. Based on the above, the embodiment of the invention provides an electronic fuse control method, which is applied to an electronic fuse controller, wherein the electronic fuse controller is deployed in a chip.
In accordance with an embodiment of the present invention, an electronic fuse control method embodiment is provided, it being noted that the steps illustrated in the flowchart of the figures may be performed in a computer system, such as a set of computer executable instructions, and, although a logical sequence is illustrated in the flowchart, in some cases, the steps illustrated or described may be performed in a different order than what is illustrated herein.
In this embodiment, an electronic fuse control method is provided and applied to a controller, and fig. 1 is a flowchart of the electronic fuse control method according to an embodiment of the present invention, as shown in fig. 1, where the flowchart includes the following steps:
step S101, a control instruction is received.
The embodiment is applied to an electronic fuse controller (eFuse controller for short), wherein the controller is arranged on a chip and can receive control instructions sent by different sending objects, and the sending objects of the control instructions at least comprise one type. Different transmission objects can transmit control instructions to the controller by adopting corresponding bus interfaces. Corresponding to different scenes, the control instruction can include performing data programming and data verification on the electronic fuse In a MBIST (Memory Built-In Self-Test) Test stage, and also performing data programming and data verification on the electronic fuse In a chip use stage.
In some alternative embodiments, the transmission object of the control instruction includes at least a JTAG register and an APB register.
JTAG (Joint Test Action Group ) is an international standard test protocol, JTAG is mainly used for testing and debugging chips, and access and control of registers inside the chips are realized through specific interfaces and protocols. JTAG registers are a core component in JTAG technology.
In integrated circuit designs, particularly for large-scale memory arrays (e.g., SRAM, DRAM, etc.), there may be some defects due to process imperfections, resulting in some memory cells not functioning properly. For this purpose, memory repair mechanisms are introduced, including detecting defective cells in the memory, replacing the defective cells with redundant rows or columns, thereby restoring the integrity and functionality of the memory. The repaired interface sequence is related to the specific tool, and the access sequence can be implemented through JTAG interface configuration. The JTAG register can access the controller through a JTAG interface, and the controller receives a control instruction sent by the JTAG register through the JTAG interface.
In integrated circuit designs and applications, identity authentication information and similar security keys may be used to ensure the security of devices, authenticate legitimate users or devices, prevent unauthorized access, etc. The user may store sensitive information by programming the configured eFuses. In this embodiment, a control instruction sent by an APB (ADVANCED PERIPHERAL Bus, advanced peripheral interface) register is received through the APB, so as to perform operations of programming and comparison and peer-to-peer.
Step S102, when the control instruction is a programming instruction, the control instruction is analyzed, and a first target register array in the control instruction is determined.
The ELD (eFuse Local Dispatcher, local scheduler) consists of a plurality of register arrays, each of which is pre-configured with data to be programmed. After receiving the control instruction, analyzing the control instruction, and determining the specific content of the control instruction. When the control instruction is a programming instruction, the programming instruction includes a register array to which data to be programmed belongs, i.e. a target register array.
Step S103, based on the address of the pre-stored register array, the data to be programmed of the first target register array is programmed to the electronic fuse.
The controller stores the address corresponding to each target register array in the electronic fuse in advance, namely the address of the register array, wherein the address comprises the initial bit address of the data of the first target register array and the position of the highest bit address in the electronic fuse, and the address can also comprise the initial bit address and the length of the data to be programmed of the target register array. Therefore, the storage position of the data to be programmed of the first target register array in the electronic fuse can be determined according to the address of the pre-stored register array. The controller may be coupled to a module in which the plurality of destination registers are located. One programming instruction may specify programming one or more target register arrays, and in the electronic fuse, there are multiple storage areas, where each storage area corresponds to a different target register array, and may store data of the different target register arrays. Based on the address of the pre-stored register array, the data to be programmed of the first target register array can be programmed to the electronic fuse. It should be noted that the electronic fuse in this embodiment may also employ other units having similar functions, such as One-Time Programmable (OTP) devices.
The electronic fuse control method provided by the embodiment is applied to a controller, the controller receives a control instruction, a sending object of the control instruction at least comprises one type, and when the control instruction is a programming instruction, the control instruction is analyzed, so that a first target register array is determined; and according to the address of the pre-stored register array, the data to be programmed of the first target register array is programmed to the electronic fuse. According to the method provided by the embodiment, the controller can acquire the instructions sent by the plurality of sending objects, correspondingly, the controller can be compatible with the data sent by the plurality of interfaces, different interfaces can be used in different control scenes, and the control efficiency of the electronic fuse is further improved by improving the reusability of the controller. Different target storage areas are arranged in the electronic fuses, and when the electronic fuses are programmed, the addresses of the register arrays are pre-stored, the data to be programmed of the target register arrays are mapped to the target storage areas, so that the storage areas of one or more electronic fuses are accessed through control instructions, and the access efficiency to the electronic fuses is improved.
In some alternative embodiments, the method further comprises:
Step S201, receiving a mode control instruction;
step S202, when the mode control instruction corresponds to the test scene, receiving a specified control instruction sent by a specified sending object, and executing the specified control instruction.
Wherein the designated transmission object corresponds to the test scene. The scene corresponding to the control instruction can be determined by the sending object of the control instruction, the test scene refers to the scene of testing Mbist and the like by ATE, the control instruction in the scene realizes instruction transmission through a JTAG interface, and the corresponding sending object is a JTAG register. In this embodiment, the transmission object is designated as a JTAG register, and the control instruction is designated as a control instruction issued by the JTAG register.
Specifically, a mode control device (e.g., a mode control register) is provided in the JTAG register, and is used for controlling whether the controller needs to be in a test mode, wherein the test mode of the controller is applied to a test scene. When the test mode is needed, the JATG register sends a mode control instruction to the controller through the mode control device, and the controller receives the mode control instruction sent by JTAG and adjusts the mode control instruction to the test mode. When the controller is in the test mode, the controller only receives the specified control instruction sent by the JATG register and executes the specified control instruction, and the specified control instruction can include a programming instruction, a reading instruction, a comparison instruction and the like.
In some alternative embodiments, step S103 in the above embodiments includes the following steps:
In step S301, a target storage area of the data to be programmed of the first target register array in the electronic fuse is determined based on the address of the pre-stored register array.
The position of the start bit address and the highest bit address of the data of the first target register array in the electronic fuse is obtained from the addresses of the pre-stored register arrays, and the position of the start bit address and the highest bit address of the data of the first target register array in the electronic fuse can also comprise the length of the data to be programmed of the start bit address and the target register array. The target storage areas in the electronic fuse can be determined according to the addresses of the pre-stored register arrays, and the target storage areas in the electronic fuse are in one-to-one correspondence with the first target register array. In an exemplary embodiment, when the address of the first target register array includes a position of a start bit address and a highest bit address of data of the first target register array in the electronic fuse, a target storage area corresponding to the first target register array is determined according to the start bit address and the highest bit address, and the data to be programmed is programmed into the target storage area. When the controller receives the programming instruction, the start bit address of the first target register array in the electronic fuse is loaded into an address accumulation register (counting unit).
Step S302, the data bits of the data to be programmed in the first target register array are sequentially read, and the data bits are judged to obtain a judgment result.
After the controller determines the first target register array, each data bit in the first target register array is sequentially read, and after the data bit is read, the state of the data bit is judged, so that a judgment result of the state of the data bit is obtained.
Specifically, step S302 includes the steps of:
step S3021, sequentially reading data bits in the target register array;
in step S3022, it is determined whether the data bit is the first data bit, and a determination result is obtained.
In this embodiment, the first data bit indicates that the data bit is 1, and the non-first data bit indicates that the data bit is 0.
Step S303, based on the judgment result, the data to be programmed is programmed to the target storage area of the electronic fuse in sequence.
Specifically, step S303 includes the steps of:
In step S3031, when the data bit is the first data bit, the write access requirement and the address signal are sent to the read-write conversion module, so that the read-write conversion module writes the data to be written corresponding to the data bit to the electronic fuse based on the write access requirement and the address signal.
The read-write conversion module is connected with the electronic fuse and the controller. The read-write conversion module is arranged between the electronic fuse and the controller and is used for converting the instruction into an access time sequence matched with the electronic fuse.
The controller reads each bit of data of the first target register array through a serial interface between the controller and the first target register array, the data bit is 1, the controller sends a programming access requirement and an address signal to the read-write conversion module, and the read-write conversion module sends a control signal to the electronic fuse for data programming according to the specific time sequence requirement of the electronic fuse after receiving the programming access requirement and the address signal. After the programming is completed, a handshake signal is sent to the controller, meanwhile, a counter in the controller is increased by 1, the first target register array moves to the next bit, and the next bit of data to be programmed is sent through a serial interface between the first target register array and the controller.
In step S3032, the next data bit is read when the data bit is the second data bit.
When the data bit is 0, the next data bit in the first target register array is read without data programming.
In step S3033, the data bit is the first data bit or the second data bit, and the counting is performed in the counting unit.
After each bit of data is read or read and programmed, the counting unit is increased by 1, so that the next data bit of the first target register array is continuously read. And repeating the shifting, judging and programming processes until the value in the counting unit is the same as the address of the highest data bit in the first target register array, which means that all the data bits in the first target register array are processed and programming is completed. In some alternative embodiments, the method further comprises the steps of:
in step S401, when the control instruction is a verification instruction, based on the verification instruction, data corresponding to the second target register array is read from the electronic fuse, and desired data is read from the second target register array.
After the data is programmed, the controller may receive a verification instruction, where the verification instruction is executed after the programming instruction is executed. Is used for verifying whether all the data are successfully written.
The programmed data corresponds to the second target register array, and since the serial data input of the second target register array in the programming instruction is from the corresponding serial data output port, the data of the second target register array is not changed after the data programming is completed, and the data (i.e. the desired data) which is desired to be programmed is still stored. If verification is required, the controller shifts out the expected data in the second target register array, and reads the programmed data from the electronic fuse.
In step S402, the desired data and the data of the second target register array are xored, and the result of writing the data of the second target register array is determined based on the result of the xored.
And performing exclusive OR operation on the expected data and the data of the second target register array, judging whether the data of the second target register array is consistent with the expected data or not through the exclusive OR operation, and if so, indicating that the writing result of the data of the second target register array is successful.
When the comparison is specifically carried out, each bit of data can be compared, and if the compared data bits are different, the result is 1; if the same, the result is 0.
The present embodiment provides an electronic fuse control device, including: the electronic fuse device comprises a controller, at least one sending object, an electronic fuse module and a register array unit, wherein the controller is used for executing the method of the embodiment and the implementation mode, the sending object is connected with the controller, the electronic fuse module is connected with the controller, and the register array unit is connected with the controller.
Illustratively, FIG. 2 is a chip under test C1, C1.1 is a controller (eFuse controller), the transmitting object includes JTAG registers (C1.2) and APB registers (C1.3), the electronic fuse module includes Efuse (C1.9) and a read-write converting unit (C1.8), and the register array unit includes module A, module B and module C. The controller C1.1 may be configured to receive instructions from either C1.2 (JTAG register) or C1.3 (APB register), and perform instruction decoding and allocate ELDs (register arrays) to work in conjunction with eFuses (electronic fuses). The JTAG register is provided with a test mode configuration register which is used for sending a mode control instruction to the controller so as to enable the controller to enter a test mode. The controller in test mode only receives control instructions from the JTAG register. When the controller is in the non-test mode, control instructions issued by the APB register may be received. The receivable control instructions comprise programming, reading, comparison verification and register array clearing.
The CPU module (C1.4) is a functional control unit of the chip, accesses the controller through the APB register and the interface i0, can send a control instruction to the controller by accessing the APB register, and can collect the state of the electronic fuse after executing the control instruction. In the figure, the module A and the module B respectively comprise a register array unit (ELD 1, ELD 2), an APB register and an APB interface i7, and the CPU module can access the APB register in the module A or the module B through the i0 interface, thereby controlling or sampling the parallel input or output data of the register array unit.
The APB registers in module a and module B may be used to bridge CPU access to ELD parallel input-output ports. The method can provide programmed parallel input data for the ELD, namely the expected programmed data of the corresponding area in the electronic fuse, and also can be used for reading the output data of the ELD through the APB after the eFuse data are transmitted to the ELD, so that a data channel is provided for the CPU to write and read the eFuse data. The controller can store the data in the electronic fuse in the ELD through the serial interface i5 and embody the data on the parallel output port of the electronic fuse, can firstly place the data to be programmed on the ELD parallel input port through the APB register, then send the programming instruction to the eFuse controller through the JTAG register (C1.2) or the APB register (C1.3), and can store the data in the eFuse IP and the internal register of the ELD after the eFuse controller analyzes the instruction. After the programming instruction is executed, a verification instruction can be sent, and the eFuse controller can compare the ELD with data read out from the electronic fuse and return to the state, so that the programming condition can be quickly confirmed.
The ELD3 unit in module C is used to store repair information for SRAM (static random access memory) in the eFuse, and the module C includes a serial interface i5 and an access interface i6, where the access interface i6 is defined by Mbist tools. The BISR (Memory Built-IN SELF REPAIR, in-memory self-repair) controller in the module C is used for decompressing the SRAM repair information in the ELD and transferring the decompressed SRAM repair information to the SRAM port with repair logic.
In the figure, an interface i0 is a general APB interface, and an interface i1 is an eFuse controller instruction interface, comprises a command, a valid identification bit, an ELD enable bit and a command execution completion identification signal. Interface i2 controls the test mode enable signal by the JTAG register. Interface i3 is a read and write command interface sent by the eFuse controller to the eFuses. Interface i4 is an interface signal for eFuses. The interface i5 is a serial interface for communication between the ELD and the eFuse controller, and adopts an IEEE1687 protocol, so that data in the electronic fuse can be moved to the ELD in a shifting state, the data are represented on a parallel output port when the shifting state is finished, and parallel input data of the ELD can be burnt to the electronic fuse through the serial interface, so that the solid storage of the data is finished. The interface i6 is an interface between the ELD and the BISR controller, and can complete the storage of the SRAM repair information to the ELD and the conversion from the eFuse to the ELD and to the SRAM port after the repair information is solidified. The interface i7 is a parallel input/output interface between the ELD and the APB register, so that the CPU can access the parallel port of the ELD through the APB bus.
When testing is needed, the ATE (or a testing terminal) runs testing software, and the testing software is communicated with a chip testing network through testing authentication, so that the controller is in a testing mode. And after receiving the instruction, the controller executes operations such as programming, verification and the like.
According to the method provided by the embodiment of the invention, the test requirements and the functional requirements are fused together through the multiplexing controller, so that various use scenes can be dealt with, various port accesses are supported, the electronic fuse is controlled, and the flexibility of accessing the electronic fuse is improved. The data in the electronic fuses are mapped into a plurality of ELDs (register array units), the size of each ELD can be defined autonomously, whether the corresponding electronic fuse is accessed or not is controlled by changing an ELD enabling signal on an interface, and the flexibility of instructions is improved. And packaging the access logic related to the electronic fuse, so that the external interface of the controller is decoupled from the time sequence interface of the electronic fuse, the reusability among different projects is improved, and the development progress of other interface parts of the projects is accelerated. ELDs that store repair information may enable the use of a variety of third party Mbist tools quickly.
In this embodiment, an electronic fuse control device is further provided, and the device is used to implement the foregoing embodiments and preferred embodiments, and will not be described in detail. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. While the means described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.
The present embodiment provides an electronic fuse control apparatus, as shown in fig. 3, including:
the instruction receiving module 501 is configured to receive a control instruction, where a transmission object of the control instruction includes at least one kind of control instruction;
The instruction parsing module 502 is configured to parse the control instruction when the control instruction is a programming instruction, and determine a first target register array in the control instruction;
The data writing module 503 is configured to write the data to be written of the first target register array to the electronic fuse based on the address of the pre-stored register array.
In some alternative embodiments, the transmission object of the control instruction includes at least a JTAG register and an APB register.
In some alternative embodiments, the data programming module 503 includes:
The storage area determining unit is used for determining a target storage area of the data to be programmed of the first target register array in the electronic fuse based on the address of the pre-stored register array;
the data judging unit is used for sequentially reading data bits of data to be programmed in the first target register array, judging the data bits and obtaining a judging result;
And the programming unit is used for sequentially programming the data to be programmed to the target storage area of the electronic fuse based on the judgment result.
In some alternative embodiments, the data determination unit includes:
a reading subunit, configured to sequentially read data bits in the target register array;
and the judging subunit is used for judging whether the data bit is the first data bit or not to obtain a judging result.
In some alternative embodiments, the programming unit includes:
the first programming subunit is used for sending programming access requirements and address signals to the read-write conversion module when the data bit is the first data bit, so that the read-write conversion module writes data to be programmed corresponding to the data bit to the electronic fuse based on the programming access requirements and the address signals, and the read-write conversion module is arranged between the electronic fuse and the controller;
A second reading subunit, configured to read a next data bit when the data bit is the second data bit;
and the counting subunit is used for counting in the counting unit when the data bit is the first data bit or the second data bit.
In some alternative embodiments, the apparatus further comprises:
the mode control instruction receiving module is used for receiving a mode control instruction;
and the appointed instruction execution module is used for receiving the appointed control instruction sent by the appointed sending object when the mode control instruction corresponds to the test scene, and executing the appointed control instruction, wherein the appointed sending object corresponds to the test scene.
In some alternative embodiments, the apparatus further comprises:
The verification reading module is used for reading data corresponding to the second target register array from the electronic fuse based on the verification instruction when the control instruction is the verification instruction, and reading expected data from the second target register array;
And the comparison module is used for performing exclusive-or operation on the expected data and the data of the second target register array, and determining the programming result of the data corresponding to the second target register array based on the result of the exclusive-or operation.
Further functional descriptions of the above respective modules and units are the same as those of the above corresponding embodiments, and are not repeated here.
The electronic fuse control device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application SPECIFIC INTEGRATED Circuit) Circuit, a processor and memory that execute one or more software or firmware programs, and/or other devices that can provide the above-described functionality.
The embodiment of the invention also provides computer equipment, which is provided with the electronic fuse control device.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a computer device according to an alternative embodiment of the present invention, as shown in fig. 4, the computer device includes: one or more processors 10, memory 20, and interfaces for connecting the various components, including high-speed interfaces and low-speed interfaces. The various components are communicatively coupled to each other using different buses and may be mounted on a common motherboard or in other manners as desired. The processor may process instructions executing within the computer device, including instructions stored in or on memory to display graphical information of the GUI on an external input/output device, such as a display device coupled to the interface. In some alternative embodiments, multiple processors and/or multiple buses may be used, if desired, along with multiple memories and multiple memories. Also, multiple computer devices may be connected, each providing a portion of the necessary operations (e.g., as a server array, a set of blade servers, or a multiprocessor system). One processor 10 is illustrated in fig. 4.
The processor 10 may be a central processor, a network processor, or a combination thereof. The processor 10 may further include a hardware chip, among others. The hardware chip may be an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general-purpose array logic, or any combination thereof.
Wherein the memory 20 stores instructions executable by the at least one processor 10 to cause the at least one processor 10 to perform the methods shown in implementing the above embodiments.
The memory 20 may include a storage program area that may store an operating system, at least one application program required for functions, and a storage data area; the storage data area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, memory 20 may optionally include memory located remotely from processor 10, which may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
Memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk, or solid state disk; the memory 20 may also comprise a combination of the above types of memories.
The computer device also includes a communication interface 30 for the computer device to communicate with other devices or communication networks.
The embodiments of the present invention also provide a computer readable storage medium, and the method according to the embodiments of the present invention described above may be implemented in hardware, firmware, or as a computer code which may be recorded on a storage medium, or as original stored in a remote storage medium or a non-transitory machine readable storage medium downloaded through a network and to be stored in a local storage medium, so that the method described herein may be stored on such software process on a storage medium using a general purpose computer, a special purpose processor, or programmable or special purpose hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, a solid state disk or the like; further, the storage medium may also comprise a combination of memories of the kind described above. It will be appreciated that a computer, processor, microprocessor controller or programmable hardware includes a storage element that can store or receive software or computer code that, when accessed and executed by the computer, processor or hardware, implements the methods illustrated by the above embodiments.
Portions of the present invention may be implemented as a computer program product, such as computer program instructions, which when executed by a computer, may invoke or provide methods and/or aspects in accordance with the present invention by way of operation of the computer. Those skilled in the art will appreciate that the form of computer program instructions present in a computer readable medium includes, but is not limited to, source files, executable files, installation package files, etc., and accordingly, the manner in which the computer program instructions are executed by a computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Herein, a computer-readable medium may be any available computer-readable storage medium or communication medium that can be accessed by a computer.
Although embodiments of the present invention have been described in connection with the accompanying drawings, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope of the invention as defined by the appended claims.