技术领域Technical Field
本发明涉及半导体技术领域，具体涉及一种浮栅结构的制备方法、浮栅结构及闪存器件。The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a floating gate structure, a floating gate structure and a flash memory device.
背景技术Background Art
闪存(Flash)是一种长寿命的非易失性存储器，因其具有集成度高、存取速度快、易于擦除和重写等优点，而被广泛应用在移动通讯、数据处理、智能终端、嵌入式系统等高新技术产业中，如个人电脑及其外部设备、汽车电子、网络交换机、互联网设备和仪器仪表等。Flash memory is a long-life non-volatile memory. Due to its advantages such as high integration, fast access speed, easy erasure and rewriting, it is widely used in high-tech industries such as mobile communications, data processing, smart terminals, embedded systems, such as personal computers and their peripherals, automotive electronics, network switches, Internet equipment and instrumentation.
浮栅（Floating Gate，FG）是闪存器件中用于存储电荷的关键结构，其性能直接影响到器件的数据保持能力、读写速度和可靠性。随着集成电路制造技术的不断发展，闪存的尺寸不断缩小，闪存中浮栅的关键尺寸也在逐渐缩小，这为形成浮栅带来了挑战。The floating gate (FG) is a key structure for storing charge in flash memory devices. Its performance directly affects the device's data retention, read/write speed, and reliability. With the continuous development of integrated circuit manufacturing technology, the size of flash memory continues to shrink, and the key size of the floating gate in flash memory is also gradually shrinking, which brings challenges to the formation of the floating gate.
目前，浮栅的形成工艺中，需要去除掩模层形成间隙以进行浮栅的填充，而掩膜层去除后容易形成纵向截面为上窄下宽的梯形间隙，这种梯形间隙的开口较小，较高的深宽比和较小的填充开口使得填充浮栅中间容易形成空洞，进而降低产品的良率。At present, in the process of forming a floating gate, it is necessary to remove the mask layer to form a gap for filling the floating gate. After the mask layer is removed, a trapezoidal gap with a narrow top and wide bottom longitudinal cross-section is easily formed. The opening of this trapezoidal gap is small, and the high aspect ratio and small filling opening make it easy to form a void in the middle of the filled floating gate, thereby reducing the yield of the product.
发明内容Summary of the invention
鉴于以上现有技术的缺点，本发明提供一种浮栅结构的制备方法、浮栅结构及闪存器件，以改善浮栅填充时的空洞问题。In view of the above shortcomings of the prior art, the present invention provides a method for preparing a floating gate structure, a floating gate structure and a flash memory device to improve the void problem during floating gate filling.
为实现上述目的及其它相关目的，本发明提供一种浮栅结构的制备方法，包括以下步骤：To achieve the above object and other related objects, the present invention provides a method for preparing a floating gate structure, comprising the following steps:
提供衬底，所述衬底上形成有至少两个隔离结构，相邻的两个所述隔离结构之间形成有上窄下宽的梯形沟槽；Providing a substrate, wherein at least two isolation structures are formed on the substrate, and a trapezoidal trench which is narrow at the top and wide at the bottom is formed between two adjacent isolation structures;
在所述梯形沟槽的底部形成隧穿氧化层；forming a tunneling oxide layer at the bottom of the trapezoidal trench;
在所述梯形沟槽的侧壁上形成多晶硅垫层，以使所述梯形沟槽转变成矩形沟槽；forming a polysilicon pad layer on the sidewall of the trapezoidal trench to transform the trapezoidal trench into a rectangular trench;
向所述矩形沟槽内填充多晶硅，形成浮栅。Polysilicon is filled into the rectangular trench to form a floating gate.
在本发明一示例中，在所述梯形沟槽的侧壁上形成多晶硅垫层，包括：In an example of the present invention, a polysilicon pad layer is formed on the sidewall of the trapezoidal trench, comprising:
在所述梯形沟槽的内壁上形成多晶硅层，所述多晶硅层覆盖所述隧穿氧化层、所述梯形沟槽的侧壁及所述梯形沟槽两侧的所述隔离结构；forming a polysilicon layer on the inner wall of the trapezoidal trench, wherein the polysilicon layer covers the tunneling oxide layer, the sidewall of the trapezoidal trench and the isolation structure on both sides of the trapezoidal trench;
去除所述隔离结构和所述隧穿氧化层上的所述多晶硅层及所述梯形沟槽侧壁上的部分所述多晶硅层，以在所述梯形沟槽的侧壁上形成多晶硅垫层，使得所述梯形沟槽形成矩形沟槽。The polysilicon layer on the isolation structure and the tunnel oxide layer and a portion of the polysilicon layer on the sidewall of the trapezoidal trench are removed to form a polysilicon pad layer on the sidewall of the trapezoidal trench, so that the trapezoidal trench forms a rectangular trench.
在本发明一示例中，去除所述隔离结构和所述隧穿氧化层上的多晶硅层及所述梯形沟槽的侧壁上的部分多晶硅层，包括：In an example of the present invention, removing the polysilicon layer on the isolation structure and the tunnel oxide layer and a portion of the polysilicon layer on the sidewall of the trapezoidal trench includes:
采用干法刻蚀工艺刻蚀所述多晶硅层，去除所述隔离结构上的多晶硅层、所述隧穿氧化层上的多晶硅层及所述梯形沟槽的侧壁上的部分多晶硅层；Etching the polysilicon layer by dry etching to remove the polysilicon layer on the isolation structure, the polysilicon layer on the tunneling oxide layer, and part of the polysilicon layer on the sidewall of the trapezoidal trench;
保留在所述梯形沟槽的侧壁上的部分多晶硅层，形成多晶硅垫层，使得所述梯形沟槽形成矩形沟槽。A portion of the polysilicon layer is retained on the sidewall of the trapezoidal trench to form a polysilicon pad layer, so that the trapezoidal trench forms a rectangular trench.
在本发明一示例中，所述多晶硅垫层与所述梯形沟槽的侧壁贴合的一侧倾斜设置，所述多晶硅垫层背离所述梯形沟槽的侧壁的一侧与所述梯形沟槽的底部相互垂直。In an example of the present invention, the side of the polysilicon pad layer that is in contact with the side wall of the trapezoidal trench is tilted, and the side of the polysilicon pad layer that is away from the side wall of the trapezoidal trench is perpendicular to the bottom of the trapezoidal trench.
在本发明一示例中，向所述矩形沟槽内填充多晶硅后，还包括：采用化学机械平坦化工艺处理所述多晶硅，以去除所述隔离结构上的多晶硅，形成浮栅。In an example of the present invention, after filling the rectangular trench with polysilicon, the method further includes: treating the polysilicon with a chemical mechanical planarization process to remove the polysilicon on the isolation structure to form a floating gate.
在本发明一示例中，至少两个隔离结构的形成过程，包括：In an example of the present invention, the process of forming at least two isolation structures includes:
在衬底上形成垫氧化层；forming a pad oxide layer on the substrate;
在所述垫氧化层上形成硬掩模层；forming a hard mask layer on the pad oxide layer;
在所述硬掩模层上形成图形化的光刻胶层，所述图形化的光刻胶层包括至少两个定义所述隔离结构的开口；forming a patterned photoresist layer on the hard mask layer, wherein the patterned photoresist layer includes at least two openings defining the isolation structure;
以所述图形化的光刻胶层为掩膜，依次刻蚀所述硬掩模层、所述垫氧化层和所述衬底，形成浅沟槽；Using the patterned photoresist layer as a mask, sequentially etching the hard mask layer, the pad oxide layer and the substrate to form a shallow trench;
在所述浅沟槽内填充隔离氧化物，形成隔离结构。An isolation oxide is filled in the shallow trench to form an isolation structure.
在本发明一示例中，在形成隔离结构之后，还包括：去除所述图形化的光刻胶层、所述硬掩模层及所述垫氧化层的步骤，相邻的两个所述隔离结构之间形成上窄下宽的梯形沟槽。In an example of the present invention, after forming the isolation structure, it also includes: a step of removing the patterned photoresist layer, the hard mask layer and the pad oxide layer, and forming a trapezoidal trench that is narrow at the top and wide at the bottom between two adjacent isolation structures.
在本发明一示例中，所述隧穿氧化层包括二氧化硅，在所述梯形沟槽的底部形成隧穿氧化层的方法包括热氧化法。In an example of the present invention, the tunnel oxide layer comprises silicon dioxide, and a method of forming the tunnel oxide layer at the bottom of the trapezoidal trench comprises a thermal oxidation method.
本发明还提供一种浮栅结构，所述浮栅结构采用上述制备方法制备而成；所述浮栅结构包括：The present invention further provides a floating gate structure, which is prepared by the above-mentioned preparation method; the floating gate structure comprises:
衬底，所述衬底上形成有至少两个隔离结构，且相邻的两个所述隔离结构之间形成有上窄下宽的梯形沟槽；A substrate, wherein at least two isolation structures are formed on the substrate, and a trapezoidal trench narrow at the top and wide at the bottom is formed between two adjacent isolation structures;
隧穿氧化层，形成在所述梯形沟槽的底部；a tunneling oxide layer formed at the bottom of the trapezoidal trench;
多晶硅垫层，形成在所述梯形沟槽的侧壁，以使所述梯形沟槽形成矩形沟槽；A polysilicon pad layer is formed on the sidewall of the trapezoidal trench so that the trapezoidal trench forms a rectangular trench;
浮栅，形成在所述矩形沟槽内。A floating gate is formed in the rectangular trench.
本发明还提供一种闪存器件，所述闪存器件包括上述浮栅结构。The present invention also provides a flash memory device, which includes the above-mentioned floating gate structure.
在本发明一示例中，所述闪存器件还包括栅间介质层和控制栅极，所述栅间介质层设置在所述浮栅上，所述控制栅极设置在所述栅间介质层上。In an example of the present invention, the flash memory device further includes an inter-gate dielectric layer and a control gate, the inter-gate dielectric layer is disposed on the floating gate, and the control gate is disposed on the inter-gate dielectric layer.
本发明浮栅结构的制备方法，在进行浮栅填充之前，先在梯形沟槽的侧壁上形成多晶硅垫层，该多晶硅垫层与梯形沟槽的侧壁完全贴合，可以将上窄下宽的梯形沟槽转变成矩形沟槽，在后续浮栅填充过程中可以有效改善的空洞现象，提高器件的可靠性。另外，采用多晶硅作为垫层与多晶硅浮栅的材质相同，在改善浮栅中空洞问题的同时还能避免引入其他杂质，提高器件的可靠性。The preparation method of the floating gate structure of the present invention forms a polysilicon pad on the side wall of the trapezoidal groove before filling the floating gate. The polysilicon pad is completely in contact with the side wall of the trapezoidal groove, and the trapezoidal groove with a narrow top and a wide bottom can be transformed into a rectangular groove. In the subsequent floating gate filling process, the void phenomenon can be effectively improved, and the reliability of the device can be improved. In addition, the polysilicon pad is made of the same material as the polysilicon floating gate, which can improve the void problem in the floating gate while avoiding the introduction of other impurities, thereby improving the reliability of the device.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
图1为现有技术中制备的浮栅结构的示意图；FIG1 is a schematic diagram of a floating gate structure prepared in the prior art;
图2为本发明浮栅结构的制备方法于一实施例中的流程图；FIG2 is a flow chart of a method for preparing a floating gate structure according to an embodiment of the present invention;
图3为本发明浮栅结构的制备方法于一实施例中衬底的结构示意图；FIG3 is a schematic structural diagram of a substrate in an embodiment of a method for preparing a floating gate structure of the present invention;
图4为本发明浮栅结构的制备方法于一实施例中形成浅沟槽的结构示意图；FIG4 is a schematic diagram of a structure of forming a shallow trench in an embodiment of a method for preparing a floating gate structure of the present invention;
图5为本发明浮栅结构的制备方法于一实施例中形成隔离结构的示意图；FIG5 is a schematic diagram of forming an isolation structure in an embodiment of a method for preparing a floating gate structure of the present invention;
图6为本发明浮栅结构的制备方法于一实施例中形成隧穿氧化层的结构示意图；FIG6 is a schematic structural diagram of a method for preparing a floating gate structure according to an embodiment of the present invention for forming a tunnel oxide layer;
图7为本发明浮栅结构的制备方法于一实施例中形成多晶硅层的结构示意图；7 is a schematic structural diagram of a polysilicon layer formed in an embodiment of a method for preparing a floating gate structure of the present invention;
图8为本发明浮栅结构的制备方法于一实施例中形成多晶硅垫层的结构示意图；8 is a schematic structural diagram of a polysilicon pad layer formed in a method for preparing a floating gate structure according to an embodiment of the present invention;
图9为图8中区域A的局部放大示意图；FIG9 is a partial enlarged schematic diagram of area A in FIG8 ;
图10为图8中区域B的局部放大示意图；FIG10 is a partial enlarged schematic diagram of area B in FIG8 ;
图11为本发明浮栅结构的制备方法于一实施例中填充浮栅多晶硅的结构示意图；FIG11 is a schematic diagram of a method for preparing a floating gate structure according to an embodiment of the present invention for filling floating gate polysilicon;
图12为本发明浮栅结构于一实施例中的结构示意图。FIG. 12 is a schematic structural diagram of a floating gate structure in an embodiment of the present invention.
元件标号说明Component number description
100、衬底；110、垫氧化层；120、硬掩模层；130、隔离结构；131、浅沟槽；140、梯形沟槽；141、隧穿氧化层；142、多晶硅层；143、多晶硅垫层；144、矩形沟槽；150、浮栅。100, substrate; 110, pad oxide layer; 120, hard mask layer; 130, isolation structure; 131, shallow trench; 140, trapezoidal trench; 141, tunnel oxide layer; 142, polysilicon layer; 143, polysilicon pad layer; 144, rectangular trench; 150, floating gate.
具体实施方式DETAILED DESCRIPTION
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。需说明的是，在不冲突的情况下，以下实施例及实施例中的特征可以相互组合。The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.
需要说明的是，以下实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and thus the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
在下文描述中，探讨了大量细节，以提供对本发明实施例的更透彻的解释，然而，对本领域技术人员来说，可以在没有这些具体细节的情况下实施本发明的实施例是显而易见的，在其他实施例中，以方框图的形式而不是以细节的形式来示出公知的结构和设备，以避免使本发明的实施例难以理解。In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present invention. However, it is obvious to those skilled in the art that the embodiments of the present invention can be implemented without these specific details. In other embodiments, well-known structures and devices are shown in the form of block diagrams rather than in detail to avoid making the embodiments of the present invention difficult to understand.
在本发明中，如出现术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等，其所指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，如出现术语“第一”、“第二”仅用于描述和区分目的，而不能理解为指示或暗示相对重要性。In the present invention, if the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, if the terms "first" and "second" appear, they are only used for description and distinction purposes, and cannot be understood as indicating or implying relative importance.
现有技术中，浮栅的制备方法包括在衬底上依次形成垫氧化层、掩模层，然后刻蚀出沟槽，再在沟槽中填充氧化物，形成隔离结构；然后去除掩膜层和垫氧化层，以在相邻的隔离结构之间形成用于填充浮栅的间隙。在上述浮栅的制备过程中，通常会形成非常厚的掩模层，而在掩膜层的刻蚀过程中容易形成梯形的隔离沟槽，导致在后续去除掩膜层后形成的用于填充浮栅的间隙也为上窄下宽的梯形间隙，这种梯形间隙在浮栅填充过程中易造成空洞（参见图1），使器件开路甚至无效，从而影响器件的可靠性。In the prior art, the preparation method of the floating gate includes sequentially forming a pad oxide layer and a mask layer on a substrate, then etching a groove, and then filling the groove with oxide to form an isolation structure; then removing the mask layer and the pad oxide layer to form a gap between adjacent isolation structures for filling the floating gate. In the above-mentioned floating gate preparation process, a very thick mask layer is usually formed, and a trapezoidal isolation groove is easily formed during the etching process of the mask layer, resulting in the gap for filling the floating gate formed after the subsequent removal of the mask layer. It is also a trapezoidal gap that is narrow at the top and wide at the bottom. This trapezoidal gap is prone to cause voids during the floating gate filling process (see Figure 1), causing the device to be open or even invalid, thereby affecting the reliability of the device.
基于此，本发明提供一种浮栅结构的制备方法、浮栅结构及闪存器件，在浮栅填充之前，通过在梯形沟槽的侧壁上形成多晶硅衬垫以将梯形沟槽转变成矩形沟槽，可以有效改善浮栅填充过程中的空洞问题。Based on this, the present invention provides a method for preparing a floating gate structure, a floating gate structure and a flash memory device. Before the floating gate is filled, a polysilicon liner is formed on the side wall of the trapezoidal trench to transform the trapezoidal trench into a rectangular trench, which can effectively improve the void problem in the floating gate filling process.
请参阅图2至图12，本发明第一方面提供一种浮栅结构的制备方法，该制备方法包括以下步骤：Referring to FIG. 2 to FIG. 12 , a first aspect of the present invention provides a method for preparing a floating gate structure, the method comprising the following steps:
S1、提供衬底100，该衬底100上形成有至少两个隔离结构130，相邻的两个隔离结构130之间形成有上窄下宽的梯形沟槽140（参见图5）；S1, providing a substrate 100, on which at least two isolation structures 130 are formed, and between two adjacent isolation structures 130, a trapezoidal trench 140 which is narrow at the top and wide at the bottom is formed (see FIG. 5);
S2、在梯形沟槽140的底部形成隧穿氧化层141（参见图6）；S2, forming a tunnel oxide layer 141 at the bottom of the trapezoidal trench 140 (see FIG. 6 );
S3、在梯形沟槽140的侧壁上形成多晶硅垫层143，以使梯形沟槽140转变成矩形沟槽144（参见图8至图10）；S3, forming a polysilicon pad layer 143 on the sidewall of the trapezoidal trench 140 to transform the trapezoidal trench 140 into a rectangular trench 144 (see FIGS. 8 to 10 );
S4、向矩形沟槽144内填充多晶硅，形成浮栅150（参见图12）。S4 . Fill the rectangular trench 144 with polysilicon to form a floating gate 150 (see FIG. 12 ).
下面结合图3至图12详细介绍本发明实施例中浮栅结构的制备方法的各步骤。The steps of the method for preparing the floating gate structure according to the embodiment of the present invention will be described in detail below in conjunction with FIG. 3 to FIG. 12 .
请参阅图3，步骤S1中衬底100可以选用硅（Si）、锗（Ge）、硅锗（SiGe）、碳化硅（SiC）、砷化镓（GaAs）、砷化铟（InAs）或者其他III/V化合物半导体材料。除此之外，衬底还可以为Si/SiGe、Si/SiC、绝缘体上硅 (SOI)、绝缘体上锗（GOI）或绝缘体上硅锗(SGOI)等层叠衬底材料。本实施例中，衬底100选用硅衬底。衬底100可通过掺杂工艺，例如离子注入工艺形成有源区。Referring to FIG. 3 , in step S1, the substrate 100 may be made of silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs) or other III/V compound semiconductor materials. In addition, the substrate may also be a stacked substrate material such as Si/SiGe, Si/SiC, silicon on insulator (SOI), germanium on insulator (GOI) or silicon germanium on insulator (SGOI). In this embodiment, the substrate 100 is a silicon substrate. The substrate 100 may be formed into an active region by a doping process, such as an ion implantation process.
请参阅图3至图5，衬底100上形成的隔离结构130向下延伸至衬底100内部，用于隔离衬底100上的有源区，每一有源区均可用于形成半导体器件；隔离结构130的顶部高于衬底100上表面，相邻两个隔离结构130之间的凹槽区域形成浮栅150的填充区域。Please refer to Figures 3 to 5. The isolation structure 130 formed on the substrate 100 extends downward into the interior of the substrate 100 and is used to isolate the active areas on the substrate 100. Each active area can be used to form a semiconductor device. The top of the isolation structure 130 is higher than the upper surface of the substrate 100, and the groove area between two adjacent isolation structures 130 forms a filling area for the floating gate 150.
在一实施例中，隔离结构130为浅沟槽隔离结构（Shallow Trench Isolation，STI）。浅沟槽隔离结构的形成过程示例如下：In one embodiment, the isolation structure 130 is a shallow trench isolation (STI) structure. The formation process of the shallow trench isolation structure is as follows:
请参阅图3，在衬底100上形成垫氧化层110。垫氧化层110包括但不限于二氧化硅（SiO2）。垫氧化层110例如可以通过热氧化法（thermal oxidation method）或化学气相沉积（Chemical Vapor Deposition，CVD）等工艺制备。3 , a pad oxide layer 110 is formed on a substrate 100. The pad oxide layer 110 includes but is not limited to silicon dioxide (SiO2 ). The pad oxide layer 110 can be prepared by, for example, a thermal oxidation method or a chemical vapor deposition (CVD) process.
在垫氧化层110上形成硬掩模层120。硬掩模层120例如为氮化硅（Si3N4），硬掩模层120可通过化学气相沉积物理气相沉积（Physical Vapor Deposition，PVD）等工艺形成。垫氧化层110可以作为缓冲层，避免硬度较大的硬掩模层120与衬底100直接接触，损伤衬底100；硬掩模层120可以作为硬掩模版，以刻蚀复制相应的图形。A hard mask layer 120 is formed on the pad oxide layer 110. The hard mask layer 120 is, for example, silicon nitride (Si3 N4 ), and can be formed by processes such as chemical vapor deposition and physical vapor deposition (PVD). The pad oxide layer 110 can be used as a buffer layer to prevent the hard mask layer 120 with a relatively high hardness from directly contacting the substrate 100 and damaging the substrate 100; the hard mask layer 120 can be used as a hard mask to etch and replicate the corresponding pattern.
进一步地，在刻蚀之前，需在硬掩模层120上形成图形化的光刻胶层（图中未示出），即先在硬掩模层120上旋涂光刻胶层，通过曝光和显影工序在光刻胶层上形成至少两个开口，以在硬掩模层120上形成具有刻蚀图案的图形化的光刻胶层。上述的至少两个开口用来定义隔离结构130的位置，且开口暴露出底部的硬掩模层120。Furthermore, before etching, a patterned photoresist layer (not shown in the figure) needs to be formed on the hard mask layer 120, that is, the photoresist layer is first spin-coated on the hard mask layer 120, and at least two openings are formed on the photoresist layer through exposure and development processes to form a patterned photoresist layer with an etching pattern on the hard mask layer 120. The at least two openings are used to define the position of the isolation structure 130, and the openings expose the bottom hard mask layer 120.
请参阅图4，以图形化的光刻胶层为掩膜，依次刻蚀硬掩模层120、垫氧化层110和部分衬底100，以形成浅沟槽131，浅沟槽131未穿透衬底100。刻蚀工艺可以使用本领域技术人员所熟知的方法进行，例如干法刻蚀和/或湿法刻蚀。形成的浅沟槽131结构自上而下逐渐变窄，此种结构有助于后续绝缘物质的填充，同时也会使得硬掩模层120自下而上逐渐变窄。Referring to FIG. 4 , the hard mask layer 120, the pad oxide layer 110 and a portion of the substrate 100 are sequentially etched using the patterned photoresist layer as a mask to form a shallow trench 131, which does not penetrate the substrate 100. The etching process can be performed using methods well known to those skilled in the art, such as dry etching and/or wet etching. The shallow trench 131 structure formed gradually narrows from top to bottom, which is helpful for subsequent filling of insulating materials, and also makes the hard mask layer 120 gradually narrow from bottom to top.
请参阅图5，浅沟槽131形成后，再在浅沟槽131内填充隔离氧化物以形成隔离结构130，隔离氧化物例如为二氧化硅等绝缘物质，当然不限于此，也可以为其他绝缘材料。隔离氧化物的填充方式例如采用高深宽比填充工艺(High Aspect Ratio Process，HARP)、低压化学气相沉积（Low Pressure Chemical Vapor Deposition，LPCVD）或等离子体化学气相沉积（Plasma Enhanced Chemical Vapor Deposition，PECVD）等工艺。隔离氧化物沉积完成后，还包括平坦化处理隔离氧化物，直至隔离氧化物的高度与硬掩模层120齐平。平坦化处理例如采用化学机械抛光（Chemical Mechanical Polishing，CMP）工艺。平坦化处理结束后，形成隔离结构130。然而本领域技术人员可以理解的是，本发明中的隔离结构130也可以采用其它本领域的现有手段，不以上述隔离结构130的制作过程为限。Please refer to FIG. 5 . After the shallow trench 131 is formed, an isolation oxide is filled in the shallow trench 131 to form an isolation structure 130. The isolation oxide is, for example, an insulating material such as silicon dioxide, but is not limited thereto and may also be other insulating materials. The isolation oxide is filled by, for example, a high aspect ratio filling process (HARP), a low pressure chemical vapor deposition (LPCVD) or a plasma enhanced chemical vapor deposition (PECVD) process. After the isolation oxide deposition is completed, the isolation oxide is planarized until the height of the isolation oxide is flush with the hard mask layer 120. The planarization process is, for example, a chemical mechanical polishing (CMP) process. After the planarization process is completed, the isolation structure 130 is formed. However, it can be understood by those skilled in the art that the isolation structure 130 in the present invention may also adopt other existing means in the art, and is not limited to the manufacturing process of the above-mentioned isolation structure 130.
隔离结构130形成之后，还包括去除图形化的光刻胶层、硬掩模层120和垫氧化层110工序，其中，图形化的光刻胶层可采用等离子体灰化工艺进行去除，硬掩模层120和垫氧化层110可采用刻蚀工艺进行去除，刻蚀工艺例如为干法刻蚀和/或湿法刻蚀。由于形成的浅沟槽131自上而下逐渐变窄，相应的，相邻两个隔离结构130之间的硬掩模层120自下而上逐渐变窄，在去除硬掩模层120和垫氧化层110之后形成自下而上逐渐变窄的梯形沟槽140，即形成的沟槽纵向截面为上窄下宽的梯形。After the isolation structure 130 is formed, the process also includes removing the patterned photoresist layer, the hard mask layer 120 and the pad oxide layer 110, wherein the patterned photoresist layer can be removed by a plasma ashing process, and the hard mask layer 120 and the pad oxide layer 110 can be removed by an etching process, such as dry etching and/or wet etching. Since the shallow trench 131 formed gradually narrows from top to bottom, the hard mask layer 120 between two adjacent isolation structures 130 gradually narrows from bottom to top, and after removing the hard mask layer 120 and the pad oxide layer 110, a trapezoidal trench 140 gradually narrows from bottom to top is formed, that is, the longitudinal cross section of the formed trench is a trapezoidal shape with a narrow top and a wide bottom.
请参阅图6和图12，执行步骤S2，在梯形沟槽140的底部形成隧穿氧化层141。隧穿氧化层141用于隔绝浮栅150与衬底100，防止电荷直接从浮栅150流向晶体管的其他部分。隧穿氧化层141允许电荷通过量子隧穿效应从一个区域移动到另一个区域。在闪存擦除过程中，存储在浮栅150上的电荷通过隧穿氧化层141隧穿到源极或体区，实现数据的擦除。隧穿氧化层141例如为二氧化硅，隧穿氧化层141可采用热氧化法、化学气相沉积、物理气相沉积等工艺形成，热氧化法例如为湿法氧化、干法氧化或原位水汽生成法。Please refer to Figures 6 and 12, and perform step S2 to form a tunneling oxide layer 141 at the bottom of the trapezoidal trench 140. The tunneling oxide layer 141 is used to isolate the floating gate 150 from the substrate 100 to prevent charges from flowing directly from the floating gate 150 to other parts of the transistor. The tunneling oxide layer 141 allows charges to move from one area to another through the quantum tunneling effect. During the flash memory erase process, the charges stored on the floating gate 150 tunnel to the source or body region through the tunneling oxide layer 141 to achieve data erasure. The tunneling oxide layer 141 is, for example, silicon dioxide, and the tunneling oxide layer 141 can be formed by thermal oxidation, chemical vapor deposition, physical vapor deposition and other processes. The thermal oxidation method is, for example, wet oxidation, dry oxidation or in-situ water vapor generation.
请参阅图6、图8、图10和图11，由于步骤S1形成的用于填充浮栅150的沟槽为纵向截面为上窄下宽的梯形沟槽140，这种形状的沟槽由于开口尺寸较小，在后续浮栅150填充过程中容易形成空洞。为了改善浮栅150填充过程中的空洞问题，本发明增加步骤S3，在梯形沟槽140的侧壁上形成多晶硅垫层143。多晶硅垫层143自上至下逐渐变宽，且多晶硅垫层143与梯形沟槽140的侧壁完全贴合，以使梯形沟槽140在多晶硅垫层143的辅助作用下转变成纵向截面为矩形的矩形沟槽144。Please refer to FIG. 6, FIG. 8, FIG. 10 and FIG. 11. Since the groove for filling the floating gate 150 formed in step S1 is a trapezoidal groove 140 with a longitudinal cross section that is narrow at the top and wide at the bottom, such a groove is easy to form voids in the subsequent floating gate 150 filling process due to its small opening size. In order to improve the void problem in the floating gate 150 filling process, the present invention adds step S3 to form a polysilicon pad layer 143 on the side wall of the trapezoidal groove 140. The polysilicon pad layer 143 gradually widens from top to bottom, and the polysilicon pad layer 143 is completely attached to the side wall of the trapezoidal groove 140, so that the trapezoidal groove 140 is transformed into a rectangular groove 144 with a rectangular longitudinal cross section under the auxiliary effect of the polysilicon pad layer 143.
请参阅图9，具体地，多晶硅垫层143与梯形沟槽140侧壁贴合的一侧倾斜设置，其倾斜角度（多晶硅垫层143的斜边与梯形沟槽140的底壁的夹角）与梯形沟槽140侧壁的倾斜角度（侧壁与梯形沟槽140底部的夹角）相同，多晶硅垫层143背离梯形沟槽140侧壁的一侧垂直于梯形沟槽140的底部，此结构的多晶硅垫层143填充在梯形沟槽140内可以弥补梯形沟槽140侧壁的倾斜角度，将梯形沟槽140转变成矩形沟槽144。并且，由于后续填充的浮栅150也采用多晶硅，本步骤以多晶硅作为垫层不会额外引入杂质。Please refer to FIG. 9 . Specifically, the side of the polysilicon pad layer 143 that is in contact with the side wall of the trapezoidal groove 140 is tilted, and its tilt angle (the angle between the hypotenuse of the polysilicon pad layer 143 and the bottom wall of the trapezoidal groove 140) is the same as the tilt angle of the side wall of the trapezoidal groove 140 (the angle between the side wall and the bottom of the trapezoidal groove 140). The side of the polysilicon pad layer 143 that is away from the side wall of the trapezoidal groove 140 is perpendicular to the bottom of the trapezoidal groove 140. The polysilicon pad layer 143 of this structure is filled in the trapezoidal groove 140 to make up for the tilt angle of the side wall of the trapezoidal groove 140, and the trapezoidal groove 140 is transformed into a rectangular groove 144. In addition, since the floating gate 150 filled later also uses polysilicon, the use of polysilicon as a pad layer in this step will not introduce additional impurities.
请参阅图7至图10，在一实施例中，多晶硅垫层143的形成过程如下：Referring to FIG. 7 to FIG. 10 , in one embodiment, the formation process of the polysilicon pad layer 143 is as follows:
在梯形沟槽140的内壁上形成多晶硅层142，该多晶硅层142覆盖梯形沟槽140底部的隧穿氧化层141、梯形沟槽140的侧壁及梯形沟槽140两侧的隔离结构130（参阅图7）。A polysilicon layer 142 is formed on the inner wall of the trapezoidal trench 140 , and the polysilicon layer 142 covers the tunnel oxide layer 141 at the bottom of the trapezoidal trench 140 , the sidewalls of the trapezoidal trench 140 , and the isolation structures 130 on both sides of the trapezoidal trench 140 (see FIG. 7 ).
多晶硅层142的形成方法包括但不限于低压化学气相沉积（LPCVD）、等离子增强化学气相沉积（PECVD）、原子层沉积（ALD）、物理气相沉积（PVD）。多晶硅层142的沉积厚度不做特别限制，只要不填满梯形沟槽140即可。进一步地，多晶硅层142的沉积厚度至少为梯形沟槽140侧壁的顶部超出底部的尺寸。例如，梯形沟槽140侧壁的顶部超出底部5nm，则多晶硅层142的沉积厚度至少为5nm，只有这样才能在后续处理过程中获得的多晶硅垫层143完全弥补梯形沟槽140侧壁的倾斜部分。更进一步地，多晶硅层142的沉积厚度小于等于梯形沟槽140顶部开口尺寸的一半，由于多晶硅层142沉积时会在梯形沟槽140相对两侧的侧壁上同时沉积，当多晶硅层142的沉积厚度等于梯形沟槽140顶部开口尺寸的一半时，梯形沟槽140的相对两侧壁的沉积厚度相加已填满梯形沟槽140的顶部开口。因此，多晶硅层142的沉积厚度小于等于梯形沟槽140顶部开口尺寸的一半。作为示例，梯形沟槽140的顶部开口尺寸为40nm，则多晶硅层142的沉积厚度小于等于20nm。The formation method of the polysilicon layer 142 includes but is not limited to low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), and physical vapor deposition (PVD). The deposition thickness of the polysilicon layer 142 is not particularly limited, as long as it does not fill the trapezoidal groove 140. Furthermore, the deposition thickness of the polysilicon layer 142 is at least the size of the top of the side wall of the trapezoidal groove 140 exceeding the bottom. For example, if the top of the side wall of the trapezoidal groove 140 exceeds the bottom by 5nm, the deposition thickness of the polysilicon layer 142 is at least 5nm. Only in this way can the polysilicon pad layer 143 obtained in the subsequent processing process completely make up for the inclined part of the side wall of the trapezoidal groove 140. Furthermore, the deposition thickness of the polysilicon layer 142 is less than or equal to half of the size of the top opening of the trapezoidal trench 140. Since the polysilicon layer 142 is deposited on the sidewalls of the trapezoidal trench 140 on both sides, when the deposition thickness of the polysilicon layer 142 is equal to half of the size of the top opening of the trapezoidal trench 140, the deposition thickness of the two sidewalls of the trapezoidal trench 140 on both sides is added to fill the top opening of the trapezoidal trench 140. Therefore, the deposition thickness of the polysilicon layer 142 is less than or equal to half of the size of the top opening of the trapezoidal trench 140. As an example, if the top opening of the trapezoidal trench 140 is 40nm, the deposition thickness of the polysilicon layer 142 is less than or equal to 20nm.
去除隔离结构130和隧穿氧化层141上的多晶硅层142及所述梯形沟槽140侧壁上的部分多晶硅层142，以在梯形沟槽140的侧壁上形成多晶硅垫层143（参阅图8和图9）。The polysilicon layer 142 on the isolation structure 130 and the tunnel oxide layer 141 and a portion of the polysilicon layer 142 on the sidewall of the trapezoidal trench 140 are removed to form a polysilicon pad layer 143 on the sidewall of the trapezoidal trench 140 (see FIGS. 8 and 9 ).
由于多晶硅层142会沉积在晶圆衬底100所有暴露的表面，即沟槽140底部的隧穿氧化层141、梯形沟槽140的侧壁及梯形沟槽140两侧的隔离结构130上均沉积有多晶硅，而形成多晶硅垫层143只需保留梯形沟槽140侧壁上的部分多晶硅，因此需去除隔离结构130和隧穿氧化层141上的多晶硅层142及梯形沟槽140侧壁上的部分多晶硅层142。本实施例中，去除多晶硅层142的工艺采用干法刻蚀，例如等离子刻蚀（Plasma Etching）、反应离子刻蚀（Reactive Ion Etching，RIE）等。由于梯形沟槽140为上宽下窄结构，在刻蚀过程中，梯形沟槽140侧壁的隔离氧化物具有一定的阻挡作用，因此，侧壁覆盖下的多晶硅层142被保留形成多晶硅垫层143，未被侧壁覆盖的多晶硅层142被刻蚀掉。刻蚀结束后，梯形沟槽140在多晶硅垫层143的辅助下转变成上下宽度一致的矩形沟槽144。Since the polysilicon layer 142 will be deposited on all exposed surfaces of the wafer substrate 100, that is, the tunneling oxide layer 141 at the bottom of the groove 140, the sidewalls of the trapezoidal groove 140, and the isolation structure 130 on both sides of the trapezoidal groove 140 are all deposited with polysilicon, and only part of the polysilicon on the sidewalls of the trapezoidal groove 140 needs to be retained to form the polysilicon pad layer 143, it is necessary to remove the polysilicon layer 142 on the isolation structure 130 and the tunneling oxide layer 141 and part of the polysilicon layer 142 on the sidewalls of the trapezoidal groove 140. In this embodiment, the process of removing the polysilicon layer 142 adopts dry etching, such as plasma etching (Plasma Etching), reactive ion etching (Reactive Ion Etching, RIE), etc. Since the trapezoidal trench 140 is a structure that is wide at the top and narrow at the bottom, the isolation oxide on the sidewall of the trapezoidal trench 140 has a certain blocking effect during the etching process, so the polysilicon layer 142 covered by the sidewall is retained to form a polysilicon pad layer 143, and the polysilicon layer 142 not covered by the sidewall is etched away. After the etching is completed, the trapezoidal trench 140 is transformed into a rectangular trench 144 with the same width at the top and bottom with the assistance of the polysilicon pad layer 143.
请参阅图10至图12，执行步骤S4，向矩形沟槽144内填充多晶硅，形成浮栅150。Referring to FIG. 10 to FIG. 12 , step S4 is performed to fill the rectangular trench 144 with polysilicon to form a floating gate 150 .
本步骤中多晶硅的填充方式可采用本领域已知的技术手段，例如低压化学气相沉积（LPCVD）、等离子增强化学气相沉积（PECVD）、原子层沉积（ALD）、物理气相沉积（PVD）等。多晶硅在填充矩形沟槽144的同时会覆盖矩形沟槽144两侧的隔离结构130，以为后续对多晶硅的平坦化处理提供余量。多晶硅沉积结束后，还包括采用化学机械平坦化工艺处理多晶硅，至暴露出隔离结构130的顶部，且剩余的多晶硅的厚度达到浮栅厚度的要求，形成浮栅150。The filling method of polysilicon in this step can adopt the technical means known in the art, such as low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), etc. While filling the rectangular groove 144, the polysilicon will cover the isolation structure 130 on both sides of the rectangular groove 144 to provide a margin for the subsequent planarization of the polysilicon. After the polysilicon deposition is completed, the polysilicon is also processed by a chemical mechanical planarization process until the top of the isolation structure 130 is exposed, and the thickness of the remaining polysilicon meets the requirements of the floating gate thickness, so as to form a floating gate 150.
请参阅图12，本发明另一方面还提供一种浮栅结构，该浮栅结构采用本发明上文所述的制备方法制备而成。该浮栅结构包括衬底100、隧穿氧化层141、多晶硅垫层143和浮栅150。12 , the present invention also provides a floating gate structure, which is prepared by the preparation method described above. The floating gate structure includes a substrate 100 , a tunneling oxide layer 141 , a polysilicon pad layer 143 and a floating gate 150 .
衬底100可以选用硅（Si）、锗（Ge）、硅锗（SiGe）、碳化硅（SiC）、砷化镓（GaAs）、砷化铟（InAs）或者其他III/V化合物半导体材料。除此之外，衬底还可以为Si/SiGe、Si/SiC、绝缘体上硅 (SOI)、绝缘体上锗（GOI）或绝缘体上硅锗(SGOI)等层叠衬底材料。本实施例中，衬底100为硅衬底。The substrate 100 may be made of silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs) or other III/V compound semiconductor materials. In addition, the substrate may also be a stacked substrate material such as Si/SiGe, Si/SiC, silicon on insulator (SOI), germanium on insulator (GOI) or silicon germanium on insulator (SGOI). In this embodiment, the substrate 100 is a silicon substrate.
衬底100上形成有至少两个隔离结构130，且隔离结构130的底部延伸至衬底100的内部，隔离结构130的顶部高于衬底100的上表面。隔离结构130例如为浅沟槽隔离结构（STI）。相邻的两个隔离结构130之间形成有上窄下宽的梯形沟槽140。At least two isolation structures 130 are formed on the substrate 100, and the bottom of the isolation structure 130 extends into the interior of the substrate 100, and the top of the isolation structure 130 is higher than the upper surface of the substrate 100. The isolation structure 130 is, for example, a shallow trench isolation (STI) structure. A trapezoidal trench 140 with a narrow top and a wide bottom is formed between two adjacent isolation structures 130.
隧穿氧化层141形成在梯形沟槽140的底部，隧穿氧化层141例如为氧化硅，其厚度可按照本领域常规手段设计即可。The tunnel oxide layer 141 is formed at the bottom of the trapezoidal trench 140 . The tunnel oxide layer 141 is, for example, silicon oxide, and its thickness can be designed according to conventional means in the art.
多晶硅垫层143形成在梯形沟槽140的侧壁上。具体地，多晶硅垫层143与梯形沟槽140侧壁贴合的一侧倾斜设置，其倾斜角度（多晶硅垫层143的斜边与梯形沟槽140的底壁的夹角）与梯形沟槽140侧壁的倾斜角度（侧壁与梯形沟槽140底部的夹角）相同，多晶硅垫层143背离梯形沟槽140侧壁的一侧垂直于梯形沟槽140的底部，此结构的多晶硅垫层143填充在梯形沟槽140内可以弥补梯形沟槽140侧壁的下部的倾斜角度，将梯形沟槽140转变成矩形沟槽144。The polysilicon pad layer 143 is formed on the side wall of the trapezoidal groove 140. Specifically, the side of the polysilicon pad layer 143 that is in contact with the side wall of the trapezoidal groove 140 is tilted, and its tilt angle (the angle between the hypotenuse of the polysilicon pad layer 143 and the bottom wall of the trapezoidal groove 140) is the same as the tilt angle of the side wall of the trapezoidal groove 140 (the angle between the side wall and the bottom of the trapezoidal groove 140). The side of the polysilicon pad layer 143 that is away from the side wall of the trapezoidal groove 140 is perpendicular to the bottom of the trapezoidal groove 140. The polysilicon pad layer 143 of this structure is filled in the trapezoidal groove 140 to make up for the tilt angle of the lower part of the side wall of the trapezoidal groove 140, and the trapezoidal groove 140 is transformed into a rectangular groove 144.
浮栅150采用多晶硅，多晶硅填充在矩形沟槽144内。The floating gate 150 is made of polysilicon, and the polysilicon is filled in the rectangular trench 144 .
本发明的浮栅结构由于在梯形沟槽内增设多晶硅垫层143，在多晶硅垫层143的作用下，梯形沟槽140转变成矩形沟槽144，后续填充过程中可以有效改善浮栅150多晶硅中的空洞问题，提高浮栅结构的可靠性。The floating gate structure of the present invention has a polysilicon pad layer 143 added in the trapezoidal trench. Under the action of the polysilicon pad layer 143, the trapezoidal trench 140 is transformed into a rectangular trench 144. In the subsequent filling process, the void problem in the polysilicon of the floating gate 150 can be effectively improved, thereby improving the reliability of the floating gate structure.
基于同一发明构思，本发明还提供一种闪存器件，该闪存器件包括上述浮栅结构。Based on the same inventive concept, the present invention also provides a flash memory device, which includes the above-mentioned floating gate structure.
在一实施例中，闪存器件还包括栅间介质层和控制栅极，栅间介质层设置在浮栅150上，控制栅极设置在栅间介质层上。栅间介质层用于隔离浮栅150和控制栅极，栅间介质层的材质可以包括氧化硅、氮化硅或氧化硅-氮化硅-氧化硅(ONO)等，控制栅极的材质可以为多晶硅。In one embodiment, the flash memory device further includes an inter-gate dielectric layer and a control gate, wherein the inter-gate dielectric layer is disposed on the floating gate 150, and the control gate is disposed on the inter-gate dielectric layer. The inter-gate dielectric layer is used to isolate the floating gate 150 from the control gate, and the material of the inter-gate dielectric layer may include silicon oxide, silicon nitride, or silicon oxide-silicon nitride-silicon oxide (ONO), etc., and the material of the control gate may be polysilicon.
本发明浮栅结构的制备方法，在进行浮栅填充之前，先在梯形沟槽的侧壁上形成多晶硅垫层，利用多晶硅垫层将上窄下宽的梯形沟槽转变成矩形沟槽，在后续填充过程中可以有效改善浮栅中的空洞现象，提高器件的可靠性。所以，本发明有效克服了现有技术中的一些实际问题从而有很高的利用价值和使用意义。The preparation method of the floating gate structure of the present invention forms a polysilicon pad on the side wall of the trapezoidal groove before filling the floating gate, and uses the polysilicon pad to transform the narrow upper and wide lower trapezoidal groove into a rectangular groove, which can effectively improve the void phenomenon in the floating gate in the subsequent filling process and improve the reliability of the device. Therefore, the present invention effectively overcomes some practical problems in the prior art and has high utilization value and use significance.
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
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| CN202411365189.4ACN118888435B (en) | 2024-09-29 | 2024-09-29 | Preparation method of floating gate structure, floating gate structure and flash memory device |
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| CN202411365189.4ACN118888435B (en) | 2024-09-29 | 2024-09-29 | Preparation method of floating gate structure, floating gate structure and flash memory device |
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| CN202411365189.4AActiveCN118888435B (en) | 2024-09-29 | 2024-09-29 | Preparation method of floating gate structure, floating gate structure and flash memory device |
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| KR20050097398A (en)* | 2004-04-03 | 2005-10-07 | 삼성전자주식회사 | Method of fabricating floating gate of flash memory |
| US20050287763A1 (en)* | 2004-06-29 | 2005-12-29 | Taek-Jung Kim | Method of manufacturing a semiconductor device |
| US20080090352A1 (en)* | 2006-10-16 | 2008-04-17 | Sang-Kyoung Lee | Nonvolatile memory device and method of manufacturing the same |
| CN105789211A (en)* | 2014-12-24 | 2016-07-20 | 上海格易电子有限公司 | Flash memory storage unit and manufacturing method therefor |
| CN105826270A (en)* | 2015-01-07 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Formation method of flash |
| CN107993978A (en)* | 2016-10-24 | 2018-05-04 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof, electronic device |
| CN109616409A (en)* | 2018-12-04 | 2019-04-12 | 武汉新芯集成电路制造有限公司 | A kind of polysilicon deposition method, flash memory and manufacturing method thereof |
| CN109887915A (en)* | 2019-03-07 | 2019-06-14 | 上海华力微电子有限公司 | Flush memory device and its manufacturing method |
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