CN1185796C - Improved correcting decoding method for non-regular low-density parity-check code - Google Patents

Abstract

Translated fromChinese

改进的非规则低密奇偶度校验码(ILDPC码)纠错译码方法属于通信技术领域，其特征在于，它利用非规则低密度奇偶校验码比特节点的保护程度随着节点阶数的提高而提高的特性在迭代过程中使高阶比特节点的迭代在完成本阶节点的纠错时就结束，而低阶节点的迭代继续进行，以简化后续迭代译码的计算复杂度，节省时间；还可以通过对高阶比特节点的译码结果进行放大，给低阶节点提供更多的有用信息。从而，在高信噪比条件下可以获得比标准和积译码方法更好的纠错性能；与最小和译码方法相比，没有明显损失ILDPC码的纠错性能。同时，本方法还可推广到磁盘存储系统中去。

The improved irregular low-density parity-check code (ILDPC code) error correction decoding method belongs to the field of communication technology, and is characterized in that it utilizes the protection degree of the irregular low-density parity-check code bit node along with the node order The improved and improved characteristics make the iteration of high-order bit nodes end when the error correction of this-order node is completed during the iterative process, while the iteration of low-order nodes continues to simplify the computational complexity of subsequent iterative decoding and save time ; It is also possible to provide more useful information to low-order nodes by amplifying the decoding results of high-order bit nodes. Therefore, under the condition of high signal-to-noise ratio, better error correction performance can be obtained than the standard sum product decoding method; compared with the minimum sum decoding method, there is no obvious loss of error correction performance of ILDPC codes. At the same time, the method can also be extended to disk storage systems.

Description

Improved non-rule low density parity check code error-correcting decoding method

Technical field

Improved non-rule low density parity check code error-correcting decoding method belongs to communication channel decoding technique field, be particularly related to effectively and the fast interpretation method of a kind of employing non-rule low density parity check code (Irregular Low-Density Parity-Check code the is called for short the ILDPC sign indicating number) correcting error of information channel when adopting forward error control (FEC) technology to be used for transfer of data and storage.

Background technology

Data cause various mistakes through regular meeting in storage and transmission course.The reason that produces this mistake has synchronization loss, the multipath fading in the wireless transmission, the magnetic track in the magnetic storage in random noise, the demodulating process damaged etc.This burst error is generally that aperiodicity occurs and duration length is indefinite.Because the existence of these mistakes, limited the memory capacity of memory under the rate of information throughput under the specific bandwidth and the particular area greatly.Particularly in wireless multimedia transmission system, because lot of data will and be subjected in the serious channel that disturbs of various bursts with very high reliability transmission at limited bandwidth, this problem becomes more outstanding.

In order to solve the integrity problem in transfer of data and the storage, adopt the method for chnnel coding usually.In current existing channel coding method, the ILDPC sign indicating number of Ti Chuing has the most powerful error correcting capability recently, has very strong application prospect.

The interpretation method that adopts the ILDPC sign indicating number to carry out error control is:

1.ILDPC the definition and the parameter of sign indicating number:

The ILDPC sign indicating number is a kind of binary packet sign indicating number, and this sign indicating number adopts the supersparsity matrix as check matrix.The number of nonzero element is very rare in every row in the matrix (every row), and the position is random distribution.For convenience of description, the number of nonzero element is the weight of this row (row) in the definition delegation (row).Because the check matrix of ILDPC sign indicating number is the matrix that generates at random, the weight of each row (row) is uncertain, therefore adopts the distribution of weight formula to describe this matrix.The column weight amount of same class ILDPC code check matrix distributes and can be expressed as with distributed:

$\mathrm{\λ}\left(x\right)=\underset{i=2}{\overset{d_v}{\mathrm{\Σ}}}{\mathrm{\λ}}_i{x}^{i-1}--\left(1\right)$

λ in the formula_iExpression weight be i be listed in deal shared in the matrix, d_vValue for the maximum of column weight amount in the matrix.Equally, the capable distribution of weight of same class ILDPC code check matrix adopts following formula to describe:

$\mathrm{\ρ}\left(x\right)=\underset{j=2}{\overset{d_c}{\mathrm{\Σ}}}{\mathrm{\ρ}}_j{x}^{j-1}--\left(2\right)$

ρ in the formula_jExpression weight is the row of j shared deal in matrix, d_cMaximum for row weight in the matrix.Because the ILDPC sign indicating number is block code, for any legal code word V, with the product of check matrix H be zero, i.e. HV^T=0.By this check equations as can be known, the same code element of the only corresponding ILDPC sign indicating number of the nonzero element of every row in the check matrix has formed a constraint that is equivalent to duplication code.For the ease of the description in the decode procedure, defining this restriction relation is a bit node, and the exponent number of node is the weight of these row.And the nonzero element of every row in the check matrix becomes a constraint that is equivalent to check code with pairing ILDPC symbol mapped.It is a check-node that this verification of same definition is closed, and the exponent number of node is the weight of this row.Each nonzero element in the matrix had both participated in the restriction relation of bit node, had participated in the restriction relation of check-node again, thereby can to define the pairing pass of matrix nonzero element be " tie line " that links these two kinds of nodes.In iterative decoding process, decoder utilizes the restriction relation of pairing check-node of the row and column of matrix and bit node to carry out iterative decoding.In iterative process, at first utilize the restriction relation of bit node to decipher, log-likelihood value that is input as the receiving sequence correspondence of each bit node (being probability that each metasymbol is got " 1 " is taken from right logarithm gained again divided by the probability of getting " 0 " value) and relevant check-node are in the output of last once iteration; Subsequently, the output of bit node is delivered to corresponding check-node by " tie line ", utilizes the restriction relation of check-node to decipher again.In this process, a kind of output of node becomes the input of another node, and nonzero element pairing " tie line " becomes " passage " of these two kinds of node input and output exchange messages in the matrix.For code length is the N bit, the ILDPC sign indicating number that the column weight amount distributes and the row distribution of weight is determined by (1) (2) two formulas respectively, and the number of its i rank bit node is:

$N_i=N\·\frac{{\mathrm{\λ}}_i/i}{\underset{i=2}{\overset{d_v}{\mathrm{\Σ}}}{\mathrm{\λ}}_i/i}=N\·\frac{{\mathrm{\λ}}_i/i}{{\∫}_0^1\mathrm{\λ}\left(x\right)\mathrm{dx}},2\≤i\≤d_v--\left(3\right)$

In like manner, the number of j rank check-node is:

$M_j=M\·\frac{{\mathrm{\ρ}}_j/j}{\underset{j=2}{\overset{d_c}{\mathrm{\Σ}}}{\mathrm{\ρ}}_j/j}=M\·\frac{{\mathrm{\ρ}}_j/j}{{\∫}_0^1\mathrm{\ρ}\left(x\right)\mathrm{dx}},2\≤j\≤d_c--\left(4\right)$

M is the length of verification code element in the ILDPC code word in the formula.

2.ILDPC the decoding of sign indicating number:

The supersparsity characteristic of check matrix has fully been used in the decoding of ILDPC sign indicating number, calculates and the output external information by the restriction relation of bit node and check-node, and feeds back mutually, carries out iterative decoding.(external information i.e. the information about some code element values that obtains of the restriction relation of all other code elements that belong to a code word by code word, and adopting external information is positive feedback to occur in iterative process alternately.) current, the interpretation method of ILDPC sign indicating number mainly contains two kinds.

Method one is and long-pending interpretation method.The log-likelihood value that is input as receiving sequence of this method, and to carrying out iterative decoding by the restriction relation of utilizing bit node and check-node under the number space.At this moment, the restriction relation of bit node show as " with " form, i.e. the output of each bit node be each input log-likelihood value and; Corresponding check-node then shows as the form that certain " amasss ", i.e. the output of each check-node is certain " continued product " of each input log-likelihood value.Because these characteristics, this method is referred to as and amasss interpretation method.

With the information transmission system under the binary input additive white gaussian noise channels is example, and length is weaved into the ILDPC code word that length is the N bit for the binary message sequence of N-M bit by the ILDPC encoder.Subsequently, this code word is modulated into value and transmits in Gaussian channel for ± 1 symbol sebolic addressing.At receiving terminal, receiver is through sequence of real numbers R that to have obtained a string length that contains noise jamming after the matched filtering be N₁^N, carry out the signal demodulation subsequently.Gaussian channel, BPSK modulation down, i code element be 1 and through modulation and after transmitting receiver receive that signal is R_iProbability be:

$P\left(R_i\right|v_i=1)=\frac{1}{\sqrt{{2\mathrm{\π\σ}}^2}}\exp \{-\frac{1}{{2\mathrm{\σ}}^2}{(R_i-1)}^2\},1\≤i\≤N--\left(5\right)$

σ wherein²Standard variance for interchannel noise.

Equally, i code element be 0 and after modulation and transmission receiver receive that signal is R_iProbability be:

$P\left(R_i\right|v_i=0)=\frac{1}{\sqrt{{2\mathrm{\π\σ}}^2}}\exp \{-\frac{1}{{2\mathrm{\σ}}^2}{(R_i+1)}^2\},1\≤i\≤N--\left(6\right)$

By Bayes' theorem, obtain:

$P(v_i=1|R_i)=\frac{P\left(R_i\right|v_i=1)\·P(v_i=1)}{P\left(R_i\right)},--\left(7\right)$

$P(v_i=0|R_i)=\frac{P\left(R_i\right|v_i=0)\·P(v_i=0)}{P\left(R_i\right)}.--\left(8\right)$

In process of transmitting, symbol is got 0 and 1 probability and is equated.For the ease of the output of restituted signal, adopt the form of log-likelihood ratio to represent the maximum a posteriori probability of i code element value receiving usually:

$\mathrm{LLR}\left(R_i\right)=\ln \frac{P(v_i=+1|R_i)}{P(v_i=-1|R_i)}--\left(9\right)$

By above various:

$\mathrm{LLR}\left(R_i\right)=\ln \frac{P(v_i=+1|R_i)}{P(v_i=-1|R_i)}=\ln \frac{P\left(R_i\right|v_i=+1)}{P\left(R_i\right|v_i=-1)}$

$=\mathrm{<figure-callout\; label="ln"\; filenames="C0214864900192.png"\; state="\{\{state\}\}">ln</figure-callout>}\frac{\frac{1}{\sqrt{{2\mathrm{\&pi;\&sigma;}}^2}}\exp \{-\frac{1}{{2\mathrm{\&sigma;}}^2}{(R_i-1)}^2\}}{\frac{1}{\sqrt{{2\mathrm{\&pi;\&sigma;}}^2}}\exp \{-\frac{1}{{2\mathrm{\&sigma;}}^2}{(R_i+1)}^2\}}=\frac{2}{{\mathrm{\&sigma;}}^2}{R}_i$

$=\mathrm{sign}\left(R_i\right)\&CenterDot;\left|\frac{2}{{\mathrm{\&sigma;}}^2}{R}_i\right|$

Sign () is a sign function in the formula.In the following formula, first sign function represented the comparative result of the former transmission signal value probability that obtained by received signal.It is that 1 probability is greater than the probability that is 0 that sign function is got on the occasion of the former symbol of expression; Get negative value and represent that then former symbol is that 0 probability is greater than the probability that is 1.The size of second absolute value has represented that then this symbol gets 1 probability and get difference degree between 0 the probability.Absolute value is big more, and then the difference of two probable values is big more.Therefore, (10) formula provides two information according to each received signal, and which value is an information get for the original signal most probable, and another information has then been represented the degree of reliability of this judgement.This demodulating process of receiver has fully kept the information of original signal, is called as " soft demodulation ", and perhaps " soft-decision ", corresponding soft-decision output is called " soft information ".

The soft information of demodulator output is sent to the ILDPC decoder and deciphers.The decoding of ILDPC decoder has made full use of the supersparsity characteristic of check matrix, the restriction relation of check matrix is decomposed into the capable check code restriction relation and the duplication code restriction relation of row, by utilizing the mutual feedback of these two kinds of restriction relations, carry out iterative decoding.For the ease of understanding the decode procedure under these two kinds of restriction relations, the decode procedure of duplication code and check code is discussed at first below.

1) restriction relation of duplication code and decoding thereof:

The coding of duplication code promptly be will input information symbol carry out N-1 repetition, longly be the code word V of N thereby obtain one₁^NTherefore, duplication code has only two legal-codes: complete 0 code word 0₁^NWith all-ones word 1₁^NAfter ovennodulation, transmission, demodulation, decoder is deciphered according to the soft information that modulator provides.At the burst that receives is R₁^NPrerequisite under, decipher according to the restriction relation of duplication code, obtain an output sequence U who adopts log-likelihood ratio to represent₁^NWherein, the log-likelihood ratio of i symbol maximum a posteriori probability value is:

$\mathrm{LLR}\left(u_i\right)=\ln \frac{p(v_i=1|R_1^N)}{p(v_i=0|R_1^N)}=\ln \frac{p(v_i=1,R_1^N)}{p(v_i=0,R_1^N)}$

$=\ln \frac{{\mathrm{\&Sigma;}}_{\underset{i^{\&prime;}\&NotEqual;i}{1\&le;i^{\&prime;}\&le;N}}\&CenterDot;\&CenterDot;\&CenterDot;\mathrm{\&Sigma;p}(v_1,v_2,\&CenterDot;\&CenterDot;\&CenterDot;,v_i=1,\&CenterDot;\&CenterDot;\&CenterDot;,v_N,R_1^N)}{{\mathrm{\&Sigma;}}_{\underset{i^{\&prime;}\&NotEqual;i}{1\&le;i^{\&prime;}\&le;N}}\&CenterDot;\&CenterDot;\&CenterDot;\mathrm{\&Sigma;p}(v_1,v_2,\&CenterDot;\&CenterDot;\&CenterDot;,v_i=0,\&CenterDot;\&CenterDot;\&CenterDot;,v_N,R_1^N)}$

$=\ln \frac{{\mathrm{\&Sigma;}}_{\underset{i^{\&prime;}\&NotEqual;i}{v_{i^{\&prime;}}\&Element;{V_1}^N}}\&CenterDot;\&CenterDot;\&CenterDot;\mathrm{\&Sigma;p}(v_1,v_2,\&CenterDot;\&CenterDot;\&CenterDot;,v_i=1,\&CenterDot;\&CenterDot;\&CenterDot;,v_N)\&CenterDot;p\left(R_1^N\right|v_1,v_2,\&CenterDot;\&CenterDot;\&CenterDot;,v_i=1,\&CenterDot;\&CenterDot;\&CenterDot;,v_N)}{{\mathrm{\&Sigma;}}_{\underset{i^{\&prime;}\&NotEqual;i}{v_{i^{\&prime;}}\&Element;V_1^N}}\&CenterDot;\&CenterDot;\&CenterDot;\mathrm{\&Sigma;p}(v_1,v_2,\&CenterDot;\&CenterDot;\&CenterDot;,v_i=0,\&CenterDot;\&CenterDot;\&CenterDot;,v_N)\&CenterDot;p\left(R_1^N\right|v_1,v_2,\&CenterDot;\&CenterDot;\&CenterDot;,v_i=0,\&CenterDot;\&CenterDot;\&CenterDot;,v_N)}--\left(11\right)$

Because duplication code has only complete 0 and complete 1 two code words, thereby first in the molecule denominator product term is only when code word is respectively all-ones word and complete 0 code word in the following formula, and probability just is not 0.Thereby (11) formula can continue abbreviation and be:

$\mathrm{LLR}\left(u_i\right)=\ln \frac{p\left(R_1^N\right|V_1^N=1_1^N)}{p\left(R_1^N\right|V_1^N=0_1^N)}=\ln \frac{\underset{i^{\&prime;}=1}{\overset{N}{\mathrm{\&Pi;}}}p\left(R_{i^{\&prime;}}\right|v_{i^{\&prime;}}=1)}{\underset{i^{\&prime;}=1}{\overset{N}{\mathrm{\&Pi;}}}p\left(R_{i^{\&prime;}}\right|v_{i^{\&prime;}}=0)}--\left(12\right)$

$=\underset{i^{\&prime;}}{\overset{N}{\mathrm{\&Sigma;}}}\mathrm{LLR}\left(v_{i^{\&prime;}}\right)=\mathrm{LLR}\left(v_i\right)+\underset{i^{\&prime;}\&NotEqual;i}{\mathrm{\&Sigma;}}\mathrm{LLR}\left(v_{i^{\&prime;}}\right)$

Result's first is the log-likelihood ratio of code element i received signal in the following formula, and the information for code element itself is had is called " prior information "; Second portion is that other code element is called " external information " according to the value information about code element i that the restriction relation of code word provides in the code word.Because prior information just has for each code element itself, thereby decoder only need be given the corresponding external information of each symbol feedback in decode procedure.The decoding relation of duplication code can adopt a node diagram shown in Figure 1 to represent.

Node among Fig. 1 has N bar tie line, a corresponding N code element.These tie lines both can be used as input and also can be used as output, respectively the input of a corresponding N code element and decoding output.In decode procedure, contact is received the demodulating information sequence of representing with the form of log-likelihood ratio by N bar tie line, and subsequently, by the computing of node, decode results is the external information by N code element of these tie lines outputs also.Wherein, every tie line be output as other each bar tie line input value add up and.In the description to the decoding of ILDPC sign indicating number, this decoding node of duplication code is also referred to as " bit node ".

2) restriction relation of check code and decoding thereof:

The check code that with the code check is N-1/N is an example, the check code that it is N that long information sequence for N-1 bit obtains a code length after through coding, and the restriction relation between the code element can be represented with following relational expression:

v₁v₂…v_N＝0 (13)

In the formula represent binary system and, i.e. distance in the binary logic.The code word V of check code gained₁^NAfter ovennodulation, transmission, demodulation, obtain comprising a soft information sequence LLR (R of this codeword information₁^N).Check code decoder is promptly deciphered according to this soft information sequence.Define two metasymbol e_iFor in the code word except i code element v_iThe binary system of outer other all code elements and, then by (13) Shi Kede:

v_ie_i＝0 (14)

By binary XOR relation and (14) formula, get code element v_iWith symbol e_iValue is identical.Thereby, code element v_iWith symbol e_iForm a relation that is equivalent to duplication code.The result that obtains is discussed as can be known by top duplication code, code element v_iBy the posterior information of deciphering the back gained be:

$\mathrm{LLR}\left({\hat{v}}_i\right)=\mathrm{LLR}\left(v_i\right)+\mathrm{LLR}\left(e_i\right)--\left(15\right)$

Obviously, second in (15) formula is exactly in decode procedure decoder and feeds back to code element v according to the restriction relation of whole sign indicating number sequence_iExternal information.Below, we are that 3 check code is an example with code length, the expression of derivation external information.Be without loss of generality, we discuss the external information expression of first code element.At code length is under the situation of 3 bits, symbol e₁Value is that 1 probability is:

p(e₁＝1)＝p(v₂＝1)·p(v₃＝0)+p(v₂＝0)·p(v₃＝1)

＝p(v₂＝1)·(1-p(v₃＝1))+(1-p(v₂＝1))·p(v₃＝1) (16)

＝p(v₂＝1)+p(v₃＝1)-2p(v₂＝1)·p(v₃＝1)

Thereby,

1-2p(e₁＝1)＝1-2p(v₂＝1)-2p(v₃＝1)+4p(v₂＝1)·p(v₃＝1) (17)

＝(1-2p(v₂＝1))·(1-2p(v₃＝1))

Introduce a function:

$\mathrm{\&Phi;}\left(x\right)=\tanh (-\frac{1}{2}x)=\frac{\exp (-\frac{1}{2}x)-\exp \left(\frac{1}{2}x\right)}{\exp (-\frac{1}{2}x)+\exp \left(\frac{1}{2}x\right)}=\frac{1-\exp \left(x\right)}{1+\exp \left(x\right)}--\left(18\right)$

So,

$\mathrm{\&Phi;}\left(\mathrm{LLR}\left(e_1\right)\right)=\mathrm{\&Phi;}\left(\ln \frac{p({\mathrm{<figure-callout\; label="e"\; filenames="C0214864900192.png"\; state="\{\{state\}\}">e</figure-callout>}}_1=1)}{p({\mathrm{<figure-callout\; label="e"\; filenames="C0214864900192.png"\; state="\{\{state\}\}">e</figure-callout>}}_1=0)}\right)=\frac{1-\exp \left(\ln \frac{p({\mathrm{<figure-callout\; label="e"\; filenames="C0214864900192.png"\; state="\{\{state\}\}">e</figure-callout>}}_1=1)}{p({\mathrm{<figure-callout\; label="e"\; filenames="C0214864900192.png"\; state="\{\{state\}\}">e</figure-callout>}}_1=0)}\right)}{1+\exp \left(\ln \frac{p({\mathrm{<figure-callout\; label="e"\; filenames="C0214864900192.png"\; state="\{\{state\}\}">e</figure-callout>}}_1=1)}{p({\mathrm{<figure-callout\; label="e"\; filenames="C0214864900192.png"\; state="\{\{state\}\}">e</figure-callout>}}_1=0)}\right)}=1-2p({\mathrm{<figure-callout\; label="e"\; filenames="C0214864900192.png"\; state="\{\{state\}\}">e</figure-callout>}}_1=1)--\left(19\right)$

By (17), (19) formula, get code element v₁: the external information representation is:

LLR(e₁)＝Φ^-1(Φ(LLR(v₂)·Φ(LLR(v₃)) (20)

(20) formula can be generalized to any one code element, also can be generalized to the situation of code length greater than 3 bits.Get under the situation for the N bit at code length, the external information of code element i is:

$\mathrm{LLR}\left(e_i\right)={\mathrm{\&Phi;}}^{-1}\left(\underset{\underset{i^{\&prime;}\&NotEqual;i}{1\&le;i^{\&prime;}\&le;N}}{\mathrm{\&Pi;}}\mathrm{\&Phi;}\left(\mathrm{LLR}\left(v_i\right)\right)\right)--\left(21\right)$

This decoding operation relation of check code also can adopt a node to represent, as shown in Figure 2:

Node has N tie line among Fig. 2, a corresponding N code element; Every tie line be input also be output.Wherein, input is corresponding to the soft information sequence that is input to decoder, and output then is decoder feeds back to each symbol by computing external information.In once deciphering, every tie line is imported the soft information that obtains after this symbol demodulation and is arrived node, by computing, gives each tie line an external information output with posterior nodal point.Notice that the output of every tie line is with the input value of other all tie lines operation result as input among Fig. 2.In the decoding of follow-up ILDPC sign indicating number, this decoding node of check code is called as " check-node ".

3) decoding of ILDPC sign indicating number:

After the coding of information sequence process ILDPC sign indicating number, modulation, the transmission, carry out matched filtering, comprised the receiving sequence R of ILDPC codeword information accordingly by receiver₁^N, this sequence is sent to the ILDPC code decoder and carries out error-correcting decoding subsequently.In decode procedure, decoder at first carries out demodulation to receiving sequence, receiving sequence is converted into the form of soft information; Subsequently, utilize the check equations HV of ILDPC sign indicating number^T=0 deciphers.The check matrix of noticing the ILDPC sign indicating number is the supersparsity matrix, and the nonzero element number of every row/row is very rare.Know by check equations, the product of the every capable ILDPC sign indicating number of matrix, be actually the code element that multiplies each other with this row nonzero element binary system and.By the constraint equation of check code as can be known, these code elements have constituted the constraint of a check code.Because check matrix has M capable, thereby can obtain M check code altogether.By adopting the interpretation method of check code, each check code can be given the external information output of this code element value condition of a reflection of each code element under restriction relation separately.And for each row of check matrix because its element only multiplies each other with same code element in the multiplication of check matrix and code word, and each nonzero element that should row all check code of correspondence to the output of this symbol value condition.So the output of these check codes has constituted the constraint of a duplication code with the soft information of the code element that receives.Since the total N row of check matrix, thereby can obtain N duplication code, corresponding with N code element of ILDPC code word respectively.The decoding of ILDPC sign indicating number promptly is the restriction relation that is decomposed into this M check code and N duplication code by the restriction relation with check matrix, exports the input that is fed back to the other side mutually by the decoding of these two kinds of sign indicating numbers, carries out parallel iteration decoding.By above discussion about duplication code and check code, the decoding grid chart of ILDPC sign indicating number can be represented by Fig. 3:

At first, after the decoded device of receiving sequence was converted into soft information, decoder was made as 0 with the initial output of all check-nodes, decoding when carrying out N bit node according to the initial output of the soft information of receiving sequence and check-node subsequently.These bit nodes are to the external information output of each code element, delivered to corresponding check-node by tie line, M node carries out the decoding of check code simultaneously subsequently, and the decoding output to each symbol of each check-node all feeds back to relevant bit node by tie line.When next iteration began, each bit node all added up own all inputs, obtains the posterior information of a code element, carries out Hard decision decoding according to this posterior information subsequently.The Hard decision decoding of N bit node obtains the valuation information sequence of a code word.If the product of check matrix and this valuation information sequence is zero, then decoder stops iterative decoding and exports this valuation as decode results; Otherwise decoder carries out the decoding iteration of bit node one check-node next time, up to gained valuation sequence be a legal ILDPC code word or reach maximum iteration time till.Decoder is output as the hard decision valuation sequence that obtains for the last time.

If r_IjFor output to the external information of bit node i, q from check-node j_IjBe external information from bit node i to check-node j, should and the iterative process of long-pending interpretation method comprise the steps:

1) decoding initialization: for the sequence of real numbers R that receives₁^N, the initial reception of corresponding i code element of ILDPC sign indicating number is worth the form that decoded device is demodulated to log-likelihood ratio:

$\mathrm{LLR}\left(R_i\right)=\frac{2}{{\mathrm{\&sigma;}}^2}{R}_i,1\&le;i\&le;N--\left(22\right)$

LLR represents that value is a log-likelihood ratio in the formula, σ²Standard variance for interchannel noise.Simultaneously, check-node without any the information about code word so the external information that check-node j outputs to bit node i is set is under the initial condition:

LLR(r_ij)＝0 (23)

2) if the hard decision result of resulting sequence is not that (wherein hard decision is meant that log-likelihood value according to each symbol of sequence determines the bit value of each symbol to a legal code word, the log-likelihood value be positive number then code element get symbol " 1 ", for negative then code element get symbol " 0 "), carry out once and the iterative process of long-pending decoding is:

A) decoding of bit node: under the restriction relation of this node, output with the input the pass be " with " relation, promptly bit node i is output as to the external information of check-node j:

$\mathrm{LLR}\left(q_{\mathrm{ij}}\right)=\underset{\underset{j^{\&prime;}\&NotEqual;j}{j^{\&prime;}\&Element;\mathrm{Col}\left[i\right]}}{\mathrm{\&Sigma;}}\mathrm{LLR}\left(r_{{\mathrm{ij}}^{\&prime;}}\right)+\mathrm{LLR}\left(R_i\right)--\left(24\right)$

Col[i in the formula] location sets of expression check matrix H i row nonzero element.

B) decoding of check-node: under the restriction relation of check-node, output is certain relation of " amassing " with the pass of input, and promptly check-node j outputs to the external information of bit node i and is:

$\mathrm{LLR}\left(r_{\mathrm{ij}}\right)={\mathrm{\&Phi;}}^{-1}\left(\underset{\underset{i^{\&prime;}\&NotEqual;i}{i^{\&prime;}\&Element;\mathrm{Row}\left[j\right]}}{\mathrm{\&Pi;}}\mathrm{\&Phi;}\left(\mathrm{LLR}\left(q_{i^{\&prime;}j}\right)\right)\right)--\left(25\right)$

Row[j in the formula] location sets of expression check matrix H j capable nonzero element, and

$\mathrm{\&Phi;}\left(x\right)=\tanh (-\frac{1}{2}x)--\left(26\right)$

3) after the iteration decode results of i bit node of gained be these all inputs of node and:

$\mathrm{LLR}\left({\hat{v}}_i\right)=\underset{j^{\&prime;}\&Element;\mathrm{Col}\left[i\right]}{\mathrm{\&Sigma;}}\mathrm{LLR}\left(r_{{\mathrm{ij}}^{\&prime;}}\right)+\mathrm{LLR}\left(R_i\right)--\left(27\right)$

Resulting decode results is carried out following hard decision, transferred to for second step then.Wherein the hard decision of i symbol is:

4) carry out the decoding of next code word if desired, jump to the first step; Otherwise, finish decoding.

Notice that this interpretation method has made full use of the character of bit node and check-node, and all information of receiving sequence, thereby can obtain decoding performance preferably that the convergence in the iterative process simultaneously is also than comparatively fast.But when code length long (more than 10000 bits), the operand of this method is still very big, is difficult to use in real system.

The interpretation method of another kind of ILDPC sign indicating number is minimum and interpretation method.The decode procedure of this method is to similar with long-pending decoding algorithm, under the constraint of bit node output with input still be " with " relation, be reduced to the continued product of symbol and get the minimum relation of importing absolute value but the relation of check-node is then approximate:

$\mathrm{LLR}\left(r_{\mathrm{ij}}\right)=\underset{\underset{i^{\&prime;}\&NotEqual;i}{i^{\&prime;}\&Element;\mathrm{Row}\left[j\right]}}{\min }\left|\mathrm{LLR}\left(q_{i^{\&prime;}j}\right)\right|\&CenterDot;\underset{\underset{i^{\&prime;\&NotEqual;i}}{i^{\&prime;}\&Element;\mathrm{Row}\left[j\right]}}{\mathrm{\&Pi;}}\mathrm{sgn}\left(\mathrm{LLR}\left(q_{i^{\&prime;}j}\right)\right)--\left(29\right)$

By adopting this approximate interpretation method, the computation complexity of decode procedure obtains bigger simplification.But, owing in the computing of check-node, adopted operate approximately, lost more information, make error-correcting performance significantly decrease.Under the situation of low signal-to-noise ratio, the convergence rate of this method is very slow, compares with method one, and the reduction of operand is not obvious, and performance has significant decline.

Summary of the invention

The objective of the invention is to overcome the deficiencies in the prior art part, proposed a kind of correction and long-pending interpretation method.This method has noticed that the ILDPC sign indicating number has the characteristics of unequal loss protection Cheng Du for same order bit node not; the protection degree of one-tenth that is ILDPC sign indicating number bit node improves along with the raising of node exponent number, makes that the mistake of higher order bits node often is repaired prior to the mistake of low order node in the process of iterative decoding.The present invention is by utilizing this specific character of ILDPC sign indicating number, the iterative decoding of higher order bits node is just finished when finishing the error correction of this rank node, and the iterative decoding of low order node is proceeded, thereby has simplified the computation complexity of successive iterations decoding.Simultaneously, when higher order bits node iteration finishes, because the erroneous level of resulting decode results is far below the erroneous level of whole sequence, the present invention provides more useful information for the low order node by the decode results of higher order bits node is amplified.Under the condition of high s/n ratio, this method can obtain than standard and the better error-correcting performance of long-pending interpretation method.Thereby, the present invention with the much smaller decoding complexity of relative said method one with the much higher error-correcting performance of relative method two, realized the decoding of ILDPC sign indicating number.

The invention is characterized in; the characteristic that it utilizes the degree of protection of ILDPC sign indicating number bit node to improve along with the raising of node exponent number; in iterative decoding; the iterative decoding of higher order bits node is just finished when finishing the error correction of this rank node; and the iterative decoding of low order node is proceeded; to simplify the computation complexity of successive iterations decoding, particularly, it contains successively and has the following steps:

(1) decoding beginning is input to bit node to receiving sequence, and the iteration end parameter of each rank bit node is set according to the noise size simultaneously$K_s\left(\mathrm{\&sigma;}\right)=\{k_2\left(\mathrm{\&sigma;}\right),k_3\left(\mathrm{\&sigma;}\right),\&CenterDot;\&CenterDot;\&CenterDot;,k_{d_v}\left(\mathrm{\&sigma;}\right)\},$The decoding iterations is changed to 0;

(2) decoder calculates the hard decision output of each rank bit node and delivers to the codeword detection node;

Whether (3) detect the hard decision sequence is a legal-code:

If, the decode results of each rank bit node of output residue, decoding finishes;

If not, then carry out next step;

(4) carry out the next iteration process: if iterations k_l(σ)＜k＜k_L-1(σ) (l=3,4 ..., d_v+ 1) carry out following step (4.1), (4.2):

(4.1) decoding of bit node: the external information from bit node i to check-node j is output as:

$\mathrm{LLR}\left(q_{\mathrm{ij}}\right)=\underset{\underset{j^{\&prime;}\&NotEqual;j}{j^{\&prime;}}\&Element;\mathrm{Col}\left[i\right]}{\mathrm{\&Sigma;}}\mathrm{LLR}\left(r_{{\mathrm{ij}}^{\&prime;}}\right)+\mathrm{LLR}\left(R_i\right),1\&le;i\&le;N-\underset{t=1}{\overset{d_v}{\mathrm{\&Sigma;}}}{N}_t;$

(4.2) decoding of check-node: the external information that check-node j outputs to bit node i is:

$\mathrm{LLR}\left(r_{\mathrm{ij}}\right)={\mathrm{\&Phi;}}^{-1}(Q_{\mathrm{ij}}\&CenterDot;\underset{\underset{\underset{i^{\&prime;}\&NotEqual;i}{i^{\&prime;}\&Element;\mathrm{Row}\left[j\right]}}{i\&le;N-\underset{t=l}{\overset{d_v}{\mathrm{\&Sigma;}}}{N}_i}}{\mathrm{\&Pi;}}\mathrm{\&Phi;}\left(\mathrm{LLR}\left(q_{i^{\&prime;}j}\right)\right));$

Otherwise, if k=k_l(σ) (l=2,3 ..., d_v), the iterative step c below carrying out), d):

(4.3) decoding of bit node: the external information output from bit node i to check-node j is used following formula instead and is calculated:

A in the formula₀Be a very big positive integer, be used to amplify q_IjThe log-likelihood value, to provide more useful information to the low step bit node;

(4.4) decoding of check-node: check-node j outputed to the external information of bit node i and was this moment:

$\mathrm{LLR}\left(r_{\mathrm{ij}}\right)={\mathrm{\&Phi;}}^{-1}(Q_{l+1j}\&CenterDot;\underset{\underset{i^{\&prime;}\&NotEqual;i}{\overset{i^{\&prime;}\&le;N-\underset{t=l+1}{\overset{d_v}{\mathrm{\&Sigma;}}}{N}_t}{i^{\&prime;}\&Element;\mathrm{Row}\left[j\right]}}}{\mathrm{\&Pi;}}\mathrm{\&Phi;}\left(\mathrm{LLR}\left(q_{i^{\&prime;}j}\right)\right));$

Finish after these operations, iterations adds 1, repeats (2)～(4) step;

(5) if iterations k=k_l(σ), l is the exponent number of higher order bits node, then:

(5.1) all l rank bit nodes calculate posterior information,

$\mathrm{LLR}\left({\hat{v}}_i\right)=\underset{j^{\&prime;}\&Element;\mathrm{Col}\left[i\right]}{\mathrm{\&Sigma;}}\mathrm{LLR}\left(r_{i{j}^{\&prime;}}\right)+\mathrm{LLR}\left(R_i\right),N-\underset{t=l}{\overset{d_v}{\mathrm{\&Sigma;}}}{N}_t<i\&le;N-\underset{t=l+1}{\overset{d_v}{\mathrm{\&Sigma;}}}{N}_t;$

All l rank bit nodes are done hard decision to the gained posterior information subsequently,

The gained result exports as the last decode results of l rank bit joint;

(5.2) Q of calculating next iteration_Lj:

$Q_{\mathrm{lj}}=Q_{l+1j}\&CenterDot;\underset{\underset{i^{\&prime;}\&Element;\mathrm{Row}\left[j\right]}{N-\underset{t=1}{\overset{d_v}{\mathrm{\&Sigma;}}}}{N}_i<i^{\&prime;}\&le;N-\underset{t=l+1}{\overset{d_v}{\mathrm{\&Sigma;}}}{N}_t}{\mathrm{\&Pi;}}\mathrm{\&Phi;}\left(\mathrm{LLR}\left(q_{i^{\&prime;}j}\right)\right);$

In successive iterations, the decoding of check-node will be adopted Q_LjReplace Q_L+1jCarry out computing, and no longer participate in computing by the numerical value that tie line outputs to check-node from l rank bit node, thus the successive iterations of simplification check-node;

(6) iterations adds 1, changes the next round iteration over to;

(7) whether the judgement iterations is less than k₂(σ);

If then get back to step (2);

If not, the decode results of each rank bit node of then output residue;

(8) whether judgement has next code vector to need decoding:

If have, then get back to step (1);

If do not have, then finish decode procedure.

Evidence: it has reached intended purposes.

Description of drawings

Fig. 1. the decoding node diagram of duplication code.

Fig. 2. the decoding node diagram of check code.

The decoding grid chart of Fig. 3 .ILDPC sign indicating number.

Fig. 4. the program flow diagram of interpretation method of the present invention.

Fig. 5. use the communication system block diagram of transmission error correction of the present invention.

Embodiment

A kind of corrections and long-pending interpretation method that the present invention proposes as shown in Figure 3, suppose that bit node arranges from left to right according to exponent number order from low to high, and then the interpretation method of the present invention's proposition may further comprise the steps:

During the decoding beginning, receiving sequence is input to bit node, and decoder carries out initialization, and the iteration end parameter of each rank bit node is set according to the size of noise simultaneously, and the decoding iterations is changed to 0.Then, decoder calculates the hard decision output of each rank bit node, delivers to node codeword detection node, detects whether the hard decision sequence is a legal-code.If the hard decision series of gained is a legal sign indicating number sequence, then decoding finishes, and exports corresponding hard decision result; Otherwise carry out one time iterative process: all each rank bit nodes calculate the output of each check-node according to the restriction relation of duplication code, deliver to corresponding check-node as input by line between node; Check-node calculates the external information that feeds back to each bit node according to the restriction relation of check code again, and its input as the bit node next iteration.After finishing these computings, iterations adds 1.Whether when next iteration began, each rank bit node calculated hard decision output once more, be a legal sign indicating number sequence by the judgement of codeword detection node subsequently.If a legal-code then finishes the decoding iteration, export corresponding hard decision sequence; Otherwise, carry out one time iterative process.If the current iteration number of times equals k_i(σ), then all l rank bit nodes calculate posterior information, and all l rank bit nodes are with gained posterior information hard decision subsequently, and the gained result exports as the end product of decoding, and these nodes no longer participate in follow-up iterative decoding.Thereby all and the associated check-node of l rank bit node can fall the simplification of corresponding tie line, so that interative computation next time.Finish after these computings, iterations adds 1, changes the next round iteration over to.Obviously, in the worst case, decoder need be finished k₂(σ) inferior iteration.

The principle and the arthmetic statement of the method for the invention are as follows:

1) definition Q_Lj(2≤l≤d_v+ 1) be check matrix j capable in exponent number more than or equal to the product of the bit node log-likelihood value of l, this variable is mainly used in the computing of simplifying check-node in successive iterations.For a known signal to noise ratio standard deviation is σ²Receiving sequence, select one group of iteration to finish parameter$K_s\left(\mathrm{\&sigma;}\right)=\{k_2\left(\mathrm{\&sigma;}\right),k_3\left(\mathrm{\&sigma;}\right),\&CenterDot;\&CenterDot;\&CenterDot;,k_{d_v}\left(\mathrm{\&sigma;}\right)\}$Give each rank bit node; The decoding of initialization simultaneously equation is:

$Q_{d_v+1j}=\mathrm{1,1}\&le;j\&le;M--\left(30\right)$

$\mathrm{LLR}\left(R_i\right)=\frac{2}{{\mathrm{\&sigma;}}^2}{R}_{i,}1<i\&le;N--\left(31\right)$

And

LLR(r_ij)＝0

2) be provided withFor the k time iteration, if k＞k₂(σ), perhaps the Hard decision decoding sequence is a legal sign indicating number sequence, finishes decoding and output hard decision series; Otherwise, carry out following iterative process:

If k_l(σ)＜k＜k_L-1(σ) (l=3,4 ..., d_v+ 1) carry out following step a), b):

A) decoding of bit node: the external information from bit node i to check-node j is output as:

$\mathrm{LLR}\left(q_{\mathrm{ij}}\right)=\underset{\underset{j^{\&prime;}\&NotEqual;j}{j^{\&prime;}\&Element;\mathrm{Col}\left[i\right]}}{\mathrm{\&Sigma;}}\mathrm{LLR}\left(r_{i{j}^{\&prime;}}\right)+\mathrm{LLR}\left(R_i\right),1\&le;i\&le;N-\underset{t=1}{\overset{d_v}{\mathrm{\&Sigma;}}}{N}_t--\left(33\right)$

B) decoding of check-node: the external information that check-node j outputs to bit node i is:

$\mathrm{LLR}\left(r_{\mathrm{ij}}\right)={\mathrm{\&Phi;}}^{-1}(Q_{\mathrm{lj}}\&CenterDot;\underset{\underset{\underset{i^{\&prime;}\&NotEqual;i}{i^{\&prime;}\&Element;\mathrm{Row}\left[j\right]}}{i^{\&prime;}\&le;N-\underset{i=t}{\overset{d_v}{\mathrm{\&Sigma;}}}{N}_t}}{\mathrm{\&Pi;}}\mathrm{\&Phi;}\left(\mathrm{LLR}\left(q_{i^{\&prime;}j}\right)\right))--\left(34\right)$

Otherwise, if k=k_l(σ) (l=2,3 ..., dv), the iterative step below carrying out:

C) decoding of bit node: the external information output from bit node i to check-node j is used following formula instead and is calculated:

A in the formula₀Be a very big positive integer, be used to amplify q_IjThe logarithm value of feeling relieved, to provide more useful information to the low step bit node.A₀Value that can be between 10-1000 specifically depends on the floating-point figure place of decoder.

D) decoding of check-node: check-node j outputed to the external information of bit node i and was this moment:

$\mathrm{LLR}\left(r_{\mathrm{ij}}\right)={\mathrm{\&Phi;}}^{-1}(Q_{l+1j}\&CenterDot;\underset{\underset{\underset{i^{\&prime;}\&NotEqual;i}{i^{\&prime;}\&Element;\mathrm{Row}\left[j\right]}}{i^{\&prime;}\&le;N-\underset{i=l+1}{\overset{d_v}{\mathrm{\&Sigma;}}}}}{\mathrm{\&Pi;}}\mathrm{\&Phi;}\left(\mathrm{LLR}\left(q_{i^{\&prime;}j}\right)\right))--\left(36\right)$

Calculate the Q of next iteration simultaneously_Lj, be used to simplify follow-up iteration:

$Q_{\mathrm{lj}}=Q_{l+1j}\&CenterDot;\underset{\underset{i^{\&prime;}\&Element;\mathrm{Row}\left[j\right]}{N-\underset{t=l}{\overset{d_v}{\mathrm{\&Sigma;}}}}{N}_t<i^{\&prime;}\&le;N-\underset{t=l+1}{\overset{d_v}{\mathrm{\&Sigma;}}}{N}_t}{\mathrm{\&Pi;}}\mathrm{\&Phi;}\left(\mathrm{LLR}\left(q_{i^{\&prime;}j}\right)\right)--\left(37\right)$

E) decode results of l rank bit node is:

$\mathrm{LLR}\left({\hat{v}}_i\right)=\underset{j^{\&prime;}\&Element;\mathrm{Col}\left[i\right]}{\mathrm{\&Sigma;}}\mathrm{LLR}\left(r_{{\mathrm{ij}}^{\&prime;}}\right)+\mathrm{LLR}\left(R_i\right),N-\underset{t=l}{\overset{d_v}{\mathrm{\&Sigma;}}}{N}_t<i\&le;N-\underset{t=l+1}{\overset{d_v}{\mathrm{\&Sigma;}}}{N}_t--\left(38\right)$

At this moment, decoder export corresponding l rank bit node the hard decision result of corresponding code element be

Notice that in an interative computation of standard and long-pending decoding algorithm, an i rank bit node will calculate i²Sub-addition, and a j rank check-node approximately will be carried out j²Inferior floating-point multiplication.Therefore, for the decoding of length for the ILDPC sign indicating number of N bit, one time iteration approximately needs

Sub-addition and generalInferior floating-point multiplication.And when adopting algorithm proposed by the invention, at the k time (k_l(σ)＜k≤k_L-1(σ)) in the iterative process, approximatelySub-addition and average$(\underset{t=l}{\overset{d_v}{\mathrm{\&Sigma;}}}{N}_t\&CenterDot;t)/(\underset{t=2}{\overset{d_v}{\mathrm{\&Sigma;}}}{N}_t\&CenterDot;t)\&CenterDot;\underset{l=2}{\overset{d_c}{\mathrm{\&Sigma;}}}{M}_l\&CenterDot;l^3$Inferior floating-point multiplication is owing to the iteration of higher order bits node finishes to be removed in advance, thereby effectively reduces decoding complexity.In addition, in this algorithm, the log-likelihood value of its gained was exaggerated when the higher order bits node was finished iterative decoding, thereby more useful information was provided for the low order node.Under the condition of high s/n ratio, this method can obtain than standard and the better error-correcting performance of long-pending interpretation method.

Embodiment: present embodiment is to realize the error-correcting decoding method that the present invention proposes with software on Tsing Hua Tong Fang's PC, as shown in Figure 4, may further comprise the steps:

During the decoding beginning, decoder forwards step 4b to from step 4a, and receiving sequence is input to bit node; Decoder is transferred to 4c after finishing this step, and the iteration that each rank bit node is set according to the size of noise finishes parameter, deciphers iterations simultaneously and is changed to 0, and carry out initialization according to (30) (31) (32) formula.Then, decoder is transferred to 4d, calculates the hard decision output of each rank bit node, and 4e judges in step.If the hard decision series of gained is a legal code word, then this time decoding finishes, and jumps to 4l, exports corresponding hard decision result; Otherwise, transfer to 4f, judge whether the current iteration number of times equals k_l(σ).If the current iteration number of times is not equal to k_l(σ), carry out one time iterative process: the output that each rank bit node calculates each node according to (33) formula, deliver to corresponding check-node as input by line between node; Check-node calculates the external information that feeds back to each bit node according to (34) formula again, and its input as the bit node next iteration.After finishing these computings, transfer to step 4j.If the current iteration number of times equals k_l(σ), then transfer to 4h.This moment, bit node calculated external information according to (35) formula, subsequently all l rank bit node finishing iteration and gained decode results hard decision exported; Calculate external information with the associated check-node of l rank bit node according to (36) formula.At step 4i, decoder is simplified check-node according to (37) formula, so that interative computation next time subsequently.Finish after these steps, decoder is transferred to 4j, and iterations adds 1, and judges that at step 4k whether iterations is less than permissible value.If, then jump to 4d, change the next round iteration over to; Otherwise, transfer to step 4l, export the decode results of remaining each rank bit node.After the operation of completing steps 4l, decoder is transferred to step 4m, judges whether decode procedure finishes: if then next step transfers to step 4n, finish decode procedure; Otherwise next step jumps back to step 4b, restarts the decoding of next code vector.

As an example, table 1 and table 2 have listed respectively that an ILDPC sign indicating number adopts and long-pending decoding algorithm and resulting decoding performance of algorithm of the present invention and corresponding calculated complexity under the BIAWGN channel.The major parameter of this ILDPC sign indicating number is: code length equals 10000 bits, and the column weight amount is distributed to be λ (x)=0.23882x+0.29515x²+ 0.03261x³+ 0.43342x¹⁰, row distribution of weight formula is ρ (x)=0.43011x⁶+ 0.56989x⁷By table 1 as seen, under the condition of low signal-to-noise ratio, both error-correcting performances are more or less the same; Under the condition of high s/n ratio, the error-correcting performance of algorithm gained of the present invention is more better than standard and long-pending decoding algorithm.In addition, as known from Table 2, the decoding complexity that method of the present invention is obviously reduces.Wherein addition approximately reduces 45%-70%, and floating-point multiplication has reduced about 25%-40%.

The performance of two kinds of decoding algorithms of table 1. under the BIAWGN channel

Eb/N0(dB)	0.72	0.82	0.91	1.01
					With long-pending decoding algorithm	2.725e-3	5.858e-4	1.364e-4	5.94e-5
Algorithm of the present invention	3.241e-3	6.614e-4	1.474e-4	5.38e-5

The average decoding complexity of two kinds of decoding algorithms of table 2.

As seen, adopt this method can obtain good error-correcting performance, improved the practicality of ILDPC sign indicating number greatly with very low decoding complexity.

With reference to Fig. 5, adopt the communication system of method transmission error correction of the present invention to comprise an information source 51 that produces digital information flow, ILDPC encoder 53, transmission channel 55, and correction error of transmission decoder 57 as shown in Figure 3.In this example, the data symbol stream 52 of the information of carrying that information source 51 produces is sent to ILDPC code coder 53, and 53 pairs of information of ILDPC code coder are carried out chnnel coding.ILDPC code stream 54 behind the coding is interfered in transmission channel 55 transmission courses and produces mistake, and the ILDPC code decoder 57 that the code stream 56 that comprises transmission error is repaired error of transmission receives.Adopt method of the present invention to finish error-correcting decoding through ILDPC code decoder 57, the code stream 58 of output is correct digital information flow.

The application that should be pointed out that the inventive method can also be generalized in the magnetic-memory system goes.

Effect of the present invention is; the unequal error protection characteristic of the not same order bit node by utilizing the ILDPC code; so that the iteration of higher order bits node is than the iteration FEFO of low step bit node, thereby under the prerequisite that does not have the significantly sacrificing decoding performance, decoding complexity is obviously reduced. Compare with existing method one, this method has significantly reduced computation complexity; Compare with existing method two, this method does not have the error-correcting performance of significantly sacrificing ILDPC code. In addition, this method is also amplified by higher order bits node log-likelihood value being carried out appropriateness, so that the low order node has obtained more useful information. Under the condition of high s/n ratio, can obtain ratio method one better error-correcting performance. Therefore, for the decoding of ILDPC code, this method obviously is better than other method.

Claims (1)

1. improved non-rule low density parity check code error-correcting decoding method; contain the non-rule low density parity code and long-pending interpretation method; its the log-likelihood value that is input as receiving sequence and to carrying out iterative decoding by the restriction relation of utilizing bit node and verification contact under the number space; it is characterized in that; the characteristic that it utilizes the degree of protection of non-rule low density parity check code bit node to improve along with the raising of node exponent number; in iterative decoding; the iterative decoding of higher order bits node is just finished when finishing the error correction of this rank node; and the iterative decoding of low order node is proceeded; to simplify the computation complexity of successive iterations decoding; particularly, it contains successively and has the following steps:

(1) decoding beginning is input to bit node to receiving sequence, and the iteration end parameter of each rank bit node is set according to the noise size simultaneously$K_s\left(\mathrm{\&sigma;}\right)=\{k_2\left(\mathrm{\&sigma;}\right),k_3\left(\mathrm{\&sigma;}\right),\&CenterDot;\&CenterDot;\&CenterDot;,k_{d_v}\left(\mathrm{\&sigma;}\right)\},$The decoding iterations is changed to 0;

(2) decoder calculates the hard decision output of each rank bit node and delivers to the codeword detection node;

Whether (3) detect the hard decision sequence is a legal-code:

If, the decode results of each rank bit node of output residue, decoding finishes;

If not, then carry out next step:

(4) carry out the next iteration process: if iterations k_l(σ)＜k＜k_L-1(σ) (l=3,4 ..., d_v+ 1) carry out following step (4.1), (4.2):

(4.1) decoding of bit node: the external information from bit node i to check-node j is output as:

$\mathrm{LLR}\left(q_{\mathrm{ij}}\right)=\underset{\underset{j^{\&prime;}\&NotEqual;j}{j^{\&prime;}\&Element;\mathrm{Col}\left[i\right]}}{\mathrm{\&Sigma;}}\mathrm{LLR}\left(r_{{\mathrm{ij}}^{\&prime;}}\right)+\mathrm{LLR}\left(R_i\right)1\&le;i\&le;N-\underset{t=l}{\overset{d_v}{\mathrm{\&Sigma;}}}{N}_t;$

(4.2) decoding of check-node: the external information that check-node j outputs to bit node i is:

Otherwise, if k=k_l(σ) (l=2,3 ..., d_v), iterative step (4.3), (4.4) below carrying out:

(4.3) decoding of bit node: the external information output from bit node i to check-node j is used following formula instead and is calculated:

A in the formula₀Be a very big positive integer, be used to amplify q_IjThe log-likelihood value, to provide more useful information to the low step bit node;

(4.4) decoding of check-node: check-node j outputed to the external information of bit node i and was this moment:

Finish after these operations, iterations adds 1, repeats (2)～(4) step;

(5) if iterations k=k_l(σ), l is the exponent number of bit node, then:

(5.1) all l rank bit nodes calculate posterior information,

$\mathrm{LLR}\left({\hat{v}}_i\right)=\underset{j^{\&prime;}\&Element;\mathrm{Col}\left[i\right]}{\mathrm{\&Sigma;}}\mathrm{LLR}\left(r_{i{j}^{\&prime;}}\right)+\mathrm{LLR}\left(R_i\right)N-\underset{t=l}{\overset{d_v}{\mathrm{\&Sigma;}}}{N}_t<i\&le;N-\underset{t=l+1}{\overset{d_v}{\mathrm{\&Sigma;}}}{N}_t;$

All l rank bit nodes are done hard decision to the gained posterior information subsequently,

The gained result exports as the last decode results of l rank bit joint;

(5.2) Q of calculating next iteration_Lj:

$Q_{\mathrm{lj}}=Q_{l+1j}\&CenterDot;\underset{\underset{i^{\&prime;}\&Element;\mathrm{Row}\left[j\right]}{N-\underset{t=l}{\overset{d_v}{\mathrm{\&Sigma;}}}{N}_t<i^{\&prime;}\&le;N-\underset{t=l+1}{\overset{d_v}{\mathrm{\&Sigma;}}}{N}_t}}{\mathrm{\&Pi;}}\mathrm{\&Phi;}\left(\mathrm{LLR}\left(q_{i^{\&prime;}j}\right)\right);$

In successive iterations, the decoding of check-node will be adopted Q_LjReplace Q_L+1jCarry out computing, and no longer participate in computing by the numerical value that tie line outputs to check-node from l rank bit node, thus the successive iterations of simplification check-node;

(6) iterations adds 1, changes the next round iteration over to;

(7) whether the judgement iterations is less than k₂(σ);

If then get back to step (2);

If not, the decode results of each rank bit node of then output residue;

(8) whether judgement has next code vector to need decoding:

If have, then get back to step (1);

If do not have, then finish decode procedure.

Images