技术领域Technical Field
本发明属于电路故障诊断技术领域，尤其是涉及一种基于图卷积神经网络的组合逻辑多故障诊断方法及系统。The present invention belongs to the technical field of circuit fault diagnosis, and in particular, relates to a combinational logic multi-fault diagnosis method and system based on graph convolutional neural network.
背景技术Background Art
在芯片规模日益增长的情况下，电子设计自动化（EDA）工具在芯片设计领域中不可或缺。为了尽早检测芯片制造中的缺陷，可测试性设计（DFT）成为重要流程。其中，良率学习阶段的故障诊断是关键步骤，分析量产芯片中的缺陷对良率提升有重要意义。早期故障诊断方法主要基于故障字典和故障失效响应分析。近年来，AI技术也被应用于故障诊断。例如通过将随机向量输入神经网络模型和测试电路，比较输出结果来评分故障；利用人工神经网络（ANN）学习输入向量与故障类型及引线之间的关系。最近的研究使用ANN训练故障诊断模型，学习输入向量与故障检测之间的关系，但未能有效处理组合逻辑多故障的增强和屏蔽关系。因此，基于仿真故障字典生成的训练数据模型无法学习多故障关系，导致对组合逻辑多故障同时存在时的诊断不准确。With the increasing scale of chips, electronic design automation (EDA) tools are indispensable in the field of chip design. In order to detect defects in chip manufacturing as early as possible, design for testability (DFT) has become an important process. Among them, fault diagnosis in the yield learning stage is a key step, and analyzing defects in mass-produced chips is of great significance to improving yield. Early fault diagnosis methods are mainly based on fault dictionaries and fault failure response analysis. In recent years, AI technology has also been applied to fault diagnosis. For example, random vectors are input into neural network models and test circuits, and the output results are compared to score faults; artificial neural networks (ANNs) are used to learn the relationship between input vectors and fault types and leads. Recent studies use ANNs to train fault diagnosis models to learn the relationship between input vectors and fault detection, but fail to effectively handle the enhancement and shielding relationship of multiple faults in combinational logic. Therefore, the training data model generated based on the simulation fault dictionary cannot learn the relationship between multiple faults, resulting in inaccurate diagnosis when multiple faults in combinational logic exist at the same time.
发明内容Summary of the invention
基于上述问题，本发明提供了一种克服上述问题或者至少部分地解决上述问题的一种基于图卷积神经网络的组合逻辑多故障诊断方法及系统，通过故障元素图方法分析随机产生的多故障数据，考虑了多个组合逻辑故障同时存在的情况，并将分析的结果送入图卷积神经网络中训练得到故障诊断模型，从而可以在很短的运行时间内，得到比较准确的故障诊断数据，提高了通过故障诊断模型预测故障发生概率的准确性。Based on the above problems, the present invention provides a combinational logic multi-fault diagnosis method and system based on a graph convolutional neural network that overcomes the above problems or at least partially solves the above problems. The randomly generated multi-fault data are analyzed by the fault element graph method, and the situation where multiple combinational logic faults exist at the same time is considered. The analysis results are sent to the graph convolutional neural network for training to obtain a fault diagnosis model, so that relatively accurate fault diagnosis data can be obtained within a very short running time, thereby improving the accuracy of predicting the probability of fault occurrence through the fault diagnosis model.
根据本发明的第一方面，提供一种基于图卷积神经网络的组合逻辑多故障诊断方法，包括如下步骤：According to a first aspect of the present invention, a combinational logic multi-fault diagnosis method based on a graph convolutional neural network is provided, comprising the following steps:
获取待诊断组合逻辑电路的网表文件并转换为逻辑电路有向图，提取所述逻辑电路有向图中各节点对应的节点特征；Obtaining a netlist file of a combinational logic circuit to be diagnosed and converting it into a directed graph of a logic circuit, and extracting node features corresponding to each node in the directed graph of the logic circuit;
向所述待诊断组合逻辑电路的随机节点位置注入随机数量故障生成随机测试向量，基于所述随机测试向量通过电路仿真模型获取失效响应数据；Injecting a random number of faults into random node positions of the combinatorial logic circuit to be diagnosed to generate a random test vector, and acquiring failure response data through a circuit simulation model based on the random test vector;
基于所述失效响应数据通过故障元素图方法构建故障元素图集合，基于所述故障元素图集合计算故障得分并与对应的故障关联生成故障训练数据；Based on the failure response data, a fault element graph set is constructed by a fault element graph method, and a fault score is calculated based on the fault element graph set and associated with the corresponding fault to generate fault training data;
将所述故障训练数据输入到图卷积神经网络模型中进行迭代训练构建故障诊断模型；Inputting the fault training data into a graph convolutional neural network model for iterative training to construct a fault diagnosis model;
基于所述故障诊断模型对待诊断组合逻辑电路的实时失效响应数据进行诊断，得到每个节点的故障概率。The real-time failure response data of the combinational logic circuit to be diagnosed is diagnosed based on the fault diagnosis model to obtain the failure probability of each node.
上述技术方案中，通过将组合逻辑电路的网表文件转换为逻辑电路有向图，并提取各节点的特征，能够高效地表示电路的结构和属性。此外，利用图卷积神经网络进行故障诊断，能够充分利用组合逻辑电路的结构信息，提高诊断的准确性和效率。通过随机选择节点位置进行故障注入，并生成随机测试向量，能够模拟各种可能的故障情况，从而构建出丰富多样的故障训练数据，使得故障诊断模型能够适应不同类型的故障，并具备较好的泛化能力。基于故障元素图方法迭代更新故障元素图集合，并计算故障得分与对应的故障关联，能够准确地识别出故障节点和故障类型。基于训练好的故障诊断模型，可以实时地对组合逻辑电路的失效响应数据进行诊断，并快速得到每个节点的故障概率，能够在电路故障发生时迅速作出响应，减少故障对系统的影响。In the above technical solution, by converting the netlist file of the combinational logic circuit into a directed graph of the logic circuit and extracting the features of each node, the structure and properties of the circuit can be efficiently represented. In addition, the use of graph convolutional neural networks for fault diagnosis can make full use of the structural information of the combinational logic circuit and improve the accuracy and efficiency of diagnosis. By randomly selecting node positions for fault injection and generating random test vectors, various possible fault conditions can be simulated, thereby constructing a rich and diverse fault training data, so that the fault diagnosis model can adapt to different types of faults and have good generalization capabilities. Based on the fault element graph method, the fault element graph set is iteratively updated, and the fault score is calculated and associated with the corresponding fault, so that the fault node and fault type can be accurately identified. Based on the trained fault diagnosis model, the failure response data of the combinational logic circuit can be diagnosed in real time, and the fault probability of each node can be quickly obtained, so that a quick response can be made when a circuit fault occurs, reducing the impact of the fault on the system.
可选地，在根据本发明的方法中，获取待诊断组合逻辑电路的网表文件并转换为逻辑电路有向图，提取所述逻辑电路有向图中各节点对应的节点特征，包括：Optionally, in the method according to the present invention, obtaining a netlist file of the combinational logic circuit to be diagnosed and converting it into a directed graph of a logic circuit, and extracting node features corresponding to each node in the directed graph of the logic circuit, include:
获取待诊断组合逻辑电路对应的网表文件；Obtaining a netlist file corresponding to the combinational logic circuit to be diagnosed;
基于所述待诊断组合逻辑电路的网表文件构建对应的逻辑电路有向图；Constructing a corresponding logic circuit directed graph based on the netlist file of the combinational logic circuit to be diagnosed;
对所述逻辑电路有向图中的所有节点进行分类得到对应的节点类型，基于所述节点类型对节点进行标记，其中，所述节点类型包括输入节点、输出节点和中间节点；Classifying all nodes in the directed graph of the logic circuit to obtain corresponding node types, and marking the nodes based on the node types, wherein the node types include input nodes, output nodes, and intermediate nodes;
提取每个所述节点的节点特征并进行归一化构建节点特征矩阵。The node features of each node are extracted and normalized to construct a node feature matrix.
上述技术方案中，通过将网表文件转换为逻辑电路有向图，能够提供一个结构化的方式来理解和分析组合逻辑电路，有助于捕捉电路中的逻辑关系和信号流动路径。通过对有向图中的节点进行分类，并基于节点类型进行标记，有助于在后续的故障诊断中区分不同类型的节点。通过提取每个节点的特征并进行归一化处理，可以消除特征之间的量纲差异，使得不同特征在数值上具有可比性，有助于图卷积神经网络模型更好地学习和理解节点的特性，提高诊断的准确性和效率。In the above technical solution, by converting the netlist file into a directed graph of logic circuits, a structured way can be provided to understand and analyze combinational logic circuits, which helps to capture the logical relationships and signal flow paths in the circuits. By classifying the nodes in the directed graph and marking them based on the node type, it helps to distinguish different types of nodes in subsequent fault diagnosis. By extracting the features of each node and normalizing them, the dimensional differences between the features can be eliminated, making different features numerically comparable, which helps the graph convolutional neural network model to better learn and understand the characteristics of the nodes and improve the accuracy and efficiency of diagnosis.
可选地，在根据本发明的方法中，基于所述待诊断组合逻辑电路的网表文件构建对应的逻辑电路有向图，包括：Optionally, in the method according to the present invention, constructing a corresponding logic circuit directed graph based on the netlist file of the combinational logic circuit to be diagnosed includes:
读取所述网表文件识别所述待诊断组合逻辑电路中各组件及各组件之间的连接关系；Reading the netlist file to identify the components in the combinational logic circuit to be diagnosed and the connection relationship between the components;
初始化用于存储节点和有向边的有向数据结构；Initialize directed data structures for storing nodes and directed edges;
遍历所述网表文件中的各组件，分别将各组件映射至所述有向数据结构对应节点得到中间有向图；Traversing each component in the netlist file, and mapping each component to a corresponding node of the directed data structure to obtain an intermediate directed graph;
将所述各组件之间的连接关系添加至所述中间有向图对应的边得到逻辑电路有向图。The connection relationship between the components is added to the corresponding edge of the intermediate directed graph to obtain a logic circuit directed graph.
上述技术方案中，通过将网表文件中的组件及其连接关系映射到有向数据结构中，能够直观地展示组合逻辑电路的结构和信号流向，方式有助于更好地理解电路的工作原理和故障可能发生的位置。在构建逻辑电路有向图的过程中，根据输入到输出的信号流向添加有向边，确保了逻辑电路有向图能够准确地反映组合逻辑电路的实际工作情况。通过遍历网表文件中的组件，并将其映射到有向数据结构中的节点，大大提高了构建逻辑电路有向图的效率。此外，由于逻辑电路有向图是基于数据结构构建的，因此后续对电路的分析和诊断也可以高效地进行。In the above technical solution, by mapping the components and their connection relationships in the netlist file to a directed data structure, the structure and signal flow of the combinational logic circuit can be intuitively displayed, which helps to better understand the working principle of the circuit and the location where the fault may occur. In the process of constructing the directed graph of the logic circuit, directed edges are added according to the signal flow from input to output, ensuring that the directed graph of the logic circuit can accurately reflect the actual working conditions of the combinational logic circuit. By traversing the components in the netlist file and mapping them to the nodes in the directed data structure, the efficiency of constructing the directed graph of the logic circuit is greatly improved. In addition, since the directed graph of the logic circuit is constructed based on the data structure, the subsequent analysis and diagnosis of the circuit can also be carried out efficiently.
可选地，在根据本发明的方法中，提取每个所述节点的节点特征并进行归一化构建节点特征矩阵，包括：Optionally, in the method according to the present invention, extracting the node features of each node and normalizing them to construct a node feature matrix includes:
提取每个节点对应的结构特征和功能特征，所述结构特征至少包括节点的度、邻接节点类型和节点层级，所述功能特征至少包括逻辑功能；Extracting structural features and functional features corresponding to each node, wherein the structural features at least include the degree of the node, the type of adjacent nodes, and the node level, and the functional features at least include the logical function;
分别将所述结构特征和所述功能特征转换为对应的特征编码；Respectively converting the structural features and the functional features into corresponding feature codes;
对所述特征编码中的数值型特征进行归一化，消除各特征编码之间的量纲差异；Normalizing the numerical features in the feature codes to eliminate the dimensional differences between the feature codes;
基于归一化后的所述特征编码作为列，对应的节点作为行构建特征矩阵。A feature matrix is constructed based on the normalized feature codes as columns and the corresponding nodes as rows.
上述技术方案中，通过提取的结构特征和功能特征并转换为对应的特征编码，确保了特征的数字化和可处理性，使得后续图卷积神经网络模型能够直接使用得到的特征。提供了节点的多维信息，有助于更全面地理解节点的性质和在网络中的角色。将特征编码作为列，对应的节点作为行构建特征矩阵，使得整个网络的数据结构能够以一个易于处理的矩阵形式表示，矩阵形式的特征表示方便进行对应的图分析。In the above technical solution, by extracting structural features and functional features and converting them into corresponding feature codes, the digitization and processability of the features are ensured, so that the subsequent graph convolutional neural network model can directly use the obtained features. Providing multi-dimensional information of the nodes helps to more comprehensively understand the nature of the nodes and their roles in the network. The feature matrix is constructed by taking the feature codes as columns and the corresponding nodes as rows, so that the data structure of the entire network can be represented in an easy-to-process matrix form, and the feature representation in matrix form facilitates the corresponding graph analysis.
可选地，在根据本发明的方法中，向所述待诊断组合逻辑电路的随机节点位置注入随机数量故障生成随机测试向量，基于所述随机测试向量通过电路仿真模型获取失效响应数据，包括：Optionally, in the method according to the present invention, injecting a random number of faults into random node positions of the combinatorial logic circuit to be diagnosed to generate a random test vector, and acquiring failure response data through a circuit simulation model based on the random test vector includes:
基于所述节点特征构建待诊断组合逻辑电路对应的电路仿真模型；Constructing a circuit simulation model corresponding to the combinational logic circuit to be diagnosed based on the node characteristics;
通过泊松分布生成用于表示故障的随机数量的随机数；generating a random number representing a random number of failures through a Poisson distribution;
遍历逻辑电路有向图中的所有节点，根据所述随机数量选择对应数量的节点向电路仿真模型注入故障信号；Traversing all nodes in the directed graph of the logic circuit, and selecting a corresponding number of nodes according to the random number to inject fault signals into the circuit simulation model;
基于均匀随机分布法生成随机测试向量，结合所述随机测试向量与注入的故障信号运行电路仿真模型，得到每个随机测试向量对应的失效响应数据。A random test vector is generated based on a uniform random distribution method, and a circuit simulation model is run in combination with the random test vector and an injected fault signal to obtain failure response data corresponding to each random test vector.
上述技术方案中，通过泊松分布生成用于表示故障的随机数量的随机数，可以模拟真实环境中故障发生的随机性，同时遍历逻辑电路有向图中的所有节点，选择对应数量的节点进行故障注入，可以全面覆盖电路的潜在故障点。这种随机性的故障注入方式相较于传统的固定故障注入方法，能够更有效地发现电路中的故障，提高故障诊断的效率。结合均匀随机分布法生成的随机测试向量，可以为电路提供多样化的输入条件，从而触发更多的电路状态变化，多样化的测试向量可以覆盖更广泛的电路行为，使得失效响应数据更加全面和准确，进而增强故障诊断的准确性。通过电路仿真模型进行故障注入和测试，可以避免在真实硬件上进行测试所带来的高成本和高风险。In the above technical solution, random numbers used to represent the random number of faults are generated through Poisson distribution, which can simulate the randomness of faults in the real environment. At the same time, all nodes in the directed graph of the logic circuit are traversed, and the corresponding number of nodes are selected for fault injection, which can fully cover the potential fault points of the circuit. Compared with the traditional fixed fault injection method, this random fault injection method can more effectively discover faults in the circuit and improve the efficiency of fault diagnosis. Combined with the random test vectors generated by the uniform random distribution method, a variety of input conditions can be provided for the circuit, thereby triggering more circuit state changes. The diversified test vectors can cover a wider range of circuit behaviors, making the failure response data more comprehensive and accurate, thereby enhancing the accuracy of fault diagnosis. Fault injection and testing through circuit simulation models can avoid the high cost and high risk of testing on real hardware.
可选地，在根据本发明的方法中，基于所述失效响应数据通过故障元素图方法构建故障元素图集合，基于所述故障元素图集合计算故障得分并与对应的故障关联生成故障训练数据，包括：Optionally, in the method according to the present invention, a fault element graph set is constructed based on the failure response data by a fault element graph method, a fault score is calculated based on the fault element graph set, and fault training data is generated by associating the fault with the corresponding fault, including:
初始化各失效响应数据对应的故障元素图空集合；Initialize an empty set of fault element graphs corresponding to each failure response data;
基于故障元素图方法迭代分析每个失效响应数据对应的故障得到对应的故障元素图；Based on the fault element graph method, iterative analysis is performed on the fault corresponding to each failure response data to obtain the corresponding fault element graph;
根据当前失效响应数据将故障元素图添加至故障元素图空集合中得到故障元素图集合；Add the fault element graph to the empty set of fault element graphs according to the current failure response data to obtain a set of fault element graphs;
结合所述故障元素图确定故障得分并将所述故障得分添加到对应的节点上；determining a fault score in combination with the fault element graph and adding the fault score to a corresponding node;
将各节点的所述故障得分和所述节点特征进行整合得到故障训练数据。The fault score of each node and the node feature are integrated to obtain fault training data.
上述技术方案中，通过故障元素图方法迭代分析每个失效响应数据对应的故障，可以精确地识别出导致电路失效的故障元素（如特定节点或组件），有助于提高故障诊断的准确率，确保诊断结果的可靠性。通过为每个失效响应数据构建对应的故障元素图，并将这些故障元素图整合成故障元素图集合，可以形成一个包含各种故障模式的丰富数据集，这个数据集可以为后续的机器学习或深度学习模型提供充足的训练数据，以提高模型的泛化能力和故障识别能力。结合故障元素图确定故障得分，并将这些得分添加到对应的节点上，可以实现故障的量化评估，量化评估有助于更准确地比较不同故障对电路性能的影响程度。将各节点的故障得分和节点特征进行整合得到故障训练数据，可以实现故障特征与电路结构特征的融合，有助于更全面地描述电路的故障状态，提高机器学习模型对故障模式的识别能力。In the above technical solution, the fault element graph method is used to iteratively analyze the fault corresponding to each failure response data, so that the fault element (such as a specific node or component) that causes the circuit failure can be accurately identified, which helps to improve the accuracy of fault diagnosis and ensure the reliability of the diagnosis result. By constructing a corresponding fault element graph for each failure response data and integrating these fault element graphs into a set of fault element graphs, a rich data set containing various fault modes can be formed. This data set can provide sufficient training data for subsequent machine learning or deep learning models to improve the generalization ability and fault recognition ability of the model. By combining the fault element graph to determine the fault score and adding these scores to the corresponding nodes, a quantitative evaluation of the fault can be achieved, and the quantitative evaluation helps to more accurately compare the degree of influence of different faults on circuit performance. Integrating the fault scores and node features of each node to obtain fault training data can achieve the fusion of fault features and circuit structure features, which helps to more comprehensively describe the fault state of the circuit and improve the ability of the machine learning model to recognize the fault mode.
可选地，在根据本发明的方法中，将所述故障训练数据输入到图卷积神经网络模型中进行迭代训练构建故障诊断模型，包括：Optionally, in the method according to the present invention, the fault training data is input into a graph convolutional neural network model for iterative training to construct a fault diagnosis model, comprising:
设置图卷积神经网络模型的网络结构和模型参数，并进行权重和偏执参数进行初始化，所述模型参数包括层数、节点特征维度和隐藏层维度；Set the network structure and model parameters of the graph convolutional neural network model, and initialize the weights and bias parameters. The model parameters include the number of layers, node feature dimensions, and hidden layer dimensions.
将所述故障训练数据输入所述图卷积神经网络模型中进行前向传播，获取预测故障得分；Inputting the fault training data into the graph convolutional neural network model for forward propagation to obtain a predicted fault score;
基于所述预测故障得分结合节点上的故障得分计算对应的损失函数；Calculate a corresponding loss function based on the predicted fault score combined with the fault score on the node;
基于梯度下降法进行反向传播，计算所述损失函数相对于模型参数的梯度，根据所述梯度更新图卷积神经网络模型的权重和偏执参数；Perform back propagation based on the gradient descent method to calculate the gradient of the loss function relative to the model parameters, and update the weights and bias parameters of the graph convolutional neural network model according to the gradient;
迭代运行前向传播到反向传播的过程，直至达到最大迭代次数得到故障诊断模型，并基于评估指标对所述故障诊断模型进行评估，所述评估指标包括准确率、召回率和F1分数。The process from forward propagation to back propagation is iterated until a maximum number of iterations is reached to obtain a fault diagnosis model, and the fault diagnosis model is evaluated based on evaluation indicators, including accuracy, recall rate and F1 score.
上述技术方案中，图卷积神经网络模型能够捕获节点之间的连接信息和依赖关系，在故障诊断中，使得模型能够学习到电路图中节点的故障特征以及它们之间的传播模式，从而更准确地识别故障。通过迭代训练，图卷积神经网络模型能够逐渐优化其权重和偏置参数，使得预测故障得分与真实故障得分之间的差距最小化，提高了模型的预测能力，使得故障诊断的准确率得以提升。图卷积神经网络模型具有处理复杂图结构的能力，能够应对组合逻辑电路中可能出现的各种复杂故障模式，通过训练模型可以学习到这些故障模式的特征，并在实际诊断中准确识别它们。In the above technical solution, the graph convolutional neural network model can capture the connection information and dependencies between nodes. In fault diagnosis, the model can learn the fault characteristics of the nodes in the circuit diagram and the propagation mode between them, so as to more accurately identify faults. Through iterative training, the graph convolutional neural network model can gradually optimize its weights and bias parameters to minimize the gap between the predicted fault score and the actual fault score, thereby improving the prediction ability of the model and improving the accuracy of fault diagnosis. The graph convolutional neural network model has the ability to process complex graph structures and can cope with various complex fault modes that may occur in combinational logic circuits. The training model can learn the characteristics of these fault modes and accurately identify them in actual diagnosis.
可选地，在根据本发明的方法中，将所述故障训练数据输入到所述图卷积神经网络模型中进行前向传播，获取预测故障得分，包括：Optionally, in the method according to the present invention, inputting the fault training data into the graph convolutional neural network model for forward propagation to obtain a predicted fault score includes:
将故障训练数据中的节点特征矩阵和对应的邻接节点输入到图卷积神经网络模型的图卷积层；Input the node feature matrix and the corresponding adjacent nodes in the fault training data into the graph convolution layer of the graph convolutional neural network model;
通过图卷积层对所述节点特征矩阵和对应的所述邻接节点进行图卷积操作聚合邻接节点的信息，并更新节点特征矩阵；Performing a graph convolution operation on the node feature matrix and the corresponding adjacent nodes through a graph convolution layer to aggregate the information of the adjacent nodes, and updating the node feature matrix;
将更新后的所述节点特征矩阵输入到图卷积神经网络模型的全连接层，转换为预测故障得分。The updated node feature matrix is input into the fully connected layer of the graph convolutional neural network model and converted into a predicted fault score.
上述技术方案中，通过将故障训练数据中的节点特征矩阵和对应的邻接节点输入到图卷积层，图卷积神经网络模型能够充分利用电路图的结构对节点特征矩阵和邻接节点进行图卷积操作，有效地聚合了邻接节点的信息，每个节点的特征不仅取决于其本身的属性，还受到其邻居节点的影响，使得模型能够学习到更丰富的特征表示，从而提高故障诊断的准确性。通过图卷积操作后，节点的特征矩阵得到了更新，反映了节点与其邻接节点之间的交互关系，使得模型能够更好地理解电路中的故障模式。将更新后的节点特征矩阵输入到全连接层，通过非线性变换和激活函数的作用，最终转换为预测故障得分，能够将模型学习到的特征表示转换为具体的诊断结果，使得模型能够直接用于故障检测和定位。In the above technical solution, by inputting the node feature matrix and the corresponding adjacent nodes in the fault training data into the graph convolution layer, the graph convolution neural network model can make full use of the structure of the circuit diagram to perform graph convolution operations on the node feature matrix and adjacent nodes, effectively aggregating the information of adjacent nodes. The characteristics of each node not only depend on its own attributes, but also are affected by its neighboring nodes, so that the model can learn richer feature representations, thereby improving the accuracy of fault diagnosis. After the graph convolution operation, the feature matrix of the node is updated, reflecting the interaction between the node and its adjacent nodes, so that the model can better understand the fault mode in the circuit. The updated node feature matrix is input into the fully connected layer, and through the action of nonlinear transformation and activation function, it is finally converted into a predicted fault score, which can convert the feature representation learned by the model into a specific diagnostic result, so that the model can be directly used for fault detection and location.
可选地，在根据本发明的方法中，基于所述故障诊断模型对待诊断组合逻辑电路的实时失效响应数据进行诊断，得到每个节点的故障概率，包括：Optionally, in the method according to the present invention, diagnosing the real-time failure response data of the combinational logic circuit to be diagnosed based on the fault diagnosis model to obtain the failure probability of each node includes:
获取待诊断组合逻辑电路的实时失效响应数据；Acquire real-time failure response data of the combinational logic circuit to be diagnosed;
将所述实时失效响应数据输入到故障诊断模型，基于所述故障诊断模型获取所述实时失效响应数据对应的故障得分；Inputting the real-time failure response data into a fault diagnosis model, and obtaining a fault score corresponding to the real-time failure response data based on the fault diagnosis model;
基于所述故障得分计算所述实时失效响应数据对应的节点的故障概率。The failure probability of the node corresponding to the real-time failure response data is calculated based on the failure score.
上述技术方案中，通过将待诊断组合逻辑电路的实时失效响应数据输入到已经训练好的故障诊断模型中，由于模型在训练阶段已经学习到了故障特征与故障得分之间的映射关系，因此能够快速地给出每个节点的故障得分，进而计算出故障概率。由于故障诊断模型是基于大量的故障训练数据通过图卷积神经网络进行迭代训练得到的，已经学习到了故障在电路中的传播规律和节点的故障特征。当实时失效响应数据输入到故障诊断模型中时，能够准确地识别出故障模式，并给出相应的故障得分，基于这些故障得分计算出的故障概率具有较高的准确性。In the above technical solution, by inputting the real-time failure response data of the combinational logic circuit to be diagnosed into the trained fault diagnosis model, since the model has learned the mapping relationship between fault characteristics and fault scores during the training stage, it can quickly give the fault score of each node and then calculate the fault probability. Since the fault diagnosis model is obtained by iterative training through a graph convolutional neural network based on a large amount of fault training data, it has learned the propagation law of the fault in the circuit and the fault characteristics of the node. When the real-time failure response data is input into the fault diagnosis model, the fault mode can be accurately identified and the corresponding fault score can be given. The fault probability calculated based on these fault scores has a high accuracy.
根据本发明的又一个方面，提供一种基于图卷积神经网络的组合逻辑多故障诊断系统，包括：According to another aspect of the present invention, a combinational logic multi-fault diagnosis system based on a graph convolutional neural network is provided, comprising:
数据预处理模块，被配置为获取待诊断组合逻辑电路的网表文件并转换为逻辑电路有向图，提取所述逻辑电路有向图中各节点对应的节点特征；A data preprocessing module is configured to obtain a netlist file of a combinational logic circuit to be diagnosed and convert it into a directed graph of a logic circuit, and extract node features corresponding to each node in the directed graph of the logic circuit;
故障注入仿真模块，被配置为向所述待诊断组合逻辑电路的随机节点位置注入随机数量故障生成随机测试向量，基于所述随机测试向量通过电路仿真模型获取失效响应数据；A fault injection simulation module is configured to inject a random number of faults into random node positions of the combinational logic circuit to be diagnosed to generate a random test vector, and obtain failure response data through a circuit simulation model based on the random test vector;
故障训练数据生成模块，被配置为基于所述失效响应数据通过故障元素图方法构建故障元素图集合，基于所述故障元素集合计算故障得分并与对应的故障关联生成故障训练数据；a fault training data generating module, configured to construct a fault element graph set based on the failure response data by a fault element graph method, calculate a fault score based on the fault element set, and generate fault training data by associating the faults with the corresponding faults;
模型训练模块，被配置为将故障训练数据输入到图卷积神经网络模型中进行迭代训练构建故障诊断模型；A model training module is configured to input fault training data into a graph convolutional neural network model for iterative training to build a fault diagnosis model;
故障诊断模块，被配置为基于故障诊断模型对待诊断组合逻辑电路的实时失效响应数据进行诊断，得到每个节点的故障概率。The fault diagnosis module is configured to diagnose the real-time failure response data of the combinational logic circuit to be diagnosed based on the fault diagnosis model to obtain the fault probability of each node.
根据本发明的又一个方面，提供一种计算设备，包括：至少一个处理器；和存储有程序指令的存储器，其中，所述程序指令被配置为适于由所述至少一个处理器执行，所述程序指令包括用于执行所述方法的指令。According to another aspect of the present invention, there is provided a computing device, comprising: at least one processor; and a memory storing program instructions, wherein the program instructions are configured to be suitable for being executed by the at least one processor, and the program instructions include instructions for executing the method.
根据本发明的又一个方面，提供一种存储有程序指令的可读存储介质，当所述程序指令被计算设备读取并执行时，使得所述计算设备执行所述的方法。According to another aspect of the present invention, a readable storage medium storing program instructions is provided. When the program instructions are read and executed by a computing device, the computing device executes the method described above.
根据本发明的方案，将组合逻辑电路的网表文件转换为逻辑电路有向图，提取各节点的特征，能够高效表示电路的结构和属性。利用图卷积神经网络进行故障诊断，利用电路的结构信息，提高诊断的准确性和效率。随机选择节点位置进行故障注入，生成随机测试向量，模拟各种故障情况，构建丰富的故障训练数据，使模型适应不同故障并具备较好的泛化能力。基于故障元素图方法迭代更新故障元素图集合，计算故障得分与关联，准确识别故障节点和类型。训练好的模型可实时诊断电路失效响应数据，快速得出每个节点的故障概率，减少故障对系统的影响。通过映射网表文件中的组件及连接关系到有向数据结构，直观展示电路结构和信号流向，理解工作原理和故障位置。提取特征并进行归一化处理，消除特征量纲差异，方便图卷积神经网络模型学习节点特性。随机故障注入和测试向量生成模拟真实环境，提高故障诊断效率。图卷积神经网络模型捕获节点连接信息和依赖关系，学习故障特征和传播模式，提高识别准确率，通过训练优化参数，提升模型预测能力，实现故障检测和定位。According to the solution of the present invention, the netlist file of the combinational logic circuit is converted into a directed graph of the logic circuit, and the features of each node are extracted, so that the structure and properties of the circuit can be efficiently represented. The graph convolutional neural network is used for fault diagnosis, and the structural information of the circuit is used to improve the accuracy and efficiency of diagnosis. The node position is randomly selected for fault injection, random test vectors are generated, various fault conditions are simulated, and rich fault training data are constructed, so that the model can adapt to different faults and have good generalization ability. The fault element graph set is iteratively updated based on the fault element graph method, the fault score and association are calculated, and the fault node and type are accurately identified. The trained model can diagnose the circuit failure response data in real time, quickly obtain the fault probability of each node, and reduce the impact of the fault on the system. By mapping the components and connection relationships in the netlist file to the directed data structure, the circuit structure and signal flow are intuitively displayed, and the working principle and fault location are understood. The features are extracted and normalized to eliminate the feature dimension differences, which facilitates the graph convolutional neural network model to learn node characteristics. Random fault injection and test vector generation simulate the real environment and improve the efficiency of fault diagnosis. The graph convolutional neural network model captures node connection information and dependencies, learns fault characteristics and propagation patterns, improves recognition accuracy, optimizes parameters through training, enhances model prediction capabilities, and achieves fault detection and location.
上述发明内容仅是本发明技术方案的概述，为了能够更清楚了解本发明的技术手段，而可依照说明书的内容予以实施，并且为了让本发明的上述和其它目的、特征和优点能够更明显易懂，以下特举本发明的具体实施方式。The above invention content is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
通过阅读参照以下附图所作的对非限制性实施例所作的详细描述，本发明的其它特征、目的和优点将会变得更明显。附图仅用于示出优选实施方式的目的，而并不认为是对本发明的限制。而且在整个附图中，用相同的参考符号表示相同的部件。Other features, objects and advantages of the present invention will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings. The drawings are only for the purpose of illustrating preferred embodiments and are not to be considered as limiting the present invention. Also, the same reference symbols are used throughout the drawings to represent the same parts.
图1为本发明公开的一种基于图卷积神经网络的组合逻辑多故障诊断方法的流程图；FIG1 is a flow chart of a combinational logic multi-fault diagnosis method based on a graph convolutional neural network disclosed in the present invention;
图2为本发明实公开的一种基于图卷积神经网络的组合逻辑多故障诊断系统的结构示意图。FIG2 is a schematic diagram of the structure of a combinational logic multi-fault diagnosis system based on a graph convolutional neural network disclosed in the present invention.
具体实施方式DETAILED DESCRIPTION
为使本发明的目的、技术方案以及优点更加清楚明白，下面结合附图和实施例对本发明作进一步详细说明，应当理解的是，此处所描述的具体实施方式仅是本发明的一种最佳实施例，仅用以解释本发明，并不限定本发明的保护范围，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific implementation method described herein is only an optimal embodiment of the present invention, which is only used to explain the present invention and does not limit the scope of protection of the present invention. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.
在更加详细地讨论示例性实施例之前，应当提到的是，一些示例性实施例被描述成作为流程图描绘的处理或方法。虽然流程图将各项操作（或步骤）描述成顺序的处理，但是其中的许多操作（或步骤）可以被并行地、并发地或者同时实施。此外，各项操作的顺序可以被重新安排。当其操作完成时处理可以被终止，但是还可以具有未包括在附图中的附加步骤；处理可以对应于方法、函数、规程、子例程、子程序等等。Before discussing the exemplary embodiments in more detail, it should be mentioned that some exemplary embodiments are described as processes or methods depicted as flow charts. Although the flow charts describe the operations (or steps) as sequential processes, many of the operations (or steps) therein may be performed in parallel, concurrently, or simultaneously. In addition, the order of the operations may be rearranged. A process may be terminated when its operations are completed, but may also have additional steps not included in the accompanying drawings; a process may correspond to a method, function, procedure, subroutine, subprogram, etc.
实施例：Example:
如图1所示，一种基于图卷积神经网络的组合逻辑多故障诊断方法，包括如下步骤：As shown in FIG1 , a combinational logic multi-fault diagnosis method based on a graph convolutional neural network includes the following steps:
S1、获取待诊断组合逻辑电路的网表文件并转换为逻辑电路有向图，提取逻辑电路有向图中各节点对应的节点特征。S1. Obtain a netlist file of the combinational logic circuit to be diagnosed and convert it into a directed graph of the logic circuit, and extract node features corresponding to each node in the directed graph of the logic circuit.
具体地，S1包括如下步骤：Specifically, S1 includes the following steps:
S11、获取待诊断组合逻辑电路对应的网表文件；S11, obtaining a netlist file corresponding to the combinational logic circuit to be diagnosed;
S12、基于待诊断组合逻辑电路的网表文件构建对应的逻辑电路有向图；S12, constructing a corresponding logic circuit directed graph based on the netlist file of the combinational logic circuit to be diagnosed;
S13、对逻辑电路有向图中的所有节点进行分类得到对应的节点类型，基于节点类型对节点进行标记，其中，节点类型包括输入节点、输出节点和中间节点；S13, classifying all nodes in the directed graph of the logic circuit to obtain corresponding node types, and marking the nodes based on the node types, wherein the node types include input nodes, output nodes, and intermediate nodes;
S14、提取每个节点的节点特征并进行归一化构建节点特征矩阵。S14. Extract node features of each node and normalize them to construct a node feature matrix.
可以理解地，本实施例主要对组合逻辑电路进行多故障诊断，本实施例首先获取待诊断组合逻辑电路的网表文件，得到的网表文件包括待诊断组合逻辑电路的逻辑门类型、输入引脚信息、输出引脚信息以及各逻辑门之间的连接关系。It can be understood that this embodiment mainly performs multi-fault diagnosis on combinational logic circuits. This embodiment first obtains the netlist file of the combinational logic circuit to be diagnosed. The obtained netlist file includes the logic gate type, input pin information, output pin information and the connection relationship between each logic gate of the combinational logic circuit to be diagnosed.
具体地，S12包括如下步骤：Specifically, S12 includes the following steps:
S121、读取网表文件识别待诊断组合逻辑电路中各组件及各组件之间的连接关系；S121, reading a netlist file to identify components in the combinational logic circuit to be diagnosed and the connection relationship between the components;
S122、初始化用于存储节点和有向边的有向数据结构；S122, initializing a directed data structure for storing nodes and directed edges;
S123、遍历网表文件中的各组件，分别将各组件映射至有向数据结构对应节点得到中间有向图；S123, traversing each component in the netlist file, and mapping each component to a corresponding node of the directed data structure to obtain an intermediate directed graph;
S124、将各组件之间的连接关系添加至中间有向图对应的边得到逻辑电路有向图。S124. Add the connection relationship between the components to the corresponding edge of the middle directed graph to obtain a logic circuit directed graph.
本实施例中，使用文件读取函数读取网表文件中的包含组合逻辑电路描述的网表文件，根据网表文件的语法和格式信息编写解析器来提取网表文件中的组件信息，组件信息包括逻辑门类型、引脚信息和逻辑门连接关系等。将解析得到的组件信息存储到对应的数据结构中，选择一个适合存储有向图的数据结构，本实施例采用邻接表。初始化一个空的节点集合用于存储有向图中的节点，同理初始化一个空的边集合用于存储有向边。遍历解析得到的组件信息列表，对于每个逻辑门，根据其类型和引脚信息在节点集合中创建一个新的节点实例，并为节点设置一个对应的节点ID，得到只添加了节点信息的中间有向图，遍历组件列表信息中的各逻辑门之间的连接关系，确定起始组件（即输出引脚所在的组件）和终止组件（即输入引脚所在的组件），在邻接表中，为起始节点的条目添加一个指向终止节点的边。遍历完所有连接关系并添加了所有边之后，得到完整的逻辑电路有向图，包含了待诊断组合逻辑电路中的所有组件和各组件之间的连接关系。In this embodiment, a file reading function is used to read a netlist file containing a description of a combinational logic circuit in a netlist file, and a parser is written according to the syntax and format information of the netlist file to extract component information in the netlist file, and the component information includes logic gate type, pin information, and logic gate connection relationship. The component information obtained by parsing is stored in a corresponding data structure, and a data structure suitable for storing a directed graph is selected. In this embodiment, an adjacency list is used. An empty node set is initialized to store nodes in a directed graph, and an empty edge set is initialized similarly to store directed edges. The component information list obtained by parsing is traversed, and for each logic gate, a new node instance is created in the node set according to its type and pin information, and a corresponding node ID is set for the node, so as to obtain an intermediate directed graph with only node information added, and the connection relationship between each logic gate in the component list information is traversed to determine the starting component (i.e., the component where the output pin is located) and the ending component (i.e., the component where the input pin is located). In the adjacency list, an edge pointing to the ending node is added to the entry of the starting node. After traversing all connection relationships and adding all edges, a complete logic circuit directed graph is obtained, which includes all components in the combinational logic circuit to be diagnosed and the connection relationships between the components.
具体地，S14包括如下步骤：Specifically, S14 includes the following steps:
S141、提取每个节点对应的结构特征和功能特征，结构特征至少包括节点的度、邻接节点类型和节点层级，功能特征至少包括逻辑功能；S141, extracting structural features and functional features corresponding to each node, wherein the structural features at least include the degree of the node, the type of adjacent nodes, and the node level, and the functional features at least include the logical function;
S142、分别将结构特征和功能特征转换为对应的特征编码；S142, converting the structural features and the functional features into corresponding feature codes respectively;
S143、对特征编码中的数值型特征进行归一化，消除各特征编码之间的量纲差异；S143, normalizing the numerical features in the feature codes to eliminate the dimensional differences between the feature codes;
S144、基于归一化后的特征编码作为列，对应的节点作为行构建特征矩阵。S144. Construct a feature matrix based on the normalized feature codes as columns and the corresponding nodes as rows.
本实施例中，遍历待诊断组合逻辑电路有向图，统计每个节点的邻接边数量，即为对应节点的度。例如，对于节点A，如果有3条边与其相连，则节点A的度为3。同步地，记录每个节点的所有邻接节点的类型（如AND门、OR门等），将这些类型编码为one-hot向量，以表示不同类型的邻接节点。从逻辑电路的输出节点开始，逐层向内遍历，为每个节点分配一个层级，输出节点为第一层，与输出节点直接相连的节点为第二层，以此类推。根据节点的类型（如AND门、OR门等），确定其逻辑功能。将逻辑功能编码为适当的表示形式，使用二进制编码或one-hot编码进行编码。结构特征编码：对于节点的度，可以直接使用其数值作为特征编码。对于邻接节点类型，使用one-hot编码来表示不同类型的邻接节点。对于节点层级，可以使用其数值或进行适当的编码（如二进制编码）。对于逻辑功能，同理根据具体的逻辑功能使用二进制编码或one-hot编码。例如，如果逻辑功能只有AND、OR和NOT三种，则使用3位的二进制编码（如001表示AND，010表示OR，100表示NOT）。使用min-max归一化方法对于每个数值型特征，找到其在所有节点中的最小值和最大值，然后将该特征的值映射到0和1之间。创建一个空的特征矩阵，其行数与逻辑电路中的节点数相同，列数与归一化后的特征数量相同。遍历逻辑电路中的每个节点，将其对应的归一化后的特征编码作为一行添加到空的特征矩阵中，并确保每个节点的特征编码与特征矩阵中的列正确对应。最终得到用于后续故障诊断的特征矩阵将用于后续的故障诊断过程。本实施例通过遍历逻辑电路图并提取节点的结构和逻辑功能特征，将节点特征编码并归一化后形成特征矩阵，提高了故障诊断的准确性和效率，使得逻辑电路的故障定位和修复更加迅速和准确。In this embodiment, the directed graph of the combinatorial logic circuit to be diagnosed is traversed, and the number of adjacent edges of each node is counted, which is the degree of the corresponding node. For example, for node A, if there are 3 edges connected to it, the degree of node A is 3. Simultaneously, the types of all adjacent nodes of each node (such as AND gate, OR gate, etc.) are recorded, and these types are encoded as one-hot vectors to represent different types of adjacent nodes. Starting from the output node of the logic circuit, traverse inward layer by layer, assign a level to each node, the output node is the first level, the node directly connected to the output node is the second level, and so on. According to the type of the node (such as AND gate, OR gate, etc.), its logical function is determined. The logical function is encoded into an appropriate representation form, and is encoded using binary encoding or one-hot encoding. Structural feature encoding: For the degree of the node, its numerical value can be directly used as the feature encoding. For the type of adjacent node, one-hot encoding is used to represent different types of adjacent nodes. For the node level, its numerical value can be used or appropriate encoding (such as binary encoding) can be performed. For the logical function, binary encoding or one-hot encoding is used according to the specific logical function. For example, if there are only three logical functions, AND, OR, and NOT, a 3-bit binary code is used (such as 001 for AND, 010 for OR, and 100 for NOT). Use the min-max normalization method to find the minimum and maximum values of each numerical feature in all nodes, and then map the value of the feature to between 0 and 1. Create an empty feature matrix with the same number of rows as the number of nodes in the logic circuit and the same number of columns as the number of normalized features. Traverse each node in the logic circuit, add its corresponding normalized feature code as a row to the empty feature matrix, and ensure that the feature code of each node corresponds correctly to the column in the feature matrix. The feature matrix finally obtained for subsequent fault diagnosis will be used in the subsequent fault diagnosis process. This embodiment traverses the logic circuit diagram and extracts the structure and logical function characteristics of the node, encodes the node features and normalizes them to form a feature matrix, thereby improving the accuracy and efficiency of fault diagnosis, making the fault location and repair of the logic circuit faster and more accurate.
S2、向待诊断组合逻辑电路的随机节点位置注入随机数量故障生成随机测试向量，基于随机测试向量通过电路仿真模型获取失效响应数据。S2. Injecting a random number of faults into random node positions of the combinational logic circuit to be diagnosed to generate a random test vector, and obtaining failure response data through a circuit simulation model based on the random test vector.
具体地，S2包括如下步骤：Specifically, S2 includes the following steps:
S21、基于节点特征构建待诊断组合逻辑电路对应的电路仿真模型；S21, constructing a circuit simulation model corresponding to the combinational logic circuit to be diagnosed based on the node characteristics;
S22、通过泊松分布生成用于表示故障的随机数量的随机数；S22. generating a random number for representing a random number of faults through Poisson distribution;
S23、遍历逻辑电路有向图中的所有节点，根据随机数量选择对应数量的节点向电路仿真模型注入故障信号；S23, traversing all nodes in the directed graph of the logic circuit, and selecting a corresponding number of nodes according to the random number to inject fault signals into the circuit simulation model;
S24、基于均匀随机分布法生成随机测试向量，结合随机测试向量与注入的故障信号运行电路仿真模型，得到每个随机测试向量对应的失效响应数据。S24. Generate a random test vector based on a uniform random distribution method, run a circuit simulation model in combination with the random test vector and the injected fault signal, and obtain failure response data corresponding to each random test vector.
本实施例中，首先，从待诊断组合逻辑电路的节点特征中提取每个节点的类型、连接关系等特征。使用电路仿真算法根据提取的节点特征构建电路仿真模型。确保仿真模型能够准确反映逻辑电路的实际行为。根据历史故障数据确定泊松分布的参数λ（表示单位时间内故障的平均发生次数）。使用随机数生成器，根据泊松分布生成一个随机数N，表示当前需要注入的故障数量，对应的故障包括。使用深度优先搜索（DFS）算法遍历逻辑电路有向图中的所有节点，从遍历到的节点中随机选择N个节点作为故障节点，每个节点被选中的概率相同。在仿真模型中，将这些故障节点的输出设置为固定值（如0或1），表示节点发生故障。根据逻辑电路的输入位数，使用均匀随机分布法生成一组随机测试向量。将生成的随机测试向量输入到仿真模型中，并结合之前注入的故障信号运行仿真模型，对于每个随机测试向量，记录仿真模型的输出结果。如果输出结果与无故障情况下的预期结果不同，则认为该测试向量对应的响应数据为失效响应数据。重复生成随机测试向量、运行仿真模型并记录失效响应数据的步骤，直到达到预设的测试次数或满足其他终止条件为止。本实施例通过构建电路仿真模型、随机故障注入、生成随机测试向量和仿真运行，实现了组合逻辑电路的故障注入与检测，能够有效模拟实际故障情况，提高故障诊断的准确性和覆盖率。In this embodiment, first, the type, connection relationship and other features of each node are extracted from the node features of the combinational logic circuit to be diagnosed. A circuit simulation algorithm is used to build a circuit simulation model based on the extracted node features. Ensure that the simulation model can accurately reflect the actual behavior of the logic circuit. Determine the parameter λ of the Poisson distribution (indicating the average number of faults per unit time) based on historical fault data. Use a random number generator to generate a random number N based on the Poisson distribution, which represents the number of faults that currently need to be injected. The corresponding faults include. Use the depth-first search (DFS) algorithm to traverse all nodes in the directed graph of the logic circuit, and randomly select N nodes from the traversed nodes as fault nodes, with the same probability of each node being selected. In the simulation model, the outputs of these faulty nodes are set to fixed values (such as 0 or 1), indicating that According to the number of input bits of the logic circuit, a set of random test vectors are generated using the uniform random distribution method. . The generated random test vector Input into the simulation model, and run the simulation model in combination with the previously injected fault signal, and for each random test vector, record the output result of the simulation model. If the output result is different from the expected result in the fault-free situation, the response data corresponding to the test vector is considered to be failure response data. Repeat the steps of generating random test vectors, running the simulation model, and recording failure response data until the preset number of tests is reached or other termination conditions are met. This embodiment realizes fault injection and detection of combinational logic circuits by constructing a circuit simulation model, random fault injection, generating random test vectors, and simulation running, which can effectively simulate actual fault conditions and improve the accuracy and coverage of fault diagnosis.
S3、基于失效响应数据通过故障元素图方法构建故障元素图集合，基于故障元素图集合计算故障得分并与对应的故障关联生成故障训练数据。S3. Construct a fault element graph set based on the failure response data by using the fault element graph method, calculate the fault score based on the fault element graph set, and associate it with the corresponding fault to generate fault training data.
具体地，S3包括如下步骤：Specifically, S3 includes the following steps:
S31、初始化各失效响应数据对应的故障元素图空集合；S31, initializing an empty set of fault element graphs corresponding to each failure response data;
S32、基于故障元素图方法迭代分析每个失效响应数据对应的故障得到对应的故障元素图；S32, iteratively analyzing the fault corresponding to each failure response data based on the fault element graph method to obtain a corresponding fault element graph;
S33、根据当前失效响应数据将故障元素图添加至故障元素图空集合中得到故障元素图集合；S33, adding the fault element graph to the fault element graph empty set according to the current failure response data to obtain a fault element graph set;
S34、结合故障元素图确定故障得分并将故障得分添加到对应的节点上；S34, determining a fault score in combination with the fault element graph and adding the fault score to the corresponding node;
S35、将各节点的故障得分和节点特征进行整合得到故障训练数据。S35. Integrate the fault score and node features of each node to obtain fault training data.
本实施例中，首先为每一个失效响应数据创建一个用于存储该失效响应数据经过分析后得到的所有可能的故障元素图的故障元素图空集合。从失效响应数据集中逐一读取每个失效响应数据，基于故障传播模型，分析可能导致该失效响应数据的故障源。将确定的故障源以及它们之间的逻辑关系（如AND、OR关系）用图形化的方式表示出来，形成故障元素图。In this embodiment, first, for each failure response data, an empty set of fault element graphs is created to store all possible fault element graphs obtained after the failure response data is analyzed. Each failure response data is read one by one from the failure response data set, and based on the fault propagation model, the fault source that may cause the failure response data is analyzed. The determined fault sources and the logical relationships between them (such as AND and OR relationships) are graphically represented to form a fault element graph.
如果故障元素图包含多个可能的故障源，则对每个可能的故障源进行迭代分析，形成多个不同的故障元素图。将基于当前失效响应数据分析得到的所有故障元素图添加到对应的故障元素图空集合中，形成该失效响应数据的故障元素图集合：If the fault element graph contains multiple possible fault sources, each possible fault source is analyzed iteratively to form multiple different fault element graphs. All fault element graphs obtained based on the current failure response data analysis are added to the corresponding fault element graph empty set to form the fault element graph set of the failure response data. :
。根据故障元素图中每个故障源的出现频率、影响范围等因素，为每个故障源（即节点）计算一个故障得分。计算得出每个节点上故障为失效响应数据的故障得分，若门未在任何一个故障元素中出现，则分数为0。将计算得到的故障得分添加到对应的节点上，作为节点的属性之一。从待诊断组合逻辑电路的电路仿真模型中提取每个节点的特征，如节点类型、连接关系等。将每个节点的故障得分和提取的节点特征进行整合，形成完整的故障训练数据，其中，待诊断组合逻辑电路中共有g个门。得到的故障训练数据用于后续的机器学习模型训练，以实现对组合逻辑电路故障的自动诊断。本实施例通过构建故障元素图、迭代分析故障源、计算故障得分，并整合节点特征与故障得分形成故障训练数据，有效提高了故障诊断的准确性和效率，可实现组合逻辑电路故障的自动诊断，提高了故障检测的智能化水平。 . Calculate a fault score for each fault source (i.e., node) based on the frequency of occurrence, impact range, and other factors of each fault source in the fault element graph. Calculate the fault score of each node where the fault is failure response data. If the gate does not appear in any fault element, the score is 0. Add the calculated fault score to the corresponding node as one of the node's attributes. Extract the features of each node, such as node type, connection relationship, etc., from the circuit simulation model of the combinational logic circuit to be diagnosed. Integrate the fault score of each node with the extracted node features to form complete fault training data , where there are g gates in the combinational logic circuit to be diagnosed. The obtained fault training data is used for subsequent machine learning model training to realize automatic diagnosis of combinational logic circuit faults. This embodiment effectively improves the accuracy and efficiency of fault diagnosis by constructing a fault element graph, iteratively analyzing the fault source, calculating the fault score, and integrating the node features and the fault score to form fault training data, which can realize automatic diagnosis of combinational logic circuit faults and improve the intelligent level of fault detection.
S4、将故障训练数据输入到图卷积神经网络模型中进行迭代训练构建故障诊断模型。S4. Input the fault training data into the graph convolutional neural network model for iterative training to build a fault diagnosis model.
具体地，S4包括如下步骤：Specifically, S4 includes the following steps:
S41、设置图卷积神经网络模型的网络结构和模型参数，并进行权重和偏执参数进行初始化，模型参数包括层数、节点特征维度和隐藏层维度；S41. Setting the network structure and model parameters of the graph convolutional neural network model, and initializing the weights and bias parameters. The model parameters include the number of layers, node feature dimensions, and hidden layer dimensions.
S42、将故障训练数据输入图卷积神经网络模型中进行前向传播，获取预测故障得分；S42, inputting the fault training data into the graph convolutional neural network model for forward propagation to obtain a predicted fault score;
S43、基于预测故障得分结合节点上的故障得分计算对应的损失函数；S43, calculating a corresponding loss function based on the predicted fault score combined with the fault score on the node;
S44、基于梯度下降法进行反向传播，计算损失函数相对于模型参数的梯度，根据梯度更新图卷积神经网络模型的权重和偏执参数；S44, perform back propagation based on the gradient descent method, calculate the gradient of the loss function relative to the model parameters, and update the weights and bias parameters of the graph convolutional neural network model according to the gradient;
S45、迭代运行前向传播到反向传播的过程，直至达到最大迭代次数得到故障诊断模型，并基于评估指标对故障诊断模型进行评估，评估指标包括准确率、召回率和F1分数。S45, iteratively running the process from forward propagation to backward propagation until a maximum number of iterations is reached to obtain a fault diagnosis model, and evaluating the fault diagnosis model based on evaluation indicators, where the evaluation indicators include accuracy, recall rate, and F1 score.
本实施例中，首先设计多层图卷积神经网络模型，例如包含2个图卷积层和1个全连接层。层数设置为3（包括2个图卷积层和1个全连接层），根据故障训练数据中节点特征的维度进行设置，假设为64维。对于图卷积层，设置隐藏层维度为128；对于全连接层，假设输出层为单个节点，因此输出维度为1（表示预测故障得分）。使用随机初始化方法（如Xavier初始化或He初始化）为模型中的权重和偏置参数赋值。将故障训练数据中的故障元素图转换为图卷积神经网络模型能够处理的形式，包括邻接矩阵和节点特征矩阵。将预处理后的数据输入到模型中，经过图卷积层进行特征提取和聚合，最后通过全连接层输出预测故障得分。使用均方误差的损失函数来计算预测故障得分与实际节点故障得分之间的误差，根据计算得到的损失函数值，使用链式法则计算损失函数相对于模型参数的梯度，使用梯度下降法根据计算得到的梯度更新模型的权重和偏置参数，重复执行前向传播、计算损失、反向传播和参数更新的过程，直到达到预设的最大迭代次数，并对训练得到的故障诊断模型进行评估，评估指标包括准确率、召回率和F1分数。准确率表示预测正确的故障数量占所有预测数量的比例，召回率表示预测正确的故障数量占实际故障数量的比例，F1分数表示准确率和召回率的调和平均数，用于综合评估故障诊断模型的性能。本实施例通过设计多层图卷积神经网络模型，并结合故障元素图进行训练，实现了对组合逻辑电路故障的自动诊断，能有效提取节点特征，提高了故障诊断的准确率，并通过综合评估指标全面评估模型性能，为电路故障检测提供了高效智能的解决方案。In this embodiment, a multi-layer graph convolutional neural network model is first designed, for example, including 2 graph convolutional layers and 1 fully connected layer. The number of layers is set to 3 (including 2 graph convolutional layers and 1 fully connected layer), and is set according to the dimension of the node features in the fault training data, assuming 64 dimensions. For the graph convolutional layer, the hidden layer dimension is set to 128; for the fully connected layer, it is assumed that the output layer is a single node, so the output dimension is 1 (indicating the predicted fault score). Use a random initialization method (such as Xavier initialization or He initialization) to assign values to the weights and bias parameters in the model. The fault element graph in the fault training data is converted into a form that can be processed by the graph convolutional neural network model, including an adjacency matrix and a node feature matrix. The preprocessed data is input into the model, feature extraction and aggregation are performed through the graph convolutional layer, and finally the predicted fault score is output through the fully connected layer. The error between the predicted fault score and the actual node fault score is calculated using the mean square error loss function. Based on the calculated loss function value, the chain rule is used to calculate the gradient of the loss function relative to the model parameters. The gradient descent method is used to update the weights and bias parameters of the model based on the calculated gradient. The forward propagation, loss calculation, back propagation and parameter update process are repeated until the preset maximum number of iterations is reached. The trained fault diagnosis model is evaluated, and the evaluation indicators include accuracy, recall and F1 score. The accuracy rate indicates the proportion of the number of correctly predicted faults to the total number of predicted faults, the recall rate indicates the proportion of the number of correctly predicted faults to the actual number of faults, and the F1 score indicates the harmonic mean of the accuracy and recall rate, which is used to comprehensively evaluate the performance of the fault diagnosis model. This embodiment realizes the automatic diagnosis of combinational logic circuit faults by designing a multi-layer graph convolutional neural network model and training it in combination with a fault element graph. It can effectively extract node features, improve the accuracy of fault diagnosis, and comprehensively evaluate the model performance through comprehensive evaluation indicators, providing an efficient and intelligent solution for circuit fault detection.
具体地，S42包括如下步骤：Specifically, S42 includes the following steps:
S421、将故障训练数据中的节点特征矩阵和对应的邻接节点输入到图卷积神经网络模型的图卷积层；S421, inputting the node feature matrix and the corresponding adjacent nodes in the fault training data into the graph convolution layer of the graph convolutional neural network model;
S422、通过图卷积层对节点特征矩阵和对应的邻接节点进行图卷积操作聚合邻接节点的信息，并更新节点特征矩阵；S422, performing a graph convolution operation on the node feature matrix and the corresponding adjacent nodes through a graph convolution layer to aggregate the information of the adjacent nodes, and updating the node feature matrix;
S423、将更新后的节点特征矩阵输入到图卷积神经网络模型的全连接层，转换为预测故障得分。S423. Input the updated node feature matrix into the fully connected layer of the graph convolutional neural network model and convert it into a predicted fault score.
本实施例中，将节点特征矩阵和邻接矩阵作为输入，传入到图卷积神经网络模型的第一个图卷积层，在图卷积层中，执行图卷积操作来聚合每个节点的邻接节点的信息。通过定义一个图卷积核来完成，该图卷积核会在每个节点的邻域内滑动，并根据邻接矩阵中的权重来加权聚合邻接节点的特征。卷积操作对应的公式如下所示：In this embodiment, the node feature matrix and the adjacency matrix are used as input and passed into the first graph convolution layer of the graph convolutional neural network model. In the graph convolution layer, a graph convolution operation is performed to aggregate the information of the adjacent nodes of each node. This is done by defining a graph convolution kernel, which slides within the neighborhood of each node and weights the features of the aggregated adjacent nodes according to the weights in the adjacency matrix. The formula corresponding to the convolution operation is as follows:
； ;
式中：表示邻接矩阵加上单位矩阵，用于包括自环；N表示节点的数量；表示添加了自环后的度矩阵；表示第l层的节点特征矩阵；表示第l层的可训练权重矩阵；表示激活函数。Where: represents the adjacency matrix plus the identity matrix to include self-loops;N represents the number of nodes; represents the degree matrix after adding the self-loop; Represents the node feature matrix of thelth layer; Represents the trainable weight matrix of layerl ; Represents the activation function.
经过图卷积层的处理后，得到了更新后的节点特征矩阵，然后将这个矩阵展平，转换为一维向量，然后输入到全连接层中。全连接层是一个简单的神经网络层，其中的每个节点都与输入层的所有节点相连。在全连接层中，通过权重矩阵和偏置项来进一步变换输入特征，并最终输出预测故障得分。假设全连接层的输出层只有一个节点，该节点的输出即为预测故障得分。使用sigmoid激活函数来确保输出值在0到1之间，以表示故障发生的概率。After being processed by the graph convolutional layer, the updated node feature matrix is obtained, which is then flattened, converted into a one-dimensional vector, and then input into the fully connected layer. The fully connected layer is a simple neural network layer in which each node is connected to all nodes in the input layer. In the fully connected layer, the input features are further transformed through the weight matrix and bias terms, and the predicted fault score is finally output. Assuming that the output layer of the fully connected layer has only one node, the output of this node is the predicted fault score. The sigmoid activation function is used to ensure that the output value is between 0 and 1 to represent the probability of a fault.
S5、基于故障诊断模型对待诊断组合逻辑电路的实时失效响应数据进行诊断，得到每个节点的故障概率。S5. Based on the fault diagnosis model, the real-time failure response data of the combinational logic circuit to be diagnosed is diagnosed to obtain the failure probability of each node.
具体地，S5包括如下步骤：Specifically, S5 includes the following steps:
S51、获取待诊断组合逻辑电路的实时失效响应数据；S51, obtaining real-time failure response data of the combinational logic circuit to be diagnosed;
S52、将实时失效响应数据输入到故障诊断模型，基于故障诊断模型获取实时失效响应数据对应的故障得分；S52, inputting the real-time failure response data into a fault diagnosis model, and obtaining a fault score corresponding to the real-time failure response data based on the fault diagnosis model;
S53、基于故障得分计算实时失效响应数据对应的节点的故障概率。S53. Calculate the failure probability of the node corresponding to the real-time failure response data based on the failure score.
本实施例中，首先获取待诊断组合逻辑电路的实时失效响应数据，将实时失效响应数据输入到故障诊断模型，基于故障诊断模型获取实时失效响应数据对应的故障得分，设定故障得分阈值，当故障诊断模型输出的故障得分超过这个阈值时，待诊断组合逻辑电路对应的节点存在故障，对于每个节点，根据其在故障得分计算过程中的贡献程度来估算其故障概率。通过分析模型在内部计算过程中对该节点的依赖程度进行计算。In this embodiment, firstly, the real-time failure response data of the combinational logic circuit to be diagnosed is obtained, and the real-time failure response data is input into the fault diagnosis model. Based on the fault diagnosis model, the fault score corresponding to the real-time failure response data is obtained, and a fault score threshold is set. When the fault score output by the fault diagnosis model exceeds this threshold, the node corresponding to the combinational logic circuit to be diagnosed has a fault. For each node, its failure probability is estimated according to its contribution in the fault score calculation process. The dependence of the node in the internal calculation process of the analysis model is calculated.
本发明的另一个实施例提供了一种基于图卷积神经网络的组合逻辑多故障诊断系统，图2为其对应系统框图，如图2所示，该系统包括：Another embodiment of the present invention provides a combinational logic multi-fault diagnosis system based on a graph convolutional neural network, and FIG2 is a corresponding system block diagram thereof. As shown in FIG2 , the system includes:
数据预处理模块M01，被配置为获取待诊断组合逻辑电路的网表文件并转换为逻辑电路有向图，提取逻辑电路有向图中各节点对应的节点特征；The data preprocessing module M01 is configured to obtain a netlist file of the combinational logic circuit to be diagnosed and convert it into a directed graph of the logic circuit, and extract node features corresponding to each node in the directed graph of the logic circuit;
故障注入仿真模块M02，被配置为向待诊断组合逻辑电路的随机节点位置注入随机数量故障生成随机测试向量，基于随机测试向量通过电路仿真模型获取失效响应数据；The fault injection simulation module M02 is configured to inject a random number of faults into random node positions of the combinational logic circuit to be diagnosed to generate a random test vector, and obtain failure response data through a circuit simulation model based on the random test vector;
故障训练数据生成模块M03，被配置为基于失效响应数据通过故障元素图方法构建故障元素图集合，基于故障元素图集合计算故障得分并与对应的故障关联生成故障训练数据；A fault training data generating module M03 is configured to construct a fault element graph set based on the failure response data by using a fault element graph method, calculate a fault score based on the fault element graph set, and generate fault training data by associating the fault with the corresponding fault;
模型训练模块M04，被配置为将故障训练数据输入到图卷积神经网络模型中进行迭代训练构建故障诊断模型；The model training module M04 is configured to input the fault training data into the graph convolutional neural network model for iterative training to build a fault diagnosis model;
故障诊断模块M05，被配置为基于故障诊断模型对待诊断组合逻辑电路的实时失效响应数据进行诊断，得到每个节点的故障概率。The fault diagnosis module M05 is configured to diagnose the real-time failure response data of the combinational logic circuit to be diagnosed based on the fault diagnosis model to obtain the fault probability of each node.
在此处所提供的说明书中，算法和显示不与任何特定计算机、虚拟系统或者其它设备固有相关。各种通用系统也可以与本发明的示例一起使用。根据上面的描述，构造这类系统所要求的结构是显而易见的。此外，本发明也不针对任何特定编程语言。应当明白，可以利用各种编程语言实现在此描述的本发明的内容，并且上面对特定语言所做的描述是为了披露本发明的较佳实施方式。In the description provided herein, algorithms and displays are not inherently related to any particular computer, virtual system or other device. Various general purpose systems can also be used together with the examples of the present invention. According to the above description, it is obvious that the structure required for constructing such systems. In addition, the present invention is not directed to any specific programming language either. It should be understood that various programming languages can be utilized to implement the content of the present invention described herein, and the above description of specific languages is for the purpose of disclosing the preferred embodiment of the present invention.
在此处所提供的说明书中，说明了大量具体细节。然而，能够理解，本发明的实施例可以在没有这些具体细节的情况下被实践。在一些实例中，并未详细示出公知的方法、结构和技术，以便不模糊对本说明书的理解。In the description provided herein, a large number of specific details are described. However, it is understood that embodiments of the present invention can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.
类似地，应当理解，为了精简本公开并帮助理解各个发明方面中的一个或多个，在上面对本发明的示例性实施例的描述中，本发明的各个特征有时被一起分组到单个实施例、图、或者对其的描述中。然而，并不应将该公开的方法解释成反映如下意图：即所要求保护的本发明要求比在每个权利要求中所明确记载的特征更多特征。更确切地说，如下面的权利要求书所反映的那样，发明方面在于少于前面公开的单个实施例的所有特征。因此，遵循具体实施方式的权利要求书由此明确地并入该具体实施方式，其中每个权利要求本身都作为本发明的单独实施例。Similarly, it should be understood that in order to streamline the present disclosure and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the present invention, the various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, this disclosed method should not be interpreted as reflecting the following intention: that the claimed invention requires more features than the features explicitly recited in each claim. More specifically, as reflected in the claims below, inventive aspects lie in less than all the features of the individual embodiments disclosed above. Therefore, the claims that follow the specific embodiment are hereby expressly incorporated into the specific embodiment, with each claim itself serving as a separate embodiment of the present invention.
本领域那些技术人员应当理解在本文所公开的示例中的设备的模块或单元或组件可以布置在如该实施例中所描述的设备中，或者可替换地可以定位在与该示例中的设备不同的一个或多个设备中。前述示例中的模块可以组合为一个模块或者此外可以分成多个子模块。Those skilled in the art will appreciate that the modules or units or components of the devices in the examples disclosed herein may be arranged in the devices described in the embodiment, or alternatively may be located in one or more devices different from the devices in the examples. The modules in the foregoing examples may be combined into one module or may be divided into multiple submodules.
本领域那些技术人员可以理解，可以对实施例中的设备中的模块进行自适应性地改变并且把它们设置在与该实施例不同的一个或多个设备中。可以把实施例中的模块或单元或组件组合成一个模块或单元或组件，以及此外可以把它们分成多个子模块或子单元或子组件。除了这样的特征和/或过程或者单元中的至少一些是相互排斥之外，可以采用任何组合对本说明书（包括伴随的权利要求、摘要和附图）中公开的所有特征以及如此公开的任何方法或者设备的所有过程或单元进行组合。除非另外明确陈述，本说明书（包括伴随的权利要求、摘要和附图）中公开的每个特征可以由提供相同、等同或相似目的的替代特征来代替。Those skilled in the art will appreciate that the modules in the devices in the embodiments may be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or components in the embodiments may be combined into one module or unit or component, and further may be divided into a plurality of submodules or subunits or subcomponents. All features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device so disclosed may be combined in any combination, except that at least some of such features and/or processes or units are mutually exclusive. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature that provides the same, equivalent or similar purpose.
此外，本领域的技术人员能够理解，尽管在此所述的一些实施例包括其它实施例中所包括的某些特征而不是其它特征，但是不同实施例的特征的组合意味着处于本发明的范围之内并且形成不同的实施例。例如，在下面的权利要求书中，所要求保护的实施例的任意之一都可以以任意的组合方式来使用。In addition, those skilled in the art will appreciate that, although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present invention and form different embodiments. For example, in the claims below, any one of the claimed embodiments may be used in any combination.
此外，所述实施例中的一些在此被描述成可以由计算机系统的处理器或者由执行所述功能的其它装置实施的方法或方法元素的组合。因此，具有用于实施所述方法或方法元素的必要指令的处理器形成用于实施该方法或方法元素的装置。此外，装置实施例的在此所述的元素是如下装置的例子：该装置用于实施为了实施该发明目的的元素所执行的功能。In addition, some of the embodiments are described herein as a combination of methods or method elements that can be implemented by a processor of a computer system or by other devices that perform the functions. Therefore, a processor with necessary instructions for implementing the method or method elements forms a device for implementing the method or method elements. In addition, the elements described herein of the device embodiments are examples of devices that are used to implement the functions performed by the elements for implementing the purpose of the invention.
如在此所使用的那样，除非另行规定，使用序数词“第一”、“第二”、“第三”等等来描述普通对象仅仅表示涉及类似对象的不同实例，并且并不意图暗示这样被描述的对象必须具有时间上、空间上、排序方面或者以任意其它方式的给定顺序。As used herein, unless otherwise specified, the use of ordinal numbers "first," "second," "third," etc. to describe common objects merely indicates that different instances of similar objects are involved, and is not intended to imply that the objects so described must have a given order in time, space, order, or in any other manner.
尽管根据有限数量的实施例描述了本发明，但是受益于上面的描述，本技术领域内的技术人员明白，在由此描述的本发明的范围内，可以设想其它实施例。此外，应当注意，本说明书中使用的语言主要是为了可读性和教导的目的而选择的，而不是为了解释或者限定本发明的主题而选择的。因此，在不偏离所附权利要求书的范围和精神的情况下，对于本技术领域的普通技术人员来说许多修改和变更都是显而易见的。对于本发明的范围，对本发明所做的公开是说明性的而非限制性的，本发明的范围由所附权利要求书限定。Although the present invention has been described according to a limited number of embodiments, it will be apparent to those skilled in the art, with the benefit of the above description, that other embodiments may be envisioned within the scope of the invention thus described. In addition, it should be noted that the language used in this specification is selected primarily for readability and teaching purposes, rather than for explaining or defining the subject matter of the present invention. Therefore, many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the appended claims. The disclosure of the present invention is illustrative and not restrictive with respect to the scope of the present invention, and the scope of the present invention is defined by the appended claims.
以上之具体实施方式为本发明一种基于图卷积神经网络的组合逻辑多故障诊断方法及系统的较佳实施方式，并非以此限定本发明的具体实施范围，本发明的范围包括并不限于本具体实施方式，凡依照本发明之形状、结构所作的等效变化均在本发明的保护范围内。The above specific implementation is a preferred implementation of a combinational logic multi-fault diagnosis method and system based on a graph convolutional neural network of the present invention. It is not intended to limit the specific implementation scope of the present invention. The scope of the present invention includes but is not limited to this specific implementation. All equivalent changes made in accordance with the shape and structure of the present invention are within the protection scope of the present invention.
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