Disclosure of Invention
The invention aims at a verification method and a system of a flash memory control chip.
According to a first aspect of the present invention, there is provided an authentication system of a flash memory control chip, comprising:
the sequence generator is used for generating UPIU data packets in the UFS protocol according to the test case;
The host behavior simulator is used for generating an excitation signal of a physical layer according to the UPIU data packet and applying the excitation signal to an input port of the flash memory control chip, then obtaining host driving expected data by monitoring the input port of the flash memory control chip, storing the host driving expected data into a first cache region, obtaining actual data of the flash memory chip, generated by the flash memory control chip executing corresponding functions based on the excitation signal, by monitoring an output port of the flash memory control chip, and storing the actual data of the flash memory chip into the first cache region;
the AXI monitoring module is used for simulating the AIX bus behavior, acquiring chip output data by monitoring an AXI interface of the flash memory control chip, and storing the chip output data into a third buffer area;
the firmware behavior simulator is used for receiving a task request from the flash memory control chip, calculating and acquiring an AXI address according to task request information, acquiring corresponding data from a third buffer area according to the AXI address, storing the corresponding data as host driving actual data into a second buffer area, simultaneously executing tasks according to the task request, storing the generated data as flash memory chip expected data into the second buffer area, and simultaneously returning the flash memory chip expected data into the flash memory control chip;
The verification module is used for respectively acquiring the host driving expected data and the host driving actual data from the first cache area and the second cache area, carrying out driving data verification, respectively acquiring the flash memory chip actual data and the flash memory chip expected data from the first cache area and the second cache area, and carrying out receiving data verification.
Optionally, the host behavior simulator includes: the host drive module comprises a host driver and a host monitor, wherein the host driver is used for converting the UPIU data packet into an excitation signal of a physical layer and applying the excitation signal to an input port of the flash memory control chip;
The host monitor is used for monitoring an input port of the flash memory control chip to obtain the host driving expected data and storing the host driving expected data into a first buffer area;
The host receiving module is used for receiving the actual data of the flash memory chip from the output port of the flash memory control chip and storing the actual data into the first buffer area.
Optionally, the firmware behavior simulator includes:
The request receiving module is used for receiving the task request from the flash memory control chip and transmitting the task request to the firmware processor under the condition that the task request is judged to be effective;
And the firmware processor is used for calculating and acquiring an AXI address according to the task request information, acquiring corresponding data from the third buffer area according to the AXI address, storing the corresponding data serving as host driving actual data into the second buffer area, simultaneously executing tasks according to the task request, storing the generated data serving as expected data of the flash memory chip into the second buffer area, and simultaneously returning the expected data of the flash memory chip into the flash memory control chip.
Optionally, the flash memory control chip and the firmware behavior simulator perform data interaction through a firmware register in the flash memory control chip.
Optionally, the host behavior simulator sends a read instruction, the flash memory control chip receives and executes the command, initiates a data transmission request of the read instruction to the firmware behavior simulator based on the register valid signal handshake, the firmware behavior simulator receives the data to be transmitted after the request, transmits the data to the third buffer area, returns a transmission response to the flash memory control chip, and the flash memory control chip receives the transmission response, executes the transmission of the data to be transmitted, and outputs the data in the third buffer area to the host behavior simulator.
According to a second aspect of the present invention, there is provided a method for verifying a flash memory control chip, comprising:
generating a UPIU data packet in the UFS protocol according to the test case;
Generating a physical-layer excitation signal according to the UPIU data packet and applying the physical-layer excitation signal to an input port of the flash memory control chip, and executing corresponding functions by the flash memory control chip;
Receiving a task request from the flash memory control chip, executing a task according to the task request, storing the generated data into a second buffer area as expected data of the flash memory chip, and simultaneously storing the expected data of the flash memory chip into the flash memory control chip;
monitoring an output port of the flash memory control chip to obtain actual data of the flash memory chip, and storing the actual data of the flash memory chip into a first buffer area;
And respectively acquiring the actual data of the flash memory chip and the expected data of the flash memory chip from the first buffer area and the second buffer area, and performing received data verification.
Optionally, the method further comprises:
The method comprises the steps of obtaining expected data of a host driver by monitoring an input port of the flash memory control chip, and storing the expected data of the host driver into a first buffer area;
Acquiring chip output data by monitoring an AXI interface of the flash memory control chip, and storing the chip output data into a third buffer area;
Acquiring an AXI address from the flash memory control chip, acquiring corresponding data from a third buffer area according to the AXI address, and storing the corresponding data serving as host driving actual data into a second buffer area;
and respectively acquiring host driving expected data and host driving actual data from the first buffer area and the second buffer area, and performing driving data verification.
Optionally, the AXI address is obtained through a firmware register in the flash control chip.
According to a third aspect of the present invention, there is provided a computing device comprising a memory and a processor, the memory further storing computer instructions executable by the processor, the computer instructions, when executed, implementing a method of verifying a flash memory control chip as any one of the above.
According to a fourth aspect of the present invention, there is provided a computer readable medium storing computer instructions executable by an electronic device, the computer instructions, when executed, implementing a method of verifying a flash memory control chip according to any one of the above.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown.
The present invention is described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth in detail. The present invention will be fully understood by those skilled in the art without the details described herein. Well-known methods, procedures, flows, components and circuits have not been described in detail so as not to obscure the nature of the invention.
Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, it is the meaning of "including but not limited to". In the description of the present invention, it should be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Furthermore, in the description of the present invention, unless otherwise indicated, the meaning of "a plurality" is two or more.
The core idea of the invention is to construct a firmware behavior simulator realized by software and to interact with a flash memory control chip by using the firmware behavior simulator to obtain a verification result. Various embodiments of the present invention are described in detail below with reference to the attached drawing figures.
Firmware behavior simulator fig. 1 is a functional exploded view of a verification system of a flash memory control chip according to an embodiment of the present invention.
As shown in the figure, verification system 1021 includes a sequencer 201, a host behavior simulator 202, a firmware behavior simulator 203, an AXI monitoring module 204, and a verification module 208. The validation system 1021 further includes a first buffer 206, a second buffer 207, and a third buffer 205. The three buffers may be considered as three dedicated storage areas partitioned on the computing device's own device memory for storing different data.
The sequence generator 201 is configured to generate various UPIU packets in UFS protocol according to test cases, and UPIU (UFS Protocol Information Units) packets are basic frame format of UTP layer transmission data of UFS, and mainly comprise two parts: the UPIU header and the fields associated with the particular UPIU, which in turn can be subdivided into a UPIU Transaction specific field (Transaction SPECIFIC FIELDS) portion and a DATA SEGMENT portion. The UPIU packets are divided into different UPIU packets according to Transaction Type (Transaction Type), and the UPIU packets of different Transaction types have Transaction specific fields (Transaction SPECIFIC FIELDS) of different formats. The sequence generator 201 sends UPIU packets of different transaction types to the host behavior simulator 202.
The host behavior simulator 202 receives the UPIU data packet generated by the sequence generator 201, generates a physical layer stimulus signal, applies the physical layer stimulus signal to an input port of the flash memory control chip 200, monitors the input port of the flash memory control chip 200 to obtain host driving expected data, stores the host driving expected data in the first buffer area 206, monitors an output port of the flash memory control chip 200 to obtain flash memory chip actual data generated by the flash memory control chip 200 executing a corresponding function under the effect of the stimulus signal converted by the UPIU data packet, and stores the flash memory chip actual data in the first buffer area 206.
As shown, in some embodiments, the host behavior simulator 202 is divided into a host driver module 2021 and a host receiver module 2022 according to specific functions. The host driver 2021 is further divided into a host driver 20211 and a host monitor 20212, and the host receiving module 2022 includes the host monitor 20221. The host driver 20211 is configured to convert the UPIU data packet received from the sequencer 201 into a physical layer stimulus signal and apply the stimulus signal to an input port of the flash control chip 200. The host monitor 20212 is configured to monitor the input port of the flash control chip 200 to obtain the stimulus signal actually received by the input port of the flash control chip 200, convert the stimulus signal into binary data as host driving expected data, and then store the host driving expected data in the first buffer 206. The host monitor 20221 monitors the output port of the flash memory control chip 200 to obtain the physical layer output signal generated by the flash memory control chip 200 executing the corresponding function under the action of the excitation signal converted from the UPIU packet, converts the physical layer output signal into binary data as the actual data of the flash memory chip, and then stores the actual data of the flash memory chip into the first buffer area 206.
The AXI monitoring module 204 obtains chip output data from the flash memory control chip 200 through monitoring the AXI interface, and stores the chip output data in the third buffer area 205.
The firmware behavior simulator 203 receives a task request generated when executing the UPIU packet input by the host driver module 2021 from the flash memory control chip 200, calculates and acquires an AXI address according to the task request information, acquires corresponding data from the third buffer area 205 according to the AXI address, stores the corresponding data as host driver actual data into the second buffer area 207, simultaneously executes a task according to the task request, stores the generated data as flash memory chip expected data into the second buffer area 207, and simultaneously configures the flash memory chip expected data into the firmware register 201 of the flash memory control chip 200. The flash control chip 200 performs a corresponding operation based on the expected data of the flash chip to generate the actual data of the flash chip and output the actual data to the host receiving module 2022.
As shown in the figures, in some embodiments, firmware behavior simulator 203 is functionally divided into a request receiving module 2031 and a firmware processor 2032. The request receiving module 2031 monitors the firmware register 209 in the flash control chip 200 to receive a task request therefrom, and the request receiving module 2031 may also receive an interrupt signal from the flash control chip 200 and receive the task request from the firmware register 2031 according to the interrupt signal, and in the case where the request is judged to be valid, transmit it to the firmware processor 2032. The firmware processor 2032 performs a task according to the task request, stores data generated by the task as flash chip expected data in the second buffer area 207, and simultaneously configures the flash chip expected data into the firmware register 209 of the flash control chip 200. The firmware processor 2032 also receives an interrupt signal from the AIX monitor module 204, calculates and acquires an AXI address according to the interrupt signal, and acquires corresponding data from the third buffer 205 according to the AXI address, and stores the corresponding data as host drive actual data in the second buffer 207.
The verification module 208 performs a verification of both the driving data and the received data: 1) Host driving expected data and host driving actual data are respectively acquired from the first buffer area 206 and the second buffer area 207, and are combined with host driving expected data and host driving actual data to perform expansion verification; 2) The flash chip actual data and the flash chip expected data are acquired from the first buffer area 206 and the second buffer area 207, respectively, and are combined with the flash chip expected data and the flash chip actual data to be expanded and verified.
According to the firmware behavior simulator for simulating the firmware behavior, the time consumption for dispatching the firmware by the CPU is shortened, the expected data of the host driver and the actual data of the host are obtained through the two data channels and checked, and the expected data of the flash memory chip and the actual data of the flash memory chip are obtained through the two data channels and checked, so that the functions and interfaces of the flash memory control chip are checked. The embodiment of the invention greatly shortens the verification time, has high verification effect and complete flow.
Table 1 is the transaction type of UPIU packet. The UPIU data packet comprises a plurality of contents such as transaction type, transmission data and size, data transmission direction, data storage address, execution sequence, offset address and the like.
Table 1
According to an embodiment of the invention, the verifiable data includes command information, task information, and transmission transaction data information. Taking the DATA transmission from the host to the flash memory control chip as an example, referring to fig. 2, the host driver 2021 sends a COMMAND UPIU to the flash memory control chip 200, the flash memory control chip 200 receives and executes the COMMAND, transmits READY TO TRANSFER UPIU to the host, confirms the size of receivable DATA, and the host driver 2021 sends DATA OUT UPIU transmission transaction DATA information again, and after receiving all the DATA, the flash memory control chip 200 replies RESPONSE UPIU to indicate that the COMMAND execution is completed. The COMMAND UPIU and the DATA OUT UPIU are DATA sent from the host to the flash memory control chip, and can be verified by the driving DATA in the verification module, and READY TO TRANSFER UPIU and RESPONSE UPIU are DATA received from the flash memory control chip by the host, and can be verified by the received DATA in the verification module.
The processing flow of the read command of the flash memory control chip is further illustrated. Referring to fig. 1, the host driver module 2021 sends a COMMAND UPIU of a read COMMAND, the flash control chip 200 receives and executes the COMMAND, initiates a DATA transmission request of the read COMMAND to the firmware behavior simulator 203 based on a register valid signal handshake, the firmware behavior simulator 203 receives the DATA to be transmitted after the request and transmits the DATA to be transmitted to the designated AXI address of the third buffer 205, and returns a transmission response through the firmware register, the flash control chip 200 receives the transmission response, executes the transmission of the DATA to be transmitted, and transmits the DATA IN the third buffer 205 to the host driver module 2021 through the DATA IN UPIU. The process is a task of the normal process of firmware processing, the firmware behavior simulator can simulate and process abnormal faults, when the flash memory control chip 200 is abnormal, an abnormal interrupt is reported, an interrupt processing module in the firmware behavior simulator acquires the interrupt, interrupt processing is performed, the abnormal processing module acquires abnormal information through a firmware register, judges and processes the abnormal, and returns the abnormal information to the host through the host receiving module 2022. For different transmission requests, the firmware behavior simulator can execute multiple requests in parallel, or can execute multiple requests in series according to priority or polling mode so as to adapt to different verification scenes.
FIG. 2 illustrates two ways in which a firmware behavior simulator may perform tasks. As shown in the figure, the request receiving module 2031 in the firmware behavior simulator receives a request through a firmware register or interrupt, and determines whether the request is valid, and if so, transfers the request to the firmware processor 2032 for execution. The firmware processor 2031 can process and respond to the request in a serial and parallel manner, the serial processing manner is a real firmware processing manner, the accuracy of a real firmware processing mode is verified, the parallel processing manner can maximally increase the transmission pressure of the flash memory control chip, and whether the functions of the module are accurate or not under larger pressure or whether the performance reaches the standard is verified.
Correspondingly, the embodiment of the invention also provides a verification method of the flash memory control chip, and a flow chart of the verification method is shown in fig. 3. The method specifically comprises the following steps.
In step S401, a UPIU packet in the UFS protocol is generated according to the test case.
In step S402, a physical layer excitation signal is generated according to the UPIU packet and applied to an input port of the flash memory control chip, and the flash memory control chip performs a corresponding function.
In step S403, a task request is received from the flash memory control chip, and a task is executed according to the task request, and the generated data is stored as flash memory chip expected data in the second buffer area, and at the same time, the flash memory chip expected data is stored in the flash memory control chip;
In step S404, the output port of the flash memory control chip is monitored to obtain the actual data of the flash memory chip, and the actual data of the flash memory chip is stored in the first buffer area;
in step S405, the actual data of the flash memory chip and the expected data of the flash memory chip are obtained from the first buffer area and the second buffer area, respectively, and the received data is verified.
In the embodiment, a firmware behavior simulator is adopted to acquire expected data of the flash memory chip and actual data of the flash memory chip through two different data channels and check the expected data and the actual data of the flash memory chip, so that functional check of the flash memory control chip is completed.
In some embodiments, further comprising acquiring and verifying host drive expected data and host actual data over two different data channels using a firmware behavior simulator. Specifically, the input port of the flash memory control chip is monitored to obtain expected data of the host driver, and the expected data of the host driver is stored in the first buffer area; then obtaining chip output data by monitoring an AXI interface of the flash memory control chip, and storing the chip output data into a third buffer area; acquiring an AXI address, acquiring corresponding data from the third buffer area according to the AXI address, and storing the corresponding data serving as actual host driving data into the second buffer area; and finally, respectively acquiring the expected data of the host drive and the actual data of the host drive from the first buffer area and the second buffer area, and checking the drive data.
Accordingly, an embodiment of the present invention provides a computing device, including a memory and a processor, where the memory further stores computer instructions executable by the processor, where the computer instructions, when executed, implement each functional unit of the verification system of a flash memory control chip or perform each step of the verification method of a flash memory control chip.
Correspondingly, the embodiment of the invention also provides a computer readable storage medium, on which a computer program is stored, which when being executed by a processor, realizes each functional unit of the verification system of the flash memory control chip or executes each step of the verification method of the flash memory control chip.
Embodiments in accordance with the present invention, as described above, are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and the full scope and equivalents thereof.