技术领域Technical Field
本公开总体上涉及芯片设计工具领域，并且更具体地涉及优化电路布局的方法、装置、设备、介质以及程序产品。The present disclosure generally relates to the field of chip design tools, and more particularly to methods, devices, apparatus, media, and program products for optimizing circuit layout.
背景技术Background Art
电子设计自动化(electronic design automation，EDA)软件被广泛应用于芯片的设计。借助于各种EDA软件，工程师可以方便地进行芯片的设计，例如架构设计和寄存器传输级(register-transfer level,RTL)代码设计、综合(synthesis)、可测性设计(designfor test，DFT)、物理实现(physical development)以及签核(signoff)等。Electronic design automation (EDA) software is widely used in chip design. With the help of various EDA software, engineers can easily carry out chip design, such as architecture design and register transfer level (RTL) code design, synthesis, design for test (DFT), physical development and signoff, etc.
在利用EDA软件进行芯片设计的过程中，高质量的电路布局布线是芯片设计成功的先决条件，而复杂耗时的布局规划是实现高质量布局布线的关键。电路布局规划的组成部分包括宏单元和标准单元的布局。宏单元主要包括存储单元以及各种定制单元，是集成电路的主要功能模块。标准单元库是底层电子逻辑功能的集合，例如各种门器件、触发器、锁存器和缓冲器。现代工业界的布局流程一般分为两个步骤，首先布局宏单元，再摆放剩下的标准单元模块。一旦所有宏单元布局完成后，剩余的空间都将留给标准单元。只有将每一个宏单元都放在合适的位置，才能实现所需目标的性能、功耗和面积。因此如何优化宏单元的布局是业界亟待解决的技术问题。In the process of chip design using EDA software, high-quality circuit layout and routing is a prerequisite for successful chip design, and complex and time-consuming layout planning is the key to achieving high-quality layout and routing. The components of circuit layout planning include the layout of macro cells and standard cells. Macro cells mainly include storage cells and various custom cells, which are the main functional modules of integrated circuits. The standard cell library is a collection of underlying electronic logic functions, such as various gate devices, triggers, latches and buffers. The layout process in modern industry is generally divided into two steps. First, the macro cells are laid out, and then the remaining standard cell modules are placed. Once all macro cells are laid out, the remaining space will be left for standard cells. Only by placing each macro cell in the right place can the required performance, power consumption and area be achieved. Therefore, how to optimize the layout of macro cells is a technical problem that needs to be solved urgently in the industry.
发明内容Summary of the invention
鉴于上述问题，本公开的实施例旨在提供一种用于优化电路布局的方案。In view of the above problems, an embodiment of the present disclosure aims to provide a solution for optimizing circuit layout.
根据本公开的第一方面，提供了一种用于优化电路布局的方法，方法包括：基于电路的初始化布局和设计目标，确定电路中的待优化的宏单元，设计目标包括时序目标、拥塞目标或宏单元规整度中的至少一项；以及基于布局规则或布线规则中的至少一项，调整待优化的宏单元在电路布局中的位置，以得到电路的目标布局。根据本公开的方案，能够实现自动布局优化，节省了时间和人工成本。同时在优化布局时综合权衡多项优化目标，使得布局优化更具有针对性。According to the first aspect of the present disclosure, a method for optimizing circuit layout is provided, the method comprising: determining the macrocells to be optimized in the circuit based on the initialization layout and design goals of the circuit, the design goals including at least one of the timing goals, congestion goals or macrocell regularity; and adjusting the positions of the macrocells to be optimized in the circuit layout based on at least one of the layout rules or wiring rules to obtain the target layout of the circuit. According to the scheme of the present disclosure, automatic layout optimization can be achieved, saving time and labor costs. At the same time, when optimizing the layout, multiple optimization goals are comprehensively weighed, making the layout optimization more targeted.
在一些实现方式中，基于电路的初始化布局和设计目标，确定电路中的待优化的宏单元包括：基于初始化布局，确定初始化布局中的拥塞区域，拥塞区域指示布线复杂程度大于阈值复杂程度的区域；以及将与拥塞区域相邻的区域中的宏单元确定为待优化的宏单元。通过这种方式，通过首先确定布线密集或者绕线复杂的区域，然后将该区域周围的宏单元确定为待优宏单元。可以准确地定位需要优化的宏单元。In some implementations, based on the initialization layout and design goals of the circuit, determining the macro cells to be optimized in the circuit includes: determining a congested area in the initialization layout based on the initialization layout, the congested area indicating an area where the wiring complexity is greater than a threshold complexity; and determining the macro cells in the area adjacent to the congested area as the macro cells to be optimized. In this way, by first determining an area with dense wiring or complex winding, and then determining the macro cells around the area as the macro cells to be optimized, the macro cells that need to be optimized can be accurately located.
在一些实现方式中，基于布局规则或布线规则中的至少一项，调整待优化的宏单元在电路布局中的位置，以得到电路的目标布局包括：基于布线规则和初始化布局，确定至少一个候选区域；基于布局规则和布线规则中的至少一项，从至少一个候选区域确定目标区域；以及将待优化的宏单元的位置调整至目标区域，以得到电路的目标布局。通过这种方式，根据电路的设计约束对已摆放的宏单元模块进行位置优化，能够提升电路整体的性能。In some implementations, adjusting the position of the macro unit to be optimized in the circuit layout based on at least one of the layout rules or the wiring rules to obtain the target layout of the circuit includes: determining at least one candidate area based on the wiring rules and the initialization layout; determining the target area from the at least one candidate area based on at least one of the layout rules and the wiring rules; and adjusting the position of the macro unit to be optimized to the target area to obtain the target layout of the circuit. In this way, the position of the placed macro unit module is optimized according to the design constraints of the circuit, which can improve the overall performance of the circuit.
在一些实现方式中，基于布线规则和初始化布局，确定至少一个候选区域包括：基于布线规则，确定与待优化的宏单元连接的非待优化的宏单元；以及基于初始化布局，将与非待优化的宏单元所在的区域相邻的区域确定为至少一个候选区域。通过这种方式，将存在连接关系的无需优化的宏单元周围的区域确定为候选区域使得布局优化更具有针对性。In some implementations, determining at least one candidate region based on the wiring rules and the initialization layout includes: determining, based on the wiring rules, non-to-be-optimized macro cells connected to the to-be-optimized macro cells; and determining, based on the initialization layout, a region adjacent to a region where the non-to-be-optimized macro cells are located as at least one candidate region. In this way, determining the region around the macro cells that are connected and do not need to be optimized as a candidate region makes the layout optimization more targeted.
在一些实现方式中，基于布局规则和布线规则中的至少一项，从至少一个候选区域确定目标区域包括：将待优化的宏单元的位置调整至至少一个候选区域，以得到电路的至少一个候选电路布局；基于布局规则和布线规则中的至少一项，确定至少一个候选电路布局的优化度量，优化度量与电路布局的拥塞度量、时序度量以及规整度量相关联；以及将与至少一个候选电路布局中的、优化度量大于阈值优化度量的候选电路布局相关联的候选区域确定为目标区域。由此可以利用少量的图案标志对电路版图中的上亿个图案进行表示。通过这种方式，根据数据流连接关系及拥塞预测，对已摆放的宏单元模块进行位置优化，使得能够优化优化时序，消除拥塞。In some implementations, based on at least one of the layout rules and the wiring rules, determining the target area from at least one candidate area includes: adjusting the position of the macro unit to be optimized to at least one candidate area to obtain at least one candidate circuit layout of the circuit; determining the optimization metric of at least one candidate circuit layout based on at least one of the layout rules and the wiring rules, the optimization metric is associated with the congestion metric, timing metric and regularity metric of the circuit layout; and determining the candidate area associated with the candidate circuit layout in at least one candidate circuit layout whose optimization metric is greater than the threshold optimization metric as the target area. In this way, hundreds of millions of patterns in the circuit layout can be represented by a small number of pattern marks. In this way, the position of the placed macro unit modules is optimized according to the data flow connection relationship and congestion prediction, so that the timing can be optimized and congestion can be eliminated.
在一些实现方式中，基于电路的初始化布局和设计目标，确定电路中的待优化的宏单元包括：基于初始化布局，确定电路中的多个宏单元之间的距离和多个宏单元之间的关联程度，关联程度与宏单元之间的连线数目和传输的数据量相关联；基于距离和关联程度，确定多个宏单元中的每个宏单元的数据流度量；以及将多个宏单元中的、数据流度量小于阈值数据流度量的宏单元确定为待优化的宏单元。通过这种方式，以宏单元之间的数据流度量作为优化目标，能够实现电路在时序上的增量式优化。。In some implementations, based on the initialization layout and design goals of the circuit, determining the macrocells to be optimized in the circuit includes: determining the distance between multiple macrocells in the circuit and the degree of association between the multiple macrocells based on the initialization layout, the degree of association being associated with the number of connections between the macrocells and the amount of data transmitted; determining the data flow metric of each macrocell in the multiple macrocells based on the distance and the degree of association; and determining the macrocells in the multiple macrocells whose data flow metric is less than a threshold data flow metric as the macrocell to be optimized. In this way, taking the data flow metric between macrocells as the optimization target, incremental optimization of the circuit in timing can be achieved. .
在一些实现方式中，基于布局规则或布线规则中的至少一项，调整待优化的宏单元在电路布局中的位置，以得到电路的目标布局包括：基于布线规则，确定与待优化的宏单元连接的非待优化宏单元；以及基于布局规则和布线规则，将待优化的宏单元调整至与非待优化宏单元所在区域相邻的目标区域中，调整包括宏单元位置互换或宏单元位置改变中的至少一项。通过这种方式，将存在连接关系的无需优化的宏单元周围的区域确定为候选区域使得布局优化更具有针对性。In some implementations, adjusting the position of the macrocell to be optimized in the circuit layout based on at least one of the layout rules or the wiring rules to obtain the target layout of the circuit includes: determining the non-to-be-optimized macrocells connected to the macrocell to be optimized based on the wiring rules; and adjusting the macrocell to be optimized to a target area adjacent to the area where the non-to-be-optimized macrocell is located based on the layout rules and the wiring rules, wherein the adjustment includes at least one of macrocell position swapping or macrocell position changing. In this way, the area around the macrocells that have a connection relationship and do not need to be optimized is determined as a candidate area, making the layout optimization more targeted.
在一些实现方式中，基于布局规则和布线规则，将待优化的宏单元调整至与非待优化宏单元相邻的目标区域中包括：响应于确定与非待优化的宏单元所在区域相邻的区域中存在至少另一待优化的宏单元，确定待优化宏单元与至少另一待优化的宏单元的相似度，相似度指示待优化宏单元与至少另一待优化宏单元的大小、引脚方向以及宏单元方向之间的差异；响应于确定相似度大于阈值相似度，将待优化宏单元与至少另一待优化宏单元的位置进行交换，以得到至少一个候选电路布局；基于布局规则和布线规则中的至少一项，确定至少一个候选电路布局的优化度量，优化度量与电路布局的拥塞度量、时序度量以及规整度量相关联；将与至少一个候选电路布局中的、优化度量大于阈值优化度量的候选电路布局相关联的候选区域确定为目标区域；以及将待优化的宏单元与目标区域中的另一待优化宏单元的位置进行交换，以得到电路的目标布局。通过这种方式，在调整电路布局时，首先确定是否存在能够互换的待优化宏单元，使得能够在调整最小的情况下完成优化，减少了优化时间并且提升了优化后电路的稳定性。In some implementations, based on the layout rules and the routing rules, adjusting the macro cell to be optimized to a target area adjacent to the macro cell not to be optimized includes: in response to determining that there is at least another macro cell to be optimized in an area adjacent to the area where the macro cell not to be optimized is located, determining the similarity between the macro cell to be optimized and the at least another macro cell to be optimized, the similarity indicating the difference between the size, pin direction and macro cell direction of the macro cell to be optimized and the at least another macro cell to be optimized; in response to determining that the similarity is greater than a threshold similarity, exchanging the position of the macro cell to be optimized with the at least another macro cell to be optimized to obtain at least one candidate circuit layout; based on at least one of the layout rules and the routing rules, determining an optimization metric of at least one candidate circuit layout, the optimization metric being associated with a congestion metric, a timing metric and a regularity metric of the circuit layout; determining a candidate area associated with a candidate circuit layout in which the optimization metric is greater than the threshold optimization metric in the at least one candidate circuit layout as a target area; and exchanging the position of the macro cell to be optimized with another macro cell to be optimized in the target area to obtain a target layout of the circuit. In this way, when adjusting the circuit layout, it is first determined whether there are macro units to be optimized that can be interchanged, so that the optimization can be completed with minimal adjustment, reducing the optimization time and improving the stability of the optimized circuit.
在一些实现方式中，基于布局规则和布线规则，将待优化的宏单元调整至与非待优化宏单元相邻的目标区域中包括：响应于确定与非待优化宏单元所在区域相邻的区域中不存在另一待优化的宏单元，将待优化宏单元调整到候选区域，以得到至少一个候选电路布局，候选区域与非待优化宏单元所在的区域相邻；基于布局规则和布线规则中的至少一项，确定至少一个候选电路布局的优化度量，优化度量与电路布局的拥塞度量、时序度量以及规整度量相关联；将与至少一个候选电路布局中的、优化度量大于阈值优化度量的候选电路布局相关联的候选区域确定为目标区域；以及将待优化的宏单元调整至目标区域，以得到电路的目标布局。通过这种方式，能够在性能、功耗和面积上对对人工电路布局结果或者自动化算法电路布局结果进行增量式调优。In some implementations, based on the layout rules and the routing rules, adjusting the macrocell to be optimized to the target area adjacent to the non-to-be-optimized macrocell includes: in response to determining that there is no other macrocell to be optimized in the area adjacent to the area where the non-to-be-optimized macrocell is located, adjusting the macrocell to be optimized to the candidate area to obtain at least one candidate circuit layout, the candidate area is adjacent to the area where the non-to-be-optimized macrocell is located; based on at least one of the layout rules and the routing rules, determining the optimization metric of at least one candidate circuit layout, the optimization metric is associated with the congestion metric, the timing metric, and the regularity metric of the circuit layout; determining the candidate area associated with the candidate circuit layout in at least one candidate circuit layout whose optimization metric is greater than the threshold optimization metric as the target area; and adjusting the macrocell to be optimized to the target area to obtain the target layout of the circuit. In this way, the manual circuit layout results or the automated algorithm circuit layout results can be incrementally tuned in terms of performance, power consumption, and area.
在一些实现方式中，规整度量与电路布局中可设置宏单元的区域的面积和周长相关联，数据流度量与宏单元之间的关联程度和距离相关联，拥塞度量与电路布局中的布线复杂程度相关联。通过这种方式，通过电路的不同特性采用多目标权衡策略进行布局优化，可以最大化优化后电路的性能。In some implementations, the regularity metric is associated with the area and perimeter of the region where the macrocell can be set in the circuit layout, the data flow metric is associated with the degree of association and distance between the macrocells, and the congestion metric is associated with the wiring complexity in the circuit layout. In this way, the performance of the optimized circuit can be maximized by using a multi-objective trade-off strategy for layout optimization based on different characteristics of the circuit.
在一些实现方式中，方法还包括：基于用于实现电路的设计信息，确定多个宏单元的平均大小；基于平均大小，将电路版图划分为多个区域；以及基于用于表征电路的网表文件，将多个宏单元设置在多个区域中，以得到始化布局。通过这种方式，将初始布局呈根宏单元大小划分为多个区域对后续的计算和宏单元位置的调整更有优势。利用网格表示电路布局也更加直观。In some implementations, the method further includes: determining an average size of the plurality of macrocells based on design information for implementing the circuit; dividing the circuit layout into a plurality of regions based on the average size; and arranging the plurality of macrocells in the plurality of regions based on a netlist file for characterizing the circuit to obtain an initial layout. In this way, dividing the initial layout into a plurality of regions based on the size of the macrocells is more advantageous for subsequent calculations and adjustment of the positions of the macrocells. Using a grid to represent the circuit layout is also more intuitive.
根据本公开的第二方面，提供了一种用于优化电路布局的装置，其特征在于，装置包括：待优化宏单元确定模块，被配置为基于电路的初始化布局和设计目标，确定所述电路中的待优化的宏单元，所述设计目标包括时序目标、拥塞目标或宏单元规整度中的至少一项；以及目标布局确定模块，被配置为基于布局规则或布线规则中的至少一项，调整所述待优化的宏单元在电路布局中的位置，以得到所述电路的目标布局。According to a second aspect of the present disclosure, a device for optimizing circuit layout is provided, characterized in that the device includes: a macro cell determination module to be optimized, configured to determine the macro cells to be optimized in the circuit based on the initialization layout and design goals of the circuit, the design goals including at least one of a timing goal, a congestion goal or macro cell regularity; and a target layout determination module, configured to adjust the position of the macro cells to be optimized in the circuit layout based on at least one of a layout rule or a wiring rule to obtain a target layout of the circuit.
在本公开的第三方面，提供了一种电子设备。该电子设备包括：至少一个计算单元；至少一个存储器，至少一个存储器被耦合到至少一个计算单元并且存储用于由至少一个计算单元执行的指令，指令当由至少一个计算单元执行时，使得设备执行第一方面或者第一方面中的任意一种实现方式中的方法。In a third aspect of the present disclosure, an electronic device is provided. The electronic device includes: at least one computing unit; and at least one memory, the at least one memory being coupled to the at least one computing unit and storing instructions for execution by the at least one computing unit, wherein when the instructions are executed by the at least one computing unit, the device executes the method in the first aspect or any one of the implementations of the first aspect.
在本公开的第四方面，提供了一种计算机可读存储介质。计算机可读存储介质存储有一条或多条计算机指令，其中一条或多条计算机指令被处理器执行实现第一方面或者第一方面中的任意一种实现方式中的方法。In a fourth aspect of the present disclosure, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores one or more computer instructions, wherein the one or more computer instructions are executed by a processor to implement the method in the first aspect or any one of the implementations of the first aspect.
在本公开的第五方面，提供一种计算机程序产品。计算机程序产品包括计算机可执行指令，计算机可执行指令在被处理器执行时，使计算机执行第一方面或者第一方面中的任意一种实现方式中的方法的部分或全部步骤的指令。In a fifth aspect of the present disclosure, a computer program product is provided, which includes computer executable instructions, which, when executed by a processor, cause a computer to execute some or all steps of the method in the first aspect or any implementation of the first aspect.
可以理解地，上述提供的第二方面的用于对电路设计进行切分的装置、第三方面的电子设备、第四方面的计算机存储介质或者第五方面的计算机程序产品均用于实现第一方面所提供的方法。因此，关于第一方面的解释或者说明同样适用于第二方面、第三方面、第四方面和第五方面。此外，第二方面、第三方面、第四方面和第五方面所能达到的有益效果可参考对应方法中的有益效果，此处不再赘述。It can be understood that the device for dividing the circuit design of the second aspect, the electronic device of the third aspect, the computer storage medium of the fourth aspect, or the computer program product of the fifth aspect provided above are all used to implement the method provided by the first aspect. Therefore, the explanation or description of the first aspect is also applicable to the second aspect, the third aspect, the fourth aspect, and the fifth aspect. In addition, the beneficial effects that can be achieved by the second aspect, the third aspect, the fourth aspect, and the fifth aspect can refer to the beneficial effects in the corresponding method, which will not be repeated here.
提供发明内容部分是为了简化的形式来介绍对概念的选择，它们在下文的具体实施方式中将被进一步描述。发明内容部分无意标识本公开内容的关键特征或主要特征，也无意限制本公开内容的范围。This summary is provided to introduce a selection of concepts in a simplified form, which are further described in the detailed description below. This summary is not intended to identify key features or essential features of the disclosure, nor is it intended to limit the scope of the disclosure.
应当理解，发明内容部分中所描述的内容并非旨在限定本公开的关键或重要特征，亦非用于限制本公开的范围。本公开的其它特征通过以下的描述将变得容易理解。It should be understood that the contents described in the summary of the invention are not intended to limit the key or important features of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
通过参考附图阅读下文的详细描述，本公开的实施例的上述以及其它目的、特征和优点将变得容易理解。在附图中，以示例性而非限制性的方式示出了本公开的若干实施例。The above and other objects, features and advantages of the embodiments of the present disclosure will become readily understood by reading the following detailed description with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present disclosure are shown in an exemplary and non-limiting manner.
图1示出了芯片的设计制造过程的流程图；FIG1 shows a flow chart of the chip design and manufacturing process;
图2示出了根据本公开的一些实施例的示例环境的框图；FIG2 illustrates a block diagram of an example environment according to some embodiments of the present disclosure;
图3示出了根据本公开的一些实施例的用于优化电路布局的流程图；FIG3 shows a flow chart for optimizing circuit layout according to some embodiments of the present disclosure;
图4示出了根据本公开的一些实施例的电路的初始化布局的示意图；FIG4 shows a schematic diagram of an initialization layout of a circuit according to some embodiments of the present disclosure;
图5A至图5C示出了根据本公开的一些实施例的电路的优化度量的示意图；5A to 5C are schematic diagrams showing optimization metrics of a circuit according to some embodiments of the present disclosure;
图6示出了根据本公开的一些实施例的用于优化电路布局的示意图；FIG6 shows a schematic diagram for optimizing circuit layout according to some embodiments of the present disclosure;
图7示出了根据本公开的另一些实施例的用于优化电路布局的示意图；FIG7 shows a schematic diagram for optimizing circuit layout according to other embodiments of the present disclosure;
图8示出了根据本公开的又一些实施例的用于优化电路布局的示意图；FIG8 shows a schematic diagram for optimizing circuit layout according to still other embodiments of the present disclosure;
图9示出了根据本公开的一些实施例的用于优化电路布局的示例装置的框图；以及FIG. 9 illustrates a block diagram of an example apparatus for optimizing circuit layout according to some embodiments of the present disclosure; and
图10示出了可以用于实施本公开的一些实施例的示例设备的示意性框图。FIG. 10 shows a schematic block diagram of an example device that may be used to implement some embodiments of the present disclosure.
具体实施方式DETAILED DESCRIPTION
下文将参考附图中示出的若干示例性实施例来描述本公开的原理和精神。应当理解，描述这些具体的实施例仅是为了使本领域的技术人员能够更好地理解并实现本公开，而并非以任何方式限制本公开的范围。在以下描述和权利要求中，除非另有定义，否则本文中使用的所有技术和科学术语具有与所属领域的普通技术人员通常所理解的含义。The principles and spirit of the present disclosure will be described below with reference to several exemplary embodiments shown in the accompanying drawings. It should be understood that the description of these specific embodiments is only to enable those skilled in the art to better understand and implement the present disclosure, and does not limit the scope of the present disclosure in any way. In the following description and claims, unless otherwise defined, all technical and scientific terms used herein have the meanings commonly understood by those of ordinary skill in the art.
在本文中使用的术语“包括”及其变形表示开放性包括，即“包括但不限于”。除非特别申明，术语“或”表示“和/或”。术语“基于”表示“至少部分地基于”。术语“一个示例实施例”和“一个实施例”表示“至少一个示例实施例”。术语“另一实施例”表示“至少一个另外的实施例”。术语“上”、“下”、“前”、“后”等指示放置或者位置关系的词汇均基于附图所示的方位或者位置关系，仅为了便于描述本公开的原理，而不是指示或者暗示所指的元件必须具有特定的方位、以特定的方位构造或操作，因此不能理解为对本公开的限制。The term "including" and its variations used in this document represent open inclusion, that is, "including but not limited to". Unless otherwise stated, the term "or" means "and/or". The term "based on" means "based at least in part on". The terms "an example embodiment" and "an embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one other embodiment". Terms such as "upper", "lower", "front", and "rear" indicating placement or positional relationships are based on the orientation or positional relationships shown in the drawings, and are only for the convenience of describing the principles of the present disclosure, and do not indicate or imply that the referred elements must have a specific orientation, be constructed or operate in a specific orientation, and therefore should not be understood as limitations on the present disclosure.
如上文所述，需要一种优化电路中宏单元的布局的解决方案。在一些相关的检查版图的方案中，在将宏单元根据版图设计文件进行摆放后，基于单一的优化模式进行多次人工调整以进行迭代，以达到电路所需目标的性能、功耗和面积。上述方案至少存在如下缺陷：(1)需要依靠人工专家经验，且迭代周期较长，耗时耗力；(2)优化模式较为单一，无针对性的优化目标。As mentioned above, a solution is needed to optimize the layout of macro cells in a circuit. In some related layout checking schemes, after the macro cells are placed according to the layout design file, multiple manual adjustments are made based on a single optimization mode for iteration to achieve the performance, power consumption and area required by the circuit. The above scheme has at least the following defects: (1) It needs to rely on manual expert experience, and the iteration cycle is long, which is time-consuming and labor-intensive; (2) The optimization mode is relatively single and there is no targeted optimization target.
在本公开的各实施例中提出了一种优化电路布局的方法，首先将根据电路的初始化布局和优化目标，确定需要被优化的宏单元，优化目标可以是对电路的时序进行优化、对电路中布线的拥塞区域进行优化或者对电路布局的规整度进行优化中的一项或者多项。然后根据电路的布局规则或布线规则，在电路布局中调整宏单元的位置，从而得到优化后的目标布局。根据本公开的方案，能够实现自动布局优化，节省了时间和人工成本。同时在优化布局时综合权衡多项优化目标，使得布局优化更具有针对性。In each embodiment of the present disclosure, a method for optimizing circuit layout is proposed. First, the macro unit to be optimized is determined according to the initial layout and optimization target of the circuit. The optimization target can be one or more of optimizing the timing of the circuit, optimizing the congested area of the wiring in the circuit, or optimizing the regularity of the circuit layout. Then, according to the layout rules or wiring rules of the circuit, the position of the macro unit is adjusted in the circuit layout to obtain the optimized target layout. According to the scheme of the present disclosure, automatic layout optimization can be achieved, saving time and labor costs. At the same time, when optimizing the layout, a number of optimization targets are comprehensively weighed to make the layout optimization more targeted.
在下文中首先介绍本公开的方案所应用的场景。图1示出了芯片的设计制造过程100的流程图。设计制造过程100开始于规格制定110。在规格制定110的阶段，确定集成电路需要达到的功能和性能方面的要求。在芯片设计120的阶段，借助于EDA软件来进行电路设计，以获得例如用于芯片制造的版图文件。基于电路的不同(例如数字电路或模拟电路)，设计120可以包括不同的设计环节。在制造140的阶段中，通过光刻、刻蚀、离子注入、薄膜沉积、抛光等工艺在晶圆上形成集成电路。在封装150的阶段，对晶圆进行切割得到裸片，并通过黏贴、焊接、模封等工艺对裸片进行封装得到芯片。所得到的芯片在测试160的阶段中被测试，以确保成品芯片的性能满足规格制定110中所确定的要求。测试合格的芯片170可以被交付客户。可以理解，上述过程仅是示意，而非对本公开的范围进行限制。在一些情形下，芯片的设计制造过程可以有所不同。例如，在制造140之前可以进行流片(tape-out)。流片所得的少量芯片可以用于进行测试以验证芯片设计是否达到预期。如果未达到预期，则这表明流片失败，并且可能需要调整芯片设计或重新设计芯片。The following first introduces the scenario in which the scheme of the present disclosure is applied. FIG. 1 shows a flow chart of a chip design and manufacturing process 100. The design and manufacturing process 100 begins with specification formulation 110. At the stage of specification formulation 110, the requirements for the functions and performances that the integrated circuit needs to achieve are determined. At the stage of chip design 120, circuit design is performed with the aid of EDA software to obtain, for example, a layout file for chip manufacturing. Based on the difference in circuits (e.g., digital circuits or analog circuits), the design 120 may include different design links. At the stage of manufacturing 140, integrated circuits are formed on wafers through processes such as lithography, etching, ion implantation, thin film deposition, and polishing. At the stage of packaging 150, the wafer is cut to obtain a bare die, and the bare die is packaged to obtain a chip through processes such as pasting, welding, and mold sealing. The obtained chip is tested at the stage of testing 160 to ensure that the performance of the finished chip meets the requirements determined in the specification formulation 110. The chip 170 that passes the test can be delivered to the customer. It can be understood that the above process is only illustrative and does not limit the scope of the present disclosure. In some cases, the design and manufacturing process of the chip may be different. For example, tape-out may be performed before manufacturing 140. A small number of chips obtained from the tape-out may be used for testing to verify whether the chip design meets expectations. If it does not meet expectations, this indicates that the tape-out has failed and the chip design may need to be adjusted or redesigned.
在一些实施例中，数字电路的设计120可以示例性地包括架构设计121、RTL设计123、功能仿真125、综合(synthesis)127、时序分析129、DFT 131、验证检查133、布局布线135、设计规则检查(design rule check，DRC)137以及生成版图139。架构设计121例如包括对芯片的架构进行设计。例如，可以使用EDA软件确定芯片系统所包括的组件或子电路的类别和数量、以及各个组件或子电路的功能、连接和交互。在RTL设计123的阶段，可以使用诸如Verilog或VHDL之类的硬件编程语言将经过确定的芯片架构在RTL级进行代码描述。功能仿真125也被称作RTL级行为仿真或前端仿真。功能仿真目的是分析设计电路逻辑关系的正确性。综合127可以将RTL转换成门级网表(gate-level netlist)。综合127例如可以包括转换(translation)、优化(optimization)和映射(mapping)。在一个实施例中，用于综合的EDA软件可以先将RTL代码转化成通用的布尔等式，并且对其进行编译。可以根据设计者施加的延时、面积等约束对网表进行优化，并且继而将RTL网表映射到工艺库以生成门级网表。In some embodiments, the design 120 of the digital circuit may exemplarily include an architecture design 121, an RTL design 123, a functional simulation 125, a synthesis 127, a timing analysis 129, a DFT 131, a verification check 133, a layout 135, a design rule check (DRC) 137, and a layout generation 139. The architecture design 121 includes, for example, designing the architecture of the chip. For example, EDA software may be used to determine the categories and quantities of components or subcircuits included in the chip system, as well as the functions, connections, and interactions of each component or subcircuit. In the stage of RTL design 123, a hardware programming language such as Verilog or VHDL may be used to describe the determined chip architecture in code at the RTL level. Functional simulation 125 is also referred to as RTL-level behavioral simulation or front-end simulation. The purpose of functional simulation is to analyze the correctness of the logical relationship of the design circuit. Synthesis 127 may convert RTL into a gate-level netlist. Synthesis 127 may include, for example, translation, optimization, and mapping. In one embodiment, the EDA software used for synthesis may first convert the RTL code into a general Boolean equation and compile it. The netlist may be optimized according to the constraints imposed by the designer, such as delay and area, and then the RTL netlist may be mapped to the process library to generate a gate-level netlist.
时序分析129通常为静态时序分析，其主要涉及对数字电路的时序计算和预计。通过对数字电路中的路径进行时序分析来确定是否实现时序收敛，从而确保各种电路的时序是否满足各种时序要求。这种数字电路的验证通常是静态完成的，并且不需要数字逻辑的模拟。在DFT 131的阶段，可以在设计中嵌入各种用于提高芯片可测试性(包括可控制性和可观测性)的硬件逻辑。通过使用这部分逻辑，可以生成测试向量以实现大规模数字电路的测试的目的。DFT例如可以包括基于扫描链(scan chain)的测试方法或内建自测试电路(built-in self-test，BIST)。在验证检查133的阶段，可以对电路进行形式验证和/或等价性检查。形式验证可以根据某个或某些形式规范或属性，使用数学的方法证明其正确性或非正确性。形式验证例如可以包括抽象解释(abstract interpretation)、形式模型检查(formal model checking，也被称作特性检查)和定理证明(theory prover)。等价性检查可以用于验证寄存器传输级设计与门级网表之间、门级网表与门级网表之间是否一致。Timing analysis 129 is usually static timing analysis, which mainly involves timing calculation and prediction of digital circuits. Timing analysis is performed on the paths in the digital circuit to determine whether timing convergence is achieved, thereby ensuring whether the timing of various circuits meets various timing requirements. The verification of such digital circuits is usually completed statically and does not require simulation of digital logic. At the stage of DFT 131, various hardware logics for improving chip testability (including controllability and observability) can be embedded in the design. By using this part of logic, test vectors can be generated to achieve the purpose of testing large-scale digital circuits. DFT can, for example, include a test method based on a scan chain or a built-in self-test circuit (BIST). At the stage of verification check 133, the circuit can be formally verified and/or equivalence checked. Formal verification can use mathematical methods to prove its correctness or incorrectness based on one or more formal specifications or attributes. Formal verification can, for example, include abstract interpretation, formal model checking (also known as characteristic checking) and theorem prover. Equivalence checking can be used to verify whether the register transfer level design is consistent with the gate-level netlist, and between the gate-level netlist and the gate-level netlist.
在布局布线135的阶段，可以对芯片电路进行布局(placement)和布线(routing)。布局可以基于面积、关键路径延时长度、功耗等因素的考量把逻辑综合127生成的门级网表合理地排布在与芯片对应的一个矩形区域内。在此之后，可以对经布局的各个组件或子电路进行布线以将其连接。布线通常期望总的走线较短、走线延时满足时序要求、符合工艺上的走线规则(如布线密度)。虽然在此将布局和布线分开描述，但这仅是示意性的而非对本公开的范围进行限制。在一些情形下，布局和布线可以同时进行或交替进行以实现布局布线的优化。In the stage of layout and routing 135, the chip circuit can be laid out (placement) and routed (routing). The layout can reasonably arrange the gate-level netlist generated by logic synthesis 127 in a rectangular area corresponding to the chip based on considerations such as area, critical path delay length, and power consumption. After this, the various components or sub-circuits that have been laid out can be routed to connect them. Routing generally expects the total routing to be short, the routing delay to meet the timing requirements, and to comply with the routing rules in the process (such as routing density). Although layout and routing are described separately here, this is only illustrative and does not limit the scope of the present disclosure. In some cases, layout and routing can be performed simultaneously or alternately to achieve optimization of layout and routing.
在DRC 137的阶段，可以检查版图是否存在违反设计规则而引起潜在断路、短路或不良效应。在通过DRC之后，可以由EDA软件生成139表示版图的文件，例如GDSII文件。可以理解，上述环节仅为示例性而非对本公开的范围进行限制，在实际设计过程中，可以根据设计需要对上述环节进行增加、删减或修改。此外，上述环节中的一些环节可以由不同的EDA软件实现，也可以被集成在一个或多个EDA软件中实现。本公开对此不进行限制。At the DRC 137 stage, the layout can be checked for potential open circuits, short circuits or adverse effects caused by violations of design rules. After passing the DRC, a file representing the layout, such as a GDSII file, can be generated 139 by the EDA software. It can be understood that the above steps are only exemplary and not intended to limit the scope of the present disclosure. In the actual design process, the above steps can be added, deleted or modified according to design needs. In addition, some of the above steps can be implemented by different EDA software or integrated in one or more EDA software. The present disclosure does not limit this.
本公开的优化电路布局的方案可以应用于综合127的阶段中的物理综合阶段。其中在宏单元被放置在电路布局中之后，根据电路的设计约束，例如布局规则和布线规则、优化目标和本公开中的算法调整宏单元在布局中的位置，从而实现电路所需目标的性能、功耗和面积。可以理解，本公开的方案还可以应用于优化其他电路旗舰的其他场景，本公开在此不做限制。The scheme for optimizing circuit layout disclosed in the present invention can be applied to the physical synthesis stage in the synthesis 127 stage. After the macro cells are placed in the circuit layout, the positions of the macro cells in the layout are adjusted according to the design constraints of the circuit, such as layout rules and routing rules, optimization goals and the algorithm in the present invention, so as to achieve the performance, power consumption and area required by the circuit. It can be understood that the scheme of the present invention can also be applied to other scenarios of optimizing other circuit flagships, and the present invention is not limited here.
可以理解，上文虽然采用特定次序描绘了各操作，但是这应当理解为不限于要求这样操作以所示出的特定次序或以顺序次序执行，或者要求所有图示的操作应被执行以取得期望的结果。在一定环境下，多任务和并行处理可能是有利的。同样地，虽然在上面论述中包含了若干具体实现细节，但是这些不应当被解释为对本公开的范围的限制。在单独的实施例的上下文中描述的某些特征还可以组合地实现在单个实现中。相反地，在单个实现的上下文中描述的各种特征也可以单独地或以任何合适的子组合的方式实现在多个实现中。It is to be understood that, although each operation is described in a specific order above, this should be understood as not being limited to requiring such operation to be performed in the specific order shown or in a sequential order, or requiring that all illustrated operations should be performed to obtain desired results. Under certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although some specific implementation details are included in the above discussion, these should not be construed as limiting the scope of the present disclosure. Some features described in the context of a separate embodiment can also be implemented in a single implementation in combination. On the contrary, the various features described in the context of a single implementation can also be implemented in multiple implementations individually or in any suitable sub-combination mode.
尽管已经采用特定于结构特征和/或方法逻辑动作的语言描述了本主题，但是应当理解所附权利要求书中所限定的主题未必局限于上面描述的特定特征或动作。相反，上面所描述的特定特征和动作仅仅是实现权利要求书的示例形式。Although the subject matter has been described in language specific to structural features and/or methodological logical actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. On the contrary, the specific features and actions described above are merely example forms of implementing the claims.
图2示出了根据本公开的一些实施例的示例环境200的框图。如图2所示，示例环境200总体上可以包括电子设备220。在一些实施例中，电子设备220可以是诸如个人计算机、工作站、服务器等具有计算功能的设备。本公开描述的过程可以由诸如个人计算机、工作站、服务器等具有计算功能的电子设备中的EDA工具软件来实现。电子设备220可以被安装有EDA软件，在芯片的EDA设计过程中，可以由用户(未示出)向EDA软件输入配置，由EDA软件自动生成逻辑电路。EDA软件包括但不限于芯片设计辅助软件、可编程芯片辅助设计软件和系统设计辅助软件。本公开的范围在此方面不受限制。FIG. 2 shows a block diagram of an example environment 200 according to some embodiments of the present disclosure. As shown in FIG. 2 , the example environment 200 may generally include an electronic device 220. In some embodiments, the electronic device 220 may be a device with computing functions such as a personal computer, a workstation, a server, etc. The process described in the present disclosure may be implemented by EDA tool software in an electronic device with computing functions such as a personal computer, a workstation, a server, etc. The electronic device 220 may be installed with EDA software, and during the EDA design process of the chip, a user (not shown) may input a configuration to the EDA software, and the EDA software may automatically generate a logic circuit. EDA software includes, but is not limited to, chip design auxiliary software, programmable chip auxiliary design software, and system design auxiliary software. The scope of the present disclosure is not limited in this respect.
电子设备220能够获取电路的初始化布局，电路的初始化布局可以包括电路中的器件(例如宏单元)的相对位置。在一些实施例中，电子设备220可以获取用于实现电路的版图文件和表征电路的网表文件作为输入，以确定电路的初始化布局。版图文件210可以例如以版图设计交换格式(Graphic Design System，GDS)文件的形式被提供给电子设备220。在一些其他实施例中，也可以将电路的初始化布局直接提供给电子设备220。将在下文结合图4描述如何确定初始化布局。The electronic device 220 can obtain an initialization layout of the circuit, and the initialization layout of the circuit may include the relative positions of devices (e.g., macro cells) in the circuit. In some embodiments, the electronic device 220 may obtain a layout file for implementing the circuit and a netlist file representing the circuit as input to determine the initialization layout of the circuit. The layout file 210 may be provided to the electronic device 220, for example, in the form of a Graphic Design System (GDS) file. In some other embodiments, the initialization layout of the circuit may also be provided directly to the electronic device 220. How to determine the initialization layout will be described below in conjunction with FIG. 4.
在获取初始化布局之后，计算设备220能够根据初始化布局和特定优化目标确定待优化的宏单元。在一些实施例中，计算设备220可以根据时序目标确定待优化的宏单元。在一些其他实施例中，计算设备220可以根据布线拥塞目标确定待优化的宏单元。备选地，在一些实施例中，计算设备220可以根据宏单元规整度目标确定待优化的宏单元。附加地或者备选地，在一些实施例中，计算设备220可以根据上述优化目标的任何组合确定待优化的宏单元。After obtaining the initialization layout, the computing device 220 can determine the macrocell to be optimized based on the initialization layout and the specific optimization goal. In some embodiments, the computing device 220 can determine the macrocell to be optimized based on the timing goal. In some other embodiments, the computing device 220 can determine the macrocell to be optimized based on the routing congestion goal. Alternatively, in some embodiments, the computing device 220 can determine the macrocell to be optimized based on the macrocell regularity goal. Additionally or alternatively, in some embodiments, the computing device 220 can determine the macrocell to be optimized based on any combination of the above-mentioned optimization goals.
在确定待优化的宏单元后，计算设备220能够根据电路的设计约束来调整待优化的宏单元的位置以得到电路的目标布局。在一些实施例中，计算设备220能够将待优化的宏单元的位置交换以得到电路的目标布局。在一些其他实施例中，计算设备220可以将待优化的宏单元的位置调整至与其连接的无需优化的宏单元。这将在下文结合图3至图8进一步详细描述。After determining the macrocell to be optimized, the computing device 220 can adjust the position of the macrocell to be optimized according to the design constraints of the circuit to obtain the target layout of the circuit. In some embodiments, the computing device 220 can swap the position of the macrocell to be optimized to obtain the target layout of the circuit. In some other embodiments, the computing device 220 can adjust the position of the macrocell to be optimized to the macrocell connected thereto that does not need to be optimized. This will be further described in detail below in conjunction with Figures 3 to 8.
图3示出了根据本公开的一些实施例的用于优化电路布局的流程图。在一些实施例中，方法300可以由如图2所示的电子设备220执行。应当理解的是，方法300还可以包括未示出的附加框和/或可以省略所示出的框，本公开的范围在此方面不受限制。3 shows a flow chart for optimizing circuit layout according to some embodiments of the present disclosure. In some embodiments, method 300 may be performed by electronic device 220 as shown in FIG2. It should be understood that method 300 may also include additional blocks not shown and/or may omit the blocks shown, and the scope of the present disclosure is not limited in this respect.
在框310，电子设备220基于电路的初始化布局和设计目标，确定电路中的待优化的宏单元，设计目标包括时序目标、拥塞目标或宏单元规整度中的至少一项。例如，电子设备220可以根据不同的优化目标确定不同的待优化的宏单元。In block 310, the electronic device 220 determines the macrocells to be optimized in the circuit based on the initial layout of the circuit and the design goal, wherein the design goal includes at least one of a timing goal, a congestion goal, or a macrocell regularity. For example, the electronic device 220 may determine different macrocells to be optimized according to different optimization goals.
为了便于后续描述的清楚性，这里首先结合图4介绍电路的初始化布局430。图4示出了根据本公开的一些实施例的电路的初始化布局的示意图。在一些实施例中，电子设备220可以基于用于实现电路的设计信息，确定多个宏单元的平均大小。然后基于平均大小，将电路版图划分为多个区域。之后基于用于表征电路的网表文件，将多个宏单元设置在多个区域中，以得到始化布局。For the sake of clarity of the subsequent description, the initialization layout 430 of the circuit is first introduced here in conjunction with Figure 4. Figure 4 shows a schematic diagram of the initialization layout of the circuit according to some embodiments of the present disclosure. In some embodiments, the electronic device 220 can determine the average size of multiple macro cells based on the design information used to implement the circuit. Then, based on the average size, the circuit layout is divided into multiple areas. Thereafter, based on the netlist file used to characterize the circuit, multiple macro cells are set in multiple areas to obtain the initialization layout.
例如，参见图4所示，电子设备220可以根据网表文件410和版图文件420确定电路的初始化布局430，并且然后将初始化布局430插入到网格区域440中以便于后续的计算和位置调整。网表文件410又称为连线表，是指数字电路连接情况的描述方式。网表通常传递了电路连接方面的信息，例如模块的实例、线网以及相关属性，例如在图4中，网表信息包含了N1、N2、N3等三条线网，线网N1中包含了三个宏单元的连接，分别为宏单元M1、宏单元M3和宏单元M4。而版图文件420包含了每个宏单元的位置和长宽大小及可以布局的区域大小，例如M1、x1、y1、w1、h1表示为宏单元M1的左下角坐标为x1、y1，宏单元M1的具体宽度和高度分别为w1和h1。在该示例中，为了方便后续描述，限定宏单元M1的信息为(12280，1133401，139307，107559)，宏单元M2的信息为(1338224，1133401，119307，107559)，宏单元M3的信息为(12280，14560，119307，107559)，宏单元M4的信息为(1338224，920800，139307，107559)。For example, as shown in FIG. 4 , the electronic device 220 can determine the initialization layout 430 of the circuit according to the netlist file 410 and the layout file 420, and then insert the initialization layout 430 into the grid area 440 for subsequent calculation and position adjustment. The netlist file 410 is also called a connection list, which refers to a description method of the connection status of a digital circuit. The netlist usually conveys information about the circuit connection, such as the instance of the module, the wire net and related attributes. For example, in FIG. 4 , the netlist information includes three wire nets, N1, N2, and N3, and the wire net N1 includes the connection of three macro units, namely, macro unit M1, macro unit M3 and macro unit M4. The layout file 420 includes the position and length and width of each macro unit and the size of the area that can be laid out. For example, M1, x1, y1, w1, and h1 represent that the coordinates of the lower left corner of the macro unit M1 are x1 and y1, and the specific width and height of the macro unit M1 are w1 and h1, respectively. In this example, in order to facilitate subsequent description, the information of macro cell M1 is limited to (12280, 1133401, 139307, 107559), the information of macro cell M2 is limited to (1338224, 1133401, 119307, 107559), the information of macro cell M3 is limited to (12280, 14560, 119307, 107559), and the information of macro cell M4 is limited to (1338224, 920800, 139307, 107559).
计算设备220可以根据宏单元的大小来确定电路的整体布局区域的大小以及每个网格区域的大小。例可以根据如下等式(1)和(2)来确定路的整体布局区域的大小：The computing device 220 may determine the size of the overall layout area of the circuit and the size of each grid area according to the size of the macro unit. For example, the size of the overall layout area of the circuit may be determined according to the following equations (1) and (2):
Boundarywidth＝1551768＝1554048-2280 等式(1)Boundarywidth = 1551768 = 1554048-2280 Equation (1)
Boundaryheight＝1436400＝1440960-4560 等式(2)Boundaryheight = 1436400 = 1440960-4560 Equation (2)
其中布局区域的矩形大小的长为Boundarywidth，高为Boundaryheight，接着可以根据如下等式(3)和(4)确定网格区域中的每个网格的大小Cellwidth和Cellheight，The length of the rectangular size of the layout area is Boundarywidth , and the height is Boundaryheight . Then, the size of each grid in the grid area, Cellwidth and Cellheight , can be determined according to the following equations (3) and (4):
其中gridx和gridy表示每个网格区域的大小，其可以根据宏单元的平均大小而被确定，这里其均被设置为100。每个宏单元M1至M4可以由矩形边框[xl，yl，xu，yu]＝[xl，yl，xl+w，yl+h]表示。其中xl，yl为矩形边框的左下角坐标，xu，yu为矩形边框的右上角坐标。则对于每个宏单元，其矩形边框可以表示为：Wherein gridx and gridy represent the size of each grid area, which can be determined according to the average size of the macro unit, and are both set to 100 here. Each macro unit M1 to M4 can be represented by a rectangular border [xl ,yl ,xu ,yu ] = [xl ,yl ,xl +w,yl +h]. Whereinxl ,yl are the coordinates of the lower left corner of the rectangular border, andxu ,yu are the coordinates of the upper right corner of the rectangular border. Then for each macro unit, its rectangular border can be represented as:
M1＝[xl，yl，xu，yu]＝[12280，1133401，151587，1240960]M1＝[xl , yl , xu , yu ]＝[12280, 1133401, 151587, 1240960]
M2＝[xl，yl，xu，yu]＝[1338224，1133401，1457531，1240960]M2＝[xl , yl , xu , yu ]=[1338224, 1133401, 1457531, 1240960]
M3＝[xl，yl，xu，yu]＝[12280，14560，131587，122119]M3＝[xl , yl , xu , yu ]=[12280, 14560, 131587, 122119]
M4＝[xl，yl，xu，yu]＝[1338224，920800，1477531，1028359]M4＝[xl , yl , xu , yu ]＝[1338224, 920800, 1477531, 1028359]
然后图网格区域440所示，计算设备220可以根据如下对应关系将宏单元映射至相应区域：Then, as shown in the grid area 440, the computing device 220 may map the macro units to the corresponding areas according to the following correspondence:
请注意，上述数值仅仅是示例性的，其不旨在限制本公开的范围。Please note that the above numerical values are merely exemplary and are not intended to limit the scope of the present disclosure.
在一些实施例中，可以将网格区域440中的子网格划分为多个网格类型，已经摆放宏单元的网格为已摆放区域，未摆放的区域为可摆放区域，边界区域为不可摆放区域。将网格区域440进行分类便于后续宏单元的位置调整。发明人发现，将初始布局呈现为网格形式对后续的计算和宏单元位置的调整更有优势。利用网格表示电路布局也更加直观。上述以网格作为布局表示仅仅是示例性的，还可以利用能够表示宏单元的相对位置的其他布局方式，本公开在此不做限制。In some embodiments, the sub-grids in the grid area 440 can be divided into multiple grid types, the grids where macro units have been placed are placed areas, the areas where no macro units have been placed are placed areas, and the boundary areas are non-placeable areas. Classifying the grid area 440 facilitates the subsequent position adjustment of the macro units. The inventors have found that presenting the initial layout in the form of a grid is more advantageous for subsequent calculations and adjustments to the positions of the macro units. It is also more intuitive to use a grid to represent the circuit layout. The above-mentioned use of a grid as a layout representation is merely exemplary, and other layout methods that can represent the relative positions of the macro units can also be used, and the present disclosure is not limited here.
在框320，电子设备220基于布局规则或布线规则中的至少一项，调整待优化的宏单元在电路布局中的位置，以得到电路的目标布局。例如，在电子设备220在得到初始布局430和待优化的宏单元，例如宏单元M1之后，电子设备220可以根据电路的设计约束调整宏单元M1，例如调整到宏单元M2旁边，以得到目标布局。目标布局在时序、布线拥塞、规整度中的至少一项上优于初始布局。将在下文详细阐述如何调整待优化的宏单元在电路布局中的位置。根据本公开的方案，能够实现自动布局优化，节省了时间和人工成本。同时在优化布局时综合权衡多项优化目标，使得布局优化更具有针对性。In box 320, the electronic device 220 adjusts the position of the macro unit to be optimized in the circuit layout based on at least one of the layout rules or the wiring rules to obtain the target layout of the circuit. For example, after the electronic device 220 obtains the initial layout 430 and the macro unit to be optimized, such as macro unit M1, the electronic device 220 can adjust the macro unit M1 according to the design constraints of the circuit, for example, adjust it to the side of the macro unit M2 to obtain the target layout. The target layout is better than the initial layout in at least one of timing, wiring congestion, and regularity. How to adjust the position of the macro unit to be optimized in the circuit layout will be described in detail below. According to the scheme disclosed in the present invention, automatic layout optimization can be achieved, saving time and labor costs. At the same time, when optimizing the layout, a number of optimization goals are comprehensively weighed, so that the layout optimization is more targeted.
下面首先结合图5描述本公开中的电路布局的设计目标和待优化的宏单元的确定。图5A至图5C示出了根据本公开的一些实施例的电路的优化度量的示意图。图5A示出了根据本公开的一些实施例的电路的拥塞度量的示意图。计算设备220可以确定电路布局中的拥塞区域。拥塞区域可以是指电路布局中的布线密度较大的区域(例如大于阈值)，可以是指在横向/纵向上绕线需求较大的区域(例如大于阈值)或者其组合。拥塞区域可以通过热图的方式而被可视化，其中颜色较深的区域表示更为拥塞。The following first describes the design goals of the circuit layout in the present disclosure and the determination of the macro units to be optimized in conjunction with Figure 5. Figures 5A to 5C show schematic diagrams of optimization metrics for circuits according to some embodiments of the present disclosure. Figure 5A shows a schematic diagram of congestion metrics for circuits according to some embodiments of the present disclosure. The computing device 220 can determine a congested area in the circuit layout. A congested area may refer to an area with a larger wiring density in the circuit layout (e.g., greater than a threshold), may refer to an area with a larger winding demand in the horizontal/vertical direction (e.g., greater than a threshold), or a combination thereof. The congested area can be visualized in the form of a heat map, where darker areas indicate more congestion.
在一些实施例中，计算设备220可以根据电路布局510，利用概率模型(RUDY)确定拥塞区域。备选地，在一些实施例中，计算设备220可以根据电路布局510，利用AI决策模型确定拥塞区域。其中预测的精度为概率模型＜AI决策模型，而运行时长为概率模型＜AI决策模型。可以根据不同的场景选择不同的拥塞度预测方式。In some embodiments, the computing device 220 may determine the congested area using a probability model (RUDY) according to the circuit layout 510. Alternatively, in some embodiments, the computing device 220 may determine the congested area using an AI decision model according to the circuit layout 510. The prediction accuracy is the probability model < AI decision model, and the running time is the probability model < AI decision model. Different congestion prediction methods can be selected according to different scenarios.
计算设备220可以根据上述得到的拥塞图进行处理以确定拥塞区域，计算设备220可以将拥塞图中的拥塞区域通过K-Mean算法进行聚类后提取。提取的拥塞区域为K个多边形的集合，如图5A中的520所示，根据拥塞预测图提取到了三个拥塞区域。拥塞区域根据如下等式(5)进行升序排序：The computing device 220 can process the congestion map obtained above to determine the congestion area. The computing device 220 can extract the congestion area in the congestion map by clustering through theKMean algorithm. The extracted congestion area is a set of K polygons, as shown in 520 in FIG5A. Three congestion areas are extracted according to the congestion prediction map. The congestion areas are sorted in ascending order according to the following equation (5):
ScorehotspotK＝α×congestionavg+β×congestionpeak (等式5)ScorehotspotK =α×congestionavg +β×congestionpeak (Equation 5)
其中α×congestionavg表示区域的平均拥塞度，β×congestionpeak表示区域的平均拥塞度，此等式计算的结果ScorehotspotK表现为，拥塞区域计算数值越大，则说明该区域的拥塞程度更严重。α和β为权重，如果α值大，则挑选平均拥塞程度较大的区域，一般此区域拥塞分布较均匀。如果β值大，则挑选峰值较大的拥塞区域。在本公开中，α＝0.5和β＝0.5，意图在于权衡拥塞区域的平均拥塞值和拥塞峰值。当然，可以选择α和β的其他值，其不旨在限制本公开的范围。由此可以得到布局中的拥塞区域图5A中的520，其中灰度越深的区域表示区域中的布线越拥塞。Where α×congestionavg represents the average congestion of the area, β×congestionpeak represents the average congestion of the area, and the result of this equation calculation, ScorehotspotK , is expressed as follows: the larger the calculated value of the congested area, the more serious the congestion in the area. α and β are weights. If the α value is large, an area with a larger average congestion degree is selected, and generally the congestion distribution in this area is more uniform. If the β value is large, a congested area with a larger peak value is selected. In the present disclosure, α=0.5 and β=0.5 are intended to weigh the average congestion value and the congestion peak value of the congested area. Of course, other values of α and β can be selected, which are not intended to limit the scope of the present disclosure. Thus, 520 in Figure 5A of the congested area in the layout can be obtained, where the darker the grayscale area, the more congested the wiring in the area.
在确定了电路布局中的拥塞区域后，计算设备220可以将与拥塞区域相邻的区域中的宏单元确定为待优化宏单元。实验数据表明，区域拥塞的原因是由其附近的宏单元所造成的。因此可以选择靠近拥塞区域的宏单元优先作为待优化的宏单元进行下一步优化。After determining the congested area in the circuit layout, the computing device 220 may determine the macro cells in the area adjacent to the congested area as the macro cells to be optimized. Experimental data show that the cause of regional congestion is caused by the macro cells nearby. Therefore, the macro cells close to the congested area may be selected as the macro cells to be optimized for the next step of optimization.
图5B示出了根据本公开的一些实施例的电路的时序/数据流度量的示意图。计算设备220根据给定的网表信息，可以确定宏单元之间的关联程度，该关联程度可以与宏单元之间的连线的数目和传输的数据的位宽相关联，也即连线数目越大，传输数据位宽越大，则关联程度越高。在一些实施例中，计算设备220可以根据网表信息创建相对应的网表连接图，再对网表连接图进行搜索，得到每个宏单元之间的连接路径，再用权重表示模块之间的连接关系，提取后的数据流连接关系如图5B中的数据流关系530所示。具体的表现为如果两个宏单元之间的连接关系越强，那么表现为两者之间的权重越大。如数据流关系530所示，四个宏单元之间的数值越高，表示宏单元之间的连接关系越强。FIG5B shows a schematic diagram of the timing/data flow metrics of the circuit according to some embodiments of the present disclosure. The computing device 220 can determine the degree of association between the macro units according to the given netlist information, and the degree of association can be associated with the number of wires between the macro units and the bit width of the transmitted data, that is, the larger the number of wires and the larger the bit width of the transmitted data, the higher the degree of association. In some embodiments, the computing device 220 can create a corresponding netlist connection diagram according to the netlist information, and then search the netlist connection diagram to obtain the connection path between each macro unit, and then use the weight to represent the connection relationship between the modules. The extracted data flow connection relationship is shown in the data flow relationship 530 in FIG5B. Specifically, if the connection relationship between two macro units is stronger, then the weight between the two is greater. As shown in the data flow relationship 530, the higher the value between the four macro units, the stronger the connection relationship between the macro units.
计算设备220然后能够根据初始布局，根据如下等式计算每个摆放的宏单元(例如宏单元A)的数据流值：The computing device 220 can then calculate the data flow value of each placed macro cell (eg, macro cell A) according to the initial layout according to the following equation:
其中M为跟宏单元A有连接的宏模块组，P为跟宏单元A有连接的电路的端口，w为两个宏单元模块之间的权重(也即图5B中的数据流关系530中的数值)，Dist为两个宏单元中心点之间的距离，这里计算的距离是两点之间的曼哈顿距离，如以下等式所示：Wherein M is a macromodule group connected to macrocell A, P is a port of a circuit connected to macrocell A, w is a weight between two macrocell modules (i.e., a value in data flow relationship 530 in FIG. 5B ), Dist is a distance between the center points of the two macrocells, and the distance calculated here is a Manhattan distance between the two points, as shown in the following equation:
Dist(A，B)＝|xA-xB|+|yA-yB| (等式7)Dist(A,B)=|xA -xB |+|yA -yB | (Equation 7)
其中xA、yA和xB、yB分别为宏单元A和宏单元B的中心点位置。等式6是通过实验得出的，具体的表现为数据流评估值跟两个相互连接宏单元的距离平方成反比、而跟两个相互连接宏单元的数据流权重成正比。此等式的意义在于过滤数据流权重数值小但是距离远的宏模块连接。将每个宏单元根据等式6的计算数值进行升序排序。值得注意的是，此计算数值越高，说明此宏单元与其他有强关联的单元(无论是宏单元模块或者是端口)之间的距离越远。具体反映为时序越差，所以可以作为候选的待优化的宏单元进行下一步的优化。这里候选的待优化的宏单元的比率可以为用户自定义参数，可以根据电路设计信息中的宏单元总数量的百分比或者固定值来限制挑选的待优化的宏单元的数量。可以理解，此值越高，则待优化的宏单元越多，那么相对应的算法运行时间则越长。WherexA ,yA andxB ,yB are the center points of macrocell A and macrocell B respectively. Equation 6 is obtained through experiments, and specifically shows that the data flow evaluation value is inversely proportional to the square of the distance between two interconnected macrocells, and is proportional to the data flow weight of the two interconnected macrocells. The significance of this equation is to filter macromodule connections with small data flow weight values but long distances. Sort each macrocell in ascending order according to the calculated value of equation 6. It is worth noting that the higher this calculated value is, the farther the distance between this macrocell and other strongly associated units (whether macrocell modules or ports) is. Specifically, it is reflected in the worse timing, so it can be used as a candidate macrocell to be optimized for the next step of optimization. Here, the ratio of the candidate macrocell to be optimized can be a user-defined parameter, and the number of selected macrocells to be optimized can be limited according to the percentage of the total number of macrocells in the circuit design information or a fixed value. It can be understood that the higher this value is, the more macrocells to be optimized, and the longer the corresponding algorithm running time.
图5C示出了根据本公开的一些实施例的电路的规整度量的示意图。规整度量是指电路布局中的可布局区域(例如电路布局540和550中的空白区域)的规整情况。可以理解，可布局区域越规整，越有利于接下来的标准单元布局和最终的绕线。本公开考虑的规整度量regularity如以下等式所示：FIG5C shows a schematic diagram of the regularity metric of a circuit according to some embodiments of the present disclosure. The regularity metric refers to the regularity of the layout-able area in the circuit layout (e.g., the blank area in the circuit layout 540 and 550). It can be understood that the more regular the layout-able area is, the more conducive it is to the subsequent standard cell layout and the final routing. The regularity metric considered in the present disclosure is shown in the following equation:
等式8中area为空白的可布局区域的面积，perimeter为空白可布局的区域的周长。如图5C所示，根据计算，电路布局540的规整度为0.77，电路布局550的规整度为0.53。此规整度量的数值越大，说明对应的可摆放区域的规整度越好。在一些实施例中，计算设备220可以调整初始布局中的宏单元，以实现更好的规整度，从而实现电路布局的优化。In equation 8, area is the area of the blank layout area, and perimeter is the perimeter of the blank layout area. As shown in FIG. 5C , according to the calculation, the regularity of circuit layout 540 is 0.77, and the regularity of circuit layout 550 is 0.53. The larger the value of this regularity metric, the better the regularity of the corresponding layout area. In some embodiments, the computing device 220 can adjust the macro units in the initial layout to achieve better regularity, thereby optimizing the circuit layout.
在图5A至图5C中介绍了设计目标和待优化的宏单元，在下文将结合图6至图8介绍待优化的宏单元的位置调整。将首先结合图6介绍以拥塞为目标的布局优化。图6示出了根据本公开的一些实施例的用于优化电路布局的示意图。如在图5A中所讨论的，计算设备220可以基于初始化布局，确定初始化布局中的拥塞区域，然后将与拥塞区域相邻的区域中的宏单元确定为待优化的宏单元。例如，如图6中所示，宏单元612被确定为待优化的宏单元。The design goal and the macrocells to be optimized are introduced in FIGS. 5A to 5C , and the position adjustment of the macrocells to be optimized will be introduced in conjunction with FIGS. 6 to 8 hereinafter. The layout optimization with congestion as the target will be first introduced in conjunction with FIG. 6 . FIG. 6 shows a schematic diagram for optimizing the circuit layout according to some embodiments of the present disclosure. As discussed in FIG. 5A , the computing device 220 may determine the congested area in the initialized layout based on the initialized layout, and then determine the macrocells in the area adjacent to the congested area as the macrocells to be optimized. For example, as shown in FIG. 6 , the macrocell 612 is determined as the macrocell to be optimized.
计算设备220可以基于布线规则和初始化布局，确定至少一个候选区域。在一些实施例中，计算设备220可以基于布线规则，确定与待优化的宏单元612连接的非待优化的宏单元，以及基于初始化布局，将与非待优化的宏单元所在的区域相邻的区域622确定为至少一个候选区域。在一些其他实施例中，计算设备220可以将待优化的宏单元612调整至邻近宏单元612的区域。备选地，在一些实施例中，计算设备220还可以基于电路布局中的所有可布局区域进行位置调整。The computing device 220 may determine at least one candidate region based on the wiring rules and the initialization layout. In some embodiments, the computing device 220 may determine the macrocells not to be optimized connected to the macrocells 612 to be optimized based on the wiring rules, and determine the region 622 adjacent to the region where the macrocells not to be optimized are located as at least one candidate region based on the initialization layout. In some other embodiments, the computing device 220 may adjust the macrocells 612 to be optimized to the region adjacent to the macrocells 612. Alternatively, in some embodiments, the computing device 220 may also perform position adjustment based on all layout-capable regions in the circuit layout.
发明人经过实验发现，是基于与待优化的宏单元连接的非待优化的宏单元周围的区域进行位置调整更加合理(也即电路布局620中的多个虚线框所标识的区域622)。因此，在本公开的后续内容中，将基于与与待优化的宏单元连接的非待优化的宏单元周围的区域进行位置调整的假设进行讨论。这仅仅是示例性的。还可以根据电路布局的需要采取其他调整方式，本公开在此不做限制。The inventor has found through experiments that it is more reasonable to adjust the position based on the area around the macro unit not to be optimized connected to the macro unit to be optimized (that is, the area 622 marked by multiple dotted boxes in the circuit layout 620). Therefore, in the subsequent content of this disclosure, the discussion will be based on the assumption that the position adjustment is performed on the area around the macro unit not to be optimized connected to the macro unit to be optimized. This is only exemplary. Other adjustment methods can also be adopted according to the needs of the circuit layout, and this disclosure is not limited here.
计算设备220然后可以基于布局规则和布线规则中的至少一项，从至少一个候选区域确定目标区域。在一些实施例中，对于电路布局620中虚线框所标识的至少一个候选区域，计算设备220可以基于布局规则和布线规则中的至少一项，确定至少一个候选电路布局的优化度量，优化度量与电路布局的拥塞度量、时序度量以及规整度量相关联。然后计算设备220可以将与至少一个候选电路布局中的、优化度量大于阈值优化度量的候选电路布局相关联的候选区域确定为目标区域。The computing device 220 may then determine a target region from at least one candidate region based on at least one of the layout rule and the routing rule. In some embodiments, for at least one candidate region identified by a dotted box in the circuit layout 620, the computing device 220 may determine an optimization metric of at least one candidate circuit layout based on at least one of the layout rule and the routing rule, the optimization metric being associated with a congestion metric, a timing metric, and a regularization metric of the circuit layout. The computing device 220 may then determine a candidate region associated with a candidate circuit layout having an optimization metric greater than a threshold optimization metric in at least one candidate circuit layout as a target region.
例如，对于每个待优化的宏单元(这里为宏单元612)，在优化前都将会先获得当前新的摆放位置，在此之前，可以根据如下等式计算出每个可以摆放的优化度量Costpos：For example, for each macro unit to be optimized (here, macro unit 612), the current new placement position will be obtained before optimization. Before this, the optimization metric Costpos of each possible placement can be calculated according to the following equation:
Costpos＝α×congestionpos+β×dataflowpos-γ×regularitypos+δ×WL (等式9)Costpos = α × congestionpos + β × dataflowpos - γ × regularitypos + δ × WL (Equation 9)
其中congestionpos为所在区域的拥塞度量(参见上文中的等式5)，dataflowpos为区域数据流度量(参见上文中的等式6)，regularitypos为新的可摆放区域的规整度量(参见上文中的等式8)、WL为线长，α、β、γ、δ例如可以被设置为0.8、0.6、0.5和0.5，意图在权衡不同的目标时，尽可能的优化主目标，同时兼顾其他的优化目标。在这里，拥塞为设计目标，因此可以将α设置为尽可能高。计算设备220可以挑选出优化度量Costpos最低的位置为对应的最佳位置622，以进行宏单元612重新摆放。之后计算设备220可以将待优化的宏单元612的位置调整至目标区域622，以得到电路的目标布局。Where congestionpos is the congestion metric of the area (see equation 5 above), dataflowpos is the regional data flow metric (see equation 6 above), regularitypos is the regularity metric of the new placeable area (see equation 8 above), WL is the line length, and α, β, γ, δ can be set to 0.8, 0.6, 0.5 and 0.5, for example, with the intention of optimizing the main goal as much as possible while taking into account other optimization goals when weighing different goals. Here, congestion is the design goal, so α can be set as high as possible. The computing device 220 can select the position with the lowest optimization metric Costpos as the corresponding optimal position 622 to rearrange the macro unit 612. The computing device 220 can then adjust the position of the macro unit 612 to be optimized to the target area 622 to obtain the target layout of the circuit.
在上文结合图6描述了以拥塞为目标的布局优化。下面结合图7和图8描述以时序为目标的布局优化。首先结合图7描述待优化的宏单元的位置的互换。图7示出了根据本公开的另一些实施例的用于优化电路布局的示意图。例如上文在图5B中所讨论的，计算设备220针对每个宏单元，基于初始化布局，确定电路中的多个宏单元之间的距离和多个宏单元之间的关联程度，关联程度与宏单元之间的连线数目和传输的数据量相关联然后可以基于距离和关联程度，确定多个宏单元中的每个宏单元的数据流度量。接着将多个宏单元中的、数据流度量小于阈值数据流度量的宏单元确定为待优化的宏单元。The layout optimization targeting congestion is described above in conjunction with FIG6. The layout optimization targeting timing is described below in conjunction with FIG7 and FIG8. First, the interchange of the positions of the macro cells to be optimized is described in conjunction with FIG7. FIG7 shows a schematic diagram for optimizing the circuit layout according to other embodiments of the present disclosure. For example, as discussed above in FIG5B, the computing device 220 determines, for each macro cell, the distance between multiple macro cells in the circuit and the degree of association between the multiple macro cells based on the initialization layout, and the degree of association is associated with the number of connections between the macro cells and the amount of data transmitted. Then, based on the distance and the degree of association, the data flow metric of each macro cell in the multiple macro cells can be determined. Then, the macro cells in the multiple macro cells whose data flow metric is less than the threshold data flow metric are determined as the macro cells to be optimized.
例如，对于图7中的电路布局710中的每个宏单元，继续以图4中的数字作为示例，计算设备220可以确定每个宏单元的数据流度量。首先，计算每个宏单元的中心点位置：For example, for each macrocell in the circuit layout 710 in FIG. 7 , continuing with the numbers in FIG. 4 as an example, the computing device 220 may determine the data flow metric for each macrocell. First, the center point position of each macrocell is calculated:
接着再计算出每个宏单元的之间的中心点距离Then calculate the center point distance between each macro unit
Dist(M1，M2)＝|xcennterM1-xCenter32|+|ycenterM1-yCener32|＝|81933-1397878|+|1187181-1187181|＝1315945Dist(M1, M2)＝|xcennterM1 -xCenter32 |+|ycenterM1 -yCener32 |＝|81933-1397878|+|1187181-1187181|＝1315945
Dist(M1，M3)＝|xcenterM1-xCenterM3|+|ycenterM1-yCenterM3|＝|81933-71933|+|1187181-68339|＝1128842Dist(M1, M3)＝|xcenterM1 -xCenterM3 |+|ycenterM1 -yCenterM3 |＝|81933-71933|+|1187181-68339|＝1128842
Dist(M1，M4)＝|xcenterM1-xCenterM4|+|ycenterM1-yCenterM4|＝|81933-1407878|+|1187181-974579|＝1538547Dist(M1, M4)＝|xcenterM1 -xCenterM4 |+|ycenterM1 -yCenterM4 |＝|81933-1407878|+|1187181-974579|＝1538547
Dist(M3，M4)＝|xcenterM3-xCenterM4|+|yrenrerM3-ycenterM4|＝|71933-1407878|+|68339-9579622|＝2242185Dist(M3, M4)＝|xcenterM3 -xCenterM4 |+|yrenrerM3 -ycenterM4 |＝|71933-1407878|+|68339-9579622|＝2242185
根据上述等式6，计算数据流度量：According to Equation 6 above, the data flow metric is calculated:
计算设备220根据数据流度量进行升序排序，得到的排序为M1、M3、M4、M2，根据算法缺省值，挑选50％的宏单元作为待优化的宏达暖，得到最终待优化候选者为M1(对应于电路布局中的宏单元712)和M3(对应于电路布局中的宏单元714)。The computing device 220 performs ascending sorting according to the data flow metric, and the resulting sorting is M1, M3, M4, M2. According to the algorithm default value, 50% of the macro cells are selected as the macro cells to be optimized, and the final candidates to be optimized are M1 (corresponding to the macro cell 712 in the circuit layout) and M3 (corresponding to the macro cell 714 in the circuit layout).
在一些实施例中，计算设备220响应于确定与非待优化的宏单元所在区域相邻的区域中存在至少另一待优化的宏单元，确定待优化宏单元与至少另一待优化的宏单元的相似度，相似度指示待优化宏单元与至少另一待优化宏单元的大小、引脚方向以及宏单元方向之间的差异。计算设备220响应于确定相似度大于阈值相似度，将待优化宏单元与至少另一待优化宏单元的位置进行交换，以得到至少一个候选电路布局。基于布局规则和布线规则中的至少一项，确定至少一个候选电路布局的优化度量，优化度量与电路布局的拥塞度量、时序度量以及规整度量相关联；将与至少一个候选电路布局中的、优化度量大于阈值优化度量的候选电路布局相关联的候选区域确定为目标区域；以及将待优化的宏单元与目标区域中的另一待优化宏单元的位置进行交换，以得到电路的目标布局。In some embodiments, the computing device 220 determines the similarity between the macro cell to be optimized and the at least one macro cell to be optimized in response to determining that there is at least one other macro cell to be optimized in an area adjacent to the area where the macro cell not to be optimized is located, and the similarity indicates the difference between the size, pin direction and macro cell direction of the macro cell to be optimized and the at least one other macro cell to be optimized. In response to determining that the similarity is greater than a threshold similarity, the computing device 220 swaps the position of the macro cell to be optimized with the at least one other macro cell to be optimized to obtain at least one candidate circuit layout. Based on at least one of the layout rules and the routing rules, an optimization metric of at least one candidate circuit layout is determined, and the optimization metric is associated with the congestion metric, the timing metric and the regularity metric of the circuit layout; a candidate area associated with the candidate circuit layout in the at least one candidate circuit layout whose optimization metric is greater than the threshold optimization metric is determined as a target area; and the position of the macro cell to be optimized is swapped with another macro cell to be optimized in the target area to obtain a target layout of the circuit.
此时，由于存在两个待优化的宏单元712和714，宏单元712处于与宏单元714相连接的宏单元周围，并且宏单元714也处于与宏单元712相连接的宏单元周围，此时可以考虑将宏单元714与宏单元712的位置交换。在一些实施例中，在交换位置之前，计算设备220确定待优化宏单元与至少另一待优化的宏单元的相似度，相似度指示待优化宏单元与至少另一待优化宏单元的大小、引脚方向以及宏单元方向之间的差异。例如计算设备220计算两个不同布局的宏单元的相似程度，根据判断其大小、引脚的朝向以及自身模块朝向是否一致来决定是否互换。如果一致，那么两个宏单元模块之间就可以通过互换的形式来进行调优。At this time, since there are two macrocells 712 and 714 to be optimized, macrocell 712 is around the macrocell connected to macrocell 714, and macrocell 714 is also around the macrocell connected to macrocell 712, it is possible to consider exchanging the positions of macrocell 714 and macrocell 712. In some embodiments, before exchanging positions, the computing device 220 determines the similarity between the macrocell to be optimized and at least another macrocell to be optimized, and the similarity indicates the difference between the size, pin direction and macrocell direction of the macrocell to be optimized and at least another macrocell to be optimized. For example, the computing device 220 calculates the similarity of two macrocells with different layouts, and determines whether to exchange them based on whether their size, pin direction and module direction are consistent. If they are consistent, then the two macrocell modules can be tuned by exchanging them.
计算设备220可以通过上述等式9计算出未经优化之前的电路布局的优化度量dataflowDistbefore和两个宏单元交换位置之后的电路布局的优化度量dataflowDistafter。如果dataflowDistafter＜dataflowDistbefore，则说明两个宏单元可以进行两两互换，因为交换后可以带来时序上的优化收益。如图7所示，对宏单元712和714进行位置的交换后，数据流连接飞线得到了优化。具体表现是两两连接的飞线距离变短了，实现了时序上的优化。The computing device 220 can calculate the optimization metric dataflowDist before of the circuit layoutbefore optimization and the optimization metric dataflowDistafter of the circuit layout after the two macro cells exchange positions through the above equation 9. If dataflowDistafter < dataflowDistbefore , it means that the two macro cells can be exchanged in pairs, because the exchange can bring timing optimization benefits. As shown in Figure 7, after the macro cells 712 and 714 are exchanged in position, the data flow connection flying wire is optimized. The specific performance is that the distance between the flying wires connected in pairs becomes shorter, which achieves timing optimization.
可以理解，在一些情况下可能不存在可以互换的宏单元，例如待优化的宏单元之间的相似度较低(低于阈值)或者仅存在一个待优化的宏单元，此时需要考虑宏单元的位置移动。接着结合图8描述待优化的宏单元的位置的调整。图8示出了根据本公开的又一些实施例的用于优化电路布局的示意图。如图8所示，需要对宏单元812进行优化，此时，不存在能够与宏单元812进行交换的宏单元。It is understood that in some cases there may not be interchangeable macrocells, for example, the similarity between the macrocells to be optimized is low (below a threshold) or there is only one macrocell to be optimized, in which case the position movement of the macrocell needs to be considered. Next, the adjustment of the position of the macrocell to be optimized is described in conjunction with FIG8. FIG8 shows a schematic diagram for optimizing circuit layout according to some other embodiments of the present disclosure. As shown in FIG8, it is necessary to optimize macrocell 812, and at this time, there is no macrocell that can be exchanged with macrocell 812.
在一些实施例中，计算设备220响应于确定与非待优化宏单元所在区域相邻的区域中不存在另一待优化的宏单元，将待优化宏单元调整到候选区域，以得到至少一个候选电路布局，候选区域与非待优化宏单元所在的区域相。计算设备220然后基于布局规则和布线规则中的至少一项，确定至少一个候选电路布局的优化度量，优化度量与电路布局的拥塞度量、时序度量以及规整度量相关联。之后将与至少一个候选电路布局中的、优化度量大于阈值优化度量的候选电路布局相关联的候选区域确定为目标区域。以及将待优化的宏单元调整至目标区域，以得到电路的目标布局。In some embodiments, in response to determining that there is no other macrocell to be optimized in an area adjacent to the area where the macrocell not to be optimized is located, the computing device 220 adjusts the macrocell to be optimized to a candidate area to obtain at least one candidate circuit layout, and the candidate area is adjacent to the area where the macrocell not to be optimized is located. The computing device 220 then determines the optimization metric of at least one candidate circuit layout based on at least one of the layout rules and the wiring rules, and the optimization metric is associated with the congestion metric, the timing metric, and the regularity metric of the circuit layout. Thereafter, the candidate area associated with the candidate circuit layout whose optimization metric is greater than the threshold optimization metric in at least one candidate circuit layout is determined as the target area. And the macrocell to be optimized is adjusted to the target area to obtain the target layout of the circuit.
例对于宏单元812，计算设备220得到所有候选的可以摆放的新位置。当得到所有的候选位置之后，将通过不同的条件对候选位置进行过滤，具体方法为根据如下等式10，分别计算出每个候选位置的数据流度量和规整度量，进行候选位置的比较，选取优化度量最低的位置作为最佳候选位置，以进行宏单元的摆放：For example, for macro unit 812, computing device 220 obtains all candidate new positions that can be placed. After all candidate positions are obtained, the candidate positions are filtered by different conditions. The specific method is to calculate the data flow metric and regularity metric of each candidate position according to the following equation 10, compare the candidate positions, and select the position with the lowest optimization metric as the best candidate position for placing the macro unit:
Costpos＝α×dataflowpos-β×regularitypos+γ×WL (等式10)Costpos = α × dataflowpos - β × regularitypos + γ × WL (Equation 10)
其中dataflowpos为区域数据流评估值，regularitypos为新的可摆放区域的规整度、WL为线长。算法中α，β，γ的设置为0.8、0.5和0.5，意图在权衡不同的目标，尽可能的优化主目标的同时，兼顾其他的优化目标。之后计算设备220可以确定目标电路布局820。Where dataflowpos is the regional data flow evaluation value, regularitypos is the regularity of the new placement area, and WL is the line length. In the algorithm, α, β, and γ are set to 0.8, 0.5, and 0.5, with the intention of weighing different goals and optimizing the main goal as much as possible while taking into account other optimization goals. The computing device 220 can then determine the target circuit layout 820.
在上文中已经参考图1至图8详细描述了根据本公开的方法的示例实现，在下文中将描述相应的装置的实现。An example implementation of the method according to the present disclosure has been described in detail above with reference to FIGS. 1 to 8 , and implementation of the corresponding apparatus will be described hereinafter.
图9示出了根据本公开的一些实施例的用于优化电路布局的示例装置的框图。该装置900例如可以用于实现如图2的电子设备。该装置900上安装有EDA软件，或者装置900实质上可以被称为EDA软件装置，装置900中的每个模块可以利用EDA软件实现不同的芯片设计和测试功能。如图9所示，装置900包括：待优化宏单元确定模块910，被配置为基于电路的初始化布局和设计目标，确定电路中的待优化的宏单元，设计目标包括时序目标、拥塞目标或宏单元规整度中的至少一项；以及目标布局确定模块920，被配置为基于布局规则或布线规则中的至少一项，调整待优化的宏单元在电路布局中的位置，以得到电路的目标布局。FIG9 shows a block diagram of an example device for optimizing circuit layout according to some embodiments of the present disclosure. The device 900 can be used to implement an electronic device as shown in FIG2, for example. EDA software is installed on the device 900, or the device 900 can be substantially called an EDA software device, and each module in the device 900 can use the EDA software to implement different chip design and test functions. As shown in FIG9, the device 900 includes: a macro cell determination module 910 to be optimized, which is configured to determine the macro cells to be optimized in the circuit based on the initialization layout and design goals of the circuit, and the design goals include at least one of the timing goals, congestion goals or macro cell regularity; and a target layout determination module 920, which is configured to adjust the position of the macro cells to be optimized in the circuit layout based on at least one of the layout rules or the wiring rules to obtain the target layout of the circuit.
在一些实施例中，待优化宏单元确定模块910可以包括：拥塞区域确定模块，被配置为基于初始化布局，确定初始化布局中的拥塞区域，拥塞区域指示布线复杂程度大于阈值复杂程度的区域；以及第一宏单元确定模块，被配置为将与拥塞区域相邻的区域中的宏单元确定为待优化宏的单元。In some embodiments, the macro cell determination module 910 to be optimized may include: a congested area determination module, configured to determine a congested area in the initialization layout based on the initialization layout, the congested area indicating an area where the wiring complexity is greater than a threshold complexity; and a first macro cell determination module, configured to determine macro cells in an area adjacent to the congested area as macro cells to be optimized.
在一些实施例中，目标布局确定模块920可以包括：第一候选区域确定模块，被配置为基于布线规则和初始化布局，确定至少一个候选区域；目标区域确定模块，被配置为基于布局规则和布线规则中的至少一项，从至少一个候选区域确定目标区域；以及第一目标布局获取模块，被配置为将待优化的宏单元的位置调整至目标区域，以得到电路的目标布局。In some embodiments, the target layout determination module 920 may include: a first candidate area determination module, configured to determine at least one candidate area based on wiring rules and initialization layout; a target area determination module, configured to determine a target area from at least one candidate area based on at least one of layout rules and wiring rules; and a first target layout acquisition module, configured to adjust the position of the macro unit to be optimized to the target area to obtain a target layout of the circuit.
在一些实施例中，第一候选区域确定模块可以包括：第一非待优化宏单元确定模块，被配置为基于布线规则，确定与待优化的宏单元连接的非待优化的宏单元；以及第二候选区域确定模块，被配置为基于初始化布局，将与非待优化的宏单元所在的区域相邻的区域确定为至少一个候选区域。In some embodiments, the first candidate area determination module may include: a first non-macro cell determination module configured to determine the non-macro cells to be optimized connected to the macro cells to be optimized based on wiring rules; and a second candidate area determination module configured to determine the area adjacent to the area where the non-macro cells to be optimized are located as at least one candidate area based on the initialization layout.
在一些实施例中，目标区域确定模块可以包括：第一候选电路布局确定模块，被配置为将待优化的宏单元的位置调整至至少一个候选区域，以得到电路的至少一个候选电路布局；第一优化度量确定模块，被配置为基于布局规则和布线规则中的至少一项，确定至少一个候选电路布局的优化度量，优化度量与电路布局的拥塞度量、时序度量以及规整度量相关联；以及第一目标区域选择模块，被配置为将与至少一个候选电路布局中的、优化度量大于阈值优化度量的候选电路布局相关联的候选区域确定为目标区域。In some embodiments, the target area determination module may include: a first candidate circuit layout determination module, configured to adjust the position of the macro unit to be optimized to at least one candidate area to obtain at least one candidate circuit layout of the circuit; a first optimization metric determination module, configured to determine the optimization metric of at least one candidate circuit layout based on at least one of the layout rules and the wiring rules, the optimization metric being associated with the congestion metric, the timing metric, and the regularity metric of the circuit layout; and a first target area selection module, configured to determine a candidate area associated with a candidate circuit layout in at least one candidate circuit layout whose optimization metric is greater than a threshold optimization metric as a target area.
在一些实施例中，待优化宏单元确定模块910可以包括：关联程度确定模块，被配置为基于初始化布局，确定电路中的多个宏单元之间的距离和多个宏单元之间的关联程度，关联程度与宏单元之间的连线数目和传输的数据量相关联；数据流度量确定模块，被配置为基于距离和关联程度，确定多个宏单元中的每个宏单元的数据流度量；以及第二宏单元确定模块，被配置为将多个宏单元中的、数据流度量小于阈值数据流度量的宏单元确定为待优化的宏单元。In some embodiments, the macro cell determination module 910 to be optimized may include: an association degree determination module, configured to determine the distance between multiple macro cells in the circuit and the degree of association between the multiple macro cells based on the initialization layout, the degree of association being associated with the number of connections between the macro cells and the amount of data transmitted; a data flow metric determination module, configured to determine the data flow metric of each macro cell among the multiple macro cells based on the distance and the degree of association; and a second macro cell determination module, configured to determine a macro cell among the multiple macro cells whose data flow metric is less than a threshold data flow metric as a macro cell to be optimized.
在一些实施例中，目标布局确定模块920可以包括：第二非待优化宏单元确定模块，被配置为基于布线规则，确定与待优化的宏单元连接的非待优化宏单元；以及宏单元调整模块，被配置为基于布局规则和布线规则，将待优化的宏单元调整至与非待优化宏单元所在区域相邻的目标区域中，调整包括宏单元位置互换或宏单元位置改变中的至少一项。In some embodiments, the target layout determination module 920 may include: a second non-macro cell determination module configured to determine the non-macro cells to be optimized connected to the macro cells to be optimized based on the wiring rules; and a macro cell adjustment module configured to adjust the macro cells to be optimized to a target area adjacent to the area where the non-macro cells to be optimized are located based on the layout rules and the wiring rules, the adjustment including at least one of macro cell position interchange or macro cell position change.
在一些实施例中，宏单元调整模块可以包括：相似度确定模块，被配置为响应于确定与非待优化的宏单元所在区域相邻的区域中存在至少另一待优化的宏单元，确定待优化宏单元与至少另一待优化的宏单元的相似度，相似度指示待优化宏单元与至少另一待优化宏单元的大小、引脚方向以及宏单元方向之间的差异；宏单元交换模块，被配置为响应于确定相似度大于阈值相似度，将待优化宏单元与至少另一待优化宏单元的位置进行交换，以得到至少一个候选电路布局；第二优化度量确定模块，被配置为基于布局规则和布线规则中的至少一项，确定至少一个候选电路布局的优化度量，优化度量与电路布局的拥塞度量、时序度量以及规整度量相关联；第二目标区域选择模块，被配置为将与至少一个候选电路布局中的、优化度量大于阈值优化度量的候选电路布局相关联的候选区域确定为目标区域；以及第二目标布局获取模块，被配置为将待优化的宏单元与目标区域中的另一待优化宏单元的位置进行交换，以得到电路的目标布局。In some embodiments, the macrocell adjustment module may include: a similarity determination module configured to determine the similarity between the macrocell to be optimized and the at least one macrocell to be optimized in response to determining that there is at least one other macrocell to be optimized in an area adjacent to the area where the macrocell not to be optimized is located, the similarity indicating the difference between the size, pin direction and macrocell direction of the macrocell to be optimized and the at least one other macrocell to be optimized; a macrocell exchange module configured to exchange the position of the macrocell to be optimized with the at least one other macrocell to be optimized in response to determining that the similarity is greater than a threshold similarity, so as to obtain at least one candidate circuit layout; a second optimization metric determination module configured to determine the optimization metric of at least one candidate circuit layout based on at least one of the layout rule and the routing rule, the optimization metric being associated with the congestion metric, the timing metric and the regularity metric of the circuit layout; a second target area selection module configured to determine a candidate area associated with a candidate circuit layout in at least one candidate circuit layout whose optimization metric is greater than the threshold optimization metric as a target area; and a second target layout acquisition module configured to exchange the position of the macrocell to be optimized with another macrocell to be optimized in the target area to obtain a target layout of the circuit.
在一些实施例中，宏单元调整模块可以包括：第二候选电路布局确定模块，被配置为响应于确定与非待优化宏单元所在区域相邻的区域中不存在另一待优化的宏单元，将待优化宏单元调整到候选区域，以得到至少一个候选电路布局，候选区域与非待优化宏单元所在的区域相邻；第三优化度量确定模块，被配置为基于布局规则和布线规则中的至少一项，确定至少一个候选电路布局的优化度量，优化度量与电路布局的拥塞度量、时序度量以及规整度量相关联；第三目标区域选择模块，被配置为将与至少一个候选电路布局中的、优化度量大于阈值优化度量的候选电路布局相关联的候选区域确定为目标区域；以及第三目标布局获取模块，被配置为将待优化的宏单元调整至目标区域，以得到电路的目标布局。In some embodiments, the macro cell adjustment module may include: a second candidate circuit layout determination module, configured to adjust the macro cell to be optimized to the candidate area in response to determining that there is no other macro cell to be optimized in the area adjacent to the area where the macro cell not to be optimized is located, so as to obtain at least one candidate circuit layout, the candidate area being adjacent to the area where the macro cell not to be optimized is located; a third optimization metric determination module, configured to determine the optimization metric of at least one candidate circuit layout based on at least one of the layout rules and the wiring rules, the optimization metric being associated with the congestion metric, the timing metric and the regularity metric of the circuit layout; a third target area selection module, configured to determine a candidate area associated with a candidate circuit layout in at least one candidate circuit layout whose optimization metric is greater than a threshold optimization metric as a target area; and a third target layout acquisition module, configured to adjust the macro cell to be optimized to the target area to obtain a target layout of the circuit.
在一些实施例中，规整度量与电路布局中可设置宏单元的区域的面积和周长相关联，数据流度量与宏单元之间的关联程度和距离相关联，拥塞度量与电路布局中的布线复杂程度相关联。In some embodiments, the regularity metric is associated with the area and perimeter of a region in the circuit layout where macro cells can be set, the data flow metric is associated with the degree of association and distance between macro cells, and the congestion metric is associated with the routing complexity in the circuit layout.
在一些实施例中，装置900还可以包括：宏单元大小确定模块，被配置为基于用于实现电路的设计信息，确定多个宏单元的平均大小；区域划分模块，被配置为基于平均大小，将电路版图划分为多个区域；以及初始布局确定模块，被配置为基于用于表征电路的网表文件，将多个宏单元设置在多个区域中，以得到始化布局。In some embodiments, the device 900 may also include: a macro cell size determination module, configured to determine the average size of multiple macro cells based on design information used to implement the circuit; a region division module, configured to divide the circuit layout into multiple regions based on the average size; and an initial layout determination module, configured to set multiple macro cells in multiple regions based on a netlist file used to characterize the circuit to obtain an initial layout.
图10示出了可以用于实施本公开的一些实施例的示例设备的示意性框图。设备1000可以用于实现电子设备。设备1000可以包括仿真系统，仿真系统上安装有EDA软件，设备1000可以利用EDA软件实施本公开所描述的过程。FIG10 shows a schematic block diagram of an example device that can be used to implement some embodiments of the present disclosure. Device 1000 can be used to implement an electronic device. Device 1000 can include a simulation system, on which EDA software is installed, and device 1000 can use the EDA software to implement the process described in the present disclosure.
图10示出了可以用于实施本公开的一些实施例的示例设备1000的示意性框图。设备1000可以用于实现电子设备。如图10所示，设备1000包括中央处理单元(CPU)1001，其可以根据存储在只读存储器(ROM)1002中的计算机程序指令或者从存储单元1008加载到随机访问存储器(RAM)1003中的计算机程序指令，来执行各种适当的动作和处理。在RAM 1003中，还可存储设备1000操作所需的各种程序和数据。CPU 1001、ROM 1002以及RAM 1003通过总线1004彼此相连。输入/输出(I/O)接口1005也连接至总线1004。FIG. 10 shows a schematic block diagram of an example device 1000 that can be used to implement some embodiments of the present disclosure. Device 1000 can be used to implement an electronic device. As shown in FIG. 10 , device 1000 includes a central processing unit (CPU) 1001, which can perform various appropriate actions and processes according to computer program instructions stored in a read-only memory (ROM) 1002 or computer program instructions loaded from a storage unit 1008 into a random access memory (RAM) 1003. In RAM 1003, various programs and data required for the operation of device 1000 can also be stored. CPU 1001, ROM 1002, and RAM 1003 are connected to each other via bus 1004. Input/output (I/O) interface 1005 is also connected to bus 1004.
设备1000中的多个部件连接至I/O接口1005，包括：输入单元1006，例如键盘、鼠标等；输出单元1007，例如各种类型的显示器、扬声器等；存储单元1008，例如磁盘、光盘等；以及通信单元1009，例如网卡、调制解调器、无线通信收发机等。通信单元1009允许设备1000通过诸如因特网的计算机网络和/或各种电信网络与其它设备交换信息/数据。A number of components in the device 1000 are connected to the I/O interface 1005, including: an input unit 1006, such as a keyboard, a mouse, etc.; an output unit 1007, such as various types of displays, speakers, etc.; a storage unit 1008, such as a disk, an optical disk, etc.; and a communication unit 1009, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 1009 allows the device 1000 to exchange information/data with other devices through a computer network such as the Internet and/or various telecommunication networks.
处理单元1001执行上文所描述的各个方法和处理，例如方法300。例如，在一些实施例中，方法300可被实现为计算机软件程序，具体可以是EDA程序，其被有形地包含于机器可读介质，例如存储单元1008。在一些实施例中，计算机程序的部分或者全部可以经由ROM1002和/或通信单元1009而被载入和/或安装到设备1000上。当计算机程序加载到RAM 1003并由CPU 1001执行时，可以执行上文描述的方法400的一个或多个步骤。备选地，在其它实施例中，CPU 1001可以通过其它任何适当的方式(例如，借助于固件)而被配置为执行方法400。The processing unit 1001 performs the various methods and processes described above, such as method 300. For example, in some embodiments, method 300 may be implemented as a computer software program, specifically an EDA program, which is tangibly contained in a machine-readable medium, such as storage unit 1008. In some embodiments, part or all of the computer program may be loaded and/or installed on the device 1000 via ROM 1002 and/or communication unit 1009. When the computer program is loaded into RAM 1003 and executed by CPU 1001, one or more steps of method 400 described above may be performed. Alternatively, in other embodiments, CPU 1001 may be configured to perform method 400 in any other appropriate manner (e.g., by means of firmware).
本文中以上描述的功能可以至少部分地由一个或多个硬件逻辑部件来执行。例如，非限制性地，可以使用的示范类型的硬件逻辑部件包括：场可编程门阵列(FPGA)、专用集成电路(ASIC)、专用标准产品(ASSP)、芯片上系统的系统(SOC)、负载可编程逻辑设备(CPLD)等等。The functions described above herein may be performed at least in part by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chip systems (SOCs), load programmable logic devices (CPLDs), and the like.
用于实施本公开的方法的程序代码可以采用一个或多个编程语言的任何组合来编写。这些程序代码可以提供给通用计算机、专用计算机或其它可编程数据处理装置的处理器或控制器，使得程序代码当由处理器或控制器执行时使流程图和/或框图中所规定的功能/操作被实施。程序代码可以完全在机器上执行、部分地在机器上执行，作为独立软件包部分地在机器上执行且部分地在远程机器上执行或完全在远程机器或服务器上执行。The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions/operations specified in the flow chart and/or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine as a stand-alone software package and partially on a remote machine, or entirely on a remote machine or server.
在本公开的上下文中，机器可读介质可以是有形的介质，其可以包含或存储以供指令执行系统、装置或设备使用或与指令执行系统、装置或设备结合地使用的程序。机器可读介质可以是机器可读信号介质或机器可读储存介质。机器可读介质可以包括但不限于电子的、磁性的、光学的、电磁的、红外的、或半导体系统、装置或设备，或者上述内容的任何合适组合。机器可读存储介质的更具体示例会包括基于一个或多个线的电气连接、便携式计算机盘、硬盘、随机存取存储器(RAM)、只读存储器(ROM)、可擦除可编程只读存储器(EPROM或快闪存储器)、光纤、便捷式紧凑盘只读存储器(CD-ROM)、光学储存设备、磁储存设备、或上述内容的任何合适组合。In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
此外，虽然采用特定次序描绘了各操作，但是这应当理解为要求这样操作以所示出的特定次序或以顺序次序执行，或者要求所有图示的操作应被执行以取得期望的结果。在一定环境下，多任务和并行处理可能是有利的。同样地，虽然在上面论述中包含了若干具体实现细节，但是这些不应当被解释为对本公开的范围的限制。在单独的实施例的上下文中描述的某些特征还可以组合地实现在单个实现中。相反地，在单个实现的上下文中描述的各种特征也可以单独地或以任何合适的子组合的方式实现在多个实现中。In addition, although each operation is described in a specific order, this should be understood as requiring such operation to be performed in the specific order shown or in a sequential order, or requiring that all illustrated operations should be performed to obtain desired results. Under certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although some specific implementation details are included in the above discussion, these should not be interpreted as limiting the scope of the present disclosure. Some features described in the context of a separate embodiment can also be implemented in a single implementation in combination. On the contrary, the various features described in the context of a single implementation can also be implemented in multiple implementations individually or in any suitable sub-combination mode.
尽管已经采用特定于结构特征和/或方法逻辑动作的语言描述了本主题，但是应当理解所附权利要求书中所限定的主题未必局限于上面描述的特定特征或动作。相反，上面所描述的特定特征和动作仅仅是实现权利要求书的示例形式。Although the subject matter has been described in language specific to structural features and/or methodological logical actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. On the contrary, the specific features and actions described above are merely example forms of implementing the claims.
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| CN202310141817.XACN118485038A (en) | 2023-02-13 | 2023-02-13 | Method, device, apparatus, medium and program product for optimizing circuit layout |
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| CN202310141817.XACN118485038A (en) | 2023-02-13 | 2023-02-13 | Method, device, apparatus, medium and program product for optimizing circuit layout |
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| CN118485038Atrue CN118485038A (en) | 2024-08-13 |
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310141817.XAPendingCN118485038A (en) | 2023-02-13 | 2023-02-13 | Method, device, apparatus, medium and program product for optimizing circuit layout |
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| CN (1) | CN118485038A (en) |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN119129513A (en)* | 2024-11-12 | 2024-12-13 | 芯行纪科技有限公司 | Method, device and storage medium for optimizing digital logic circuit layout |
| CN119167872A (en)* | 2024-11-22 | 2024-12-20 | 苏州元脑智能科技有限公司 | Printed circuit board wiring method, device, medium and computer program product |
| CN120430272A (en)* | 2025-07-07 | 2025-08-05 | 珠海格力电器股份有限公司 | Chip layout determining method and device, electronic equipment and storage medium |
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN119129513A (en)* | 2024-11-12 | 2024-12-13 | 芯行纪科技有限公司 | Method, device and storage medium for optimizing digital logic circuit layout |
| CN119167872A (en)* | 2024-11-22 | 2024-12-20 | 苏州元脑智能科技有限公司 | Printed circuit board wiring method, device, medium and computer program product |
| CN120430272A (en)* | 2025-07-07 | 2025-08-05 | 珠海格力电器股份有限公司 | Chip layout determining method and device, electronic equipment and storage medium |
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| PB01 | Publication | ||
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