Disclosure of Invention
The embodiment of the application provides a display panel and a display device, which can fully realize the partitioned multi-frequency display of a display screen, thereby effectively improving the display effect of the display screen.
In a first aspect, an embodiment of the present application provides a display panel including a display area including a plurality of pixel circuits including a target transistor, and a gate driving signal line; the pixel circuit is electrically connected with the logic control module;
The control end of the logic control module is electrically connected with the partition control signal line, the first end of the logic control module is electrically connected with the grid drive signal line, and the second end of the logic control module is electrically connected with the control end of the target transistor;
The logic control module is used for controlling the target transistor to display at low frequency or high frequency.
According to an embodiment of the first aspect of the present application, the logic conversion module comprises a logic control unit; the control end of the logic control unit is electrically connected with the partition control signal line, the first end of the logic control unit is electrically connected with the grid drive signal line, and the second end of the logic control unit is electrically connected with the control end of the target transistor.
According to an embodiment of the first aspect of the present application, the logic conversion module further includes a unidirectional conductive unit, and the target transistor is further electrically connected to the memory cell; the first end of the unidirectional conduction unit is electrically connected with the grid driving signal line, and the second end of the unidirectional conduction unit is electrically connected with the control end of the target transistor; the first end of the memory unit is electrically connected with the control end of the target transistor, and the second end of the memory unit is electrically connected with the target reference level voltage signal line; the target reference level voltage signal line is used for providing constant voltage; when the gate driving signal supplied from the gate driving signal line is at a low level and the voltage level stored in the memory cell is at a high level, the unidirectional conduction unit is unidirectional conducted from the first end of the memory cell in the direction of the gate driving signal line.
According to an embodiment of the first aspect of the present application, the target transistor comprises a P-type transistor or an N-type transistor.
According to an embodiment of the first aspect of the present application, the logic control unit comprises a first transistor; the control end of the first transistor is electrically connected with the partition control signal line, the first end of the first transistor is electrically connected with the grid drive signal line, and the second end of the first transistor is electrically connected with the control end of the target transistor.
According to an embodiment of the first aspect of the present application, the unidirectional-conduction unit includes a second transistor or a target diode; if the unidirectional conduction unit comprises a second transistor, the control end and the first end of the second transistor are electrically connected with the grid driving signal line if the second transistor is a P-type transistor, and the second end of the second transistor is electrically connected with the control end of the target transistor; or if the second transistor is an N-type transistor, the first end of the second transistor is electrically connected with the grid driving signal line, and the control end and the second end of the second transistor are electrically connected with the control end of the target transistor; in the case where the unidirectional conduction unit includes a target diode, a cathode of the target diode is electrically connected to the gate driving signal line, and an anode of the target diode is electrically connected to the control terminal of the target transistor.
According to an embodiment of the first aspect of the application, the memory cell comprises a storage capacitor; the first pole of the storage capacitor is electrically connected with the control end of the target transistor, and the second pole of the storage capacitor is electrically connected with the target reference level voltage signal line.
According to an embodiment of the first aspect of the application, the first transistor comprises a P-type transistor or an N-type transistor.
According to an embodiment of the first aspect of the application, the first transistor is of the same type as the second transistor.
According to an embodiment of the first aspect of the present application, the display area includes a first display area and a second display area, and the partition control signal line is used for transmitting the first partition control signal and/or the second partition control signal; when the first display area displays at the first refresh frequency and the second display area displays at the second refresh frequency, the logic control module electrically connected with the pixel circuits in the first display area is turned off under the control of the first partition control signal, the logic control module electrically connected with the pixel circuits in the second display area is turned on under the control of the second partition control signal, and the gate drive signal of the gate drive signal line is transmitted to the control end of the target transistor in the second display area through the logic control module electrically connected with the pixel circuits in the second display area.
According to an embodiment of the first aspect of the application, the second refresh frequency is greater than the first refresh frequency.
According to an embodiment of the first aspect of the present application, the display area further comprises at least one third display area; the third display area is displayed with a third refresh rate.
According to an embodiment of the first aspect of the application, the third refresh frequency is different from the first refresh frequency and different from the second refresh frequency.
According to an embodiment of the first aspect of the present application, the second display area comprises a first sub-display area and a second sub-display area; the first sub-display area and the second sub-display area are not adjacent.
According to an embodiment of the first aspect of the present application, in the case where the first display area is displayed at the first refresh frequency and the second display area is displayed at the second refresh frequency, one picture refresh period of the first display area includes a write frame and a hold frame, and one picture refresh period of the second display area includes a write frame.
According to an embodiment of the first aspect of the present application, when the first display area is in the hold frame, the logic control module in the first display area is turned off under the control of the first partition control signal; when the second display area is in the writing frame, the logic control module in the second display area is conducted under the control of the second partition control signal.
According to an embodiment of the first aspect of the present application, when the first display area is in the write frame, the logic control module in the first display area is turned on under the control of the second partition control signal.
According to an embodiment of the first aspect of the present application, a display panel includes a plurality of gate driving signal lines; the display panel comprises a plurality of sub-pixels which are arranged in an array; the sub-pixel comprises a pixel circuit and a logic control module; the subpixels of the same row are electrically connected to the same gate driving signal line, and the subpixels of the same column are electrically connected to the same partition control signal line.
According to an embodiment of the first aspect of the present application, the partition control signal line is configured to provide the time-sharing control signal to the logic control module in the sub-pixel in the same column in a time-sharing manner.
According to an embodiment of the first aspect of the present application, the effective pulse of the gate driving signal line connected to the ith row of sub-pixels overlaps with the effective pulse of the gate driving signal line connected to the jth row of sub-pixels, i, j are positive integers, and i is smaller than j; the partition control signal line provides an active level before the target time, and the partition control signal line provides an inactive level after the target time; the target time is set between a first time and a second time, wherein the first time is the starting time of the effective pulse of the gate driving signal line connected with the ith row of sub-pixels, and the second time is the ending time of the effective pulse of the gate driving signal line connected with the jth row of sub-pixels.
According to an embodiment of the first aspect of the present application, the target time does not overlap with a third time, and/or the target time does not overlap with a fourth time, the third time being an end time of an effective pulse of the gate driving signal line connected to the ith row of sub-pixels, the fourth time being a start time of an effective pulse of the gate driving signal line connected to the jth row of sub-pixels.
According to an embodiment of the first aspect of the application, the target time is arranged between the third time and the second time and/or the target time is arranged between the fourth time and the third time.
According to an embodiment of the first aspect of the present application, the gate driving signal line includes a first gate driving signal line and a second gate driving signal line; the storage unit comprises a first storage unit and a second storage unit; the first gate driving signal line and the second gate driving signal line provide different gate driving signals; the target transistor includes a first target transistor and a second target transistor; the logic control module comprises a first logic control module and a second logic control module; the control end of the first logic control module is electrically connected with the partition control signal line, the first end of the first logic control module is electrically connected with the first grid driving signal line, and the second end of the first logic control module is electrically connected with the control end of the first target transistor; the control end of the second logic control module is electrically connected with the partition control signal line, the first end of the second logic control module is electrically connected with the second grid driving signal line, and the second end of the second logic control module is electrically connected with the control end of the second target transistor.
According to an embodiment of the first aspect of the present application, the first target transistor is electrically connected to the first memory cell, and the second target transistor is electrically connected to the second memory cell; a first end of the first memory cell is electrically connected with the control end of the first target transistor, and a second end of the first memory cell is electrically connected with the first target reference level voltage signal line; the first target reference level voltage signal line is used for providing constant voltage; the first end of the second memory cell is electrically connected with the control end of the second target transistor, and the second end of the second memory cell is electrically connected with the second target reference level voltage signal line; the second target reference level voltage signal line is used for providing a constant voltage.
According to an embodiment of the first aspect of the present application, the first target transistor comprises a P-type transistor or an N-type transistor, and the second target transistor comprises a P-type transistor or an N-type transistor;
According to an embodiment of the first aspect of the application, the first target transistor is of the same type as the second target transistor.
According to an embodiment of the first aspect of the present application, the first target transistor is a threshold compensation transistor; the second target transistor is an initialization transistor; the pixel circuit further includes a driving transistor; the control end of the threshold compensation transistor is electrically connected with the second end of the first logic control module, the first end of the threshold compensation transistor is electrically connected with the control end of the driving transistor, and the second end of the threshold compensation transistor is electrically connected with the first end of the driving transistor; the control end of the initialization transistor is electrically connected with the second end of the second logic control module, the first end of the initialization transistor is electrically connected with the control end of the driving transistor, and the second end of the initialization transistor is electrically connected with the first reference level voltage signal line.
According to an embodiment of the first aspect of the present application, in the initialization stage, the second logic control module is turned on under the control of the partition control signal line, and the initialization transistor is turned on under the control of the second gate driving signal line, so as to transmit the first reference level voltage signal provided by the first reference level voltage signal line to the control end of the driving transistor; in the threshold compensation stage, the first logic control module is conducted under the control of the partition control signal line, and the threshold compensation transistor is conducted under the control of the first gate drive signal line so as to be communicated with the control end and the first end of the drive transistor.
According to an embodiment of the first aspect of the present application, the threshold compensation transistor is electrically connected to the first storage capacitor, and the initialization transistor is electrically connected to the second storage capacitor; a first pole of the first storage capacitor is electrically connected with the control end of the threshold compensation transistor, and a second pole of the first storage capacitor is electrically connected with the first reference level voltage signal line; the first pole of the second storage capacitor is electrically connected with the control end of the initializing transistor, and the second pole of the second storage capacitor is electrically connected with the first reference level voltage signal line.
Based on the same inventive concept, in a second aspect, an embodiment of the present application provides a display device including the display panel according to any one of the embodiments of the foregoing first aspect of the present application.
According to an embodiment of the second aspect of the present application, a display panel includes a plurality of gate driving signal lines; the display panel comprises a plurality of sub-pixels which are arranged in an array;
The same row of sub-pixels are electrically connected with the same grid driving signal line, and the same column of sub-pixels are electrically connected with the same partition control signal line; the display device also comprises a shift register circuit and a level conversion circuit; the level conversion circuit comprises N level signal output ends, wherein N is a positive integer; the N level signal output ends are electrically connected with the N partition control signal lines in a one-to-one correspondence manner; the shift register circuit is used for receiving display information of a target picture corresponding to a target sub-pixel row, generating N first level signals according to the display information, and transmitting the N first level signals to the level conversion circuit; the level conversion circuit is used for converting the N first level signals into N second level signals corresponding to one by one and transmitting the N second level signals to N level signal output ends corresponding to one by one.
According to an embodiment of the second aspect of the present application, the display panel includes a target subpixel row therein; a first part of sub-pixels in the target sub-pixel row are positioned in the first display area, and a second part of sub-pixels in the target sub-pixel row are positioned in the second display area;
when the first display area is displayed at the first refresh frequency and the second display area is displayed at the second refresh frequency, the partition control signal line electrically connected to the first part of the sub-pixels provides an inactive level and the partition control signal line electrically connected to the second part of the sub-pixels provides an active level.
According to an embodiment of the second aspect of the present application, the shift register circuit is disposed on the display panel, the flexible circuit board, or the printed circuit board.
According to an embodiment of the second aspect of the present application, the level shifter circuit is provided on the display panel, the flexible circuit board, or the printed circuit board.
According to the display panel and the display device provided by the embodiment of the application, the pixel circuit in the display area is electrically connected with the logic control module, the first end of the logic control module is electrically connected with the grid driving signal line, and the second end of the logic control module is electrically connected with the control end of the target transistor. Therefore, for the pixel circuits at different positions in the display area, whether the gate driving signals of the gate driving signal lines can be transmitted to the control end of the target transistor can be indirectly controlled only by switching on or switching off the control logic control module, so that the partition control of the high-frequency or low-frequency display work of the different pixel circuits in the display area is realized. According to the display panel and the display device, the logic control module is added to flexibly control whether the grid driving signals enter the corresponding pixel circuits, so that effective control of high-frequency or low-frequency display work of different pixel circuits in the display area is fully realized, the display screen is favorably used for carrying out regional multi-frequency display, and the display effect of the display screen is effectively improved.
Detailed Description
Features and exemplary embodiments of various aspects of the present application will be described in detail below, and in order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be described in further detail below with reference to the accompanying drawings and the detailed embodiments. It should be understood that the particular embodiments described herein are meant to be illustrative of the application only and not limiting. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the application by showing examples of the application.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
It should be understood that the term "and/or" as used herein is merely one relationship describing the association of the associated objects, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.
It should be noted that, the transistor in the embodiment of the present application may be an N-type transistor or a P-type transistor. For an N-type transistor, the on level is high and the off level is low. That is, the gate of the N-type transistor is on between the first and second poles when the gate is high, and is off between the first and second poles when the gate is low. For a P-type transistor, the on level is low and the off level is high. That is, when the control of the P-type transistor is at a very low level, the first pole and the second pole are turned on, and when the control of the P-type transistor is at a high level, the first pole and the second pole are turned off. In a specific implementation, the gate of each transistor is used as a control electrode, and the first electrode of each transistor may be used as a source electrode, the second electrode may be used as a drain electrode, or the first electrode may be used as a drain electrode, and the second electrode may be used as a source electrode, which is not distinguished herein.
In embodiments of the present application, the term "electrically connected" may refer to two components being directly electrically connected, or may refer to two components being electrically connected via one or more other components.
In the embodiment of the present application, the first node, the second node, and the third node are defined only for convenience in describing the circuit structure, and the first node, the second node, and the third node are not one actual circuit unit.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Accordingly, it is intended that the present application covers the modifications and variations of this application provided they come within the scope of the appended claims (the claims) and their equivalents. The embodiments provided by the embodiments of the present application may be combined with each other without contradiction.
Before describing the technical solution provided by the embodiments of the present application, in order to facilitate understanding of the embodiments of the present application, the present application firstly specifically describes the problems existing in the related art:
As described above, with the development of display technology, AMOLED (Active Matrix Organic LIGHT EMITTING Diode) flat panel display panels are manufactured using organic materials to fabricate light emitting devices, and TFTs (thin film transistors) are used to construct pixel circuits. The pixels are arranged in an array mode, and the display screen is in a progressive scanning refreshing mode. After LTPO (Low Temperature Polysilicon Oxide ) technology enters mass production, the AMOLED display technology is further upgraded. Based on LTPO technology, a technology of controlling the refresh rate of a screen in a divided area, namely a screen divided into a plurality of display areas, wherein the refresh rate of each area is different, which is called a divided multi-frequency technology. This technique will determine the refresh rate actually required for each region based on the actual display content. Areas not requiring high frequency refresh will be reduced to low frequency refresh, thus reducing the logic power consumption of the display screen.
However, the inventor of the present application further research found that, at the present stage, since the pixels in the same row in the display screen are controlled by the same scan control signal, there is a problem that the display screen cannot be displayed in a partitioned manner according to different display columns in the conventional design. Based on this, how to realize the partition display of the display panel more flexibly is a problem to be solved in the current display technology field.
In order to solve the problem of flexible partition display of a display panel, the embodiment of the application provides a display panel and a display module. It should be noted that the examples provided by the present application are not intended to limit the scope of the present disclosure.
The following first describes a display panel provided by an embodiment of the present application.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the application. As shown in fig. 1, an embodiment of the present application provides a display panel 100, where the display panel 100 may include a display area AA and a gate driving signal line SCAN. The display area AA includes a plurality of pixel circuits 10, and the pixel circuits 10 include a target transistor T0. The pixel circuit 10 is electrically connected to the logic control module 20.
Specifically, a first terminal of the logic control module 20 is electrically connected to the gate driving signal line SCAN, and a second terminal of the logic control module 20 is electrically connected to the control terminal of the target transistor T0. The logic control module 20 may be used to control the display area AA to perform a low frequency or high frequency display operation. The logic control module 20 may be specifically configured to control the display area AA to perform the low-frequency or high-frequency display operation in the sub-area in combination with the actual display requirement. More specifically, as shown in fig. 1, the control terminal of the logic control module 20 is electrically connected to the partition control signal line CCL.
Under the condition that the partition control signal line CCL provides the on level for the logic control module 20, the logic control module 20 is turned on to transmit the gate driving signal of the gate driving signal line SCAN to the control end of the target transistor T0, so that the target transistor T0 performs the corresponding high-frequency display operation under the control of the gate driving signal.
Under the condition that the partition control signal line CCL provides the cut-off level for the logic control module 20, the logic control module 20 is turned off, and the gate driving signal of the gate driving signal line SCAN is blocked by the logic control module 20 so as not to be transmitted to the control end of the target transistor T0, which is equivalent to that the target transistor T0 performs the corresponding low-frequency display operation under the control of the logic control module 20.
In the display panel 100 provided by the embodiment of the application, the pixel circuit 10 in the display area AA is electrically connected with the logic control module 20, the control end of the logic control module 20 is electrically connected with the partition control signal line CCL, the first end of the logic control module 20 is electrically connected with the gate driving signal line SCAN, and the second end of the logic control module 20 is electrically connected with the control end of the target transistor T0. In this way, for the pixel circuits 10 located at different positions in the display area AA, only the partition control signal line CCL is needed to control the logic control module 20 to be turned on or off, so as to indirectly control whether the gate driving signal of the gate driving signal line SCAN can be transmitted to the control terminal of the target transistor T0, thereby implementing the partition control for the high-frequency or low-frequency display operation of the different pixel circuits 10 in the display area AA. According to the display panel 100 of the embodiment of the application, the logic control module 20 is added to flexibly control whether the grid driving signals of the grid driving signal lines SCAN enter the corresponding pixel circuits 10, so that the effective control of the high-frequency or low-frequency display operation of different pixel circuits 10 in the display area AA is fully realized, the display screen is favorably subjected to the zoned multi-frequency display, and the display effect of the display screen is effectively improved.
It should be noted that the target transistor T0 may be a transistor in the pixel circuit 10 associated with switching the high-low frequency display driving, for example, a threshold compensation transistor in a 7T1C pixel circuit or an initializing transistor for initializing the gate of the driving transistor, which is not limited herein.
It should be understood that, in the case where there are a plurality of transistors related to switching the display drive of the high and low frequencies in the pixel circuit 10, a plurality of the same logic control modules described above may be provided to control the high and low frequency display operations of the plurality of transistors, respectively.
Alternatively, in other possible embodiments, only a portion of the transistors related to switching the display driving with high and low frequencies may be used as the target transistors, and the remaining transistors related to switching the display driving with high and low frequencies may be controlled by other control methods (for example, directly performing gate driving scanning on the remaining transistors by digital driving), which is not strictly limited herein.
Referring to fig. 2, fig. 2 is a schematic structural diagram of another display panel according to an embodiment of the application. Optionally, in order to more reasonably realize the control of the logic control module 20 on whether the gate driving signals under the different refresh rates enter the pixel circuit 10 to perform the scan driving according to some embodiments of the present application, the logic conversion module may specifically include the logic control unit 101.
The control terminal of the logic control unit 101 is electrically connected to the partition control signal line CCL, the first terminal of the logic control unit 101 is electrically connected to the gate driving signal line, and the second terminal of the logic control unit 101 is electrically connected to the control terminal of the target transistor T0.
Referring to fig. 3, fig. 3 is a schematic structural diagram of another display panel according to an embodiment of the application. As shown in fig. 3, optionally, in order to more reasonably realize the control of the multi-frequency display of the display panel, the logic conversion module may further include a unidirectional conduction unit 102, and the target transistor T0 may be further electrically connected to the storage unit 103.
It should be added that the storage unit 103 may be disposed in the pixel circuit 10 or the logic control module 20, that is, the pixel circuit 10 or the logic control module 20 may further include the storage unit 103. Alternatively, as shown in fig. 3, the storage unit 103 may be provided independently of the pixel circuit 10 and the logic control module 20, and the present application is not limited thereto.
In fig. 3, a first terminal of the unidirectional conduction unit 102 is electrically connected to the gate driving signal line SCAN, and a second terminal of the unidirectional conduction unit 102 is electrically connected to the control terminal of the target transistor T0.
The first terminal of the memory cell 103 is electrically connected to the control terminal of the target transistor T0, and the second terminal of the memory cell 103 is electrically connected to the target reference level voltage signal line Vref 0. The target reference level voltage signal line Vref0 is used to supply a constant voltage, for example, -3V, etc., which is not strictly limited in the present embodiment.
When the gate driving signal supplied from the gate driving signal line SCAN is at a low level and the voltage level stored in the memory cell 103 is at a high level, the unidirectional conduction unit 102 is unidirectional-conducted in the direction of the gate driving signal line SCAN from the first terminal of the memory cell 103.
The target transistor T0 includes a P-type transistor or an N-type transistor, which is not limited in this embodiment.
For example, if the target transistor T0 is an N-type transistor, if the voltage level stored in the memory cell 103 is a high level, the unidirectional conduction unit 102 is unidirectional conducted only by the low level of the gate driving signal provided by the gate driving signal line SCAN, so as to effectively ensure timely discharging of the stored charge of the memory cell 103, and further avoid that the continuous conduction of the target transistor T0 under the high level of the memory cell 103 affects the partitioned multi-frequency display control.
Referring to fig. 4, fig. 4 is a schematic structural diagram of another display panel according to an embodiment of the application. As shown in fig. 4, according to some embodiments of the present application, more specifically, in connection with an actual device arrangement, the logic control unit 101 may specifically include a first transistor T8.
The control terminal of the first transistor T8 is electrically connected to the partition control signal line CCL, the first terminal of the first transistor T8 is electrically connected to the gate driving signal line SCAN, and the second terminal of the first transistor T8 is electrically connected to the control terminal of the target transistor T0.
Optionally, referring to fig. 4, the unidirectional conduction unit 102 may include a second transistor T9 or a target diode according to some embodiments of the present application.
In fig. 4, the unidirectional conduction unit 102 includes a second transistor T9, and the second transistor T9 is a P-type transistor. In this case, the control terminal and the first terminal of the second transistor T9 are electrically connected to the gate driving signal line SCAN, and the second terminal of the second transistor T9 is electrically connected to the control terminal of the target transistor T0, thereby forming a diode structure that is turned on unidirectionally from the first terminal of the memory cell 103 in the direction of the gate driving signal line SCAN.
Alternatively, in some other embodiments, if the unidirectional conducting unit 102 includes the second transistor T9, and the second transistor T9 is an N-type transistor, the first end of the second transistor T9 is electrically connected to the gate driving signal line SCAN, and the control end and the second end of the second transistor T9 are both electrically connected to the control end of the target transistor T0, so as to form a unidirectional conducting diode structure.
In the case where the unidirectional conduction unit 102 includes the target diode, the cathode of the target diode is electrically connected to the gate driving signal line SCAN, and the anode of the target diode is electrically connected to the control terminal of the target transistor T0.
When the potential of the anode of the target diode is higher than the potential of the cathode of the target diode, the target diode is turned on unidirectionally from the anode to the cathode, so that the memory cell 103 discharges, and the potential adjustment function can be performed on the gate of the target transistor T0.
Optionally, referring to fig. 4, the memory cell 103 may specifically include a storage capacitor C1 according to some embodiments of the present application. The first pole of the storage capacitor C1 is electrically connected to the control terminal of the target transistor T0, and the second pole of the storage capacitor C1 is electrically connected to the target reference level voltage signal line Vref 0.
According to some embodiments of the present application, the first transistor T8 may alternatively include a P-type transistor or an N-type transistor, which may be specifically determined according to actual logic control requirements.
Further, in order to sufficiently secure the control effect of the logic control module 20, the type of the first transistor T8 and the type of the second transistor T9 are the same.
It should be noted that, in the case where the first transistor T8 and the second transistor T9 are both N-type devices, the N-type transistor is specifically lower in off-state leakage current, and the influence on the target transistor T0 in the pixel circuit 10 is smaller in the actual logic control operation process, so that the gate potential of the target transistor T0 is more accurate.
Referring to fig. 5, fig. 5 is a schematic structural diagram of another display panel according to the present application. The display area AA includes a first display area AA1 and a second display area AA2. The partition control signal line is used for transmitting the first partition control signal and/or the second partition control signal.
In the case that the first display area AA1 is displayed at the first refresh frequency and the second display area AA2 is displayed at the second refresh frequency, the logic control module 20 electrically connected to the pixel circuit 10 in the first display area AA1 is turned off under the control of the first partition control signal, the logic control module 20 electrically connected to the pixel circuit 10 in the second display area AA2 is turned on under the control of the second partition control signal, and the gate driving signal of the gate driving signal line SCAN is transmitted to the control end of the target transistor T0 in the second display area AA2 through the logic control module 20 in the second display area AA 2.
With continued reference to fig. 5, in accordance with some embodiments of the application, the second refresh rate is greater than the first refresh rate. Illustratively, the first refresh frequency is, for example, 30HZ and the second refresh frequency is, for example, 60HZ, although the application is not limited in this regard.
According to the display panel provided by the embodiment of the application, by arranging the logic control module 20, the control end of the logic control module 20 is electrically connected with the partition control signal line CCL, the first end of the logic control module 20 is electrically connected with the grid drive signal line SCAN, and the second end of the logic control module 20 is electrically connected with the control end of the target transistor T0. In this way, in the case where the first display area AA1 is displayed at the first refresh frequency and the second display area AA2 is displayed at the second refresh frequency, the logic control module 20 in the first display area AA1 in the display panel may be turned off under the control of the first partition control signal. The logic control module 20 in the second display area AA2 may be turned on under the control of the second partition control signal, and the gate driving signal of the gate driving signal line SCAN is transmitted to the control terminal of the target transistor T0 in the second display area AA2 through the logic control module 20 in the second display area AA 2. According to the display panel 100 provided by the embodiment of the application, the logic control module 20 is added to control whether the grid driving signals under the conditions of different refresh rates enter the pixel circuit 10 for scanning driving, so that the multi-frequency display of the display screen can be fully realized, and the display effect of the display screen is effectively improved.
Referring to fig. 6, fig. 6 is a schematic structural diagram of another display panel according to an embodiment of the application. As shown in fig. 6, according to some embodiments of the present application, optionally, in order to fully secure the multi-division display of the display panel 100, the display panel may further include at least one third display area AA3. The third display area AA3 is displayed with a third refresh rate.
According to some embodiments of the application, optionally, the third refresh rate is different from the first refresh rate and different from the second refresh rate. Illustratively, the first refresh frequency is, for example, 30HZ, the second refresh frequency is, for example, 60HZ, and the third refresh frequency is, for example, 120HZ, which is not strictly limited in this embodiment.
According to some embodiments of the application, the second display area AA2 may optionally include a first sub-display area and a second sub-display area. The first and second sub-display areas are not adjacent, for example, the first and second sub-display areas may be separated by the first display area AA 1.
According to some embodiments of the present application, optionally, in the case where the first display area AA1 is displayed at the first refresh frequency and the second display area AA2 is displayed at the second refresh frequency, one screen refresh period of the first display area AA1 may include a write frame and a hold frame, and one screen refresh period of the second display area AA2 may include a write frame.
Illustratively, the first refresh frequency is, for example, 30HZ and the second refresh frequency is, for example, 60HZ. One screen refresh period of the first display area AA1 may include one write frame and one hold frame, and one screen refresh period of the second display area AA2 may include one write frame, which is not strictly limited in this embodiment.
Referring to fig. 7, fig. 7 is a timing diagram of a display panel according to an embodiment of the application. As shown in fig. 7, for example, the first partition control signal supplied from the partition control signal line CCL is at a low level, and the second partition control signal supplied from the partition control signal line CCL is at a high level. The active level corresponding to the control end of the target transistor T0 is high level, and the inactive level is low level.
In this case, the partition control signal line CCL continuously supplies the first partition control signal when the first display area AA1 is in the hold frame. The logic control module 20 in the first display area AA1 is turned off under the control of the first partition control signal, the gate potential of the target transistor T0 is maintained at a low level, and the target transistor T0 is maintained in an off state.
Optionally, referring to fig. 7, when the first display area AA1 is in the write frame, the partition control signal line CCL provides the second partition control signal, the logic control module 20 in the first display area AA1 is turned on under the control of the second partition control signal, the gate of the target transistor T0 is turned on under the high level of the second partition control signal, and the gate driving signal provided by the gate driving signal line SCAN is transmitted to the gate of the target transistor T0 through the turned-on logic control module 20.
Referring to fig. 8, fig. 8 is a timing diagram of another display panel according to an embodiment of the application. As shown in fig. 8, when the second display area AA2 is in the writing frame, the logic control module 20 in the second display area AA2 is turned on under the control of the second partition control signal provided by the partition control signal line CCL, and the gate driving signal provided by the gate driving signal line SCAN is transmitted to the gate of the target transistor T0 through the turned-on logic control module 20.
Referring to fig. 9, fig. 9 is a schematic structural diagram of another display panel according to an embodiment of the application. As shown in fig. 9, the display panel 100 may optionally include a plurality of gate driving signal lines SCAN in order to more reasonably realize the partitioned multi-frequency control of the display panel 100 according to some embodiments of the present application. The display panel 100 may include a plurality of sub-pixels arranged in an array. The sub-pixel includes a pixel circuit 10 and a corresponding electrically connected logic control module 20.
In fig. 9, the subpixels of the same row may be electrically connected to the same gate driving signal line SCAN, and the subpixels of the same column may be electrically connected to the same partition control signal line CCL.
Alternatively, the partition control signal line CCL may be used to provide time-shared control signals to the logic control modules 20 in the subpixels in the same column.
For example, if the gate driving signal line SCAN is scanned row by row, the partition control signal line CCL may provide a time-sharing control signal for the sub-pixels in the corresponding area according to the current scanning area of the gate driving signal line SCAN. The time-sharing control signal may be determined according to a refresh frequency corresponding to a display area where the sub-pixel is located, and the time-sharing control signal may specifically be an active level or an inactive level.
In this embodiment, the above-mentioned grid driving signal line SCAN connected to the same row of sub-pixels and the partition control signal line CCL connected to the same column of sub-pixels implement the sub-pixel partition frequency control of any row and any column in the display panel 100, so that the display panel partition setting with adjustable signals at any position and any size can be implemented, and parameters such as the number, position and size of the partition can be changed in real time without power failure.
Referring to fig. 10, fig. 10 is a timing diagram of a display panel according to another embodiment of the application. As shown in fig. 10, optionally, in some cases, the effective pulse provided by the gate driving signal line SCAN is a wide pulse, and the effective pulse of the gate driving signal line SCAN connected to the ith row of sub-pixels overlaps with the effective pulse of the gate driving signal line SCAN connected to the jth row of sub-pixels, where i and j are positive integers, and i is smaller than j.
The partition control signal line CCL provides an active level before the target time t0, and the partition control signal line provides an inactive level after the target time t 0.
The target time t0 is set between a first time t 1and a second time t2, where the first time t1 is a start time of an active pulse of the gate driving signal line SCAN connected to the ith row of sub-pixels, and the second time t2 is an end time of an active pulse of the gate driving signal line SCAN connected to the jth row of sub-pixels.
According to some embodiments of the present application, optionally, the target time t0 does not overlap with the third time t3, and/or the target time t0 does not overlap with the fourth time t4, where the third time t3 is an end time of an active pulse of the gate driving signal line connected to the ith row of sub-pixels, and the fourth time t4 is a start time of an active pulse of the gate driving signal line SCAN connected to the jth row of sub-pixels.
According to some embodiments of the application, optionally, the target time t0 is set between the third time t3 and the second time t2, and/or the target time t0 is set between the fourth time t4 and the third time t 3. As shown in fig. 10, a case where the target time t0 is set between the third time t3 and the second time t2 is shown.
In this embodiment, by limiting the condition that the SCAN pulse of the gate driving signal line SCAN is a wide pulse waveform, the level jump position of the partition control signal line CCL is not overlapped with the level jump position of the gate driving signal line connected to the ith row of sub-pixels, and the level jump position of the gate driving signal line connected to the j row of sub-pixels is not overlapped, so as to avoid logic errors occurring in the process of partition control and influence on normal partition display of the display panel 100.
Referring to fig. 11, fig. 11 is a timing diagram of a display panel according to another embodiment of the application. Fig. 11 shows that in the case where the pulse supplied from the gate driving signal line SCAN is a wide pulse (there is overlap between the effective pulses of the adjacent two rows), the gate driving signal lines SCAN corresponding to the sub-pixels of the consecutive 5 rows are shifted row by row and there is overlap.
In this embodiment, the logic control module 20 is composed of a first transistor T8 and a second transistor T9, wherein the first transistor T8 is connected to the gate driving signal line SCAN and the gate of the target transistor T0, the second transistor T9 is connected in a diode manner, a gate of the target transistor T0 is connected to one pole of the storage capacitor C1, and the other pole of the storage capacitor C1 is electrically connected to the target reference level voltage signal line Vref0 providing a constant voltage.
In this case, the level transition position of the partition control signal line CCL is set before the end time of the effective pulse of the gate drive signal line SCAN-N (N) to which the sub-pixel of the nth row is correspondingly connected, and the target transistor T0 of the nth row to the n+3th row can be turned on when the gate drive signal line of the corresponding row provides the effective level due to the voltage maintaining action of the storage capacitor C1 and the unidirectional conduction discharging action of the second transistor T9, so that the target transistor T0 in the pixel circuit 10 can receive the normal gate control signal when the gate drive signal control using the wide pulse is realized, and the flexible setting of the partition position can be realized without changing the hardware.
Referring to fig. 12, fig. 12 is a schematic structural diagram of another display panel according to an embodiment of the application. As shown in fig. 12, according to some embodiments of the present application, optionally, in combination with the operation performance in the pixel circuit at different refresh frequencies in an actual scene, the gate driving signal line SCAN may include a first gate driving signal line SCAN-N1 and a second gate driving signal line SCAN-N2. The storage unit 103 includes a first storage unit and a second storage unit. The first and second gate driving signal lines SCAN-N1 and SCAN-N2 provide different gate driving signals.
The target transistor T0 may include a first target transistor and a second target transistor.
The logic control module 20 may include a first logic control module 21 and a second logic control module 22.
The control end of the first logic control module 21 is electrically connected to the partition control signal line CCL, the first end of the first logic control module 21 is electrically connected to the first gate driving signal line SCAN-N1, and the second end of the first logic control module 21 is electrically connected to the control end of the first target transistor.
The control end of the second logic control module 22 is electrically connected to the partition control signal line CCL, the first end of the second logic control module 22 is electrically connected to the second gate driving signal line SCAN-N2, and the second end of the second logic control module 22 is electrically connected to the control end of the second target transistor.
According to some embodiments of the application, optionally, the first target transistor is electrically connected to a first memory cell and the second target transistor is electrically connected to a second memory cell. The first terminal of the first memory cell is electrically connected to the control terminal of the first target transistor, and the second terminal of the first memory cell is electrically connected to a first target reference level voltage signal line, which may be used to provide a constant voltage.
The first end of the second memory cell is electrically connected with the control end of the second target transistor, and the second end of the second memory cell is electrically connected with the second target reference level voltage signal line; the second target reference level voltage signal line may be used to provide a constant voltage.
Optionally, and more specifically, referring to fig. 12, the first target transistor is a threshold compensation transistor T3, and the second target transistor is an initialization transistor T4. The first target transistor may include a P-type transistor or an N-type transistor, and the second target transistor may include a P-type transistor or an N-type transistor. Further, the type of the first target transistor is the same as the type of the second target transistor.
The pixel circuit 10 may further include a driving transistor T1.
The control terminal of the threshold compensation transistor T3 is electrically connected to the second terminal of the first logic control module 21, the first terminal of the threshold compensation transistor T3 is electrically connected to the control terminal of the driving transistor T1, and the second terminal of the threshold compensation transistor T3 is electrically connected to the first terminal of the driving transistor T1.
The control terminal of the initialization transistor T4 is electrically connected to the second terminal of the second logic control module 22, the first terminal of the initialization transistor T4 is electrically connected to the control terminal of the driving transistor T1, and the second terminal of the initialization transistor T4 is electrically connected to the first reference level voltage signal line Vref 1. Alternatively, the threshold compensation transistor T3 and the initialization transistor T4 may be N-type oxide TFTs.
More specifically, with continued reference to fig. 12, the threshold compensation transistor T3 is electrically connected to the first storage capacitor C1, and the initialization transistor T4 is electrically connected to the second storage capacitor C2. A first pole of the first storage capacitor C1 is electrically connected with a control end of the threshold compensation transistor T3, and a second pole of the first storage capacitor C1 is electrically connected with a first reference level voltage signal line Vref 1; a first pole of the second storage capacitor C2 is electrically connected to the control terminal of the initializing transistor T4, and a second pole of the second storage capacitor C2 is electrically connected to the first reference level voltage signal line Vref 1.
More specifically, in fig. 12, the first logic control module 21 may include a first transistor T8 and a second transistor T9, and the first logic control module 21 may include a third transistor T10 and a fourth transistor T11. In fig. 12, the first transistor T8, the second transistor T9, the third transistor T10, and the fourth transistor T11 are P-type transistors. The P-type transistor may be implemented by LTPS (low temperature polysilicon technology, low Temperature Poly-silicon) transistor, which is not limited in this embodiment.
The control end of the first transistor T8 is electrically connected to the partition control signal line CCL, the first end of the first transistor T8 is electrically connected to the first gate driving signal line SCAN-N1, and the second end of the first transistor T8 is electrically connected to the control end of the threshold compensation transistor T3. The control end and the first end of the second transistor T9 are electrically connected with the first grid driving signal line SCAN-N1, and the second end of the second transistor T9 is electrically connected with the control end of the threshold compensation transistor T3, so that a diode structure which is conducted unidirectionally from the first pole of the first storage capacitor C1 to the first grid driving signal line SCAN-N1 is formed.
The control terminal of the third transistor T10 is electrically connected to the partition control signal line CCL, the first terminal of the third transistor T10 is electrically connected to the second gate driving signal line SCAN-N2, and the second terminal of the third transistor T10 is electrically connected to the control terminal of the initialization transistor T4. The control terminal and the first terminal of the fourth transistor T11 are electrically connected to the second gate driving signal line SCAN-N2, and the second terminal of the fourth transistor T11 is electrically connected to the control terminal of the initialization transistor T4, thereby forming a diode structure that is turned on unidirectionally from the first pole of the second storage capacitor C2 to the second gate driving signal line SCAN-N2.
According to some embodiments of the present application, optionally, in connection with the actual pixel circuit display driving operation stage, the second logic control module 22 may be turned on under the control of the partition control signal line CCL in the initialization stage, and the initialization transistor T4 may be turned on under the control of the second gate driving signal line SCAN-N1 to transmit the first reference level voltage signal provided by the first reference level voltage signal line Vref1 to the control terminal of the driving transistor T1.
In the threshold compensation phase, the first logic control module 21 may be turned on under the control of the partition control signal line CCL, and the threshold compensation transistor T3 is turned on under the control of the first gate driving signal line SCAN-N1 to communicate the control terminal and the first terminal of the driving transistor T1.
It should be added that the transistor types of the first transistor T8 in the first logic control module 21 and the third transistor T10 in the second logic control module 22 may be identical, i.e. P-type transistors or N-type transistors, and only one partition control signal line CCL corresponding to the same pixel circuit 10 is needed in this case, so that synchronous on-off control of the first logic control module 21 and the second logic control module 22 can be realized.
Of course, the transistor types of the first transistor T8 and the third transistor T10 may also be different. In this case, if the synchronous on-off control of the first logic control module 21 and the second logic control module 22, which are correspondingly and electrically connected to the same pixel circuit 10, is to be realized, two partition control signal lines CCL with different output signals may be adaptively used to respectively perform on-off control on the first transistor T8 and the third transistor T10, which is not described in detail herein.
In order to facilitate understanding of the pixel circuit and the logic control module in this embodiment, fig. 13 is a schematic structural diagram of another display panel according to an embodiment of the present application. The specific circuit structure of the pixel circuit is perfected in fig. 13.
As shown in fig. 13, the control terminal of the driving transistor T1 is electrically connected to the first pole of the storage capacitor Cst, the first terminal of the driving transistor T1 is electrically connected to the second terminal of the first light emitting control transistor T5, and the second terminal of the driving transistor T1 is electrically connected to the first terminal of the second light emitting control transistor T6; the control end of the Data writing transistor T2 is electrically connected with the first scanning signal line SP1, the first end of the Data writing transistor T2 is electrically connected with the Data signal line Data, and the second end of the Data writing transistor T2 is electrically connected with the first end of the driving transistor T1; the control end of the threshold compensation transistor T3 is electrically connected with the second electrode of the first storage capacitor C1, the first end of the threshold compensation transistor T3 is electrically connected with the control end of the driving transistor T1, and the second end of the threshold compensation transistor T3 is electrically connected with the second end of the driving transistor T1; the control end of the initializing transistor T4 is electrically connected with the first pole of the second storage capacitor C2, the first end of the initializing transistor T4 is electrically connected with the control end of the driving transistor T1, and the second end of the initializing transistor T4 is electrically connected with the first reference level voltage signal line Vref 1; the control end of the first light-emitting control transistor T5 is electrically connected with a light-emitting control signal line, the first end of the first light-emitting control transistor T5 is electrically connected with a first power supply voltage signal line VDD, and the second end of the first light-emitting control transistor T5 is electrically connected with the first end of the driving transistor T1; the control end of the second light-emitting control transistor T6 is electrically connected with the light-emitting control signal line EM, the first end of the second light-emitting control transistor T6 is electrically connected with the second end of the driving transistor T1, and the second end of the second light-emitting control transistor T6 is electrically connected with the anode of the light-emitting element D; the control end of the anode reset transistor T7 is electrically connected with the second scanning signal line, the first end of the anode reset transistor T7 is electrically connected with the anode of the light-emitting element D, and the second end of the anode reset transistor T7 is electrically connected with the second reference level voltage signal line Vref2; the cathode of the light emitting element D is electrically connected to the second power supply voltage signal line VSS.
It will be appreciated that for reasons similar to those of the previous embodiments, the specific operation of the other devices in the pixel circuit 10 shown in fig. 11 will not be described here for brevity, considering the wide range of applications of the 7T1C basic pixel structure in the panel field.
However, it should be added that if the pixel circuit 10 is operated in the hold frame, the threshold compensation transistor T3 and the initialization transistor T4 are turned off under the control of the first logic control module 21 and the second logic control module 22, respectively, when the first gate driving signal line SCAN-N1 and the second gate driving signal line SCAN-N2 both provide high frequency signals.
When the type of the data writing transistor T2 is the same as the type of the threshold compensating transistor T3, for example, both are N-type transistors, the first SCAN signal line SP1 may multiplex the first gate driving signal line SCAN-N1, and the data writing transistor T2 has an on period in a non-light emitting stage of the sustain frame. In this on period, the signal of the Data signal line Data is transmitted to the first and second terminals of the driving transistor T1. Since the threshold compensation transistor T3 is in an off state, the signal of the signal Data signal line Data is not written to the gate of the driving transistor T1, and the gate of the driving transistor T1 is not refreshed. In the light emission stage of the holding frame, the light emission control signal line EM provides a turn-on level, and the first light emission control signal line T5 and the second light emission control signal line T6 are turned on under the control of the light emission control signal line EM, and the potential of the first terminal of the driving transistor T1 is refreshed by the first power supply voltage signal line VDD in this light emission stage. Therefore, even if the first SCAN signal line SP1 multiplexes the first gate driving signal line SCAN-N1 in the hold frame, the pixel circuit 10 can maintain the normal hold frame operation state.
When the type of the data writing transistor T2 is opposite to the type of the threshold compensating transistor T3, for example, the data writing transistor T2 is a P-type transistor, the threshold compensating transistor T3 is an N-type transistor, the first scanning signal line SP1 needs to be controlled by a separate signal line, and the data writing transistor and the threshold compensating transistor in the 7T1C pixel circuit of LTPO can be referred to.
It should be noted that, in addition to the above-listed several pixel circuit 10 structures, the pixel circuit 10 of the present application may further include other numbers of electronic devices (such as transistors, capacitors, etc.) and other connection relationships, and these electronic devices together form a plurality of types of pixel circuits 10, which are not particularly limited in this regard.
Fig. 14 is a timing diagram of still another display panel according to an embodiment of the present application, corresponding to the foregoing configuration shown in fig. 12 or 13, which shows the relevant waveforms of the pixel circuit 10 under the writing frame. Fig. 15 is a timing diagram of still another display panel according to an embodiment of the present application, which shows waveforms associated with the pixel circuit 10 in a hold frame. Fig. 16 is a timing diagram of another display panel according to an embodiment of the present application, which shows waveforms associated with the pixel circuit 10 in the SCAN wide pulse condition. Specifically, fig. 14, 15 and 16 show the level signal valid conditions of the first gate driving signal line SCAN-N1, the second gate driving signal line SCAN-N2, the partition control signal line CCL, and the on or off conditions corresponding to the threshold compensation transistor T3 and the initialization transistor T4 of the pixel circuit 10 in fig. 12 or 13, respectively, in the write frame, the hold frame, and the operation principle thereof is similar to that described in the foregoing embodiments.
In conjunction with the specific development of the timing diagram, in the embodiment of the present application, a second logic control module 22 is newly added between the second gate driving signal line SCAN-N2 and the initializing transistor T4, a first logic control module 21 is newly added between the first gate driving signal line SCAN-N1 and the threshold compensation transistor T3, a corresponding first storage capacitor C1 is set between the threshold compensation transistor T3 and the first reference level voltage signal line Vref1, and a second storage capacitor C2 is set between the initializing transistor T4 and the first reference level voltage signal line Vref 1. Thus, the present embodiment is realized by connecting LTPS switches in series to the first gate driving signal line scan_n1 and the second gate driving signal line scan_n2 signal lines: the first transistor T8 and the second transistor T9 are controlled by the partition control signal line CCL.
For the case shown in fig. 14, in the case where the partition control signal line CCL provides a low level, the first transistor T8 and the second transistor T9 are turned on, and the gate driving signals provided by the first gate driving signal line scan_n1 and the second gate driving signal line scan_n2 may reach the gates of the threshold compensation transistor T3 and the initialization transistor T4, respectively, thereby achieving the gate refresh (writing frame) of the driving transistor T1.
For the case shown in fig. 15, when the partition control signal line CCL is at a high level, the first transistor T8 and the second transistor T9 are turned off, the gate driving signals provided by the first gate driving signal line scan_n1 and the second gate driving signal line scan_n2 cannot reach the gates of the threshold compensation transistor T3 and the initialization transistor T4, and the threshold compensation transistor T3 and the initialization transistor T4 keep the original low level under the action of the first storage capacitor C1 and the second storage capacitor C2, so that the gates of the driving transistor T1 are not refreshed (kept in frames).
In addition, it should be further added that, for the case shown in fig. 16, in the case that the gate driving signals provided by the first gate driving signal line scan_n1 and the second gate driving signal line scan_n2 are wide pulses and different rows overlap, taking the first gate driving signal line scan_n1 as an example, when the partition control signal line CCL jumps to occur in the stage where scan_n1 is high level, the unidirectional conduction (diode mode) of the second transistor T9 can be utilized to pull the gate level of the threshold compensation transistor T3 to low level, so the scheme is also applicable to the case of the scan_n signal with wide pulses.
In summary, in the embodiment of the present application, by adding the first logic control module 21, the second logic control module 22, etc., the SCAN driving signal SCAN provided by the gate driving signal line does not directly enter the pixel circuit 10, but determines whether to enter the gate driving signal provided by the gate driving signal line SCAN according to the control signal provided by the partition control signal line CCL, which is favorable for fully realizing the effective control of the high-frequency or low-frequency display operation of different pixel circuits 10, further being favorable for the partition multi-frequency display of the display screen, and being favorable for effectively improving the display effect of the display screen.
Referring to fig. 17, fig. 17 is a schematic structural diagram of another display panel according to an embodiment of the application. In some other embodiments, as shown in fig. 17, the first logic control module 21 may include a first transistor T8 and a second transistor T9, and the first logic control module 21 may include a third transistor T10 and a fourth transistor T11. Fig. 17 shows a case where the first transistor T8, the second transistor T9, the third transistor T10, and the fourth transistor T11 are all N-type transistors.
Fig. 18 is a timing diagram of still another display panel according to an embodiment of the present application, corresponding to the structure shown in fig. 17, showing the waveforms associated with the pixel circuit 10 in the write frame. Fig. 19 is a timing diagram of still another display panel according to an embodiment of the present application, which shows waveforms associated with the pixel circuit 10 in the hold frame. Fig. 20 is a timing diagram of still another display panel according to an embodiment of the present application, which shows waveforms associated with the pixel circuit 10 in the SCAN wide pulse condition. Specifically, fig. 18, 19 and 20 show the level signal valid conditions of the first gate driving signal line SCAN-N1, the second gate driving signal line SCAN-N2, the partition control signal line CCL, and the on or off conditions corresponding to the threshold compensation transistor T3 and the initialization transistor T4 of the pixel circuit 10 in fig. 17 under the write frame, the hold frame, respectively, and the operation principle thereof is similar to that described in the foregoing embodiments.
In connection with the specific development of the timing, in the case shown in fig. 18, in the case where the partition control signal line CCL provides the high level, the first transistor T8 and the second transistor T9 are turned on, and the gate driving signals provided by the first gate driving signal line scan_n1 and the second gate driving signal line scan_n2 may reach the gates of the threshold compensation transistor T3 and the initialization transistor T4, respectively, thereby realizing the gate refresh (writing frame) of the driving transistor T1.
For the case shown in fig. 19, when the partition control signal line CCL is at a low level, the first transistor T8 and the second transistor T9 are turned off, the gate driving signals provided by the first gate driving signal line scan_n1 and the second gate driving signal line scan_n2 cannot reach the gates of the threshold compensation transistor T3 and the initialization transistor T4, and the threshold compensation transistor T3 and the initialization transistor T4 maintain the original low level under the action of the first storage capacitor C1 and the second storage capacitor C2, so that the gates of the driving transistors T1 are not refreshed (hold frames).
In addition, it should be further added that, for the case shown in fig. 20, in the case that the gate driving signals provided by the first gate driving signal line scan_n1 and the second gate driving signal line scan_n2 are wide pulses and different rows overlap, taking the first gate driving signal line scan_n1 as an example, when the partition control signal line CCL jumps to occur in the stage where scan_n1 is high level, the unidirectional conduction (diode mode) of the second transistor T9 can be utilized to pull the gate level of the threshold compensation transistor T3 to low level, so the scheme is also applicable to the case of the scan_n signal with wide pulses.
Based on the display panel 100 provided in the above embodiment, correspondingly, the application also provides a display device, including the display panel 100 provided in the application. Referring to fig. 21, fig. 21 is a schematic structural diagram of a display device according to an embodiment of the application. Fig. 21 provides a display device 1000 including a display panel 100 according to any of the above embodiments of the present application.
The embodiment of fig. 21 is described with respect to the display device 1000 by taking a mobile phone as an example, and it is to be understood that the display device provided in the embodiment of the present application may be any other display device having a display function, such as a wearable product, a computer, a television, and a vehicle-mounted display device, which is not particularly limited in the present application.
The display device provided by the embodiment of the present application has the beneficial effects of the display panel 100 provided by the embodiment of the present application, and the specific description of the display panel 100 in the above embodiments may be referred to in the embodiments, and the description of the embodiment is omitted herein.
Referring to fig. 22, fig. 22 is a schematic structural diagram of another display device according to an embodiment of the application. As shown in fig. 22, the display panel 100 may optionally include a plurality of gate driving signal lines according to some embodiments of the present application. The display panel 100 may include a plurality of sub-pixels arranged in an array. Specifically, the same row of subpixels are electrically connected to the same gate driving signal line SCAN, and the same column of subpixels are electrically connected to the same partition control signal line CCL.
The display device 1000 described above may further include a shift register circuit 200 and a level shift circuit 300. The level shift circuit may include N level signal outputs, N being a positive integer.
The N level signal output ends are electrically connected with the N partition control signal lines in a one-to-one correspondence manner.
The shift register circuit 200 may be configured to receive display information of a target frame corresponding to a target sub-pixel row, generate N first level signals according to the display information, and transmit the N first level signals to the level conversion circuit.
The level conversion circuit 300 may be configured to convert the N first level signals into N second level signals corresponding to one another, and transmit the N second level signals to N level signal output terminals corresponding to one another.
Optionally, a target subpixel row may be included in the display panel 100 according to some embodiments of the present application. A first portion of the subpixels in the target subpixel row are located in the first display area AA1, and a second portion of the subpixels in the target subpixel row are located in the second display area AA2.
When the first display area AA1 is displayed at the first refresh frequency and the second display area AA2 is displayed at the second refresh frequency, the partition control signal line CCL electrically connected to the first sub-pixels provides inactive levels and the partition control signal line CCL electrically connected to the second sub-pixels provides active levels.
In this embodiment, the gate driving signal line SCAN is laterally routed as shown in fig. 18. The present embodiment adds a logic control module 20 between the SCAN signal and the pixel circuit 10. The logic control module 20 determines whether the gate driving signal provided by the gate driving signal line SCAN can enter the pixel circuit 10. Wherein the number of the added logic control modules 20 corresponds to the number of the pixel circuits 10 one by one. Each sub-pixel column is added with a vertically oriented signal line, called a zoned multi-frequency signal line CCL, and the columns are not connected to ensure independent control. The zoned multi-frequency signal line CCL may be used to time-division control the on or off of the newly added logic control module 20 on the corresponding sub-pixel column.
The display information of the target frame corresponding to the target subpixel row may be sent to the shift register circuit 200 by a client or a TCON (Timer Control Register, timing control board) chip. The shift register circuit 200 can perform serial-parallel conversion of data and output the data to the level shift circuit 300 in parallel (LEVEL SHIFTER). The level conversion circuit converts the first level signal into a second level signal (VGH/VGL) and outputs the second level signal to the partition control signal line CCL of the corresponding column, thereby time-sharing controlling the on or off of the logic control module 20 newly added in the display area.
Considering the partition refresh rate technique for any location, which is related to the embodiment of the present application, the partition location may be changed in real time by an electrical signal, and the partition for any location may include a row-by-row partition and a column-by-column partition. In order to better understand the principle of implementing the partitioned multi-frequency display of the display panel in the embodiment of the present application, please refer to fig. 23. Fig. 23 is a schematic structural diagram of a partition refresh of a display device according to an embodiment of the present application.
The left part of fig. 23 shows the case of the display panel 100 being divided into two areas, and the right part shows the case of the display panel 100 being divided into three areas. Specifically, in fig. 23, a large square indicates the entire display panel 100 of the display screen, a small square indicates the partitioned display area, the refresh frequency is different from that of the main screen, and a black line in the row direction indicates the row position where the current scanning operation is located. The shift register circuit 200 is disposed below the display panel 100, and the value of the shift register circuit 200 determines whether the signal received by the corresponding partition control signal line CCL is valid, i.e. whether the logic control module 20 corresponding to the display column is turned on. Wherein, 1 indicates that the logic control module 20 is turned off, and 0 indicates that the logic control module 20 is turned on.
In order to more fully understand the principle of implementing the partitioned multi-frequency display of the display panel 100, please refer to fig. 24, fig. 24 is a schematic diagram of a structure of a partition refresh of a display device according to an embodiment of the present application.
In fig. 24, the register value of the shift register circuit 200 is shown in fig. 24 by taking a small square area as an example of high-frequency refresh. After each scan of a row of sub-pixels, the value of the shift register is updated once according to the upstream information. When the current scan line is at the low frequency position, the register value of the shift register circuit 200 is all 1, and the logic control module 20 corresponding to the pixel line is disconnected. When the current scanning line is that part of the sub-pixels are high frequency and part of the sub-pixels are low frequency, the register value of the column where the low frequency sub-pixels are located is 1, and the logic control module 20 is turned off; the register value of the column in which the high frequency sub-pixel is located is 0, and the corresponding logic control module 20 is turned on.
In this embodiment, the partition position and the partition size can be completely controlled by using the display information of the corresponding pixel row. If the partition position is to be changed, the display device 1000 does not need to be powered off, the partition information can be updated directly through updating the partition information at the client or TCON, and parameters such as the number, the position and the size of the partitions can be changed in real time under the condition of not powering off, so that any partition position setting and any partition size setting updating can be realized.
Further, referring to fig. 25, fig. 25 is a timing diagram of a partition refresh of a display device according to an embodiment of the application, where the timing diagram corresponds to fig. 24. As shown in fig. 25, fig. 25 shows waveforms of two frames, the first Frame (Frame 1) is in the write Frame in full screen, the second Frame is in the write Frame in block 1 and block 2, and the other areas are in the hold Frame. Taking the two pixel columns of A/B, the waveforms of the zoned multi-frequency signal line CCL are drawn as shown in FIG. 25. During the first frame scanning, all pixels can receive the gate driving signals provided by the gate driving signal lines SCAN, so that data voltages can be conveniently obtained for data writing refreshing.
During the second Frame (Frame 2) scanning, the pixels in Block1 and Block2 can receive the gate driving signal provided by the gate driving signal line SCAN, and other areas cannot receive the gate driving signal provided by the gate driving signal line SCAN, and data holding is performed without refreshing.
Optionally, in order to more reasonably achieve reasonable arrangement of circuit positions, the shift register circuit 200 is disposed on the display panel 100, the flexible circuit board, or the printed circuit board according to some embodiments of the present application. Similarly, the level shifter circuit 300 described above may be provided on the display panel 100, a flexible circuit board, or a printed circuit board.
In this embodiment, the shift register circuit 200 and the level shift circuit 300 may be located on a display screen body, or may be located on an FPC (Flexible Printed Circuit board, a flexible circuit board) or a PCB (Printed Circuit Board, a printed circuit board), so as to achieve reasonable placement of the location and the area of the newly added circuit module in the display device 1000, which is not limited herein.
It should be understood that the specific structures of the circuits and the cross-sectional structures of the display panels provided in the drawings according to the embodiments of the present application are only examples, and are not intended to limit the present application. In addition, the above embodiments provided by the present application may be combined with each other without contradiction.
It should be understood that, in the present specification, each embodiment is described in an incremental manner, and the same or similar parts between the embodiments are all referred to each other, and each embodiment is mainly described in a different point from other embodiments. These embodiments are not exhaustive of all details, nor are they intended to limit the application to the precise embodiments disclosed, in accordance with the application. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and the practical application, to thereby enable others skilled in the art to best utilize the application and various modifications as are suited to the particular use contemplated. The application is limited only by the claims and the full scope and equivalents thereof.
Those skilled in the art will appreciate that the above-described embodiments are exemplary and not limiting. The different technical features presented in the different embodiments may be combined to advantage. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in view of the drawings, the description, and the claims. In the claims, the term "comprising" does not exclude other structures; the amounts refer to "a" and do not exclude a plurality; the terms "first," "second," and the like, are used for designating a name and not for indicating any particular order. Any reference signs in the claims shall not be construed as limiting the scope. The presence of certain features in different dependent claims does not imply that these features cannot be combined to advantage.