技术领域Technical Field
本申请涉及电路技术领域，尤其涉及一种驱动电路、隔离装置和电子设备。The present application relates to the field of circuit technology, and in particular to a driving circuit, an isolation device and an electronic device.
背景技术Background technique
电子设备在做电路设计时，有时需利用金属氧化物半导体(Metal OxideSemiconductor，MOS)场效应晶体管(简称MOS管)做信号的隔离，如电源信号的隔离，以保证电路的可靠性、稳定性等。When designing circuits for electronic devices, metal oxide semiconductor (MOS) field effect transistors (MOS tubes for short) are sometimes needed to isolate signals, such as power supply signals, to ensure the reliability and stability of the circuit.
MOS管的导通和截止一般由驱动芯片驱动。然而，现有的驱动芯片由于复杂的结构以及复杂的集成工艺等导致成本较高，不利于电子设备降低成本。The on and off of the MOS tube is generally driven by a driver chip. However, the existing driver chip has a high cost due to its complex structure and complex integration process, which is not conducive to reducing the cost of electronic equipment.
发明内容Summary of the invention
为了解决上述技术问题，本申请提供一种驱动电路、隔离装置和电子设备。结构简单，有利于电子设备降低成本。In order to solve the above technical problems, the present application provides a driving circuit, an isolation device and an electronic device, which have a simple structure and are conducive to reducing the cost of the electronic device.
第一方面，本申请提供一种驱动电路，该驱动电路包括：电压调整模块；电压调整模块包括N组升压组、积分单元和驱动信号输出端，每组升压组包括存储单元和单向传输单元，其中，N为大于或等于1的正整数；偶数升压组的所述单向传输单元的第一端、所述偶数升压组的前一升压组的单向传输单元的第二端和所述偶数升压组的前一升压组的存储单元的第一端耦合于第一节点；除第一组升压组外，奇数升压组的单向传输单元的第一端、所述奇数升压组的前一升压组的单向传输单元的第二端和所述奇数升压组的前一升压组的存储单元的第一端耦合于第二节点；第一组升压组的单向传输单元的第一端用于接收电源信号，所述奇数升压组的存储单元的第二端用于接收第一脉冲宽度调制信号，所述偶数升压组的存储单元的第二端用于接收第二脉冲宽度调制信号，所述第一脉冲宽度调制信号和所述第二脉冲宽度调制信号频率相同，相位相反；第N组升压组的单向传输单元的第二端和所述第N组升压组的存储单元的第一端耦合于第三节点；所述第三节点和所述驱动信号输出端之间设置有所述积分单元。In a first aspect, the present application provides a driving circuit, which includes: a voltage adjustment module; the voltage adjustment module includes N groups of boosting groups, an integration unit and a driving signal output terminal, each group of boosting groups includes a storage unit and a unidirectional transmission unit, wherein N is a positive integer greater than or equal to 1; the first end of the unidirectional transmission unit of the even-numbered boosting group, the second end of the unidirectional transmission unit of the previous boosting group of the even-numbered boosting group and the first end of the storage unit of the previous boosting group of the even-numbered boosting group are coupled to a first node; except for the first group of boosting groups, the first end of the unidirectional transmission unit of the odd-numbered boosting group, the second end of the unidirectional transmission unit of the previous boosting group of the odd-numbered boosting group and the The first end of the storage unit of the previous boost group of the odd boost group is coupled to the second node; the first end of the unidirectional transmission unit of the first boost group is used to receive the power supply signal, the second end of the storage unit of the odd boost group is used to receive the first pulse width modulation signal, and the second end of the storage unit of the even boost group is used to receive the second pulse width modulation signal, the first pulse width modulation signal and the second pulse width modulation signal have the same frequency and opposite phase; the second end of the unidirectional transmission unit of the Nth boost group and the first end of the storage unit of the Nth boost group are coupled to the third node; the integration unit is arranged between the third node and the drive signal output end.
基于第一脉冲宽度调制信号和第二脉冲宽度调制信号，N组升压组通过存储单元对第一组升压组的单向传输单元的第一端接收电源信号进行依次升压，以形成高低的方波信号，积分单元对该方波信号进行积分，以得到直流信号，并通过驱动信号输出端输出至NMOS管的栅极，无需设置复杂的升压结构即可实现较高的驱动电压(驱动NMOS管导通或关闭的驱动信号)的输出。即本申请提供的驱动电路结构简单，有利于电子设备成本的降低。Based on the first pulse width modulation signal and the second pulse width modulation signal, the N boost groups sequentially boost the power signal received by the first end of the unidirectional transmission unit of the first boost group through the storage unit to form high and low square wave signals, and the integration unit integrates the square wave signal to obtain a DC signal, and outputs it to the gate of the NMOS tube through the drive signal output end, so that a higher drive voltage (drive signal that drives the NMOS tube to turn on or off) can be output without setting a complex boost structure. That is, the drive circuit structure provided by the present application is simple, which is conducive to reducing the cost of electronic equipment.
示例性的，第一脉冲宽度调制信号和第二脉冲宽度调制信号的频率和占空比可调，调节第一脉冲宽度调制信号和第二脉冲宽度调制信号的频率和/或占空比，可改变驱动信号输出端输出至NMOS管的栅极的驱动信号的大小。Exemplarily, the frequency and duty cycle of the first pulse width modulation signal and the second pulse width modulation signal are adjustable. By adjusting the frequency and/or duty cycle of the first pulse width modulation signal and the second pulse width modulation signal, the size of the driving signal output from the driving signal output terminal to the gate of the NMOS tube can be changed.
示例性的，当N为偶数时，第三节点也可称为第N组升压组的第二节点。当N为奇数时，第三节点也可称为第N组升压组的第一节点。Exemplarily, when N is an even number, the third node may also be referred to as the second node of the Nth boost group. When N is an odd number, the third node may also be referred to as the first node of the Nth boost group.
示例性的，该驱动电路可以用于驱动NMOS管，当然，这不构成对本申请的限定。Exemplarily, the driving circuit can be used to drive an NMOS tube. Of course, this does not constitute a limitation to the present application.
根据第一方面，驱动电路还包括关断模块，关断模块的第一端与驱动信号输出端电连接，关断模块的第二端接地设置，关断模块的控制端用于接收开关控制信号；当关断模块根据接收的开关控制信号导通时，驱动信号输出端接地设置。According to the first aspect, the driving circuit also includes a shutdown module, a first end of the shutdown module is electrically connected to the driving signal output end, a second end of the shutdown module is grounded, and a control end of the shutdown module is used to receive a switch control signal; when the shutdown module is turned on according to the received switch control signal, the driving signal output end is grounded.
即该驱动电路不仅可以导通NMOS管，还可以关闭NMOS管，使得驱动电路的应用更加的广泛。That is, the driving circuit can not only turn on the NMOS tube, but also turn off the NMOS tube, so that the application of the driving circuit is more extensive.
根据第一方面，或者以上第一方面的任意一种实现方式，电压调整模块包括第一组升压组和第二组升压组；第二组升压组的单向传输单元的第一端、第一组升压组的单向传输单元的第二端和第一组升压组的存储单元的第一端耦合于第一节点；第二组升压组的单向传输单元的第二端和所述第二组升压组的存储单元的第一端耦合于第三节点；第一组升压组的存储单元的第二端用于接收第一脉冲宽度调制信号，第二组升压组的存储单元的第二端用于接收第二脉冲宽度调制信号。According to the first aspect, or any implementation of the first aspect above, the voltage adjustment module includes a first boost group and a second boost group; the first end of the unidirectional transmission unit of the second boost group, the second end of the unidirectional transmission unit of the first boost group and the first end of the storage unit of the first boost group are coupled to the first node; the second end of the unidirectional transmission unit of the second boost group and the first end of the storage unit of the second boost group are coupled to the third node; the second end of the storage unit of the first boost group is used to receive a first pulse width modulation signal, and the second end of the storage unit of the second boost group is used to receive a second pulse width modulation signal.
通过两组升压组即可实现电源信号的升压，结构简单，占用区域小。The power signal can be boosted by two boost groups, which has a simple structure and occupies a small area.
根据第一方面，或者以上第一方面的任意一种实现方式，存储单元包括存储电容；奇数升压组的所述存储电容的第一极与第一节点电连接，奇数升压组的存储电容的第二极用于接收第一脉冲宽度调制信号；偶数升压组的存储电容的第一极与第二节点电连接，偶数升压组的存储电容的第二极用于接收第二脉冲宽度调制信号。According to the first aspect, or any implementation of the first aspect above, the storage unit includes a storage capacitor; the first electrode of the storage capacitor of the odd-numbered boost group is electrically connected to the first node, and the second electrode of the storage capacitor of the odd-numbered boost group is used to receive a first pulse width modulation signal; the first electrode of the storage capacitor of the even-numbered boost group is electrically connected to the second node, and the second electrode of the storage capacitor of the even-numbered boost group is used to receive a second pulse width modulation signal.
通过一个电容即可实现存储功能，存储单元的结构简单，进而使得驱动电路的结构简单，成本低。The storage function can be realized by a capacitor, and the structure of the storage unit is simple, thereby making the structure of the driving circuit simple and low-cost.
根据第一方面，或者以上第一方面的任意一种实现方式，单向传输单元包括二极管；偶数升压组的二极管的阳极、偶数升压组的前一升压组的二极管的阴极和偶数升压组的前一升压组的存储单元的第一端耦合于第一节点；除第一组升压组外，奇数升压组的二极管的阳极、奇数升压组的前一升压组的二极管的阴极和奇数升压组的前一升压组的存储单元的第一端耦合于第二节点。According to the first aspect, or any implementation of the first aspect above, the unidirectional transmission unit includes a diode; the anode of the diode of the even-numbered boosting group, the cathode of the diode of the previous boosting group of the even-numbered boosting group, and the first end of the storage unit of the previous boosting group of the even-numbered boosting group are coupled to the first node; except for the first boosting group, the anode of the diode of the odd-numbered boosting group, the cathode of the diode of the previous boosting group of the odd-numbered boosting group, and the first end of the storage unit of the previous boosting group of the odd-numbered boosting group are coupled to the second node.
通过一个二极管即可实现单向导通功能，避免第一节点和第二节点处的信号之间干扰，单向传输单元的结构简单，进而使得驱动电路的结构简单，成本低。The unidirectional conduction function can be realized by a diode to avoid interference between the signals at the first node and the second node. The structure of the unidirectional transmission unit is simple, thereby making the structure of the driving circuit simple and low in cost.
根据第一方面，或者以上第一方面的任意一种实现方式，积分单元可以包括第一电阻和积分电容；第一电阻的第一端与第三节点电连接，第一电阻的第二端分别与积分电容的第一极以及驱动信号输出端电连接，积分电容的第二极接地设置。According to the first aspect, or any implementation of the first aspect above, the integration unit may include a first resistor and an integration capacitor; the first end of the first resistor is electrically connected to the third node, the second end of the first resistor is electrically connected to the first pole of the integration capacitor and the drive signal output end respectively, and the second pole of the integration capacitor is grounded.
积分单元的结构简单，进而使得驱动电路的结构简单，成本低。The structure of the integration unit is simple, so that the structure of the driving circuit is simple and the cost is low.
根据第一方面，或者以上第一方面的任意一种实现方式，驱动电路还包括保护模块，保护模块的第一端与驱动信号输出端电连接，保护模块的第二端接地设置；保护模块用于在驱动电路未接收到电源信号、开关控制信号、第一脉冲宽度调制信号和第二脉冲宽度调制信号时，将驱动信号输出端处的信号下拉至地。According to the first aspect, or any implementation of the first aspect above, the driving circuit also includes a protection module, a first end of the protection module is electrically connected to the driving signal output end, and a second end of the protection module is grounded; the protection module is used to pull the signal at the driving signal output end to the ground when the driving circuit does not receive the power signal, the switch control signal, the first pulse width modulation signal, and the second pulse width modulation signal.
这样设置，可以避免NMOS管的栅极由于一些其他信号的干扰等原因而非正常导通的问题。This arrangement can avoid the problem that the gate of the NMOS tube is not turned on normally due to interference from some other signals.
根据第一方面，或者以上第一方面的任意一种实现方式，保护模块包括第二电阻，第二电阻的第一端与驱动信号输出端电连接，第二电阻的第二端接地设置。According to the first aspect, or any implementation of the first aspect above, the protection module includes a second resistor, a first end of the second resistor is electrically connected to the drive signal output end, and a second end of the second resistor is grounded.
保护模块的结构简单，进而使得驱动电路的结构简单，成本低。The protection module has a simple structure, which in turn makes the drive circuit simple in structure and low in cost.
根据第一方面，或者以上第一方面的任意一种实现方式，关断模块包括金属氧化物半导体场效应晶体管等，本申请对关断模块的具体结构不作限定，只要在驱动电路未上电时，关断模块可以将NMOS管关断即可，避免NMOS管的栅极由于一些其他信号的干扰等原因而非正常导通的问题。According to the first aspect, or any implementation method of the first aspect above, the shutdown module includes a metal oxide semiconductor field effect transistor, etc. The present application does not limit the specific structure of the shutdown module. As long as the driving circuit is not powered on, the shutdown module can shut down the NMOS tube to avoid the problem that the gate of the NMOS tube is not normally turned on due to interference from some other signals.
根据第一方面，或者以上第一方面的任意一种实现方式，当关断模块根据接收的开关控制信号导通时，关断模块导通时长大于或等于预设时长。这样，NMOS管栅极处的电压可以快速的泄放到地，且积分电路中的积分电容上电压也可以快速的泄放到地，使得NMOS管栅极的电压快速的变为0V，即，加快关断NMOS管的速度。According to the first aspect, or any implementation of the first aspect above, when the shutdown module is turned on according to the received switch control signal, the turn-on time of the shutdown module is greater than or equal to the preset time. In this way, the voltage at the gate of the NMOS tube can be quickly discharged to the ground, and the voltage on the integral capacitor in the integral circuit can also be quickly discharged to the ground, so that the voltage at the gate of the NMOS tube quickly becomes 0V, that is, the speed of turning off the NMOS tube is accelerated.
示例性的，预设时长例如为50微秒、60微秒、70微秒或80微秒等。Exemplarily, the preset duration is, for example, 50 microseconds, 60 microseconds, 70 microseconds, or 80 microseconds.
根据第一方面，或者以上第一方面的任意一种实现方式，当N为偶数时，第三节点处最高电压Vmax满足：According to the first aspect, or any implementation of the first aspect above, when N is an even number, the maximum voltage Vmax at the third node satisfies:
Vmax＝V0+(N/2)VP1+(N/2)VP2-NVd；Vmax =V0+(N/2)VP1 +(N/2)VP2 -NVd ;
第三节点处最低电压Vmin满足：The minimum voltageVmin at the third node satisfies:
Vmin＝V0+(N/2)VP1+{(N-2)/2}VP2-NVd；Vmin =V0+(N/2)VP1 +{(N-2)/2}VP2 -NVd ;
当N为奇数时，第三节点处最高电压Vmax满足：When N is an odd number, the maximum voltage Vmax at the third node satisfies:
Vmax＝V0+{(N+1)/2}VP1+{(N-1)/2}VP2-NVd；Vmax =V0+{(N+1)/2}VP1 +{(N-1)/2}VP2 -NVd ;
第三节点处最低电压Vmin满足：The minimum voltageVmin at the third node satisfies:
Vmin＝V0+{(N-1)/2}VP1+{(N-1)/2}VP2-NVd；Vmin =V0+{(N-1)/2}VP1 +{(N-1)/2}VP2 -NVd ;
其中，Vd为单向导通单元的压降，VP1为第一脉冲宽度调制信号的最大电压，VP2为第二脉冲宽度调制信号的最大电压。Wherein,Vd is the voltage drop of the unidirectional conductive unit,VP1 is the maximum voltage of the first pulse width modulation signal, andVP2 is the maximum voltage of the second pulse width modulation signal.
需要说明的是，以上公式适用于各二极管的压降相同的情况。对于各二极管的压降不同的情况，可以依次减去各二极管的压降。It should be noted that the above formula is applicable to the case where the voltage drops of the diodes are the same. If the voltage drops of the diodes are different, the voltage drops of the diodes can be subtracted in turn.
根据第一方面，或者以上第一方面的任意一种实现方式，驱动电路还包括控制模块，控制模块用于输出第一脉冲宽度调制信号和第二脉冲宽度调制信号。According to the first aspect, or any implementation of the first aspect above, the driving circuit further includes a control module, and the control module is used to output a first pulse width modulation signal and a second pulse width modulation signal.
驱动电路可以单独设置控制模块，这样，使得该驱动电路应用范围更加的广泛。当然，当驱动电路应用于电子设备时，驱动电路也可以用电子设备内的其他模块，如PMU，为其提供第一脉冲宽度调制信号和第二脉冲宽度调制信号。The driving circuit can be provided with a control module separately, so that the application range of the driving circuit is wider. Of course, when the driving circuit is applied to electronic equipment, the driving circuit can also use other modules in the electronic equipment, such as PMU, to provide the first pulse width modulation signal and the second pulse width modulation signal.
第二方面，本申请提供一种隔离装置，该隔离装置包括NMOS管和述第一方面以及第一方面的任意一种实现方式所对应的驱动电路，NMOS管的栅极与驱动电路的驱动信号输出端电连接；驱动电路用于通过驱动信号输出端向NMOS管的栅极提供驱动信号，以驱动NMOS管导通或截止。In a second aspect, the present application provides an isolation device, which includes an NMOS tube and a driving circuit corresponding to the first aspect and any one of the implementation methods of the first aspect, wherein the gate of the NMOS tube is electrically connected to the driving signal output terminal of the driving circuit; the driving circuit is used to provide a driving signal to the gate of the NMOS tube through the driving signal output terminal to drive the NMOS tube to be turned on or off.
第二方面以及第二方面的任意一种实现方式分别与第一方面以及第一方面的任意一种实现方式相对应。第二方面以及第二方面的任意一种实现方式所对应的技术效果可参见上述第一方面以及第一方面的任意一种实现方式所对应的技术效果，此处不再赘述。The second aspect and any implementation of the second aspect correspond to the first aspect and any implementation of the first aspect respectively. The technical effects corresponding to the second aspect and any implementation of the second aspect can refer to the technical effects corresponding to the first aspect and any implementation of the first aspect, which will not be repeated here.
第三方面，本申请提供一种电子设备，该电子设备包括第二方向所述的隔离装置。In a third aspect, the present application provides an electronic device, which includes the isolation device described in the second direction.
第三方面以及第三方面的任意一种实现方式分别与第二方面以及第二方面的任意一种实现方式相对应。第三方面以及第三方面的任意一种实现方式所对应的技术效果可参见上述第二方面以及第二方面的任意一种实现方式所对应的技术效果，此处不再赘述。The third aspect and any implementation of the third aspect correspond to the second aspect and any implementation of the second aspect, respectively. The technical effects corresponding to the third aspect and any implementation of the third aspect can refer to the technical effects corresponding to the above-mentioned second aspect and any implementation of the second aspect, which will not be repeated here.
根据第三方面，电子设备还包括电源管理芯片，电源管理芯片用于输出第一脉冲宽度调制信号和第二脉冲宽度调制信号。According to a third aspect, the electronic device further includes a power management chip, and the power management chip is used to output the first pulse width modulation signal and the second pulse width modulation signal.
即直接利用电子设备中的电源管理芯片输出第一脉冲宽度调制信号和第二脉冲宽度调制信号，无需为驱动电路单独设置控制模块，简化驱动电路的结构，且有利于电子设备降低成本。That is, the power management chip in the electronic device is directly used to output the first pulse width modulation signal and the second pulse width modulation signal, without the need to set up a separate control module for the drive circuit, thus simplifying the structure of the drive circuit and helping to reduce the cost of the electronic device.
根据第三方面，或者以上第三方面的任意一种实现方式，电子设备包括第一电池和第二电池；NMOS管的源极与第一电池电连接，NMOS管的漏极与第二电池电连接。According to the third aspect, or any implementation of the third aspect above, the electronic device includes a first battery and a second battery; the source of the NMOS tube is electrically connected to the first battery, and the drain of the NMOS tube is electrically connected to the second battery.
隔离装置用于隔离第一电池和第二电池，且当第一电池和第二电池相通(如，其中一者为另一者充电)时，隔离装置还用于对第一电池和第二电池的电压进行电压均衡，这样，可使得隔离装置连接的两个电池的电压均衡，以降低隔离装置连接的两个电池的电压差，进而限制隔离装置连接的两个电池之间的互充电流。当该电子设备为折叠式电子设备时，降低因隔离装置连接的两个电池之间产生的大电流互充而烧毁FPC上分布的走线的可能性，提高折叠式电子设备的安全性和可靠性。The isolation device is used to isolate the first battery and the second battery, and when the first battery and the second battery are connected (e.g., one of them charges the other), the isolation device is also used to balance the voltage of the first battery and the second battery, so that the voltage of the two batteries connected to the isolation device can be balanced to reduce the voltage difference between the two batteries connected to the isolation device, thereby limiting the mutual charging current between the two batteries connected to the isolation device. When the electronic device is a foldable electronic device, the possibility of burning the wiring distributed on the FPC due to the large current mutual charging generated between the two batteries connected to the isolation device is reduced, thereby improving the safety and reliability of the foldable electronic device.
根据第三方面，或者以上第三方面的任意一种实现方式，电子设备包括电池和负载；NMOS管的源极与电池电连接，NMOS管的漏极与负载电连接。According to the third aspect, or any implementation of the third aspect above, the electronic device includes a battery and a load; the source of the NMOS tube is electrically connected to the battery, and the drain of the NMOS tube is electrically connected to the load.
隔离装置用于隔离电池和负载，且当电池和负载相通(如，电池为负载供电)时，隔离装置还用于对电池提供给负载的电压进行调整，这样，可使得隔离装置连接的电池和负载的电压均衡，以降低隔离装置连接的两个电池以满足供电要求。The isolation device is used to isolate the battery and the load, and when the battery and the load are connected (for example, the battery supplies power to the load), the isolation device is also used to adjust the voltage provided by the battery to the load, so that the voltage of the battery and the load connected to the isolation device can be balanced to reduce the voltage of the two batteries connected to the isolation device to meet the power supply requirements.
当然，隔离装置在电子设备中的应用并不限于上述两种情况，只要器件之间需要隔离，均可采用上述隔离装置。Of course, the application of the isolation device in electronic equipment is not limited to the above two situations. As long as isolation is required between devices, the above isolation device can be used.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
图1为NMOS管的输出特性曲线；Figure 1 is the output characteristic curve of the NMOS tube;
图2为本申请实施例提供的一种折叠式电子设备的结构示意图；FIG2 is a schematic diagram of the structure of a foldable electronic device provided in an embodiment of the present application;
图3a为本申请实施例提供的折叠式手机折叠时的一种示意图；FIG3a is a schematic diagram of a foldable mobile phone provided in an embodiment of the present application when folded;
图3b为本申请实施例提供的折叠式手机折叠时的又一种示意图；FIG3 b is another schematic diagram of the foldable mobile phone provided in an embodiment of the present application when folded;
图4为本申请实施例提供的又一种折叠式电子设备的结构示意图；FIG4 is a schematic structural diagram of another foldable electronic device provided in an embodiment of the present application;
图5为本申请实施例提供的折叠式电子设备的部分结构示意图；FIG5 is a schematic diagram of a partial structure of a foldable electronic device provided in an embodiment of the present application;
图6为本申请实施例提供的折叠式电子设备的一种电路图；FIG6 is a circuit diagram of a foldable electronic device provided in an embodiment of the present application;
图7为本申请实施例提供的折叠式电子设备的又一种电路图；FIG7 is another circuit diagram of a foldable electronic device provided in an embodiment of the present application;
图8为本申请实施例提供的折叠式电子设备的又一种电路图；FIG8 is another circuit diagram of a foldable electronic device provided in an embodiment of the present application;
图9为本申请实施例提供的折叠式电子设备的又一种电路图；FIG9 is another circuit diagram of a foldable electronic device provided in an embodiment of the present application;
图10为本申请实施例提供的折叠式电子设备的又一种电路图；FIG10 is another circuit diagram of a foldable electronic device provided in an embodiment of the present application;
图11为本申请实施例提供的折叠式电子设备的又一种电路图；FIG11 is another circuit diagram of a foldable electronic device provided in an embodiment of the present application;
图12为本申请实施例提供的第一PWM信号和第二PWM信号的波形图；FIG12 is a waveform diagram of a first PWM signal and a second PWM signal provided in an embodiment of the present application;
图13为本申请实施例提供的隔离电路的又一种电路图；FIG13 is another circuit diagram of an isolation circuit provided in an embodiment of the present application;
图14为本申请实施例提供的第一节点处的信号和第二节点处的信号的波形图；FIG14 is a waveform diagram of a signal at a first node and a signal at a second node provided in an embodiment of the present application;
图15为本申请实施例提供的第二节点处的信号的波形图积分后的电压波形图。FIG. 15 is a voltage waveform diagram after integration of the waveform diagram of the signal at the second node provided in an embodiment of the present application.
具体实施方式Detailed ways
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。The term "and/or" in this article is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and/or B can mean: A exists alone, A and B exist at the same time, and B exists alone.
本申请实施例的说明书和权利要求书中的术语“第一”和“第二”等是用于区别不同的对象，而不是用于描述对象的特定顺序。例如，第一目标对象和第二目标对象等是用于区别不同的目标对象，而不是用于描述目标对象的特定顺序。The terms "first" and "second" in the description and claims of the embodiments of the present application are used to distinguish different objects rather than to describe a specific order of objects. For example, a first target object and a second target object are used to distinguish different target objects rather than to describe a specific order of target objects.
在本申请实施例中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.
在本申请实施例的描述中，除非另有说明，“多个”的含义是指两个或两个以上。例如，多个处理单元是指两个或两个以上的处理单元；多个系统是指两个或两个以上的系统。In the description of the embodiments of the present application, unless otherwise specified, the meaning of "multiple" refers to two or more than two. For example, multiple processing units refer to two or more processing units; multiple systems refer to two or more systems.
为了便于描述，以下先对本申请实施例涉及的MOS管进行简单介绍。For the convenience of description, the MOS tube involved in the embodiment of the present application is briefly introduced below.
MOS管包括PMOS管和NMOS管，PMOS管和NMOS均包括栅极(一般用G表示)、源极(一般用S表示)和漏极(一般用D表示)。PMOS管和NMOS管均有两种状态，即导通状态和截止状态(也称为关闭状态)。MOS管由截止状态到导通状态时，需要驱动电压进行驱动，MOS管驱动电压与各状态的关系如表1所示。MOS tubes include PMOS tubes and NMOS tubes. Both PMOS tubes and NMOS tubes include a gate (generally represented by G), a source (generally represented by S) and a drain (generally represented by D). Both PMOS tubes and NMOS tubes have two states, namely, an on state and an off state (also called a closed state). When a MOS tube changes from an off state to an on state, a driving voltage is required to drive it. The relationship between the MOS tube driving voltage and each state is shown in Table 1.
表1MOS管驱动电压与各状态的关系Table 1 Relationship between MOS tube driving voltage and various states
VG表示MOS管的栅极电压，VS表示MOS管的源极电压，VD表示MOS管的漏极电压。VGS表示MOS管的栅极和源极电压差(也称为栅源电压差)，VDS表示MOS管的漏极和源极电压差(也称为漏源电压差)，Vth表示MOS管的阈值电压(也称为门限电压)。一般而言，PMOS管的阈值电压为负电压，NMOS管的阈值电压为正电压。VG represents the gate voltage of the MOS tube,VS represents the source voltage of the MOS tube, and VD represents the drain voltage of the MOS tube. VGS represents the gate-source voltage difference of the MOS tube (also called the gate-source voltage difference), VDS represents the drain-source voltage difference of the MOS tube (also called the drain-source voltage difference), and Vth represents the threshold voltage of the MOS tube (also called the threshold voltage). Generally speaking, the threshold voltage of the PMOS tube is a negative voltage, and the threshold voltage of the NMOS tube is a positive voltage.
由表1可知，对于PMOS管而言，当栅源电压差VGS小于阈值电压Vth时，PMOS管导通；当栅源电压差VGS大于阈值电压Vth时，PMOS管关闭。对于NMOS管而言，当栅源电压差VGS大于阈值电压Vth时，NMOS管导通；当栅源电压差VGS小于阈值电压Vth时，NMOS管关闭。As can be seen from Table 1, for the PMOS tube, when the gate-source voltage difference VGS is less than the threshold voltage Vth , the PMOS tube is turned on; when the gate-source voltage difference VGS is greater than the threshold voltage Vth , the PMOS tube is turned off. For the NMOS tube, when the gate-source voltage difference VGS is greater than the threshold voltage Vth , the NMOS tube is turned on; when the gate-source voltage difference VGS is less than the threshold voltage Vth , the NMOS tube is turned off.
此外，对MOS管工作在线性区和饱和区的概念进行介绍，其中，以NMOS管工作在线性区和饱和区为例进行介绍。In addition, the concept of MOS tube working in linear region and saturation region is introduced, wherein the concept of NMOS tube working in linear region and saturation region is introduced as an example.
图1为NMOS管的输出特性曲线，其中，横坐标VDS为漏源电压差，纵坐标ID为漏极电流，VGS为栅源电压差。参见图1，MOS管的输出特性可以分为三个区：截止区(也为关断区)、恒流区(也为饱和区)和可变电阻区(也为线性区)。当VGS＞Vth时，ID随着VDS的提升，会先呈现出一段线性增长，然后再区域平缓。线性增长的阶段称为可变电阻区。在这一阶段，MOS管等效于一个电阻，其阻值即为其斜率的倒数。当VGS不同时，电阻的阻值就会不同，即在该区域MOS管相当于一个由VGS控制的可变电阻，亦即当对MOS管的栅极电压进行调节时，可以调节MOS管在可变电阻区(也为线性区)的电阻值。可以理解的是，当电阻值改变时，通过MOS管的电压值和电流值就会发生相应的改变。平缓的阶段称为恒流区(也为饱和区)。在这一阶段，ID不随VDS的变化而变化，即经过MOS管的电流不变。且由于MOS管导通内阻Rds(on)极小，所以经过MOS管后的压降很小，MOS管导通时源极和漏极的电压几乎相等。FIG1 is an output characteristic curve of an NMOS tube, wherein the horizontal axis VDS is the drain-source voltage difference, the vertical axisID is the drain current, and VGS is the gate-source voltage difference. Referring to FIG1 , the output characteristics of the MOS tube can be divided into three regions: the cut-off region (also the turn-off region), the constant current region (also the saturation region), and the variable resistance region (also the linear region). When VGS > Vth ,ID will first show a linear growth as VDS increases, and then the region will be flat. The linear growth stage is called the variable resistance region. In this stage, the MOS tube is equivalent to a resistor, and its resistance value is the inverse of its slope. When VGS is different, the resistance value of the resistor will be different, that is, in this region, the MOS tube is equivalent to a variable resistor controlled by VGS , that is, when the gate voltage of the MOS tube is adjusted, the resistance value of the MOS tube in the variable resistance region (also the linear region) can be adjusted. It can be understood that when the resistance value changes, the voltage value and current value passing through the MOS tube will change accordingly. The gentle stage is called the constant current region (also known as the saturation region). In this stage,ID does not change with the change ofVDS , that is, the current passing through the MOS tube remains unchanged. And because the on-state internal resistance Rds(on) of the MOS tube is extremely small, the voltage drop after passing through the MOS tube is very small, and the voltage of the source and drain is almost equal when the MOS tube is turned on.
本发明提供了一种电子设备。本申请实施例提供的电子设备可以是手机、电脑、平板电脑、个人数字助理(personal digital assistant，简称PDA)、车载电脑、电视、智能穿戴式设备、智能家居设备、充电宝、新能源汽车等电子设备，此外，本申请提供的电子设备可以为直板式电子设备(如直板式手机)，也可以为折叠式电子设备(如折叠式手机)，本申请实施例对上述电子设备的具体类型和具体形态不作限定。以下为了方便说明，以电子设备是折叠式手机为例进行说明。The present invention provides an electronic device. The electronic device provided in the embodiment of the present application may be a mobile phone, a computer, a tablet computer, a personal digital assistant (PDA), a car computer, a television, a smart wearable device, a smart home device, a power bank, a new energy vehicle and other electronic devices. In addition, the electronic device provided in the present application may be a straight-type electronic device (such as a straight-type mobile phone) or a foldable electronic device (such as a foldable mobile phone). The embodiment of the present application does not limit the specific type and specific form of the above-mentioned electronic device. For the convenience of explanation, the following description is taken as an example that the electronic device is a foldable mobile phone.
参见图2，图2为本申请实施例提供的一种折叠式电子设备的结构示意图。如图2所示，折叠式手机100包括柔性屏(也称为折叠屏等)10。Referring to Fig. 2 , Fig. 2 is a schematic diagram of the structure of a foldable electronic device provided in an embodiment of the present application. As shown in Fig. 2 , a foldable mobile phone 100 includes a flexible screen (also called a foldable screen, etc.) 10 .
柔性屏10例如为具有柔性的显示屏。柔性屏10例如包括有机发光二极管(OrganicLight Emitting Diode，OLED)显示屏。OLED显示屏无需背光模组，且OLED显示屏中的衬底基板例如可以采用柔性树脂材料，例如为聚对苯二甲酸乙二醇酯(Polyethyleneterephthalate，PET)，使得OLED显示屏具有可弯折的特性。当然，柔性屏10的类型包括但是不限于OLED显示屏，只要可以实现弯折的显示屏均在本申请的保护范围内，例如还可以为液晶显示(Liquid Crystal Display，LCD)屏、LED显示屏(例如包括Micro-LED显示屏、Mini-LED显示屏)等。The flexible screen 10 is, for example, a flexible display screen. The flexible screen 10 includes, for example, an organic light emitting diode (OLED) display screen. The OLED display screen does not require a backlight module, and the substrate substrate in the OLED display screen can, for example, be made of a flexible resin material, such as polyethylene terephthalate (PET), so that the OLED display screen has a bendable property. Of course, the types of flexible screens 10 include but are not limited to OLED display screens. As long as the display screen can be bent, it is within the protection scope of this application. For example, it can also be a liquid crystal display (LCD) screen, an LED display screen (for example, including a Micro-LED display screen, a Mini-LED display screen), etc.
继续参见图2，折叠式手机100还包括结构组件。结构组件包括第一机身20、第二机身30和转轴结构40，第一机身20和第二机身30位于转轴结构40的两侧，转轴结构40分别与第一机身20和第二机身30相连接。第一机身20、转轴结构40、第二机身30可以用于承载柔性屏10。第一机身20、第二机身30可以分别绕转轴结构40的轴线S0进行旋转，实现柔性屏10的折叠或展开等状态，即实现折叠式手机100的折叠或展开等状态。Continuing to refer to FIG. 2 , the foldable mobile phone 100 also includes a structural component. The structural component includes a first body 20, a second body 30 and a hinge structure 40. The first body 20 and the second body 30 are located on both sides of the hinge structure 40, and the hinge structure 40 is connected to the first body 20 and the second body 30 respectively. The first body 20, the hinge structure 40, and the second body 30 can be used to carry the flexible screen 10. The first body 20 and the second body 30 can be rotated around the axis S0 of the hinge structure 40 respectively to realize the folding or unfolding state of the flexible screen 10, that is, to realize the folding or unfolding state of the foldable mobile phone 100.
图2示出的是折叠式手机展开后的示意图。图3a和3b示出的是折叠式手机折叠时的示意图。图3a中，当折叠式手机折叠时，其可以朝向柔性屏10的出光方向(图3a中箭头所指)折叠，即第一机身20、第二机身30绕转轴结构40的轴线S0进行旋转的方向与柔性屏10的出光方向相同。图3b中，当折叠式手机折叠时，其可以朝背离柔性屏10的出光方向(图3b中箭头所指)折叠，即第一机身20、第二机身30绕转轴结构40的轴线S0进行旋转的方向与柔性屏10的出光方向相反。FIG. 2 shows a schematic diagram of a foldable mobile phone after unfolding. FIG. 3a and FIG. 3b show schematic diagrams of a foldable mobile phone when folded. In FIG. 3a, when the foldable mobile phone is folded, it can be folded toward the light emitting direction of the flexible screen 10 (indicated by the arrow in FIG. 3a), that is, the direction in which the first body 20 and the second body 30 rotate around the axis S0 of the rotating shaft structure 40 is the same as the light emitting direction of the flexible screen 10. In FIG. 3b, when the foldable mobile phone is folded, it can be folded away from the light emitting direction of the flexible screen 10 (indicated by the arrow in FIG. 3b), that is, the direction in which the first body 20 and the second body 30 rotate around the axis S0 of the rotating shaft structure 40 is opposite to the light emitting direction of the flexible screen 10.
此处需要说明的是，该折叠式手机100可以在多个位置处发生折叠，相应的，结构组件可以包括多个转轴结构40和多个机身。例如可以包括两个转轴结构40和三个机身，相邻的两个机身之间通过一个转轴结构40相连，这样一来，该折叠式手机100具有两个折叠位置。可见，结构组件包括至少一个转轴结构40和至少两个机身，相邻两个机身通过一个转轴结构40相连。为了方便说明，本申请实施例均以结构组件包括一个转轴结构40和两个机身(即第一机身20和第二机身30)为例进行说明。It should be noted here that the foldable mobile phone 100 can be folded at multiple positions, and accordingly, the structural component may include multiple hinge structures 40 and multiple fuselages. For example, two hinge structures 40 and three fuselages may be included, and two adjacent fuselages are connected by a hinge structure 40, so that the foldable mobile phone 100 has two folding positions. It can be seen that the structural component includes at least one hinge structure 40 and at least two fuselages, and two adjacent fuselages are connected by a hinge structure 40. For the convenience of explanation, the embodiments of the present application are all described by taking the structural component including a hinge structure 40 and two fuselages (i.e., the first fuselage 20 and the second fuselage 30) as an example.
还需要说明的是，如图2所示，折叠式手机100在折叠时，可以形成左右两个屏，但不构成对本申请的限定。在本申请的其他可选实施例中，参见图4，折叠式手机100在折叠时，还可以形成上下两个屏等。It should also be noted that, as shown in FIG2 , the foldable mobile phone 100 can form two left and right screens when folded, but this does not constitute a limitation of the present application. In other optional embodiments of the present application, see FIG4 , the foldable mobile phone 100 can also form two upper and lower screens when folded.
继续参见图2，第一机身20包括第一壳体21和第一中框22，柔性屏10、第一壳体21和第一中框22围城第一容纳空间23。第二机身分部30包括第二壳体32和第二中框32，柔性屏10、第二壳体31和第二中框32围城第二容纳空间33。2 , the first body 20 includes a first shell 21 and a first middle frame 22, and the flexible screen 10, the first shell 21 and the first middle frame 22 surround a first accommodating space 23. The second body section 30 includes a second shell 32 and a second middle frame 32, and the flexible screen 10, the second shell 31 and the second middle frame 32 surround a second accommodating space 33.
此处需要说明的是，第一壳体21和第二壳体32可以均为折叠式手机100的外壳；也可以均为用于显示的显示屏；还可以第一壳体21和第二壳体32中的一者为显示屏，另一者为折叠式手机100的外壳，本申请实施例对此不作限定。It should be noted here that the first shell 21 and the second shell 32 can both be the outer shell of the foldable mobile phone 100; or both can be display screens for display; or one of the first shell 21 and the second shell 32 can be a display screen and the other can be the outer shell of the foldable mobile phone 100, and the embodiment of the present application is not limited to this.
参见图5，图5为本申请实施例提供的折叠式电子设备的部分结构示意图。如图5所示，折叠式手机100还包括第一主板50、第二主板60、柔性电路板(flexible printedcircuit，FPC)70等。第一主板50位于第一容纳腔体23内，第二主板60位于第二容纳腔体33内。柔性电路板70的一端与第一主板50电连接，柔性电路板70的另一端与第二主板60电连接，从而使得第一主板50和第二主板60通过柔性电路板70电连接。Referring to FIG. 5 , FIG. 5 is a partial structural diagram of a foldable electronic device provided in an embodiment of the present application. As shown in FIG. 5 , the foldable mobile phone 100 further includes a first mainboard 50, a second mainboard 60, a flexible printed circuit (FPC) 70, etc. The first mainboard 50 is located in the first accommodating cavity 23, and the second mainboard 60 is located in the second accommodating cavity 33. One end of the flexible printed circuit 70 is electrically connected to the first mainboard 50, and the other end of the flexible printed circuit 70 is electrically connected to the second mainboard 60, so that the first mainboard 50 and the second mainboard 60 are electrically connected through the flexible printed circuit 70.
此处需要说明的是，可以通过一个柔性电路板70实现第一主板50和第二主板60的电连接；也可以通过多个(至少两个)柔性电路板70实现第一主板50和第二主板60的电连接，图5仅以通过一个柔性电路板71实现第一主板50和第二主板60的电连接为例进行的说明。It should be noted here that the electrical connection between the first main board 50 and the second main board 60 can be achieved through a flexible circuit board 70; the electrical connection between the first main board 50 and the second main board 60 can also be achieved through multiple (at least two) flexible circuit boards 70. Figure 5 only uses the example of achieving the electrical connection between the first main board 50 and the second main board 60 through a flexible circuit board 71.
还需要说明的是，上述示例仅以折叠式手机100包括一个连接第一主板50和第二主板60的柔性电路板70作为示例，折叠式手机100还包括其他的柔性电路板，实现其他元件与第一主板50或第二主板60的连接。It should also be noted that the above example only takes the foldable mobile phone 100 including a flexible circuit board 70 connecting the first main board 50 and the second main board 60 as an example. The foldable mobile phone 100 also includes other flexible circuit boards to realize the connection of other components with the first main board 50 or the second main board 60.
为了实现折叠式手机100的续航等功能，参见图6，图6为本申请实施例提供的折叠式电子设备的一种电路图。如图6所示，折叠式手机100还包括处理模块80、第一电池81、第二电池82、通用串行总线(universal serial bus，USB)接口83、电源管理芯片(PowerManagement Units，PMU)84、隔离电路85等。In order to realize the functions of battery life of the foldable mobile phone 100, see FIG6, which is a circuit diagram of a foldable electronic device provided in an embodiment of the present application. As shown in FIG6, the foldable mobile phone 100 also includes a processing module 80, a first battery 81, a second battery 82, a universal serial bus (USB) interface 83, a power management chip (Power Management Units, PMU) 84, an isolation circuit 85, etc.
可以理解的是，本申请实施例示意的结构并不构成对折叠式手机100的具体限定。在本申请的其他实施例中，折叠式手机100可以包括比图示更多或更少的部件，或者组合某些部件，或者部件位置的改变。图示的部件可以以硬件、软件或硬件和软件的组合实现。It is understood that the structure illustrated in the embodiment of the present application does not constitute a specific limitation on the foldable mobile phone 100. In other embodiments of the present application, the foldable mobile phone 100 may include more or fewer components than shown in the figure, or combine certain components, or change the position of components. The components shown in the figure may be implemented in hardware, software, or a combination of hardware and software.
第一容纳腔体23内设置有第一电池81，第二容纳腔体33内设置有第二电池82，即第一电池81和第二电池82分别位于转轴结构40的左右两侧。A first battery 81 is disposed in the first accommodating cavity 23 , and a second battery 82 is disposed in the second accommodating cavity 33 , that is, the first battery 81 and the second battery 82 are respectively located on the left and right sides of the rotating shaft structure 40 .
处理模块80和PMU 84可以设置于第一容纳腔体23内的第一主板50上，通过第一主板50实现处理模块80和PMU 84的电连接。第一机身20的第一中框22上开设有开孔，USB接口83嵌于该开孔内。The processing module 80 and the PMU 84 can be disposed on the first mainboard 50 in the first accommodating cavity 23, and the processing module 80 and the PMU 84 are electrically connected through the first mainboard 50. An opening is provided on the first middle frame 22 of the first body 20, and the USB interface 83 is embedded in the opening.
处理模块80可以是MCU(Microcontroller Unit，微控制单元)，也可以是SOC(System on Chip，系统级芯片)，还可以是任意具有数据处理功能的器件，本实施例对此不做限定。例如，当电子设备为笔记本电脑时，处理模块80可以为MCU，当电子设备为手机时，处理模块80可以为SOC。The processing module 80 may be an MCU (Microcontroller Unit), or a SOC (System on Chip), or any device having a data processing function, which is not limited in this embodiment. For example, when the electronic device is a notebook computer, the processing module 80 may be an MCU, and when the electronic device is a mobile phone, the processing module 80 may be an SOC.
处理模块80可以包括一个或多个接口，通过接口实现与其他模块的连接和信号的交互。接口可以包括通用输入输出(General-Purpose Input/output，GPIO)接口等。The processing module 80 may include one or more interfaces, through which connection with other modules and signal interaction are realized. The interface may include a general-purpose input/output (GPIO) interface, etc.
USB接口83是符合USB标准规范的接口，具体可以是Mini USB接口，Micro USB接口，USB Type C接口等。USB接口83可以用于连接充电器为第一电池81和/或第二电池82充电，也可以用于折叠式手机100与外围设备之间传输数据。也可以用于连接耳机，通过耳机播放音频。该接口还可以用于连接其他电子设备，例如AR设备等。The USB interface 83 is an interface that complies with the USB standard specification, and specifically can be a Mini USB interface, a Micro USB interface, a USB Type C interface, etc. The USB interface 83 can be used to connect a charger to charge the first battery 81 and/or the second battery 82, and can also be used to transmit data between the foldable mobile phone 100 and peripheral devices. It can also be used to connect headphones to play audio through the headphones. The interface can also be used to connect other electronic devices, such as AR devices, etc.
在一些实施例中，USB接口83和第一电池81之间还设置有第一电压转换单元(图中未示出)，USB接口83和第二电池82之间还设置有第二电压转换单元。In some embodiments, a first voltage conversion unit (not shown in the figure) is further provided between the USB interface 83 and the first battery 81 , and a second voltage conversion unit is further provided between the USB interface 83 and the second battery 82 .
第一电压转换单元可以将USB接口83处的充电功率转换为第一电池81所需的待充电电压和待充电电流。第二电压转换单元可以将USB接口83处的充电功率转换为第二电池82所需的待充电电压和待充电电流。The first voltage conversion unit can convert the charging power at the USB interface 83 into the charging voltage and charging current required by the first battery 81. The second voltage conversion unit can convert the charging power at the USB interface 83 into the charging voltage and charging current required by the second battery 82.
需要说明的是，第一电压转换单元和第二电压转换单元可以单独设置，也可以集成在一个模块中，该模块可以为充电管理模块，如图7所示。充电管理模块也可以称为Charger IC。It should be noted that the first voltage conversion unit and the second voltage conversion unit may be provided separately or integrated into one module, which may be a charging management module, as shown in Fig. 7. The charging management module may also be referred to as a Charger IC.
隔离电路85可以位于第一容纳腔体23内的第一主板50上，也可以位于第二容纳腔体33内的第二主板60上，本申请实施例以隔离电路85位于第二容纳腔体33内的第二主板60上为例进行的说明。继续参见图7，隔离电路85通过FPC 70和第一主板50与第一电池81电连接，隔离电路85通过第二主板60与第二电池82电连接。第一电池81通过第一主板50与PMU84电连接，第二电池82通过第二主板60、第二主板60上的隔离电路85、FPC 70、第一主板50与PMU 84电连接；或者，参见图8，第二电池81通过第二主板60、FPC 70与PMU 84电连接，第一电池81通过第一主板50、FPC 70、第二主板60上的隔离电路85与PMU 84电连接。The isolation circuit 85 may be located on the first main board 50 in the first accommodating cavity 23, or on the second main board 60 in the second accommodating cavity 33. The present embodiment of the application is described by taking the isolation circuit 85 located on the second main board 60 in the second accommodating cavity 33 as an example. Continuing to refer to FIG. 7, the isolation circuit 85 is electrically connected to the first battery 81 through the FPC 70 and the first main board 50, and the isolation circuit 85 is electrically connected to the second battery 82 through the second main board 60. The first battery 81 is electrically connected to the PMU 84 through the first main board 50, and the second battery 82 is electrically connected to the PMU 84 through the second main board 60, the isolation circuit 85 on the second main board 60, the FPC 70, and the first main board 50; or, referring to FIG. 8, the second battery 81 is electrically connected to the PMU 84 through the second main board 60 and the FPC 70, and the first battery 81 is electrically connected to the PMU 84 through the first main board 50, the FPC 70, and the isolation circuit 85 on the second main board 60.
隔离电路85用于隔离第一电池81和第二电池82。且当第一电池81和第二电池82相通时，隔离电路85还用于对第一电池81和第二电池82的电压进行电压均衡，这样，可使得隔离电路85连接的两个电池的电压均衡，以降低隔离电路连接的两个电池的电压差，进而限制隔离电路连接的两个电池之间的互充电流，也就降低因隔离电路连接的两个电池之间产生的大电流互充而烧毁FPC 70上分布的走线的可能性，提高折叠式电子设备的安全性和可靠性。The isolation circuit 85 is used to isolate the first battery 81 and the second battery 82. When the first battery 81 and the second battery 82 are connected, the isolation circuit 85 is also used to balance the voltages of the first battery 81 and the second battery 82, so that the voltages of the two batteries connected to the isolation circuit 85 can be balanced to reduce the voltage difference between the two batteries connected to the isolation circuit, thereby limiting the mutual charging current between the two batteries connected to the isolation circuit, thereby reducing the possibility of burning the wiring distributed on the FPC 70 due to the large current mutual charging generated between the two batteries connected to the isolation circuit, and improving the safety and reliability of the foldable electronic device.
PMU 84基于处理模块80的控制可以将第一电池81和/或第二电池82提供的电池电压转换为系统电压并提供给处理模块80、柔性屏10等需要供电的负载，以对处理模块80、柔性屏10等负载进行供电。Based on the control of the processing module 80, the PMU 84 can convert the battery voltage provided by the first battery 81 and/or the second battery 82 into a system voltage and provide it to the processing module 80, the flexible screen 10 and other loads that need power, so as to power the processing module 80, the flexible screen 10 and other loads.
需要说明的是，当第一电池81与PMU 84电连接，第二电池82通过隔离电路85与PMU84电连接(如图7所示)时，可以仅第一电池81为PMU 84提供电池电压，在此情况下，隔离电路85关闭，第二电池82无法通过隔离电路85为PMU 84提供电池电压；也可以第一电池81和第二电池82同时为PMU 84提供电池电压，在此情况下，隔离电路85导通，第二电池82通过隔离电路85为PMU 84提供电池电压。当第二电池82与PMU 84电连接，第一电池81通过隔离电路85与PMU 84电连接(如图8所示)时，可以仅第二电池82为PMU 84提供电池电压，在此情况下，隔离电路85关闭，第一电池81无法通过隔离电路85为PMU 84提供电池电压；也可以第一电池81和第二电池82同时为PMU 84提供电池电压，在此情况下，隔离电路85导通，第一电池81通过隔离电路85为PMU 84提供电池电压。It should be noted that, when the first battery 81 is electrically connected to the PMU 84 and the second battery 82 is electrically connected to the PMU 84 through the isolation circuit 85 (as shown in FIG. 7 ), only the first battery 81 may provide the battery voltage to the PMU 84. In this case, the isolation circuit 85 is turned off, and the second battery 82 cannot provide the battery voltage to the PMU 84 through the isolation circuit 85. Alternatively, the first battery 81 and the second battery 82 may provide the battery voltage to the PMU 84 at the same time. In this case, the isolation circuit 85 is turned on, and the second battery 82 provides the battery voltage to the PMU 84 through the isolation circuit 85. When the second battery 82 is electrically connected to the PMU 84 and the first battery 81 is electrically connected to the PMU 84 through the isolation circuit 85 (as shown in FIG. 8 ), only the second battery 82 may provide the battery voltage to the PMU 84. In this case, the isolation circuit 85 is turned off, and the first battery 81 cannot provide the battery voltage to the PMU 84 through the isolation circuit 85. Alternatively, the first battery 81 and the second battery 82 may provide the battery voltage to the PMU 84 at the same time. In this case, the isolation circuit 85 is turned on, and the first battery 81 provides the battery voltage to the PMU 84 through the isolation circuit 85.
可以理解的是，当需要通过第二电池82对第一容纳腔体23内的负载供电时，第二电池82提供的电池电压经过转轴结构40处设置的FPC 70上分布的电源走线，传输至第一容纳腔体23内设置的PMU 84，PMU 84将第二电池82提供的电池电压转换为系统电压，对第一容纳腔体23内的负载进行供电。当需要通过第一电池81对第二容纳腔体33内的负载供电时，第一电池81提供的电池电压传输至PMU 84，PMU 84将第一电池81提供的电池电压转换为系统电压，通过FPC 70上分布的电源走线，传输至第二容纳腔体33内设置的负载，从而对第二容纳腔体33内的负载进行供电。当需要通过第二电池82对第二容纳腔体33内的负载供电时，第二电池82提供的电池电压经过转轴结构40处设置的FPC 70上分布的电源走线，传输至第一容纳腔体23内设置的PMU 84，PMU 84将第二电池82提供的电池电压转换为系统电压，该系统电压再通过FPC 70上分布的电源走线，传输至第二容纳腔体33内设置的负载，从而对第二容纳腔体33内的负载进行供电。It can be understood that when the load in the first accommodating cavity 23 needs to be powered by the second battery 82, the battery voltage provided by the second battery 82 is transmitted to the PMU 84 provided in the first accommodating cavity 23 through the power supply wiring distributed on the FPC 70 provided at the shaft structure 40, and the PMU 84 converts the battery voltage provided by the second battery 82 into a system voltage to power the load in the first accommodating cavity 23. When the load in the second accommodating cavity 33 needs to be powered by the first battery 81, the battery voltage provided by the first battery 81 is transmitted to the PMU 84, and the PMU 84 converts the battery voltage provided by the first battery 81 into a system voltage, and transmits it to the load provided in the second accommodating cavity 33 through the power supply wiring distributed on the FPC 70, thereby powering the load in the second accommodating cavity 33. When it is necessary to power the load in the second accommodating cavity 33 through the second battery 82, the battery voltage provided by the second battery 82 is transmitted to the PMU 84 set in the first accommodating cavity 23 through the power wiring distributed on the FPC 70 set at the hinge structure 40. The PMU 84 converts the battery voltage provided by the second battery 82 into a system voltage, and the system voltage is then transmitted to the load set in the second accommodating cavity 33 through the power wiring distributed on the FPC 70, thereby powering the load in the second accommodating cavity 33.
需要说明的是，下述内容以第一电池81与PMU 84电连接，第二电池82通过隔离电路85与PMU 84电连接为例进行的说明。It should be noted that the following content is described by taking the example that the first battery 81 is electrically connected to the PMU 84 , and the second battery 82 is electrically connected to the PMU 84 via the isolation circuit 85 .
参见图9，图9为本申请实施例提供的折叠式电子设备的又一种电路图。如图9所示，隔离电路85包括PMOS管851和驱动电路852，PMOS管851的栅极与驱动电路852电连接，PMOS管851的源极与第一电池81电连接，PMOS管851的漏极与第二电池82电连接；或者，PMOS管851的源极与第二电池82电连接，PMOS管851的漏极与第一电池81电连接。驱动电路852用于为PMOS管851的栅极提供电压，以使PMOS管851根据栅极电压的大小导通或关闭。当PMOS管851导通时，可以通过改变PMOS管851栅极的电压调节PMOS管851的电阻值。由于I＝(V1-V2)/R0，其中，I为两个电池之间的互充电流，V1为第一电池81处的电压，V2为第二电池82处的电压，R0为PMOS管851的电阻值，因此，当MOS管851的电阻值R0改变时，隔离电路85连接的两个电池之间的互充电流就会改变，也就降低因隔离电路85连接的两个电池之间产生的大电流互充而烧毁FPC 70上分布的走线的可能性，提高折叠式电子设备的安全性和可靠性。Referring to FIG. 9 , FIG. 9 is another circuit diagram of a foldable electronic device provided in an embodiment of the present application. As shown in FIG. 9 , the isolation circuit 85 includes a PMOS tube 851 and a driving circuit 852. The gate of the PMOS tube 851 is electrically connected to the driving circuit 852, the source of the PMOS tube 851 is electrically connected to the first battery 81, and the drain of the PMOS tube 851 is electrically connected to the second battery 82; or, the source of the PMOS tube 851 is electrically connected to the second battery 82, and the drain of the PMOS tube 851 is electrically connected to the first battery 81. The driving circuit 852 is used to provide a voltage to the gate of the PMOS tube 851 so that the PMOS tube 851 is turned on or off according to the size of the gate voltage. When the PMOS tube 851 is turned on, the resistance value of the PMOS tube 851 can be adjusted by changing the voltage of the gate of the PMOS tube 851. Since I=(V1-V2)/R0, where I is the mutual charging current between the two batteries, V1 is the voltage at the first battery 81, V2 is the voltage at the second battery 82, and R0 is the resistance value of the PMOS tube 851, when the resistance value R0 of the MOS tube 851 changes, the mutual charging current between the two batteries connected to the isolation circuit 85 will change, thereby reducing the possibility of burning the wiring distributed on the FPC 70 due to the large current mutual charging generated between the two batteries connected to the isolation circuit 85, thereby improving the safety and reliability of the foldable electronic device.
驱动PMOS管851的驱动电路852结构简单，驱动电路852输出0V电压即可打开PMOS管851，停止输出可关闭PMOS管851。且由前述内容可知，当PMOS管851栅极的电压改变(栅极从0V到电池电压之间的改变)时，PMOS管851的电阻值也会相应改变。The driving circuit 852 for driving the PMOS tube 851 has a simple structure. The driving circuit 852 can turn on the PMOS tube 851 by outputting a 0V voltage, and can turn off the PMOS tube 851 by stopping the output. It can be seen from the above content that when the voltage of the gate of the PMOS tube 851 changes (the gate changes from 0V to the battery voltage), the resistance value of the PMOS tube 851 will also change accordingly.
然而，经过研究发现，PMOS管851的源极端的电压(当源极与第一电池81电连接时，源极电压为第一电池81的输出电压；当源极与第二电池82电连接时，源极电压为第二电池82的输出电压)是实时变化的。当PMOS管851的源极端的电压降低时，在栅极电压一定的情况下，PMOS管851的VGS就会变大，PMOS管851的阻抗就会变大，这样，当需要PMOS管851完全导通时，PMOS管851并不能完全导通(驱动电路852输出的最小电压为0V，)，而是具有一定的阻值，且该阻值会随着PMOS管851的源极端的电压的变化而变化，无法实现PMOS管851的稳定导通。However, after research, it is found that the voltage at the source end of the PMOS tube 851 (when the source is electrically connected to the first battery 81, the source voltage is the output voltage of the first battery 81; when the source is electrically connected to the second battery 82, the source voltage is the output voltage of the second battery 82) changes in real time. When the voltage at the source end of the PMOS tube 851 decreases, under the condition of a constant gate voltage, the VGS of the PMOS tube 851 will increase, and the impedance of the PMOS tube 851 will increase. In this way, when the PMOS tube 851 needs to be fully turned on, the PMOS tube 851 cannot be fully turned on (the minimum voltage output by the drive circuit 852 is 0V), but has a certain resistance value, and the resistance value will change with the change of the voltage at the source end of the PMOS tube 851, and the stable conduction of the PMOS tube 851 cannot be achieved.
基于此，本申请实施例还提供一种隔离电路。参见图10，图10为本申请实施例提供的折叠式电子设备的又一种电路图。如图10所示，该隔离电路85包括NMOS管853和驱动芯片854。由前述内容可知，NMOS管853要想实现导通，其栅极电压必须为高电平电压，即VG-Vs>Vth才能打开NMOS管853，亦即VG需大于NMOS管853的源极端的电压(当源极与第一电池81电连接时，源极电压为第一电池81的输出电压；当源极与第二电池82电连接时，源极电压为第二电池82的输出电压)和NMOS管853的阈值电压之和，即，驱动芯片854输出的电压大于NMOS管853的源极端的电压和NMOS管853的阈值电压之和即可实现NMOS管853的稳定导通。Based on this, the embodiment of the present application also provides an isolation circuit. Referring to FIG. 10, FIG. 10 is another circuit diagram of a foldable electronic device provided in the embodiment of the present application. As shown in FIG. 10, the isolation circuit 85 includes an NMOS tube 853 and a driver chip 854. As can be seen from the above content, in order for the NMOS tube 853 to be turned on, its gate voltage must be a high-level voltage, that is, VG -Vs >Vth can turn on the NMOS tube 853, that is, VG needs to be greater than the voltage of the source terminal of the NMOS tube 853 (when the source is electrically connected to the first battery 81, the source voltage is the output voltage of the first battery 81; when the source is electrically connected to the second battery 82, the source voltage is the output voltage of the second battery 82) and the sum of the threshold voltage of the NMOS tube 853, that is, the voltage output by the driver chip 854 is greater than the sum of the voltage of the source terminal of the NMOS tube 853 and the threshold voltage of the NMOS tube 853 to achieve stable conduction of the NMOS tube 853.
虽然，NMOS管853和驱动芯片854的配合，可以实现NMOS管853的稳定导通。但是，驱动芯片854的结构十分的复杂，这是因为，电子设备的最高电压为电池电压，而驱动芯片854的输出电压需大于NMOS管853的源极端的电压(本申请实施例中即为电池电压)和NMOS管853的阈值电压之和，因此需要设计复杂的升压电路。而复杂的结构和复杂的集成工艺形成的驱动芯片854成本会较高，不利于电子设备降低成本。Although the cooperation between the NMOS tube 853 and the driver chip 854 can realize the stable conduction of the NMOS tube 853. However, the structure of the driver chip 854 is very complicated, because the highest voltage of the electronic device is the battery voltage, and the output voltage of the driver chip 854 needs to be greater than the sum of the voltage at the source end of the NMOS tube 853 (that is, the battery voltage in the embodiment of the present application) and the threshold voltage of the NMOS tube 853, so a complex boost circuit needs to be designed. The driver chip 854 formed by the complex structure and the complex integration process will have a high cost, which is not conducive to reducing the cost of the electronic device.
基于此，本申请实施例提供一种驱动电路，该驱动电路可以驱动NMOS管，且结构简单，相比于通过复杂的结构和复杂的集成工艺形成的驱动芯片，有利于电子设备降低成本。Based on this, an embodiment of the present application provides a driving circuit that can drive an NMOS tube and has a simple structure. Compared with a driving chip formed by a complex structure and a complex integration process, it is beneficial to reduce the cost of electronic equipment.
下面对驱动驱动NMOS管导通或关闭的驱动电路进行详细介绍。The following is a detailed introduction to the driving circuit that drives the NMOS tube to turn on or off.
参见图11，图11为本申请实施例提供的隔离电路的一种电路图。如图11所示，隔离电路(也称为隔离装置)85包括NMOS管853、驱动电路855、保护模块856和控制模块(图中未示出)。驱动电路855包括电压调整模块8551和关断模块8552。电压调整模块8551用于控制NMOS管853的导通和导通时电阻的调节，关断模块8552用于控制NMOS管853的关闭。控制模块用于控制驱动电路855，以使驱动电路855控制NMOS管853的导通和导通时电阻的调节，以及，控制NMOS管853的关闭。保护模块856用于在控制模块未上电(即未对驱动电路855进行控制)时，使NMOS管853处于关闭状态，避免在控制模块未上电时，NMOS管853的栅极由于一些其他信号的干扰等原因而导通的问题。Referring to FIG. 11, FIG. 11 is a circuit diagram of an isolation circuit provided in an embodiment of the present application. As shown in FIG. 11, the isolation circuit (also referred to as an isolation device) 85 includes an NMOS tube 853, a drive circuit 855, a protection module 856 and a control module (not shown in the figure). The drive circuit 855 includes a voltage adjustment module 8551 and a shutdown module 8552. The voltage adjustment module 8551 is used to control the conduction of the NMOS tube 853 and the adjustment of the resistance when it is turned on, and the shutdown module 8552 is used to control the closure of the NMOS tube 853. The control module is used to control the drive circuit 855 so that the drive circuit 855 controls the conduction of the NMOS tube 853 and the adjustment of the resistance when it is turned on, and controls the closure of the NMOS tube 853. The protection module 856 is used to turn off the NMOS tube 853 when the control module is not powered on (i.e., the drive circuit 855 is not controlled), so as to avoid the problem that the gate of the NMOS tube 853 is turned on due to interference from some other signals when the control module is not powered on.
电压调整模块8551包括N组升压组8551a和积分单元8551b，其中，N为大于或等于1的正整数。每组升压组8551a包括存储单元8551a1和单向传输单元8551a2。存储单元8551a1和单向传输单元8551a2均包括第一端和第二端。偶数升压组8551a的单向传输单元8551a2的第一端、该偶数升压组8551a的前一组升压组8551a的单向传输单元8551a2的第二端和前一组的存储单元8551a1的第一端耦合于第一节点A。除第一组升压组8551a外，奇数升压组8551a的单向传输单元8551a2的第一端、该奇数升压组8551a的前一组升压组8551a的单向传输单元8551a2的第二端和该奇数升压组8551a的前一组升压组8551a的存储单元8551a1的第一端耦合于第二节点B。第一组升压组8551a的单向传输单元8551a2的第一端用于接收电源信号V0(该电源信号V0可以由第一电池81提供，也可以由第二电池82提供等，也可以为第一电池81或第二电池82经过升压或降压等处理后得到的信号)。奇数升压组8551a的存储单元8551a1的第二端用于接收第一脉冲宽度调制(Pulse Width Modulation，PWM)信号，偶数升压组8551a的存储单元8551a1的第二端用于接收第二PWM信号，第一PWM信号和第二PWM信号频率相同，相位相反。The voltage adjustment module 8551 includes N groups of boost groups 8551a and integration units 8551b, wherein N is a positive integer greater than or equal to 1. Each group of boost groups 8551a includes a storage unit 8551a1 and a unidirectional transmission unit 8551a2. The storage unit 8551a1 and the unidirectional transmission unit 8551a2 each include a first end and a second end. The first end of the unidirectional transmission unit 8551a2 of the even-numbered boost group 8551a, the second end of the unidirectional transmission unit 8551a2 of the previous group of boost groups 8551a of the even-numbered boost group 8551a, and the first end of the previous group of storage units 8551a1 are coupled to the first node A. Except for the first boost group 8551a, the first end of the unidirectional transmission unit 8551a2 of the odd boost group 8551a, the second end of the unidirectional transmission unit 8551a2 of the previous boost group 8551a of the odd boost group 8551a, and the first end of the storage unit 8551a1 of the previous boost group 8551a of the odd boost group 8551a are coupled to the second node B. The first end of the unidirectional transmission unit 8551a2 of the first boost group 8551a is used to receive the power signal V0 (the power signal V0 can be provided by the first battery 81, or by the second battery 82, etc., or can be a signal obtained by the first battery 81 or the second battery 82 after being processed by boosting or stepping down). The second end of the storage unit 8551a1 of the odd-numbered boost group 8551a is used to receive a first pulse width modulation (PWM) signal, and the second end of the storage unit 8551a1 of the even-numbered boost group 8551a is used to receive a second PWM signal. The first PWM signal and the second PWM signal have the same frequency and opposite phases.
第N组升压组8551a的单向传输单元8551a2的第二端以及第N组升压组8551a的存储单元8551a1的第一端与积分单元8551b的第一端耦合于第三节点。当N为偶数时，第三节点也可称为第N组升压组8551a的第二节点B。当N为奇数时，第三节点也可称为第N组升压组8551a的第一节点A。The second end of the unidirectional transmission unit 8551a2 of the Nth boost group 8551a, the first end of the storage unit 8551a1 of the Nth boost group 8551a, and the first end of the integration unit 8551b are coupled to the third node. When N is an even number, the third node may also be referred to as the second node B of the Nth boost group 8551a. When N is an odd number, the third node may also be referred to as the first node A of the Nth boost group 8551a.
积分单元8551b的第二端接地设置，积分单元8551b的第三端、保护模块856的第一端、NMOS管853的栅极、关断模块8552的第一端耦合于第五节点E(也称为驱动NMOS管的驱动信号的驱动信号输出端)，保护模块856的第二端和关断模块8552的第二端均接地设置。关断模块8552的控制端用于接收开关控制信号GPIO，当关断模块8552的控制端用于接收开关控制信号GPIO为第一开关控制信号时，关断模块8552导通；当关断模块8552的控制端用于接收开关控制信号GPIO为第二开关控制信号时，关断模块8552关断。NMOS管853的源极和漏极分别电连接需要隔离的两个结构，如第一电池81和第二电池82。当然，这并不构成对本申请的限定，在本申请的其他可选实施例中，继续参见图10，NMOS管853的源极和漏极分别电连接电源模块86和负载87，其中，电源模块86可以为第一电池81或第二电池82，也可以为第一电池81和一些外围电路(如升压电路或降压电路)形成的可以输出负载87所需电压的电源模块，还可以为第二电池82和一些外围电路(如升压电路或降压电路)形成的可以输出负载87所需电压的电源模块。负载87可以为任意需要供电才可以运行的器件。在电源模块86和负载87之间设置隔离电路85可以更好的保护负载87，避免当电源模块86由于损坏等问题输出较大的电压而损坏负载87等问题。The second end of the integration unit 8551b is grounded, the third end of the integration unit 8551b, the first end of the protection module 856, the gate of the NMOS tube 853, and the first end of the shutdown module 8552 are coupled to the fifth node E (also called the drive signal output end of the drive signal driving the NMOS tube), and the second end of the protection module 856 and the second end of the shutdown module 8552 are both grounded. The control end of the shutdown module 8552 is used to receive the switch control signal GPIO. When the control end of the shutdown module 8552 is used to receive the switch control signal GPIO as the first switch control signal, the shutdown module 8552 is turned on; when the control end of the shutdown module 8552 is used to receive the switch control signal GPIO as the second switch control signal, the shutdown module 8552 is turned off. The source and drain of the NMOS tube 853 are respectively electrically connected to two structures that need to be isolated, such as the first battery 81 and the second battery 82. Of course, this does not constitute a limitation of the present application. In other optional embodiments of the present application, referring to FIG. 10, the source and drain of the NMOS tube 853 are electrically connected to the power module 86 and the load 87, respectively, wherein the power module 86 can be the first battery 81 or the second battery 82, or can be a power module formed by the first battery 81 and some peripheral circuits (such as a boost circuit or a buck circuit) that can output the voltage required by the load 87, or can be a power module formed by the second battery 82 and some peripheral circuits (such as a boost circuit or a buck circuit) that can output the voltage required by the load 87. The load 87 can be any device that needs power to operate. Providing an isolation circuit 85 between the power module 86 and the load 87 can better protect the load 87, and avoid problems such as the power module 86 outputting a large voltage due to damage and other problems and damaging the load 87.
对于单向传输单元8551a2、存储单元8551a1、积分单元8551b、关断模块8552和保护模块856的具体结构，本申请实施例对单向传输单元8551a2、存储单元8551a1、积分单元8551b、关断模块8552和保护模块856的具体结构不作限定，本领域技术人员可以根据实际情况进行设置。Regarding the specific structures of the unidirectional transmission unit 8551a2, the storage unit 8551a1, the integration unit 8551b, the shutdown module 8552 and the protection module 856, the embodiments of the present application do not limit the specific structures of the unidirectional transmission unit 8551a2, the storage unit 8551a1, the integration unit 8551b, the shutdown module 8552 and the protection module 856, and those skilled in the art can make arrangements according to actual conditions.
在一些实施例中，存储单元8551a1可以包括存储电容等可以对电源信号进行存储的器件，单向传输单元8551a2可以包括二极管等可以单向导通的器件。继续参见图11，为了便于描述，当奇数升压组8551a的存储单元8551a1包括存储电容时，该包括存储电容也称为第一电容C1，当奇数升压组8551a的单向传输单元8551a2可以包括二极管时，该二极管也称为第一二极管D1。当偶数升压组8551a的存储单元8551a1包括存储电容时，该包括存储电容也称为第二电容C2，当偶数升压组8551a的单向传输单元8551a2可以包括二极管时，该二极管也称为第二二极管D2。In some embodiments, the storage unit 8551a1 may include a device such as a storage capacitor that can store a power signal, and the unidirectional transmission unit 8551a2 may include a device such as a diode that can be unidirectionally conducted. Continuing to refer to FIG. 11, for ease of description, when the storage unit 8551a1 of the odd-numbered boosting group 8551a includes a storage capacitor, the storage capacitor is also referred to as a first capacitor C1, and when the unidirectional transmission unit 8551a2 of the odd-numbered boosting group 8551a may include a diode, the diode is also referred to as a first diode D1. When the storage unit 8551a1 of the even-numbered boosting group 8551a includes a storage capacitor, the storage capacitor is also referred to as a second capacitor C2, and when the unidirectional transmission unit 8551a2 of the even-numbered boosting group 8551a may include a diode, the diode is also referred to as a second diode D2.
积分单元8551b可以包括第一电阻R1和第三电容C3等。关断模块8552可以包括NMOS管Q1等。保护模块856可以包括第二电阻R2等。The integration unit 8551b may include a first resistor R1 and a third capacitor C3, etc. The shutdown module 8552 may include an NMOS transistor Q1, etc. The protection module 856 may include a second resistor R2, etc.
在此基础上，各结构的连接关系为：第二二极管D2的阳极、第一二极管D1的阴极和第一电容C1的第一极耦合于第一节点A，第一电容C1的第二极用于接收第一PWM信号。除第一组升压组8551a外，奇数升压组8551a的第一二极管D1的阳极、该奇数升压组8551a的前一组升压组8551a的第二二极管D2的阴极和该奇数升压组8551a的前一组升压组8551a的第二电容C2的第一极耦合于第二节点B。第二电容C2的第二极用于接收第二PWM信号，第一PWM信号和第二PWM信号频率相同，相位相反。On this basis, the connection relationship of each structure is as follows: the anode of the second diode D2, the cathode of the first diode D1 and the first electrode of the first capacitor C1 are coupled to the first node A, and the second electrode of the first capacitor C1 is used to receive the first PWM signal. Except for the first boost group 8551a, the anode of the first diode D1 of the odd boost group 8551a, the cathode of the second diode D2 of the previous boost group 8551a of the odd boost group 8551a and the first electrode of the second capacitor C2 of the previous boost group 8551a of the odd boost group 8551a are coupled to the second node B. The second electrode of the second capacitor C2 is used to receive the second PWM signal, and the first PWM signal and the second PWM signal have the same frequency and opposite phase.
第一组升压组8551a的第一二极管D1的阳极用于接收电源信号(该电源信号可以由第一电池81提供，也可以由第二电池82提供等，也可以为第一电池81或第二电池82经过升压或降压等处理后得到的信号)。The anode of the first diode D1 of the first boost group 8551a is used to receive a power signal (the power signal can be provided by the first battery 81, or by the second battery 82, etc., or it can be a signal obtained by the first battery 81 or the second battery 82 after boosting or stepping down.
当N为偶数时，第N组升压组8551a的第二二极管D2的阴极以及第N组升压组8551a的第二电容C2的第一极与积分单元8551b的第一端耦合于第二节点B。当N为奇数时，第N组升压组8551a的第一二极管D1的阴极以及第N组升压组8551a的第一电容C1的第一极与积分单元8551b的第一端耦合于第一节点A。When N is an even number, the cathode of the second diode D2 of the Nth boost group 8551a and the first electrode of the second capacitor C2 of the Nth boost group 8551a are coupled to the first end of the integration unit 8551b at the second node B. When N is an odd number, the cathode of the first diode D1 of the Nth boost group 8551a and the first electrode of the first capacitor C1 of the Nth boost group 8551a are coupled to the first node A.
积分单元8551b中第一电阻R1的第二端、第三电容C3的第一极、保护模块856中第二电阻R2的第一端、NMOS管853的栅极、NMOS管Q1的漏极耦合于第五节点E。第三电容C3的第二极、第二电阻R2的第二端以及NMOS管Q1的源极均接地设置。The second end of the first resistor R1 in the integration unit 8551b, the first electrode of the third capacitor C3, the first end of the second resistor R2 in the protection module 856, the gate of the NMOS transistor 853, and the drain of the NMOS transistor Q1 are coupled to the fifth node E. The second electrode of the third capacitor C3, the second end of the second resistor R2, and the source of the NMOS transistor Q1 are all grounded.
上述第一PWM信号、第二PWM信号和开关控制信号GPIO均由控制模块提供，控制模块可以为电子设备中单独设置的模块，也可以为电子设备已经设置的结构，如，电子设备中的PMU84为该控制模块，即PMU84不仅具有将电池(第一电池81和/或第二电池82)提供的电池电压转换为系统电压的功能，其还具有输出第一PWM信号、第二PWM信号和开关控制信号GPIO的功能。再如，电子设备中的处理模块80为该控制模块，即处理模块80不仅具有上述处理功能，其还具有输出第一PWM信号、第二PWM信号和开关控制信号GPIO的功能。还如，电子设备中的处理模块80和PMU 84为该控制模块，处理模块80输出开关控制信号GPIO，PMU 84输出第一PWM信号和第二PWM信号。The above-mentioned first PWM signal, second PWM signal and switch control signal GPIO are all provided by the control module, and the control module can be a module separately set in the electronic device, or a structure already set in the electronic device, such as, the PMU84 in the electronic device is the control module, that is, the PMU84 not only has the function of converting the battery voltage provided by the battery (the first battery 81 and/or the second battery 82) into the system voltage, but also has the function of outputting the first PWM signal, the second PWM signal and the switch control signal GPIO. For another example, the processing module 80 in the electronic device is the control module, that is, the processing module 80 not only has the above-mentioned processing function, but also has the function of outputting the first PWM signal, the second PWM signal and the switch control signal GPIO. For another example, the processing module 80 and the PMU 84 in the electronic device are the control module, the processing module 80 outputs the switch control signal GPIO, and the PMU 84 outputs the first PWM signal and the second PWM signal.
基于上述结构，首先，对驱动电路855驱动NMOS管导通的具体工作过程进行介绍。其中，结合图12，图12为本申请实施例提供的第一PWM信号和第二PWM信号的波形图，图12(1)为第一PWM信号的波形图，图12(2)为第二PWM信号的波形图。如图12所示，第一PWM信号和第二PWM信号均包括多个脉冲周期T0，每个脉冲周期T0包括在第一时间段T1的高电平信号和在第二时间段T2的低电平信号，第一PWM信号的高电平信号的电压可以为VP1，低电平信号的电压可以为0V，第二PWM信号的高电平信号的电压可以为VP2，低电平信号的电压可以为0V，图12中以VP1等于VP2为例进行的说明。为了方便描述，在后续内容中，当PWM信号为高电平信号，该高电平信号可以用1表示；PWM信号为低电平信号，低电平信号可以为0表示。当第一PWM信号在第一时间段T1为高电平信号时，第二PWM信号在第一时间段T1为低电平信号；当第一PWM信号在第一时间段T1为低电平信号时，第二PWM信号在第一时间段T1为高电平信号。Based on the above structure, first, the specific working process of the driving circuit 855 driving the NMOS tube to turn on is introduced. In combination with Figure 12, Figure 12 is a waveform diagram of the first PWM signal and the second PWM signal provided in the embodiment of the present application, Figure 12 (1) is a waveform diagram of the first PWM signal, and Figure 12 (2) is a waveform diagram of the second PWM signal. As shown in Figure 12, the first PWM signal and the second PWM signal both include multiple pulse periods T0, each pulse period T0 includes a high-level signal in the first time period T1 and a low-level signal in the second time period T2, the voltage of the high-level signal of the first PWM signal can be VP1 , and the voltage of the low-level signal can be 0V, the voltage of the high-level signal of the second PWM signal can be VP2 , and the voltage of the low-level signal can be 0V. Figure 12 takes VP1 equal to VP2 as an example for explanation. For the convenience of description, in the subsequent content, when the PWM signal is a high-level signal, the high-level signal can be represented by 1; when the PWM signal is a low-level signal, the low-level signal can be represented by 0. When the first PWM signal is a high level signal in the first time period T1, the second PWM signal is a low level signal in the first time period T1; when the first PWM signal is a low level signal in the first time period T1, the second PWM signal is a high level signal in the first time period T1.
在第一时刻t1，PWM1＝0，PWM2＝1，GPIO＝0。此时，NMOS管Q1为关闭状态。电源信号V0通过第一组升压组8551a内的第一二极管D1给第一电容C1充电，第一电容C1的电压为V0，相应的，第一节点A处的电压为V0，即，在第一时刻t1，第一组升压组8551a输出的电压为V0。亦即，第一组升压组8551a输出的最低电压为电源信号V0。At the first moment t1, PWM1=0, PWM2=1, GPIO=0. At this time, the NMOS tube Q1 is in the off state. The power signal V0 charges the first capacitor C1 through the first diode D1 in the first boost group 8551a. The voltage of the first capacitor C1 is V0. Correspondingly, the voltage at the first node A is V0, that is, at the first moment t1, the voltage output by the first boost group 8551a is V0. That is, the lowest voltage output by the first boost group 8551a is the power signal V0.
在第二时刻t2，PWM1＝1，PWM2＝0，GPIO＝0。此时，NMOS管Q1仍为关闭状态。PWM1的高电平信号使得第一组升压组8551a的第一电容C1的调压被抬高到电源信号V0和PWM1的高电平信号之和，相应的，第一组升压组8551a内第一节点A处的电压被抬高到电源信号V0和PWM1的高电平信号之和。即，第一组升压组8551a内第一节点A处的最高电压为电源信号V0和PWM1的高电平信号之和。亦即，第一组升压组8551a输出的最高电压为电源信号V0和PWM1的高电平信号之和。At the second moment t2, PWM1=1, PWM2=0, GPIO=0. At this time, the NMOS tube Q1 is still in the off state. The high level signal of PWM1 causes the voltage regulation of the first capacitor C1 of the first boost group 8551a to be raised to the sum of the power signal V0 and the high level signal of PWM1. Correspondingly, the voltage at the first node A in the first boost group 8551a is raised to the sum of the power signal V0 and the high level signal of PWM1. That is, the highest voltage at the first node A in the first boost group 8551a is the sum of the power signal V0 and the high level signal of PWM1. That is, the highest voltage output by the first boost group 8551a is the sum of the power signal V0 and the high level signal of PWM1.
第一组升压组8551a内第一节点A处的电压被抬高之后，第一节点A处的电压同时经过第二组升压组8551a的第二二极管D2给第二电容C2充电。此时第二电容C2的电压为：电源信号V0和PWM1的高电平信号之和，相应的，第二组升压组8551a内第二节点B处的电压为电源信号V0和PWM1的高电平信号之和。即，在第二时刻t2，第二组升压组8551a输出的电压为V0和PWM1的高电平信号之和。亦即，第二组升压组8551a输出的最低电压为电源信号V0和PWM1的高电平信号之和。After the voltage at the first node A in the first boost group 8551a is raised, the voltage at the first node A simultaneously charges the second capacitor C2 through the second diode D2 of the second boost group 8551a. At this time, the voltage of the second capacitor C2 is: the sum of the power signal V0 and the high level signal of PWM1, and correspondingly, the voltage at the second node B in the second boost group 8551a is the sum of the power signal V0 and the high level signal of PWM1. That is, at the second moment t2, the voltage output by the second boost group 8551a is the sum of the high level signal of V0 and PWM1. That is, the minimum voltage output by the second boost group 8551a is the sum of the high level signal of the power signal V0 and PWM1.
在第三时刻t3，PWM1＝0，PWM2＝1，GPIO＝0。此时，NMOS管Q1仍为关闭状态。电源信号V0通过第一组升压组8551a内的第一二极管D1给第一电容C1充电。PWM2的高电平信号使得第二组升压组8551a的第二电容C2的调压被抬高到电源信号V0加上PWM1的高电平信号加上PWM2的高电平信号之和，相应的，第二组升压组8551a内第二节点B处的电压被抬高到电源信号V0加上PWM1的高电平信号加上PWM2的高电平信号之和。即，第二组升压组8551a内第二节点B处的最高电压为电源信号V0加上PWM1的高电平信号加上PWM2的高电平信号之和。亦即，第二组升压组8551a输出的最高电压为电源信号V0加上PWM1的高电平信号加上PWM2的高电平信号之和。At the third moment t3, PWM1=0, PWM2=1, GPIO=0. At this time, the NMOS tube Q1 is still in the off state. The power signal V0 charges the first capacitor C1 through the first diode D1 in the first boost group 8551a. The high level signal of PWM2 causes the voltage regulation of the second capacitor C2 of the second boost group 8551a to be raised to the sum of the power signal V0 plus the high level signal of PWM1 plus the high level signal of PWM2. Correspondingly, the voltage at the second node B in the second boost group 8551a is raised to the sum of the power signal V0 plus the high level signal of PWM1 plus the high level signal of PWM2. That is, the highest voltage at the second node B in the second boost group 8551a is the sum of the power signal V0 plus the high level signal of PWM1 plus the high level signal of PWM2. That is, the highest voltage output by the second boost group 8551a is the sum of the power signal V0 plus the high level signal of PWM1 plus the high level signal of PWM2.
第二组升压组8551a内第二节点B处的电压被抬高之后，第二节点B处的电压同时经过第三组升压组8551a内的第一二极管D1给第一电容C1充电。此时第三组升压组8551a内的第一电容C1的电压为：电源信号V0加上PWM1的高电平信号加上PWM2的高电平信号之和，相应的，第三组升压组8551a内第一节点A处的电压为电源信号V0加上PWM1的高电平信号加上PWM2的高电平信号之和。即，在第三时刻t3，第三组升压组8551a输出的电压为电源信号V0加上PWM1的高电平信号加上PWM2的高电平信号之和。亦即，第三组升压组8551a输出的最低电压为电源信号V0加上PWM1的高电平信号加上PWM2的高电平信号之和。After the voltage at the second node B in the second boost group 8551a is raised, the voltage at the second node B simultaneously charges the first capacitor C1 through the first diode D1 in the third boost group 8551a. At this time, the voltage of the first capacitor C1 in the third boost group 8551a is: the sum of the power signal V0 plus the high level signal of PWM1 plus the high level signal of PWM2. Correspondingly, the voltage at the first node A in the third boost group 8551a is the sum of the power signal V0 plus the high level signal of PWM1 plus the high level signal of PWM2. That is, at the third moment t3, the voltage output by the third boost group 8551a is the sum of the power signal V0 plus the high level signal of PWM1 plus the high level signal of PWM2. That is, the lowest voltage output by the third boost group 8551a is the sum of the power signal V0 plus the high level signal of PWM1 plus the high level signal of PWM2.
在第四时刻t4，PWM1＝1，PWM2＝0，GPIO＝0。此时，NMOS管Q1仍为关闭状态。PWM1的高电平信号使得第三组升压组8551a的第一电容C1的调压被抬高到V0加上PWM1的高电平信号加上PWM2的高电平信号加上PWM1的高电平信号之和，相应的，第三组升压组8551a内第一节点A处的电压被抬高到电源信号V0加上PWM1的高电平信号加上PWM2的高电平信号加上PWM1的高电平信号之和，即电源信号V0加上两倍的PWM1的高电平信号加上PWM2的高电平信号之和。即，第三组升压组8551a内第一节点A处的最高电压为电源信号V0加上两倍的PWM1的高电平信号加上PWM2的高电平信号之和。At the fourth moment t4, PWM1=1, PWM2=0, GPIO=0. At this time, the NMOS tube Q1 is still in the off state. The high level signal of PWM1 causes the voltage regulation of the first capacitor C1 of the third boost group 8551a to be raised to the sum of V0 plus the high level signal of PWM1 plus the high level signal of PWM2 plus the high level signal of PWM1. Correspondingly, the voltage at the first node A in the third boost group 8551a is raised to the sum of the power signal V0 plus the high level signal of PWM1 plus the high level signal of PWM2 plus the high level signal of PWM1, that is, the power signal V0 plus twice the high level signal of PWM1 plus the high level signal of PWM2. That is, the highest voltage at the first node A in the third boost group 8551a is the sum of the power signal V0 plus twice the high level signal of PWM1 plus the high level signal of PWM2.
第三组升压组8551a内第一节点A处的电压被抬高之后，第一节点A处的电压同时经过第四组升压组8551a内第二二极管D2给第二电容C2充电。此时第四组升压组8551a的第二电容C2的电压为：V0加上两倍的PWM1的高电平信号加上PWM2的高电平信号之和，相应的，第四组升压组8551a的内第二节点B处的电压为电源信号V0加上两倍的PWM1的高电平信号加上PWM2的高电平信号之和。亦即，第四组升压组8551a输出的最低电压为电源信号V0加上两倍的PWM1的高电平信号加上PWM2的高电平信号之和。After the voltage at the first node A in the third boost group 8551a is raised, the voltage at the first node A simultaneously charges the second capacitor C2 through the second diode D2 in the fourth boost group 8551a. At this time, the voltage of the second capacitor C2 of the fourth boost group 8551a is: V0 plus twice the high level signal of PWM1 plus the high level signal of PWM2, and correspondingly, the voltage at the second node B in the fourth boost group 8551a is the power signal V0 plus twice the high level signal of PWM1 plus the high level signal of PWM2. That is, the lowest voltage output by the fourth boost group 8551a is the power signal V0 plus twice the high level signal of PWM1 plus the high level signal of PWM2.
在第五时刻t5，PWM1＝0，PWM2＝1，GPIO＝0。此时，NMOS管Q1仍为关闭状态。电源信号V0通过第一组升压组8551a内的第一二极管D1给第一电容C1充电。PWM2的高电平信号使得第四组升压组8551a的第二电容C2的调压被抬高到电源信号V0加上两倍的PWM1的高电平信号加上两倍PWM2的高电平信号之和，相应的，第四组升压组8551a内第二节点B处的电压被抬高到电源信号V0加上两倍的PWM1的高电平信号加上两倍PWM2的高电平信号之和。即，第四组升压组8551a内第二节点B处的最高电压为电源信号V0加上两倍的PWM1的高电平信号加上两倍PWM2的高电平信号之和。亦即，第四组升压组8551a输出的最高电压为电源信号V0加上两倍的PWM1的高电平信号加上两倍PWM2的高电平信号之和。At the fifth moment t5, PWM1=0, PWM2=1, GPIO=0. At this time, the NMOS tube Q1 is still in the off state. The power signal V0 charges the first capacitor C1 through the first diode D1 in the first boost group 8551a. The high level signal of PWM2 causes the voltage regulation of the second capacitor C2 of the fourth boost group 8551a to be raised to the sum of the power signal V0 plus twice the high level signal of PWM1 plus twice the high level signal of PWM2. Correspondingly, the voltage at the second node B in the fourth boost group 8551a is raised to the sum of the power signal V0 plus twice the high level signal of PWM1 plus twice the high level signal of PWM2. That is, the highest voltage at the second node B in the fourth boost group 8551a is the sum of the power signal V0 plus twice the high level signal of PWM1 plus twice the high level signal of PWM2. That is, the highest voltage output by the fourth boost group 8551a is the sum of the power signal V0 plus twice the high-level signal of PWM1 plus twice the high-level signal of PWM2.
第四组升压组8551a内第二节点B处的电压被抬高之后，第二节点B处的电压同时经过第五组升压组8551a内的第一二极管D1给第一电容C1充电。此时第五组升压组8551a内的第一电容C1的电压为：电源信号V0加上两倍的PWM1的高电平信号加上两倍PWM2的高电平信号之和，相应的，第五组升压组8551a内第一节点A处的电压为电源信号V0加上两倍的PWM1的高电平信号加上两倍PWM2的高电平信号之和。即，在第五时刻t5，第五组升压组8551a输出的电压为电源信号V0加上两倍的PWM1的高电平信号加上两倍PWM2的高电平信号之和。亦即，第五组升压组8551a输出的最低电压为电源信号V0加上两倍的PWM1的高电平信号加上两倍PWM2的高电平信号之和。After the voltage at the second node B in the fourth boost group 8551a is raised, the voltage at the second node B simultaneously charges the first capacitor C1 through the first diode D1 in the fifth boost group 8551a. At this time, the voltage of the first capacitor C1 in the fifth boost group 8551a is: the power signal V0 plus the high level signal of PWM1 twice plus the high level signal of PWM2 twice, and correspondingly, the voltage at the first node A in the fifth boost group 8551a is the power signal V0 plus the high level signal of PWM1 twice plus the high level signal of PWM2 twice. That is, at the fifth moment t5, the voltage output by the fifth boost group 8551a is the power signal V0 plus the high level signal of PWM1 twice plus the high level signal of PWM2 twice. That is, the minimum voltage output by the fifth boost group 8551a is the power signal V0 plus the high level signal of PWM1 twice plus the high level signal of PWM2 twice.
依次类推，当N为偶数时，第N组升压组8551a输出的最高电压为电源信号V0加上二分之N倍的PWM1的高电平信号加上二分之N倍的PWM2的高电平信号之和；第N组升压组8551a输出的最低电压为电源信号V0加上二分之N倍的PWM1的高电平信号加上二分之(N-2)倍的PWM2的高电平信号之和。也就是说，当N为偶数时，N组升压组8551a最后输出的最高电压为Vmax＝V0+(N/2)VP1+(N/2)VP2；N组升压组8551a最后输出的最低电压为Vmin＝V0+(N/2)VP1+{(N-2)/2}VP2；By analogy, when N is an even number, the highest voltage output by the Nth boost group 8551a is the sum of the power signal V0 plus the high level signal of PWM1 at half N times plus the high level signal of PWM2 at half N times; the lowest voltage output by the Nth boost group 8551a is the sum of the power signal V0 plus the high level signal of PWM1 at half N times plus the high level signal of PWM2 at half (N-2) times. That is to say, when N is an even number, the highest voltage finally output by the Nth boost group 8551a is Vmax =V0+(N/2)VP1 +(N/2)VP2 ; the lowest voltage finally output by the Nth boost group 8551a is Vmin =V0+(N/2)VP1 +{(N-2)/2}VP2 ;
当N为奇数时，第N组升压组8551a输出的最高电压为电源信号V0加上二分之(N+1)倍的PWM1的高电平信号加上二分之(N-1)倍的PWM2的高电平信号之和；第N组升压组8551a输出的低高电压为电源信号V0加上二分之(N-1)倍的PWM1的高电平信号加上二分之(N-1)倍的PWM2的高电平信号之和。也就是说，当N为奇数时，N组升压组8551a最后输出的最高电压为Vmax＝V0+{(N+1)/2}VP1+{(N-1)/2}VP2；N组升压组8551a最后输出的最低电压为Vmin＝V0+{(N-11)/2}VP1+{(N-1)/2}VP2。When N is an odd number, the highest voltage output by the Nth boost group 8551a is the sum of the power signal V0 plus the high level signal of PWM1 at half (N+1) times and the high level signal of PWM2 at half (N-1) times; the low-high voltage output by the Nth boost group 8551a is the sum of the power signal V0 plus the high level signal of PWM1 at half (N-1) times and the high level signal of PWM2 at half (N-1) times. That is to say, when N is an odd number, the highest voltage finally output by the Nth boost group 8551a is Vmax =V0+{(N+1)/2}VP1 +{(N-1)/2}VP2 ; the lowest voltage finally output by the Nth boost group 8551a is Vmin =V0+{(N-11)/2}VP1 +{(N-1)/2}VP2 .
此外，在实际场景中，各二极管D1处均有压降。如果各第一二极管D1的压降相同，如均为Vd1；各第二二极管D2的压降相同，如均为Vd2。则当N为偶数时，N组升压组8551a最后输出的最高电压为Vmax＝V0+(N/2)VP1+(N/2)VP2-(N/2)Vd1-(N/2)Vd2；N组升压组8551a最后输出的最低电压为Vmin＝V0+(N/2)VP1+{(N-2)/2}VP2-(N/2)Vd1-(N/2)Vd2。当N为奇数时，N组升压组8551a最后输出的最高电压为Vmax＝V0+{(N+1)/2}VP1+{(N-1)/2}VP2-{(N+1)/2}Vd1-{(N-1)/2}Vd2；N组升压组8551a最后输出的最低电压为Vmin＝V0+{(N-1)/2}VP1+{(N-1)/2}VP2-{(N+1)/2}Vd1-{(N-1)/2}Vd2。In addition, in actual scenarios, each diode D1 has a voltage drop. If the voltage drops of the first diodes D1 are the same, such as Vd1 ; the voltage drops of the second diodes D2 are the same, such as Vd2 . Then when N is an even number, the highest voltage finally output by the N-group boost group 8551a is Vmax =V0+(N/2)VP1 +(N/2)VP2 -(N/2)Vd1 -(N/2)Vd2 ; the lowest voltage finally output by the N-group boost group 8551a is Vmin =V0+(N/2)VP1 +{(N-2)/2}VP2 -(N/2)Vd1 -(N/2)Vd2 . When N is an odd number, the highest voltage finally output by the N-group boost group 8551a is Vmax =V0+{(N+1)/2}VP1 +{(N-1)/2}VP2 -{(N+1)/2}Vd1 -{(N-1)/2}Vd2 ; the lowest voltage finally output by the N-group boost group 8551a is Vmin =V0+{(N-1)/2}VP1 +{(N-1)/2}VP2 -{(N+1)/2}Vd1 -{(N-1)/2}Vd2 .
如果VP1和VP2的电压均与电源信号的电压V0相等时，且如果各二极管(包括第一二极管D1和第二二极管D2)的压降相同，如均为Vd。不管N为奇数还是偶数，Vmax＝(N+1)V0-NVd；Vmin＝N(V0-Vd)。If the voltages ofVP1 andVP2 are both equal to the voltage V0 of the power signal, and if the voltage drops of the diodes (including the first diode D1 and the second diode D2) are the same, such asVd , no matter N is an odd number or an even number,Vmax = (N+1)V0-NVd ;Vmin = N(V0-Vd ).
由此可知，N组升压组8551a最后输出的电压为高低变化的方波信号，其中，高为N组升压组8551a最后输出的最高电压为Vmax，低为N组升压组8551a最后输出的最低电压为Vmin。该方波信号经过积分单元8551b中第一电阻R1和第三电容C3的积分后，变为直流电压，该直流电压可以驱动NMOS管导通。且可以通过调节第一PWM信号和第二PWM信号的频率和占空比调节该直流电压的高低，进而控制NMOS是工作在线性区，还是工作在饱和区。It can be seen that the voltage finally output by the N-group boost group 8551a is a square wave signal with high and low variations, wherein high is the highest voltage finally output by the N-group boost group 8551a, which is Vmax , and low is the lowest voltage finally output by the N-group boost group 8551a, which is Vmin . After the square wave signal is integrated by the first resistor R1 and the third capacitor C3 in the integration unit 8551b, it becomes a DC voltage, which can drive the NMOS tube to turn on. And the DC voltage can be adjusted by adjusting the frequency and duty cycle of the first PWM signal and the second PWM signal, thereby controlling whether the NMOS works in the linear region or the saturation region.
需要说明的是，本申请实施例对N的具体值不作限定，本领域技术人员可以根据实际场景中NMOS管需要的电压进行设置，N的值越大，N组升压组8551a最后输出的最高电压一般较高。It should be noted that the embodiment of the present application does not limit the specific value of N. Those skilled in the art can set it according to the voltage required by the NMOS tube in the actual scenario. The larger the value of N, the higher the maximum voltage finally output by the N group boost group 8551a is generally.
示例性的，参见图13，图13为本申请实施例提供的隔离电路的又一种电路图。如图13所示，电压调整模块8551包括两组升压组8551a，两组升压组8551a包括第一组升压组8551a和第二组升压组8551a，第一组升压组8551a的第一二极管D1的阳极用于接收电源信号V0。第一组升压组8551a内的第一二极管D1的阴极和第一电容C1的第一极与第二组升压组8551a内的第二二极管D2的阳极耦合于第一节点A，第一电容C1的第二极用于接收第一PWM信号。第二组升压组8551a内的第二二极管D2的阴极和第二电容C2的第一极与积分单元8551b中第一电阻R1的第一端耦合于第二节点B，第二电容C2的第二极用于接收第二PWM信号，第一PWM信号和第二PWM信号频率相同，相位相反。积分单元8551b中第一电阻R1的第二端、第三电容C3的第一极、保护模块856中第二电阻R2的第一端、NMOS管853的栅极、NMOS管Q1的漏极耦合于第五节点E。第三电容C3的第二极、第二电阻R2的第二端以及NMOS管Q1的源极均接地设置。第一PWM信号的高电平信号的电压VP1为电源信号的电压V0，第二PWM信号的高电平信号的电压VP2也为电源信号的电压V0。此外，第一组升压组8551a的第一二极管D1的压降为Vd1，第二组升压组8551a的第二二极管D2的压降为Vd2。For example, see FIG. 13 , which is another circuit diagram of the isolation circuit provided in the embodiment of the present application. As shown in FIG. 13 , the voltage adjustment module 8551 includes two boost groups 8551a, and the two boost groups 8551a include a first boost group 8551a and a second boost group 8551a. The anode of the first diode D1 of the first boost group 8551a is used to receive the power supply signal V0. The cathode of the first diode D1 in the first boost group 8551a and the first pole of the first capacitor C1 are coupled to the anode of the second diode D2 in the second boost group 8551a at the first node A, and the second pole of the first capacitor C1 is used to receive the first PWM signal. The cathode of the second diode D2 in the second boost group 8551a and the first pole of the second capacitor C2 are coupled to the first end of the first resistor R1 in the integration unit 8551b at the second node B, and the second pole of the second capacitor C2 is used to receive the second PWM signal. The first PWM signal and the second PWM signal have the same frequency and opposite phase. The second end of the first resistor R1 in the integration unit 8551b, the first electrode of the third capacitor C3, the first end of the second resistor R2 in the protection module 856, the gate of the NMOS transistor 853, and the drain of the NMOS transistor Q1 are coupled to the fifth node E. The second electrode of the third capacitor C3, the second end of the second resistor R2, and the source of the NMOS transistor Q1 are all grounded. The voltage VP1 of the high-level signal of the first PWM signal is the voltage V0 of the power signal, and the voltage VP2 of the high-level signal of the second PWM signal is also the voltage V0 of the power signal. In addition, the voltage drop of the first diode D1 of the first boost group 8551a is Vd1 , and the voltage drop of the second diode D2 of the second boost group 8551a is Vd2 .
结合图14，图14为本申请实施例提供的第一节点处的信号和第二节点处的信号的波形图，图14中虚线代表第一节点A处的电压信号，图14中实线代表第二节点B处的电压信号。当第一PWM信号为0(低电平信号)时，第一节点A处的电压为V0-Vd1；当第一PWM信号为1(高电平信号)时，第一节点A处的电压为2V0-Vd1。即第一节点A处的电压高低变化的方波信号，其中，高为2V0-Vd1，低为V0-Vd1。In conjunction with FIG14, FIG14 is a waveform diagram of a signal at a first node and a signal at a second node provided by an embodiment of the present application, wherein the dotted line in FIG14 represents a voltage signal at the first node A, and the solid line in FIG14 represents a voltage signal at the second node B. When the first PWM signal is 0 (low-level signal), the voltage at the first node A is V0-Vd1 ; when the first PWM signal is 1 (high-level signal), the voltage at the first node A is 2V0-Vd1 . That is, the voltage at the first node A is a square wave signal with high and low changes, wherein the high voltage is 2V0-Vd1 and the low voltage is V0-Vd1 .
由前述内容可知，如果VP1和VP2的电压均与电源信号的电压V0相等时，不管N为奇数还是偶数，Vmax＝(N+1)V0-NVd；Vmin＝N(V0-Vd)。因此，当电压调整模块8551包括两组升压组8551a，两组升压组8551a包括第一组升压组8551a和第二组升压组8551a时，两组升压组8551a最后输出的最高电压(即第二节点B处的电压)为Vmax＝3V0-Vd1-Vd2；两组升压组8551a最后输出的最低电压为Vmin＝2V0-Vd1-Vd2。即，两组升压组8551a最后输出的电压为高低变化的方波信号，其中，高为N组升压组8551a最后输出的最高电压为Vmax＝3V0-Vd1-Vd2，低为N组升压组8551a最后输出的最低电压为Vmin＝2V0-Vd1-Vd2。该方波信号经过积分单元8551b中第一电阻R1和第三电容C3的积分后，变为直流电压F，如图15所示，该直流电压F可以驱动NMOS管导通。且可以通过调节第一PWM信号和第二PWM信号的频率和占空比调节该直流电压的高低，进而控制NMOS是工作在线性区，还是工作在饱和区。As can be seen from the foregoing, if the voltages ofVP1 andVP2 are both equal to the voltage V0 of the power signal, no matter N is an odd number or an even number,Vmax = (N+1)V0-NVd ;Vmin = N(V0-Vd ). Therefore, when the voltage adjustment module 8551 includes two boost groups 8551a, and the two boost groups 8551a include a first boost group 8551a and a second boost group 8551a, the highest voltage (i.e., the voltage at the second node B) finally output by the two boost groups 8551a isVmax = 3V0-Vd1 -Vd2 ; the lowest voltage finally output by the two boost groups 8551a isVmin = 2V0-Vd1 -Vd2 . That is, the voltage finally output by the two boost groups 8551a is a square wave signal with high and low variations, wherein the high voltage is the highest voltage finally output by the N boost groups 8551a, which is Vmax =3V0-Vd1 -Vd2 , and the low voltage is the lowest voltage finally output by the N boost groups 8551a, which is Vmin =2V0-Vd1 -Vd2 . After the square wave signal is integrated by the first resistor R1 and the third capacitor C3 in the integration unit 8551b, it becomes a DC voltage F, as shown in FIG15 , and the DC voltage F can drive the NMOS tube to conduct. And the DC voltage can be adjusted by adjusting the frequency and duty cycle of the first PWM signal and the second PWM signal, thereby controlling whether the NMOS works in the linear region or the saturation region.
以上，对驱动电路855驱动NMOS管导通的具体工作过程进行了介绍。下面，对驱动电路855关闭NMOS管853的具体工作过程进行了介绍。The above describes the specific operation process of the driving circuit 855 driving the NMOS transistor to conduct. The following describes the specific operation process of the driving circuit 855 turning off the NMOS transistor 853.
当需要关闭NMOS管853时，PWM1＝1，PWM2＝1，GPIO＝1，且GPIO＝1的持续时长大于或等于预设时长后，GPIO＝0。其中，预设时长可以为50us，即NMOS管Q1栅极处的开关控制信号为高电平信号，且高电平信号持续50us或大于50us，亦即NMOS管Q1导通的时长大于或等于预设时长。这样，NMOS管Q1可以完全导通，且导通的时间较长，NMOS管853栅极处的电压泄放到地，且第三电容C3上电压也可以快速的泄放到地。进而，使得NMOS管853栅极的电压快速的变为0V，即，加快关断NMOS管853的速度。When the NMOS tube 853 needs to be turned off, PWM1=1, PWM2=1, GPIO=1, and after the duration of GPIO=1 is greater than or equal to the preset duration, GPIO=0. The preset duration can be 50us, that is, the switch control signal at the gate of the NMOS tube Q1 is a high-level signal, and the high-level signal lasts for 50us or greater than 50us, that is, the duration of the conduction of the NMOS tube Q1 is greater than or equal to the preset duration. In this way, the NMOS tube Q1 can be fully turned on, and the conduction time is relatively long, the voltage at the gate of the NMOS tube 853 is discharged to the ground, and the voltage on the third capacitor C3 can also be quickly discharged to the ground. In addition, the voltage at the gate of the NMOS tube 853 quickly becomes 0V, that is, the speed of turning off the NMOS tube 853 is accelerated.
以上，对驱动电路855驱动NMOS管导通和关闭的具体工作过程进行了介绍。通过以上内容可知，本申请实施例提供的驱动电路855通过二极管和电容等简单的结构设计，即可实现较大电压的输出，如，该驱动电路855可以输出大于NMOS管853的源极端的电压(本申请实施例中即为电池电压)和NMOS管853的阈值电压之和，可实现NMOS管导通和关闭，且当NMOS管导通时，可以通过调节PWM信号的频率和/或占空比调节驱动电路855的输出电压的大小，进而控制NMOS管853工作于线性区的节点(即NMOS管853的阻值大小)。在具体应用场景中，该隔离电路85可以隔离第一电池81和第二电池82的同时，还可以对第一电池81和第二电池82的电压进行电压均衡，这样，可使得隔离电路85连接的两个电池的电压均衡，以降低隔离电路连接的两个电池的电压差，进而限制隔离电路连接的两个电池之间的互充电流，也就降低因隔离电路连接的两个电池之间产生的大电流互充而烧毁FPC 70上分布的走线的可能性，提高折叠式电子设备的安全性和可靠性。The specific working process of the driving circuit 855 driving the NMOS tube to turn on and off is introduced above. From the above content, it can be seen that the driving circuit 855 provided in the embodiment of the present application can achieve a relatively large voltage output through a simple structural design such as a diode and a capacitor. For example, the driving circuit 855 can output a voltage greater than the sum of the source terminal of the NMOS tube 853 (that is, the battery voltage in the embodiment of the present application) and the threshold voltage of the NMOS tube 853, which can realize the NMOS tube to turn on and off, and when the NMOS tube is turned on, the magnitude of the output voltage of the driving circuit 855 can be adjusted by adjusting the frequency and/or duty cycle of the PWM signal, thereby controlling the node where the NMOS tube 853 works in the linear region (that is, the resistance value of the NMOS tube 853). In a specific application scenario, the isolation circuit 85 can isolate the first battery 81 and the second battery 82, and can also balance the voltages of the first battery 81 and the second battery 82. In this way, the voltages of the two batteries connected to the isolation circuit 85 can be balanced to reduce the voltage difference between the two batteries connected to the isolation circuit, thereby limiting the mutual charging current between the two batteries connected to the isolation circuit, thereby reducing the possibility of burning the wiring distributed on the FPC 70 due to the large current mutual charging generated between the two batteries connected to the isolation circuit, thereby improving the safety and reliability of the foldable electronic device.
以上所述，以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311477516.0ACN118444733A (en) | 2023-11-07 | 2023-11-07 | Driving circuit, isolation device and electronic equipment |
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311477516.0ACN118444733A (en) | 2023-11-07 | 2023-11-07 | Driving circuit, isolation device and electronic equipment |
| Publication Number | Publication Date |
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| CN118444733Atrue CN118444733A (en) | 2024-08-06 |
| Application Number | Title | Priority Date | Filing Date |
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| CN202311477516.0APendingCN118444733A (en) | 2023-11-07 | 2023-11-07 | Driving circuit, isolation device and electronic equipment |
| Country | Link |
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| CN (1) | CN118444733A (en) |
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| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information | ||
| CB02 | Change of applicant information | Country or region after:China Address after:Unit 3401, unit a, building 6, Shenye Zhongcheng, No. 8089, Hongli West Road, Donghai community, Xiangmihu street, Futian District, Shenzhen, Guangdong 518040 Applicant after:Honor Terminal Co.,Ltd. Address before:3401, unit a, building 6, Shenye Zhongcheng, No. 8089, Hongli West Road, Donghai community, Xiangmihu street, Futian District, Shenzhen, Guangdong Applicant before:Honor Device Co.,Ltd. Country or region before:China |