Disclosure of Invention
The application provides a photoetching process control method and device for a circuit lead hole, which are used for avoiding transverse over-corrosion of an oxide layer in the photoetching process of the circuit lead hole, and further avoiding the influence on the electrical parameters of the lead hole.
The application provides a photoetching process control method for a circuit lead hole, which comprises the following steps:
Controlling corresponding photoetching process associated equipment based on a first lead hole photoetching process sub-process to carry out first lead hole photoetching on the silicon wafer to be processed so as to obtain a pre-processed silicon wafer with a plurality of lead holes with first depths; the silicon wafer to be processed is a silicon wafer to be subjected to a lead hole photoetching process, and comprises an N-type substrate, an N-type epitaxial layer and an oxide layer, wherein the oxide layer comprises a first sub-oxide layer formed by high-temperature silicon dioxide and a second sub-oxide layer formed by low-temperature silicon dioxide, and the N-type substrate, the N-type epitaxial layer, the first sub-oxide layer and the second sub-oxide layer are sequentially and tightly arranged from bottom to top;
and controlling corresponding photoetching process related equipment based on a second lead hole photoetching process sub-process to carry out secondary lead hole photoetching on the pre-processed silicon wafer so as to obtain a processed silicon wafer with a plurality of lead holes with target depths.
According to the lithography process control method for the circuit lead hole, the first lead hole lithography process sub-flow and the second lead hole lithography process sub-flow comprise a plurality of process node indication information which are sequentially arranged in time sequence, and each process node indication information comprises a corresponding process node identifier and a corresponding process parameter index.
According to the photoetching process control method for the circuit lead hole, the process nodes corresponding to the first lead hole photoetching process sub-flow comprise a first gluing node, a first pre-baking node, a first exposure node, a first developing node, a first hardening node, a first corrosion node and a first photoresist removing node which are sequentially arranged in time sequence;
The process nodes corresponding to the second lead hole photoetching process sub-flow comprise a second gluing node, a second pre-baking node, a second exposure node, a second developing node, a second hardening node, a second corrosion node, a third corrosion node and a second photoresist removing node which are sequentially arranged in time sequence;
The first etching nodes are used for etching the second sub-oxide layer, the second etching nodes are used for etching the first sub-oxide layer, and the third etching nodes are used for etching the residual parts of the first sub-oxide layer and the second sub-oxide layer in the lead holes.
According to the photoetching process control method for the circuit lead hole, the first depth is the thickness of the second sub-oxide layer, and the target depth is the sum of the thicknesses of the first sub-oxide layer and the second sub-oxide layer.
According to the method for controlling the photoetching process of the circuit lead hole, which is provided by the application, the corresponding photoetching process associated equipment is controlled to carry out the first lead hole photoetching on the silicon wafer to be processed based on the first lead hole photoetching process sub-flow, and the method specifically comprises the following steps:
determining a plurality of process node indication information corresponding to the first lead hole lithography based on the first lead hole lithography process sub-flow;
Determining photoetching process related equipment corresponding to each process node and a control instruction sequence of each photoetching process related equipment based on a plurality of process node indication information corresponding to the first lead hole photoetching;
and sequentially sending a control instruction sequence to corresponding photoetching process related equipment based on the time sequence so as to control the photoetching process related equipment to carry out first lead hole photoetching on the silicon wafer to be processed.
According to the lithography process control method for the circuit lead hole provided by the application, the lithography process associated equipment corresponding to each process node and the control instruction sequence of each lithography process associated equipment are determined based on a plurality of process node indication information corresponding to the first lead hole lithography, and the lithography process control method concretely comprises the following steps:
Determining a process node identifier and a process parameter index corresponding to each process node based on a plurality of process node indication information corresponding to the first lead hole lithography;
Corresponding photoetching process related equipment is determined based on the process node identifiers corresponding to the process nodes, and a control instruction sequence of the photoetching process related equipment is generated based on the process parameter indexes corresponding to the process nodes.
According to the photoetching process control method for the circuit lead hole, the first corrosion node and the second corrosion node are subjected to wet corrosion, corresponding process parameter indexes comprise corrosion time and corrosion temperature, the third corrosion node is subjected to dry corrosion, and corresponding process index parameters comprise corrosion time, corrosion temperature and corrosion pressure;
wherein the first etching time and the first etching temperature corresponding to the first etching node are determined based on the thickness and the etching speed of the second sub-oxide layer; the second etching time and the second etching temperature corresponding to the second etching node are determined based on the thickness and the etching speed of the first sub-oxide layer; the third etching time, the third etching temperature and the first etching pressure corresponding to the third etching node are determined based on the thicknesses and the etching speeds of the residual portions of the first sub-oxide layer and the second sub-oxide layer.
The application also provides a photoetching process control device for the circuit lead hole, which comprises the following steps:
The first photoetching control unit is used for controlling corresponding photoetching process association equipment to carry out first lead hole photoetching on the silicon wafer to be processed based on a first lead hole photoetching process sub-flow so as to obtain a pre-processed silicon wafer with a plurality of lead holes with a first depth; the silicon wafer to be processed is a silicon wafer to be subjected to a lead hole photoetching process, and comprises an N-type substrate, an N-type epitaxial layer and an oxide layer, wherein the oxide layer comprises a first sub-oxide layer formed by high-temperature silicon dioxide and a second sub-oxide layer formed by low-temperature silicon dioxide, and the N-type substrate, the N-type epitaxial layer, the first sub-oxide layer and the second sub-oxide layer are sequentially and tightly arranged from bottom to top;
and the second photoetching control unit is used for controlling corresponding photoetching process association equipment to carry out second lead hole photoetching on the pre-processed silicon wafer based on a second lead hole photoetching process sub-flow so as to obtain a processed silicon wafer with a plurality of lead holes with target depths.
The present application also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of a method of controlling a lithographic process of a circuit lead hole as described in any of the above.
The present application also provides a computer program product comprising a computer program which when executed by a processor performs the steps of a method of controlling a lithographic process of a circuit lead hole as described in any one of the above.
The application provides a photoetching process control method and a photoetching process control device for a circuit lead hole, wherein the method comprises the following steps: controlling corresponding photoetching process associated equipment based on a first lead hole photoetching process sub-process to carry out first lead hole photoetching on the silicon wafer to be processed so as to obtain a pre-processed silicon wafer with a plurality of lead holes with first depths; the silicon wafer to be processed is a silicon wafer to be subjected to a lead hole photoetching process, and comprises an N-type substrate, an N-type epitaxial layer and an oxide layer, wherein the oxide layer comprises a first sub-oxide layer formed by high-temperature silicon dioxide and a second sub-oxide layer formed by low-temperature silicon dioxide, and the N-type substrate, the N-type epitaxial layer, the first sub-oxide layer and the second sub-oxide layer are sequentially and tightly arranged from bottom to top; and controlling corresponding photoetching process associated equipment based on a second lead hole photoetching process sub-process to carry out second lead hole photoetching on the pre-processed silicon wafer so as to obtain a processed silicon wafer with a plurality of lead holes with target depth, carrying out layer-by-layer corrosion on an oxide layer through a two-time photoetching process and removing the residual part, thereby avoiding the problem of transverse over-corrosion of the oxide layer caused by inconsistent corrosion rate of the oxide layer in the circuit lead hole photoetching process, and further avoiding the influence on electrical parameters of the lead holes.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Fig. 1 is a schematic flow chart of a control method of a photolithography process of a circuit lead hole, as shown in fig. 1, the method includes:
Step 101, controlling corresponding photoetching process association equipment based on a first lead hole photoetching process sub-process to carry out first lead hole photoetching on a silicon wafer to be processed so as to obtain a pre-processed silicon wafer with a plurality of lead holes with a first depth; the silicon wafer to be processed is a silicon wafer to be subjected to a lead hole photoetching process, and comprises an N-type substrate, an N-type epitaxial layer and an oxide layer, wherein the oxide layer comprises a first sub-oxide layer formed by high-temperature silicon dioxide and a second sub-oxide layer formed by low-temperature silicon dioxide, and the N-type substrate, the N-type epitaxial layer, the first sub-oxide layer and the second sub-oxide layer are sequentially and tightly arranged from bottom to top;
And 102, controlling corresponding photoetching process association equipment based on a second lead hole photoetching process sub-process to carry out second lead hole photoetching on the pre-processed silicon wafer so as to obtain a processed silicon wafer with a plurality of lead holes with target depths.
Specifically, fig. 2 is a schematic structural diagram of a silicon wafer to be processed provided by the application, as shown in fig. 2, the silicon wafer to be processed comprises an N-type substrate, an N-type epitaxial layer and an oxide layer, the oxide layer comprises a first sub-oxide layer formed by high-temperature silicon dioxide and a second sub-oxide layer formed by low-temperature silicon dioxide, and the N-type substrate, the N-type epitaxial layer, the first sub-oxide layer and the second sub-oxide layer are sequentially and tightly arranged from bottom to top. An N-type substrate refers to a substrate layer in a semiconductor material that is doped with N-type impurities to impart N-type conductivity properties. The N-type impurity is typically a pentavalent element, such As phosphorus (P) or arsenic (As), which introduces additional free electrons into the crystal lattice, thereby forming an N-type semiconductor. An N-type epitaxial layer is a layer of semiconductor material grown on an N-type substrate, which is also doped with N-type impurities. The epitaxial layer may be grown by Chemical Vapor Deposition (CVD) or Molecular Beam Epitaxy (MBE) techniques. The purpose of the epitaxial layer is to form additional functional layers, such as transistors, diodes, etc., on the substrate to perform the functions of the integrated circuit. The N-type epitaxial layer typically has the same conductive properties as the N-type substrate. The first sub-oxide layer is a protective layer on the surface of the substrate and is composed of high-temperature silicon dioxide. The high temperature silica refers to silica prepared at a relatively high temperature, and the temperature at which the high temperature silica is prepared is typically between 800 degrees celsius and 1200 degrees celsius. The second sub-oxide layer is an insulating layer and is composed of low-temperature silicon dioxide and used for isolating a metal layer grown by a subsequent photoetching process. The low temperature silica refers to silica prepared at a relatively low temperature, typically in the range of room temperature to 400 degrees celsius. Examples of the low-temperature silica include USG (Ultra Thin Silicon Dioxide, ultra-thin silica) and the like, and the embodiments of the present application are not particularly limited herein.
Based on the foregoing, since the oxide layers are of a multi-layer structure (in the embodiment of the present application, the first sub-oxide layer and the second sub-oxide layer) and the corrosion rates of the respective layer structures (i.e., the low-temperature silicon dioxide and the high-temperature silicon dioxide) are significantly different, if only one corrosion process (usually wet corrosion) is performed, the second sub-oxide layer structure (i.e., the second sub-oxide layer) with a relatively fast corrosion rate will have serious lateral overetching (the specific reason is that the corrosion liquid will simultaneously perform lateral and longitudinal corrosion in the corrosion process, and the corrosion liquid will first corrode the second sub-oxide layer and will start to corrode the first sub-oxide layer after the second sub-oxide layer is longitudinally corroded, but during the corrosion of the first sub-oxide layer, the corrosion liquid will still perform lateral etching to the second sub-oxide layer, and finally, when the first sub-oxide layer is longitudinally corroded, the second sub-oxide layer will have serious lateral overetching will occur, so that the corresponding pattern of the wire hole will be enlarged and adhered, and the electrical parameters of the wire hole will be affected. In order to solve the problem, the embodiment of the application provides a photoetching process control method for a circuit lead hole, which is characterized in that the second sub-oxide layer, the first sub-oxide layer and the residual part of the second sub-oxide layer are respectively corroded through two photoetching processes, so that the second sub-oxide layer is prevented from being corroded transversely to the maximum extent, and the accuracy of the size of the lead hole obtained through corrosion is ensured. Meanwhile, the efficiency of the circuit lead hole photoetching process is improved to the maximum extent in an automatic control mode.
More specifically, in order to ensure efficient and accurate control of the two-time wire hole lithography process, the embodiment of the present application configures the process flows of the two-time wire hole lithography process (i.e., the first wire hole lithography process sub-flow and the second wire hole lithography process sub-flow) in advance. The first lead hole photoetching process sub-flow and the second lead hole photoetching process sub-flow comprise a plurality of process node indication information which are sequentially arranged in time sequence, and each process node indication information comprises a corresponding process node identifier and a corresponding process parameter index. Based on the process node identifier, the lithography process control device for the circuit lead hole can determine the type of the process node, and further determine lithography process related equipment (such as a gumming machine, an exposure machine, a silicon wafer transfer machine and the like) corresponding to the process node. Based on the technological parameter index, the photoetching technology control device of the circuit lead hole can determine the control parameter of the photoetching technology related equipment corresponding to the technology node, and then generate a corresponding control instruction.
Further, the process nodes corresponding to the first lead hole photoetching process sub-flow comprise a first gluing node, a first pre-baking node, a first exposure node, a first developing node, a first hardening node, a first corrosion node and a first photoresist removing node which are sequentially arranged in time sequence;
The process nodes corresponding to the second lead hole photoetching process sub-flow comprise a second gluing node, a second pre-baking node, a second exposure node, a second developing node, a second hardening node, a second corrosion node, a third corrosion node and a second photoresist removing node which are sequentially arranged in time sequence;
The first etching nodes are used for etching the second sub-oxide layer, the second etching nodes are used for etching the first sub-oxide layer, and the third etching nodes are used for etching the residual parts of the first sub-oxide layer and the second sub-oxide layer in the lead holes.
It is understood that, for the first glue applying node and the second glue applying node, the first pre-baking node and the second pre-baking node, the first exposure node and the second exposure node, the first developing node and the second developing node, the first hardening node and the second hardening node, and the first photoresist removing node and the second photoresist removing node, conventional process parameter indexes may be adopted, which is not particularly limited in the embodiment of the present application. Preferably, the process nodes of the same type can adopt the same process parameter index, so that the complexity of process control can be simplified to the maximum extent and the process efficiency can be ensured. It should be noted that, the first exposure node and the corresponding mask (i.e., the mask) of the second exposure node are the same, and are both lead hole masks, i.e., the patterns of the two exposures are the same. Based on the method, the same lead hole can be corroded by the photoetching process for two times, further the corrosion of the second sub-oxide layer is accurately controlled by the first corrosion node, the corrosion of the first sub-oxide layer is completed by the second corrosion node, and the corrosion of the residual parts of the first sub-oxide layer and the second sub-oxide layer is completed by the third corrosion node. Based on this, it can be appreciated that the first depth is the thickness of the second sub-oxide layer, and the target depth is the sum of the thicknesses of the first sub-oxide layer and the second sub-oxide layer.
It should be noted that the first corrosion node and the second corrosion node are both wet-etched, the corresponding technological parameter indexes include corrosion time and corrosion temperature, the third corrosion node is dry-etched, and the corresponding technological parameter indexes include corrosion time, corrosion temperature and corrosion pressure;
wherein the first etching time and the first etching temperature corresponding to the first etching node are determined based on the thickness and the etching speed of the second sub-oxide layer; the second etching time and the second etching temperature corresponding to the second etching node are determined based on the thickness and the etching speed of the first sub-oxide layer; the third etching time, the third etching temperature and the first etching pressure corresponding to the third etching node are determined based on the thicknesses and the etching speeds of the residual portions of the first sub-oxide layer and the second sub-oxide layer.
Based on the foregoing, it can be appreciated that since the second sub-oxide layer etches faster, there is only a slight lateral overetching at the completion of the second sub-oxide layer etch, when the hole diameter error of the wire holes is within an acceptable range. Based on this, in the embodiment of the present application, after the first lead hole lithography is completed, the second lead hole lithography is continued, and at the second glue spreading node, the photoresist may enter the lead hole (including the over-etched region) in addition to being formed on the surface of the second sub-oxide layer, so that after passing through the second developing node, the photoresist in the over-etched region may remain to form the sidewall protection film of the lead hole. Based on the above, in the process of corroding the first sub-oxide layer by the second corrosion node, the second sub-oxide layer cannot be further corroded transversely due to the protection effect of the side wall protection film of the lead hole. Meanwhile, since the corrosion speed of the first sub-oxide layer is slower, serious lateral overetching occurs when the corrosion reaches the target depth, in order to avoid the occurrence of the situation, in the embodiment of the application, the hole diameter of the lead hole at the upper part of the lead hole region corresponding to the first sub-oxide layer is just the required hole diameter (namely, the lateral overetching does not happen) when the corrosion reaches the target depth by controlling the second corrosion time and the second corrosion temperature corresponding to the second corrosion node, however, based on the foregoing, the lower part of the lead hole region corresponding to the first sub-oxide layer is insufficiently corroded, namely, the hole diameter of the lower part is reduced. In order to solve the problem, the embodiment of the application further introduces a third corrosion node to corrode the residual parts of the first sub-oxide layer and the second sub-oxide layer in the lead hole so as to ensure that the diameters of the lead holes are consistent.
Because the wet etching speed is faster than that of the dry etching, the embodiment of the application etches the second sub-oxide layer and the first sub-oxide layer through the first etching node and the second etching node, and then etches the residual parts of the first sub-oxide layer and the second sub-oxide layer through the third etching node, so that the etching efficiency of the lead hole can be improved to the maximum extent on the basis of avoiding the photoetching quality problem of the lead hole caused by transverse overetching to the maximum extent. Meanwhile, since dry etching is generally performed at a relatively high temperature, removal of residual wet etching liquid is facilitated. Therefore, in the case that the shapes of the wet etching and the dry etching are the same, the embodiment of the present application can omit the steps of cleaning and drying after the second etching node, and directly perform the third etching node. Based on this, the efficiency of the wire hole lithography can be further improved.
The etching solution preferably used for the first and second etching nodes in the embodiment of the application is BOE (Buffered Oxide Etchant, buffer oxide etching solution) prepared by adopting 30-40% of NH4 F solution and 40-50% of HF solution according to a volume ratio of 6:1. The third corrosion node is preferably corroded by a reactive ion etching method, and CHF3 can be used as a corresponding corrosion gas. It can be understood that after determining the etching solutions corresponding to the first and second etching nodes and the etching gas corresponding to the third etching node, the embodiment of the application can determine the first sub-oxide etching speed and the second sub-oxide etching speed corresponding to different etching temperatures in advance through experiments, further determine the first etching temperature and the second etching temperature based on the process requirement, determine the corresponding first sub-oxide etching speed and the corresponding second sub-oxide etching speed, and further determine the first etching time and the second etching time corresponding to the first etching node and the second etching node based on the thicknesses of the first sub-oxide and the second sub-oxide. Similarly, the embodiment of the application can also respectively determine the first sub-oxide layer corrosion speed and the second sub-oxide layer corrosion speed corresponding to different corrosion temperature and corrosion pressure combinations through experiments in advance, further determine the third corrosion temperature and the first corrosion pressure based on process requirements, determine the corresponding first sub-oxide layer corrosion speed and second sub-oxide layer corrosion speed, and further accurately determine the third corrosion time corresponding to the third corrosion node based on the thicknesses of the residual parts of the first sub-oxide layer and the second sub-oxide layer.
On the basis of the above, fig. 3 is a schematic diagram of a control flow of first lead hole lithography provided by the present application, as shown in fig. 3, where the first lead hole lithography is performed on a silicon wafer to be processed based on a lithography process association device corresponding to a sub-flow control of the first lead hole lithography process, and specifically includes:
step 1011, determining a plurality of process node indication information corresponding to the first lead hole lithography based on the first lead hole lithography process sub-flow;
Step 1012, determining photolithography process related equipment corresponding to each process node and control instruction sequences of the photolithography process related equipment based on the plurality of process node indication information corresponding to the first lead hole photolithography;
Step 1013, sequentially sending a control instruction sequence to the corresponding lithography process related equipment based on the time sequence, so as to control the lithography process related equipment to perform first lead hole lithography on the silicon wafer to be processed.
Specifically, the determining, based on the indication information of the plurality of process nodes corresponding to the first lead hole lithography, the lithography process related equipment corresponding to each process node and the control instruction sequence of each lithography process related equipment specifically includes:
Determining a process node identifier and a process parameter index corresponding to each process node based on a plurality of process node indication information corresponding to the first lead hole lithography;
Corresponding photoetching process related equipment is determined based on the process node identifiers corresponding to the process nodes, and a control instruction sequence of the photoetching process related equipment is generated based on the process parameter indexes corresponding to the process nodes.
Based on the foregoing, the lithography process control device for the circuit lead hole according to the embodiment of the application can determine the type of the process node based on the process node identifier, thereby determining the lithography process related equipment (such as a gumming machine, an exposure machine, a silicon wafer transfer machine, etc.) corresponding to the process node. Based on the technological parameter index, the photoetching technology control device of the circuit lead hole can determine the control parameter of the photoetching technology related equipment corresponding to the technology node, and then generate a corresponding control instruction. For example, the photolithography process related equipment corresponding to the first gluing node is a gluing machine table, the corresponding process parameter indexes are glue layer thickness and gluing time, and after the glue layer thickness and the gluing time are determined, the photolithography process control device of the circuit lead hole can generate a control instruction sequence of the gluing machine table to control parameters such as gluing quantity, gluing speed and the like. The control flow of other process nodes is the same as the above, and the embodiments of the present application are not exhaustive herein. Based on the above, the automatic control of the first lead hole photoetching can be realized. It can be appreciated that the control flow of the second time of lead hole lithography is similar to that of the first time of lead hole lithography, and the embodiments of the present application will not be described herein.
In summary, the embodiment of the application can etch the oxide layer by layer and remove the residual part by two photolithography processes, thereby avoiding the problem of lateral over-etching of the oxide layer caused by inconsistent etching rate of the oxide layer in the photolithography process of the circuit lead hole, and further avoiding the influence on the electrical parameters of the lead hole. Fig. 4 is a schematic view showing the effect of the first lead hole lithography process provided by the present application, as shown in fig. 4, in which a lead hole with a first depth is obtained after etching, and at this time, there is slight lateral overetching, but the aperture error of the lead hole is within an acceptable range. Fig. 5 is a schematic view of the effect of the second lead hole lithography process provided by the present application, as shown in fig. 5, in the second lead hole lithography process, the glue coating covers the lead hole formed by the first lithography, after development, the side surface of the lead hole may remain with part of photoresist, so as to avoid the lateral corrosion caused by the second corrosion node, but the plurality of lead holes with the target depth obtained after the second corrosion have slopes (i.e. the remaining part), and on the basis, the slope is removed by the third corrosion node, so that the lead hole with the consistent aperture can be obtained. It will be appreciated that although there is a slight lateral overetching after the first etching node, the pore size error is within an acceptable range and therefore the resulting wire hole may be considered to be uniform in pore size. Based on the above, the wire hole meeting the requirements can be obtained after the photoresist is removed through the second photoresist removing node.
The method provided by the embodiment of the application comprises the following steps: controlling corresponding photoetching process associated equipment based on a first lead hole photoetching process sub-process to carry out first lead hole photoetching on the silicon wafer to be processed so as to obtain a pre-processed silicon wafer with a plurality of lead holes with first depths; the silicon wafer to be processed is a silicon wafer to be subjected to a lead hole photoetching process, and comprises an N-type substrate, an N-type epitaxial layer and an oxide layer, wherein the oxide layer comprises a first sub-oxide layer formed by high-temperature silicon dioxide and a second sub-oxide layer formed by low-temperature silicon dioxide, and the N-type substrate, the N-type epitaxial layer, the first sub-oxide layer and the second sub-oxide layer are sequentially and tightly arranged from bottom to top; and controlling corresponding photoetching process associated equipment based on a second lead hole photoetching process sub-process to carry out second lead hole photoetching on the pre-processed silicon wafer so as to obtain a processed silicon wafer with a plurality of lead holes with target depth, carrying out layer-by-layer corrosion on an oxide layer through a two-time photoetching process and removing the residual part, thereby avoiding the problem of transverse over-corrosion of the oxide layer caused by inconsistent corrosion rate of the oxide layer in the circuit lead hole photoetching process, and further avoiding the influence on electrical parameters of the lead holes.
The photolithography process control device for the circuit lead hole provided by the application is described below, and the photolithography process control device for the circuit lead hole described below and the photolithography process control method for the circuit lead hole described above can be referred to correspondingly.
Based on any of the above embodiments, fig. 6 is a schematic structural diagram of a control device for a photolithography process of a circuit lead hole according to the present application, as shown in fig. 6, the device includes:
A first photolithography control unit 201, configured to control corresponding photolithography process related equipment based on a first wire hole photolithography process sub-process to perform a first wire hole photolithography on the silicon wafer to be processed to obtain a pre-processed silicon wafer having a plurality of wire holes with a first depth; the silicon wafer to be processed is a silicon wafer to be subjected to a lead hole photoetching process, and comprises an N-type substrate, an N-type epitaxial layer and an oxide layer, wherein the oxide layer comprises a first sub-oxide layer formed by high-temperature silicon dioxide and a second sub-oxide layer formed by low-temperature silicon dioxide, and the N-type substrate, the N-type epitaxial layer, the first sub-oxide layer and the second sub-oxide layer are sequentially and tightly arranged from bottom to top;
And the second lithography control unit 202 is configured to control the corresponding lithography process related equipment to perform second lead hole lithography on the pre-processed silicon wafer based on the second lead hole lithography process sub-flow to obtain a processed silicon wafer with a plurality of lead holes with target depths.
The device provided by the embodiment of the application comprises: a first photolithography control unit 201, configured to control corresponding photolithography process related equipment based on a first wire hole photolithography process sub-process to perform a first wire hole photolithography on the silicon wafer to be processed to obtain a pre-processed silicon wafer having a plurality of wire holes with a first depth; the silicon wafer to be processed is a silicon wafer to be subjected to a lead hole photoetching process, and comprises an N-type substrate, an N-type epitaxial layer and an oxide layer, wherein the oxide layer comprises a first sub-oxide layer formed by high-temperature silicon dioxide and a second sub-oxide layer formed by low-temperature silicon dioxide, and the N-type substrate, the N-type epitaxial layer, the first sub-oxide layer and the second sub-oxide layer are sequentially and tightly arranged from bottom to top; and the second photolithography control unit 202 is configured to control corresponding photolithography process related equipment based on a second photolithography process sub-process to perform second time photolithography on the pre-processed silicon wafer to obtain a processed silicon wafer with a plurality of lead holes with target depths, and perform layer-by-layer etching on the oxide layer and remove the residual part through two photolithography processes, so that the problem of lateral over-etching of the oxide layer caused by inconsistent etching rates of the oxide layer in the circuit lead hole photolithography process is avoided, and further, the influence on electrical parameters of the lead holes is avoided.
Based on the above embodiment, the first and second sub-processes of the lead hole lithography process each include a plurality of process node indication information sequentially arranged in time sequence, and each process node indication information includes a corresponding process node identifier and a process parameter index.
Based on any one of the above embodiments, the process nodes corresponding to the first lead hole lithography process sub-process include a first glue spreading node, a first pre-baking node, a first exposure node, a first developing node, a first hardening node, a first etching node, and a first photoresist removing node, which are sequentially arranged in time sequence;
The process nodes corresponding to the second lead hole photoetching process sub-flow comprise a second gluing node, a second pre-baking node, a second exposure node, a second developing node, a second hardening node, a second corrosion node, a third corrosion node and a second photoresist removing node which are sequentially arranged in time sequence;
The first etching nodes are used for etching the second sub-oxide layer, the second etching nodes are used for etching the first sub-oxide layer, and the third etching nodes are used for etching the residual parts of the first sub-oxide layer and the second sub-oxide layer in the lead holes.
Based on any of the above embodiments, the first depth is a thickness of the second sub-oxide layer, and the target depth is a sum of thicknesses of the first sub-oxide layer and the second sub-oxide layer.
Based on any one of the above embodiments, the controlling the corresponding photolithography process association equipment based on the first wire hole photolithography process sub-process to perform the first wire hole photolithography on the silicon wafer to be processed specifically includes:
determining a plurality of process node indication information corresponding to the first lead hole lithography based on the first lead hole lithography process sub-flow;
Determining photoetching process related equipment corresponding to each process node and a control instruction sequence of each photoetching process related equipment based on a plurality of process node indication information corresponding to the first lead hole photoetching;
and sequentially sending a control instruction sequence to corresponding photoetching process related equipment based on the time sequence so as to control the photoetching process related equipment to carry out first lead hole photoetching on the silicon wafer to be processed.
Based on any one of the above embodiments, the determining, based on the plurality of process node indication information corresponding to the first lead hole lithography, a lithography process association device corresponding to each process node and a control instruction sequence of each lithography process association device specifically includes:
Determining a process node identifier and a process parameter index corresponding to each process node based on a plurality of process node indication information corresponding to the first lead hole lithography;
Corresponding photoetching process related equipment is determined based on the process node identifiers corresponding to the process nodes, and a control instruction sequence of the photoetching process related equipment is generated based on the process parameter indexes corresponding to the process nodes.
Based on any one of the above embodiments, the first corrosion node and the second corrosion node are both wet-etched, the corresponding technological parameter indexes include corrosion time and corrosion temperature, and the third corrosion node is dry-etched, and the corresponding technological parameter indexes include corrosion time, corrosion temperature and corrosion pressure;
wherein the first etching time and the first etching temperature corresponding to the first etching node are determined based on the thickness and the etching speed of the second sub-oxide layer; the second etching time and the second etching temperature corresponding to the second etching node are determined based on the thickness and the etching speed of the first sub-oxide layer; the third etching time, the third etching temperature and the first etching pressure corresponding to the third etching node are determined based on the thicknesses and the etching speeds of the residual portions of the first sub-oxide layer and the second sub-oxide layer.
Fig. 7 illustrates a physical schematic diagram of an electronic device, as shown in fig. 7, which may include: processor 301, communication interface (Communications Interface) 302, memory 303, and communication bus 304, wherein processor 301, communication interface 302, and memory 303 communicate with each other via communication bus 304. The processor 301 may invoke logic instructions in the memory 303 to perform the lithography process control method for the circuit lead hole provided by the methods described above, the method comprising: controlling corresponding photoetching process associated equipment based on a first lead hole photoetching process sub-process to carry out first lead hole photoetching on the silicon wafer to be processed so as to obtain a pre-processed silicon wafer with a plurality of lead holes with first depths; the silicon wafer to be processed is a silicon wafer to be subjected to a lead hole photoetching process, and comprises an N-type substrate, an N-type epitaxial layer and an oxide layer, wherein the oxide layer comprises a first sub-oxide layer formed by high-temperature silicon dioxide and a second sub-oxide layer formed by low-temperature silicon dioxide, and the N-type substrate, the N-type epitaxial layer, the first sub-oxide layer and the second sub-oxide layer are sequentially and tightly arranged from bottom to top; and controlling corresponding photoetching process related equipment based on a second lead hole photoetching process sub-process to carry out secondary lead hole photoetching on the pre-processed silicon wafer so as to obtain a processed silicon wafer with a plurality of lead holes with target depths.
Further, the logic instructions in the memory 303 may be implemented in the form of software functional units and stored in a computer readable storage medium when sold or used as a stand alone product. Based on this understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
In another aspect, the present application also provides a computer program product, the computer program product including a computer program, the computer program being storable on a non-transitory computer readable storage medium, the computer program, when executed by a processor, being capable of executing a method for controlling a lithography process of a circuit lead hole provided by the above methods, the method comprising: controlling corresponding photoetching process associated equipment based on a first lead hole photoetching process sub-process to carry out first lead hole photoetching on the silicon wafer to be processed so as to obtain a pre-processed silicon wafer with a plurality of lead holes with first depths; the silicon wafer to be processed is a silicon wafer to be subjected to a lead hole photoetching process, and comprises an N-type substrate, an N-type epitaxial layer and an oxide layer, wherein the oxide layer comprises a first sub-oxide layer formed by high-temperature silicon dioxide and a second sub-oxide layer formed by low-temperature silicon dioxide, and the N-type substrate, the N-type epitaxial layer, the first sub-oxide layer and the second sub-oxide layer are sequentially and tightly arranged from bottom to top; and controlling corresponding photoetching process related equipment based on a second lead hole photoetching process sub-process to carry out secondary lead hole photoetching on the pre-processed silicon wafer so as to obtain a processed silicon wafer with a plurality of lead holes with target depths.
In yet another aspect, the present application also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, is implemented to perform a method of controlling a lithography process of a circuit lead hole provided by the above methods, the method comprising: controlling corresponding photoetching process associated equipment based on a first lead hole photoetching process sub-process to carry out first lead hole photoetching on the silicon wafer to be processed so as to obtain a pre-processed silicon wafer with a plurality of lead holes with first depths; the silicon wafer to be processed is a silicon wafer to be subjected to a lead hole photoetching process, and comprises an N-type substrate, an N-type epitaxial layer and an oxide layer, wherein the oxide layer comprises a first sub-oxide layer formed by high-temperature silicon dioxide and a second sub-oxide layer formed by low-temperature silicon dioxide, and the N-type substrate, the N-type epitaxial layer, the first sub-oxide layer and the second sub-oxide layer are sequentially and tightly arranged from bottom to top; and controlling corresponding photoetching process related equipment based on a second lead hole photoetching process sub-process to carry out secondary lead hole photoetching on the pre-processed silicon wafer so as to obtain a processed silicon wafer with a plurality of lead holes with target depths.
The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
From the above description of the embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus necessary general hardware platforms, or of course may be implemented by means of hardware. Based on this understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method described in the respective embodiments or some parts of the embodiments.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application.