Disclosure of Invention
In order to solve the technical problems, the invention provides a testing method of a field effect transistor to solve the existing problems.
The test method of the field effect transistor adopts the following technical scheme:
One embodiment of the invention provides a method for testing a field effect transistor, which comprises the following steps:
Collecting the current of the grid electrode and the drain electrode of the field effect transistor at each time point, and the grid source voltage and the drain source voltage, and constructing a local grid source voltage sequence, a local drain source voltage sequence, a local grid current sequence and a local drain current sequence at each time point;
Obtaining inductance disturbance drain current factors of each drain current in the local drain current sequence of each time point according to the relation between each drain current in the local drain current sequence of each time point; obtaining the voltage-current ratio of the local drain current sequence and each time point in the local drain-source voltage sequence according to the local drain current sequence and the local drain-source voltage sequence of each time point; obtaining a drain-source voltage-current ratio stable index of each drain-source voltage in the local drain-source voltage sequence of each time point according to the voltage-current ratio; constructing an inductance voltage-current ratio intensity index at each time point according to the voltage-current ratio, the drain-source voltage-current ratio stability index and the inductance disturbance drain current factor; obtaining a local drain current residual contribution rate sequence and a local gate current residual contribution rate sequence of each time point according to the local drain current sequence and the local gate current sequence of the time point; constructing drain gate current residual variation indexes of all time points according to the inductance voltage-current ratio intensity indexes of all time points and the differences between elements in the local drain current residual contribution rate sequence and the local gate current residual contribution rate sequence; obtaining residual correction inductance factors of all time points according to the inductance voltage-current ratio intensity index and the drain gate current residual variation index of all time points;
and (3) obtaining the grid current, the drain current, the grid source voltage and the drain source voltage after correction and compensation at each time point by using the inductance-voltage-current ratio intensity index, the residual error correction inductance factor, the currents of the grid electrode and the drain electrode and the grid source and drain source voltages at each time point, and testing the field effect transistor.
Preferably, the constructing the local gate-source voltage sequence, the local drain-source voltage sequence, the local gate current sequence, and the local drain current sequence at each time point includes:
And for each time point, respectively taking a sequence formed by gate-source voltage, drain-source voltage, gate current and drain current of a preset number of time points before each time point as a local gate-source voltage sequence, a local drain-source voltage sequence, a local gate current sequence and a local drain current sequence of each time point, wherein when the number of time points before each time point is less than the preset number, elements in the sequence are filled by a regression filling method.
Preferably, the inductance disturbance drain current factor of each drain current in the local drain current sequence at each time point is obtained according to the relationship between each drain current in the local drain current sequence at each time point, and the expression is:
，
in the method, in the process of the invention,The inductance of the d-th drain current in the sequence of local drain currents representing the a-th point in time perturbs the drain current factor,、、Respectively represent the (d-1) th, the (d) th and the (d+1) th drain currents in the local drain current sequence,Representing an exponential reconciliation factor of 1 or greater.
Preferably, the obtaining the voltage-current ratio of the local drain current sequence and the local drain-source voltage sequence at each time point according to the local drain current sequence and the local drain-source voltage sequence at each time point includes:
For each time point, calculating the absolute value of the difference value between each drain-source voltage and the previous drain-source voltage in the local drain-source voltage sequence of the time point a, recording the absolute value as a first absolute value, calculating the absolute value of the difference value between each drain current and the previous drain current in the local drain current of the time point a, recording the absolute value as a second absolute value, obtaining the sum value of the second absolute value and a preset value larger than zero, and taking the ratio of the first absolute value to the sum value as the voltage-current ratio of each time point in the local drain current sequence and the local drain-source voltage sequence of the time point a.
Preferably, the obtaining the drain-to-source voltage ratio stability index of each drain-to-source voltage in the local drain-to-source voltage sequence at each time point according to the voltage-to-current ratio includes:
and for the d-th drain-source voltage in the local drain-source voltage sequence of each time point, calculating the voltage-current ratio of the local drain current sequence of each time point to the d-th time point in the local drain-source voltage sequence, subtracting the absolute value of the difference value of the voltage-current ratio of the (d-1) time point, marking the absolute value as a third absolute value, taking the third absolute value as an independent variable of a sigmoid function, and taking the function value of the sigmoid function as the drain-source voltage-current ratio stability index of the d-th drain-source voltage in the local drain-source voltage sequence of each time point.
Preferably, the inductance-voltage-current ratio strength index at each time point is expressed as follows:
，
in the method, in the process of the invention,Indicating the inductance-to-voltage ratio strength index at time a, b indicating the length of the local drain current sequence,The inductance of the d-th drain current in the sequence of local drain currents representing the a-th point in time perturbs the drain current factor,、The (d-1) th and the d-th gate-source voltages in the local gate-source voltage sequence at the a-th time point respectively,、Local gate-source voltage sequences at time points a respectivelyWith local gate current sequenceThe pressure-flow ratio of the d-th and (d-1) -th time points.
Preferably, the local drain current residual contribution rate sequence and the local gate current residual contribution rate sequence at each time point include:
Regarding the local drain current sequence of each time point, taking the local drain current sequence as the input of an STL decomposition algorithm to obtain a residual term of the local drain current sequence;
Taking the ratio of the absolute value of the residual value of each time point in the local drain current sequence to the drain current of each time point in the local drain current sequence as the residual contribution rate of each time point in the local drain current sequence, and forming a local drain current residual contribution rate sequence by the residual contribution rates of all time points in the local drain current sequence;
and for the local grid current sequence, constructing the local grid current residual contribution rate sequence by adopting an acquisition method of the local drain current residual contribution rate sequence.
Preferably, the drain gate current residual variation index at each time point has the following expression:
，
in the method, in the process of the invention,A drain gate current residual variation index at a time point, b represents the length of the local drain current sequence,The inductor current ratio strength index of the time point corresponding to the c-th drain current in the local drain current sequence of the a-th time point is shown,、The values of the c-th and (c-1) -th elements in the local drain current residual contribution rate sequence at the a-th time point are respectively shown,、The values of the c-th and (c-1) -th elements in the partial gate current residual contribution rate sequence at the a-th time point are respectively represented.
Preferably, the obtaining the residual correction inductance factor of each time point according to the inductance voltage-current ratio intensity index and the drain gate current residual variation index of each time point includes:
And taking the product of the inductance voltage-current ratio intensity index and the drain gate current residual variation index at each time point as the residual correction inductance factor at each time point.
Preferably, the gate current, the drain current, the gate-source voltage and the drain-source voltage after the correction and compensation at each time point include:
Calculating standard deviations of all elements in a local gate-source voltage sequence, a local drain-source voltage sequence, a local gate current sequence and a local drain current sequence at each time point respectively, and forming an inductance-voltage-current ratio intensity index, a residual error correction inductance factor and four standard deviations at each time point into feature vectors at each time point;
And taking the characteristic vector of each time point and the grid current, the drain current, the grid source voltage and the drain source voltage of each time point as inputs of the RNN circulating neural network, and outputting the grid current, the drain current, the grid source voltage and the drain source voltage which are subjected to calibration compensation at each time point.
The invention has at least the following beneficial effects:
According to the invention, the influence characteristics of the inductor on the drain current are analyzed to construct an inductor disturbance drain current factor, and the influence degree of the inductor current time point circuit at the historical time point is reflected through the change of the drain current; analyzing the change rule characteristics of voltage and current in the MOSFET testing process, and constructing an inductance voltage-current ratio strength index by combining an inductance disturbance drain current factor to reflect the degree of inductance existing at the current time point; according to the change characteristics of drain current and gate current, analyzing the degree of noise existing in a circuit at each time point in the MOSFET testing process, and correcting the inductance voltage-current ratio intensity index to enable the subsequent calibration compensation of data to be more accurate; and constructing a characteristic vector based on the inductance-voltage-current ratio intensity index and the residual error correction inductance factor, calibrating and compensating original voltage and current data through an RNN (RNN-cycle neural network), testing the field effect transistor according to the calibrated and compensated data, obtaining more accurate source-drain breakdown voltage, and improving the testing precision.
Detailed Description
In order to further describe the technical means and effects adopted by the invention to achieve the preset aim, the following is a detailed description of specific implementation, structure, characteristics and effects of a field effect transistor according to the invention in combination with the accompanying drawings and preferred embodiments. In the following description, different "one embodiment" or "another embodiment" means that the embodiments are not necessarily the same. Furthermore, the particular features, structures, or characteristics of one or more embodiments may be combined in any suitable manner.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.
The following specifically describes a specific scheme of the testing method of the field effect transistor provided by the invention with reference to the accompanying drawings.
The present invention provides a method for testing a field effect transistor, and in particular, provides a method for testing a field effect transistor, referring to fig. 1, the method includes the following steps:
and S001, collecting voltage and current data in the MOSFET testing process and preprocessing.
Because the metal oxide field effect Transistor (Metal Oxide Semiconductor FIELD EFFECT Transistor, MOSFET) has the characteristics of simple manufacturing process, high integration level and the like, the metal oxide field effect Transistor is widely applied to electronic equipment, and the embodiment takes the source-drain breakdown voltage test of the MOSFET as an example for analysis.
The current passing through the grid electrode and the drain electrode of the MOSFET is collected through the current sensor, and the grid electrode-source electrode voltage and the drain electrode-source electrode voltage of the MOSFET are collected through the voltage sensor and are respectively recorded as the grid source voltage and the drain source voltage, the collection interval is recorded as A, the collection time is recorded as 0.1s, the collection times is recorded as B, and the collection time is recorded as 600.
In order to avoid the influence of the missing value on subsequent calculation, the embodiment uses a regression filling method to fill the missing value, and meanwhile uses a Z-score normalization method to normalize the acquired data in order to avoid the influence of different dimensions on subsequent calculation results. The regression filling method and the Z-score normalization method are known techniques, and the specific process is not described in detail in this embodiment.
Step S002, constructing an inductance disturbance drain current factor, calculating an inductance voltage-current ratio intensity index based on the change characteristics of the inductance disturbance drain current factor analysis voltage and the current transformation, constructing a residual error correction inductance factor to correct the inductance voltage-current ratio intensity index, and constructing a feature vector based on the inductance voltage-current ratio intensity index and the residual error correction inductance factor.
First, the present embodiment will combine the inductance characteristics to construct an inductance disturbance drain current factor.
When the current passing through one wire or coil changes, a magnetic field is generated, the intensity and the direction of the magnetic field are related to the rate of current change, then the magnetic field can be obtained according to Faraday's law of electromagnetic induction, a changing magnetic field generates inductance in the wire to block the change of current, so that the current change tends to be slow, and the blocking degree is related to the length of the wire, since the grid electrode and the source electrode are both positioned on the front side of the field effect tube, the drain electrode is positioned on the back side of the field effect tube, the wire between the drain electrode and the source electrode is longer, the wire between the grid electrode and the source electrode is shorter, and the current between the drain electrode and the source electrode is relatively greatly influenced by the inductance; meanwhile, the inductance blocks the change of current through the storage and release of energy in the circuit, so that the longer the two time points are separated, the smaller the influence of the inductance generated by the former time point on the current and voltage of the latter time point is. Based on the analysis, the invention constructs the inductance disturbance drain current factor, reflects the influence of inductance in the MOSFET circuit on current, and constructs the inductance disturbance drain current factor as follows:
Taking the a-th time point as an example, the sequence formed by the drain currents of the first b time points of the a-th time point is recorded as a local drain current sequence, and the value of b in the embodiment is 10, so that the operator can set the sequence by himself. If the a-th time point is at the beginning of data acquisition, that is, the number of time points before the time point is less than b, filling insufficient data by a regression filling method to make the length of the obtained local sequence be b, wherein the regression filling method is a known technology, and the specific process is not repeated. Then an inductance disturbance drain current factor can be constructed, the calculation formula of which is as follows:
，
in the method, in the process of the invention,The inductance of the d-th drain current in the sequence of local drain currents representing the a-th point in time perturbs the drain current factor,、、The values of the (d-1) th, d-th and (d+1) th elements in the local drain current sequence are respectively represented,The exponent harmonic factor is used for enabling the base part of the exponent function to be greater than or equal to 1, so that the exponent function is an increasing function, and the value of the exponent harmonic factor is 1 in the embodiment, and an implementer can set the exponent harmonic factor by himself;
the larger the difference between adjacent two elements in the local drain current sequence, i.e、The larger the drain current changes, the larger the drain current changes in a shorter time, the more likely the inductance appears in the lead between the drain and the source of the field effect transistor according to Faraday electromagnetic induction law, meanwhile, the closer the time point of the larger drain current changes to the a-th time point, namely, the larger d is, the greater the degree of obstruction of the generated inductance to the current at the a-th time point is, so that the calculated inductance disturbance drain current factor is greater.
Then, the embodiment constructs an inductance-to-voltage ratio strength index according to the inductance disturbance drain current factor.
The drain current factor is disturbed by the inductance of each time point obtained through the steps, the blocking degree of the inductance of each time point to the current is reflected, and the voltage and the current in the circuit show a linear relation when the rest conditions are unchanged, and the voltage and the current can possibly show a nonlinear relation after the current is influenced by the inductance. Based on the analysis, the invention constructs the inductance-voltage-current ratio intensity index based on the inductance disturbance drain current factor, reflects the inductance intensity of the drain in the circuit in the process of testing the MOSFET, and constructs the inductance-voltage-current ratio intensity index as follows:
Similarly, for the a-th time point, the sequence formed by the gate-source voltage, the drain-source voltage and the gate current at the b time points before the a-th time point is respectively marked as a local gate-source voltage sequence, a local drain-source voltage sequence and a local gate current sequence, wherein each element in the sequence corresponds to one time point. If the a-th time point is at the beginning of data acquisition, and the number of time points before the time point is less than b, the insufficient data is complemented by a regression filling method to make the length of the obtained sequence be b, wherein the regression filling method is a known technology, and the specific process is not repeated. The inductive piezoelectric flow ratio intensity index can be calculated as follows:
，
，
，
Wherein,The voltage-to-current ratio of the local drain current sequence at the a-th time point to the d-th time point in the local drain-to-source voltage sequence is shown,、Respectively representing a local drain current sequence and a local drain source voltage sequence at a time point a,、Respectively represent the (d-1) th and the (d) th drain currents in the local drain current sequence,、Respectively represent the (d-1) th and the (d) th drain-source voltages in the local drain-source voltage sequence,The value which is larger than zero is preset, so that the situation that the calculation cannot be performed due to the fact that the denominator is 0 is avoided, and the value is 0.01 in the embodiment;
Drain-to-source voltage ratio stability index of the d-th drain-to-source voltage in the local drain-to-source voltage sequence representing the a-th time point, sig () represents a sigmoid function for identifying a minute difference of data in the parentheses around 0;
The inductance-to-voltage ratio strength index at time a, b, the length of the local drain current sequence, in this example a value of 10,The inductance of the d-th drain current in the sequence of local drain currents representing the a-th point in time perturbs the drain current factor,、The (d-1) th and the (d) th gate-source voltages in the local gate-source voltage sequence at the a-th time point are respectively expressed,、Respectively representing the voltage-to-current ratio of the local gate-source voltage sequence at the a-th time point to the d-th and (d-1) -th time points in the local gate current sequence,、The partial gate-source voltage sequence and the partial gate current sequence at the a-th time point are respectively shown.
The larger the voltage and current changes at adjacent time points are not in line with the linear relation, namely the more likely the circuit is blocked by inductance, so that the calculated drain-source voltage-current ratio stability index is larger;
The smaller the difference between adjacent two elements in the local gate-source voltage sequence, i.eThe smaller the voltage-current ratio between two adjacent time points in the local gate-source voltage sequence and the local gate current sequence is, namelyThe smaller the grid and the source are, the shorter the wire connected with the grid and the source is, and the smaller the grid current is, the less the influence of inductance is on the wire connected with the grid and the source, so that the more likely no inductance interference occurs in the circuit, the more likely the change of the drain current is that the wire of the drain and the source is overlong, so that inductance occurs in the wire; meanwhile, the larger the inductance disturbance drain current factor, drain-source voltage-current ratio stability index of each time point is, namely、The larger the inductor interference appears in the lead wires of the drain electrode and the source electrode, the larger the calculated inductor voltage-current ratio strength index is.
Further, the embodiment constructs a residual correction inductance factor based on the inductance-to-voltage-current ratio intensity index.
The inductance-voltage-current ratio intensity index of each time point obtained through the steps reflects the possibility of inductance interference in the conducting wire of the drain electrode and the source electrode in the MOSFET at each time point, but because the current in the circuit is relatively small, noise can exist in drain current, gate-source voltage and drain-source voltage data acquired through the sensor, and the noise is usually a random and aperiodic interference signal and is different from the influence characteristic of the inductance on the current. Based on the analysis, the invention constructs the residual correction inductance factor, corrects the inductance-voltage-current ratio intensity index obtained in the steps, and constructs the residual correction inductance factor as follows:
Taking the local drain current sequence and the local gate current sequence at the a-th time point as the input of the STL decomposition algorithm and outputting trend terms, period terms and residual terms of the local drain current sequence and the local gate current sequence respectively, the residual contribution rate at each time point, specifically, the ratio of the absolute value of the residual value at each time point to the drain current, for example: the residual contribution rate of the a-th time point in the local drain current sequence is the ratio of the absolute value of the residual of the a-th time point to the drain current of the a-th time point, the sequence formed by the residual contribution rate of each element in the local drain current sequence and the local gate current sequence of the a-th time point is respectively recorded as a local drain current residual contribution rate sequence and a local gate current residual contribution rate sequence, and the local gate current residual contribution rate sequence is mainly a noise component because the wires of the current passing through the gate are short, and the local drain current residual contribution rate sequence contains the noise component and the component which is changed due to the influence of inductance, wherein the STL decomposition algorithm is a known technology, and the specific process is not repeated in the embodiment. Based on the above analysis, the residual correction inductance can be calculated as follows:
，
，
in the method, in the process of the invention,The drain gate current residual variation index at time point a is shown,The inductor current ratio strength index of the time point corresponding to the c-th drain current in the local drain current sequence of the a-th time point is shown,、The values of the c-th and (c-1) -th elements in the local drain current residual contribution rate sequence at the a-th time point are respectively shown,、The values of the c-th and (c-1) -th elements in the partial gate current residual contribution rate sequence at the a-th time point are respectively represented.
The residual correction inductance of the a-th time point is shown, the residual correction inductance extraction flow diagram of each time point is shown in figure 2,The induction-to-voltage flow ratio strength index at time point a is shown.
Since the local gate residual contribution rate sequence mainly contains noise components and components which change due to the influence of inductance, the ratio of the local drain current residual contribution rate to the local gate residual contribution rate at adjacent time points changes more, namelyThe larger the inductor voltage-current ratio strength index is, the more likely the inductor voltage-current ratio strength index is affected by noise, namelyThe smaller the influence of inductance is, the less the influence is in the circuit, namely the influence is mainly noise, so the larger the calculated drain gate current residual variation index is;
The larger the drain-gate current residual variation index at the a-th time point is, namelyThe larger the inductor voltage-current ratio intensity index is, the larger the inductor voltage-current ratio intensity index is required to be corrected, and the larger the calculated residual correction inductance factor is.
Finally, the present embodiment constructs a feature vector based on the inductance-to-voltage-current ratio intensity index and the residual correction inductance factor.
The inductance-voltage-current ratio intensity index and residual correction inductance factor of each time point obtained through the steps respectively reflect the degree of inductance in a circuit and the degree of influence of noise on voltage and current when testing the MOSFET, and then the characteristic vector of each time point can be constructed and can be specifically expressed as the following form:
，
Wherein the method comprises the steps ofA feature vector representing the a-th point in time,The induction-to-voltage flow ratio strength index at time point a is shown,The residual correction inductance factor representing the a-th point in time,、、、The standard deviation of all elements in the local gate-source voltage sequence, the local drain-source voltage sequence, the local gate current sequence and the local drain current sequence at the a time point are respectively shown.
And step S003, based on the feature vector and the original data of each time point, calibrating and compensating the original data through the RNN cyclic neural network, and testing the field effect tube according to the calibrated and compensated data.
Based on the feature vector of each time point obtained in the above step, and the gate current, the drain current, the gate source voltage and the drain source voltage of each time point as the input of the RNN cyclic neural network, adam is used as an optimization algorithm, root mean square error MSE is used as a loss function, and the gate current, the drain current, the gate source voltage and the drain source voltage after calibration compensation of each time point are output, then the field effect transistor can be tested based on the data after calibration compensation, specifically, a numerical control constant voltage source is used as a power supply, the voltage with the step length of 1V is gradually applied from 0 voltage, the drain current change after calibration compensation is detected, when the drain current changes from linear change to exponential change along with the voltage, the source-drain breakdown voltage is indicated to be reached at this time, and the accurate source-drain breakdown voltage test result of the field effect transistor is obtained. The RNN recurrent neural network is a known technology, and the specific process of this embodiment is not described in detail.
It should be noted that: the sequence of the embodiments of the present invention is only for description, and does not represent the advantages and disadvantages of the embodiments. And the foregoing description has been directed to specific embodiments of this specification. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
In this specification, each embodiment is described in a progressive manner, and the same or similar parts of each embodiment are referred to each other, and each embodiment mainly describes differences from other embodiments.
The above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; the technical solutions described in the foregoing embodiments are modified or some of the technical features are replaced equivalently, so that the essence of the corresponding technical solutions does not deviate from the scope of the technical solutions of the embodiments of the present application, and all the technical solutions are included in the protection scope of the present application.