Detailed Description
The same reference indicators will be used throughout the drawings and the detailed description to refer to the same or like parts. Embodiments of the present invention will be readily understood from the following detailed description in conjunction with the accompanying drawings.
Spatial descriptions such as "upper," "lower," "left," "right," "top," "bottom," "vertical," "horizontal," "side," "upper," "lower," etc., are intended to be relative to a certain component or group of components, or a plane of a component or group of components, for the orientation of the components shown in the figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and that specific implementations of the structures described herein may be spatially arranged in any orientation or manner without departing from the spirit of the present invention.
Further, it should be noted that, subject to device manufacturing conditions, in an actual device, the actual shape of the various structures depicted as being approximately rectangular may be curved, or have rounded corners, or have a slightly non-uniform thickness, etc. Straight lines and right angles are only used to facilitate the presentation of layers and features.
In the following description, a semiconductor device/die/package and a method for manufacturing the same are set forth as preferred examples. It will be apparent that modifications, including additions and/or substitutions, may be made without departing from the scope and spirit of the invention. Specific details may be omitted to avoid obscuring. However, the present invention was written in order to enable any person skilled in the art to practice the teachings thereof without undue experimentation.
Fig. 1 is a vertical cross-sectional view of a nitride-based semiconductor device 1A according to some embodiments of the present invention. The nitride-based semiconductor device 1A includes a substrate 10, a buffer layer 12, nitride-based semiconductor layers 14, 16, a doped III-V semiconductor layer 20, a gate 22, n-type doped nitride-based semiconductor layers 30, 32, p-type doped nitride-based semiconductor layers 34, 36, electrodes 40, 42, and a passivation layer 50.
The substrate 10 may be a semiconductor substrate. Exemplary materials for substrate 10 may include, but are not limited to, si, siGe, siC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor-on-insulator (e.g., silicon-on-insulator (SOI)) or other suitable substrate materials. In some embodiments, the substrate 10 may include, but is not limited to, a group III element, a group IV element, a group V element, or a combination thereof (e.g., a III-V compound). In other embodiments, the substrate 10 may include, but is not limited to, one or more other features, such as doped regions, buried layers, epitaxial (epi) layers, or combinations thereof.
The buffer layer 12 is disposed between the substrate 10 and the nitride-based semiconductor layer 16. The buffer layer 12 is configured to reduce lattice and thermal mismatch between the substrate 10 and the nitride-based semiconductor layer 14, thereby overcoming defects caused by mismatch/difference. Buffer layer 12 may include a III-V compound. The III-V compounds may include, but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Accordingly, exemplary materials for buffer layer 12 may further include, but are not limited to GaN, alN, alGaN, inAlGaN or combinations thereof.
In some embodiments, the semiconductor device 1A may further include a nucleation layer (not shown). A nucleation layer may be formed between the substrate 10 and the buffer layer 12. The nucleation layer is configured to provide a transition to accommodate the mismatch/difference between the III-nitride layers of the substrate 10 and the buffer layer 12. Exemplary materials for the nucleation layer may include, but are not limited to, alN or any alloy thereof.
A nitride-based semiconductor layer 14 may be disposed on the buffer layer 12. The nitride-based semiconductor layer 16 may be disposed on the nitride-based semiconductor layer 14. Exemplary materials for nitride-based semiconductor layer 14 may include, but are not limited to, nitrides or III-V compounds, such as GaN, alN, inN, inxAlyGa(1-x-y) N (x+y.ltoreq.1), or AlxGa(1-x) N (x.ltoreq.1). Exemplary materials for nitride-based semiconductor layer 16 may include, but are not limited to, nitrides or III-V compounds, such as GaN, alN, inxAlyGa(1-x-y) N (x+y.ltoreq.1), or AlyGa(1-y) N (y.ltoreq.1).
The exemplary materials of the nitride-based semiconductor layers 14 and 16 are selected such that the band gap (i.e., the forbidden band width) of the nitride-based semiconductor layer 16 is greater than the band gap of the nitride-based semiconductor layer 14, thereby making their electron affinities different from each other and forming a heterojunction therebetween. For example, when nitride-based semiconductor layer 14 is an undoped GaN layer having a bandgap of about 3.4eV, nitride-based semiconductor layer 16 may be selected to be a GaN layer having a bandgap of about 4.0 eV. In this way, the nitride-based semiconductor layers 14 and 16 may function as a channel layer and a barrier layer, respectively. A triangular trap potential is generated at the bonding interface between the channel and the barrier layer such that electrons accumulate in the triangular trap, thereby creating a two-dimensional electron gas (2 DEG) region 15 adjacent to or along the heterojunction. Accordingly, the semiconductor device 1A can be used for a High Electron Mobility Transistor (HEMT) including at least one GaN group.
Further, the nitride-based semiconductor layer 14 has a portion 142 and a portion 144 connected to the portion 142. Portion 142 is surrounded by portion 144. The thickness T1 of portion 142 is greater than the thickness T2 of portion 144. The nitride-based semiconductor layer 16 on the nitride-based semiconductor layer 14 may be confined within the portion 144 of the nitride-based semiconductor layer 14.
A doped III-V semiconductor layer 20 is disposed on the nitride-based semiconductor layer 16. The doped III-V semiconductor layer 20 may be in contact with the nitride-based semiconductor layer 16. The nitride-based semiconductor device 1A enters an enhancement mode through the doped III-V semiconductor layer 20. The doped III-V semiconductor layer 20 may be a p-type doped III-V semiconductor layer. Exemplary materials for the p-doped III-V semiconductor layer may include, but are not limited to, p-doped III-V nitride semiconductor materials such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof. In some embodiments, the p-doped material is achieved by using p-type impurities (e.g., be, zn, cd, and Mg).
A gate 22 is disposed on the doped III-V semiconductor layer 20. The gate 22 may be formed as a single layer, or as multiple layers of the same or different composition. Exemplary materials for the metal or metal compound may include, but are not limited to, W, au, pd, ti, ta, co, ni, pt, mo, tiN, taN, metal alloys or compounds thereof, or other metal compounds.
N-type doped nitride-based semiconductor layers 30 and 32 are disposed on portion 144 of nitride-based semiconductor layer 14. A portion 142 of nitride-based semiconductor layer 14 is located between n-doped nitride-based semiconductor layers 30 and 32. The conductivity types of the n-type doped nitride-based semiconductor layers 30 and 32 include "n+", "n-" and "n". The n+ doped portion has a higher doping concentration than the n doped portion; and the n-doped portion has a higher doping concentration than the n-doped portion. In some embodiments, n-type doped nitride-based semiconductor layers 30 and 32 may be n+ doped III-V semiconductor layers. Exemplary materials for n-doped nitride-based semiconductor layers 30 and 32 may include, but are not limited to, n-doped group III-V nitride semiconductor materials such as n-type GaN, n-type AlGaN, n-type InN, n-type AlInN, n-type InGaN, n-type AlInGaN, or combinations thereof. In some embodiments, the n-doped material is implemented by using n-type impurities such as Si, C, ge, se, and Te. The n-doped nitride-based semiconductor layers 30 and 32 are configured to improve the contact resistance of the conductor relative to the semiconductor.
N-type doped nitride-based semiconductor layers 30 and 32 may abut nitride-based semiconductor layers 14 and 16. For example, the portion 142 of the nitride-based semiconductor layer 14 may extend horizontally to abut side surfaces of the n-type doped nitride-based semiconductor layers 30 and 32. n-type doped nitride-based semiconductor layers 30 and 32 are connected to nitride-based semiconductor layers 14 and 16. The n-type doped nitride-based semiconductor layers 30 and 32 may extend vertically from the portion 144 of the nitride-based semiconductor layer 14 to a position above the interface between the nitride-based semiconductor layers 14 and 16.
P-type doped nitride-based semiconductor layers 34 and 36 are disposed on n-type doped nitride-based semiconductor layers 30 and 32, respectively. The p-type doped nitride-based semiconductor layers 34 and 36 may be in contact with the n-type doped nitride-based semiconductor layers 30 and 32, respectively. The p-doped nitride-based semiconductor layers 34 and 36 are located entirely above the nitride-based semiconductor layers 14 and 16. The n-type doped nitride-based semiconductor layers 30 and 32 may form interfaces with the p-type doped nitride-based semiconductor layers 34 and 36, respectively, at locations above the interface between the nitride-based semiconductor layers 14 and 16. In some embodiments, the thickness of n-type doped nitride-based semiconductor layers 30 and 32 is greater than the thickness of p-type doped nitride-based semiconductor layers 34 and 36.
In some embodiments, the doping concentration of each of n-type doped nitride-based semiconductor layers 30 and 32 is greater than the doping concentration of each of p-type doped nitride-based semiconductor layers 34 and 36. For example, n-type doped nitride-based semiconductor layers 30 and 32 may be used as "n+" nitride-based semiconductor layers, while p-type doped nitride-based semiconductor layers 34 and 36 may be used as "p" -nitride-based semiconductor layers.
Exemplary materials for p-type doped nitride-based semiconductor layers 34 and 36 may include, but are not limited to, p-type doped group III-V nitride semiconductor materials such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof. In some embodiments, the p-doped material is achieved by using p-type impurities (e.g., be, zn, cd, and Mg). In some embodiments, doped III-V semiconductor layer 20 and p-type doped nitride-based semiconductor layers 34 and 36 have the same material. In some embodiments, doped III-V semiconductor layer 20 and p-type doped nitride-based semiconductor layers 34 and 36 are formed by patterning a single blanket p-type doped nitride-based semiconductor layer.
The electrode 40 is disposed on the n-type doped nitride-based semiconductor layer 30 and the p-type doped nitride-based semiconductor layer 34. The electrode 40 may pass through the p-type doped nitride-based semiconductor layer 34 to contact the n-type doped nitride-based semiconductor layer 30. The electrode 40 may extend downward such that a bottom surface of the electrode 40 is lower than a bottom surface of the p-type doped nitride-based semiconductor layer 34. The bottom surface of the electrode 40 is within the thickness range of the n-type doped nitride-based semiconductor layer 30. The bottom surface of the electrode 40 is at a position higher than the nitride-based semiconductor layer 16. The electrode 40 has a side surface in contact with the inner side surfaces of the p-type doped semiconductor layer 34 and the n-type doped nitride-based semiconductor layer 30.
An electrode 42 is disposed on the n-type doped nitride-based semiconductor layer 32 and the p-type doped nitride-based semiconductor layer 36. The electrode 42 may pass through the p-type doped nitride-based semiconductor layer 36 to contact the n-type doped nitride-based semiconductor layer 32. The electrode 42 may extend downward such that a bottom surface of the electrode 42 is lower than a bottom surface of the p-type doped nitride-based semiconductor layer 36. The bottom surface of the electrode 42 is within the thickness range of the n-type doped nitride-based semiconductor layer 32. The bottom surface of the electrode 42 is at a position higher than the nitride-based semiconductor layer 16. The electrode 42 has a side surface in contact with the inside surfaces of the p-type doped semiconductor layer 36 and the n-type doped nitride-based semiconductor layer 32.
Each electrode 40 and 42 may function as a source or drain. For example, electrode 40 is a source and electrode 42 is a drain. In some embodiments, electrodes 40 and 42 may be referred to as ohmic electrodes. The electrodes 40, 42 and the gate 22 may constitute an enhancement HEMT.
In some embodiments, electrodes 40 and 42 may include, but are not limited to, metals, alloys, doped semiconductor materials (e.g., doped crystalline silicon), compounds such as silicides and nitrides, other conductor materials, or combinations thereof. Exemplary materials for electrodes 40 and 42 may include, but are not limited to, ti, alSi, tiN, or combinations thereof. The electrodes 40 and 42 may be single or multiple layers of the same or different composition. In some embodiments, electrodes 40 and 42 may form ohmic contacts with nitride-based semiconductor layer 16. Ohmic contact may be achieved by applying Ti, al or other suitable materials to electrodes 40 and 42.
In some embodiments, each electrode 40 and 42 is formed from at least one conformal layer and a conductive filler. The conformal layer may encapsulate the conductive filler. Exemplary materials for the conformal layer include, but are not limited to, ti, ta, tiN, al, au, alSi, ni, pt, or combinations thereof. Exemplary materials for the conductive filler may include, but are not limited to AlSi, alCu, or combinations thereof.
The p-type doped nitride-based semiconductor layers 34 and 36 may define carrier inlets for the electrodes 40 and 42. Electrodes 40 and 42 pass through p-type doped nitride-based semiconductor layers 34 and 36 to inject carriers into n-type doped nitride-based semiconductor layers 30 and 32. The sidewalls of the electrodes 40 and 42 adjacent to the top surfaces of the n-type doped nitride-based semiconductor layers 30 and 32 are covered by the p-type doped nitride-based semiconductor layers 34 and 36. The resistance of p-doped nitride-based semiconductor layers 34 and 36 may block leakage current from electrodes 40 and 42. In other cases, once the sidewalls of the electrode adjacent to the top surface of the n-doped nitride-based semiconductor layer are covered with a dielectric, interface defects between the electrode and the dielectric may cause leakage currents. In addition, due to the resistance of the p-type doped nitride-based semiconductor layers 34 and 36, the electrodes 40 and 42 need to pass completely through the p-type doped nitride-based semiconductor layers 34 and 36.
In addition, this structure is compatible with a process of forming the p-type doped nitride-based semiconductor layers 34 and 36 after forming the n-type doped nitride-based semiconductor layers 30 and 32. Accordingly, once the p-type doped nitride-based semiconductor layer is formed on the channel layer before the n-type doped nitride-based semiconductor layer is formed, dopants in the p-type doped nitride-based semiconductor layer may diffuse into the channel layer during the formation of the n-type doped nitride-based semiconductor layer, resulting in reduced channel mobility and carrier concentration.
A passivation layer 50 is disposed on the nitride-based semiconductor layer 16. The passivation layer 50 covers the n-type doped nitride-based semiconductor layers 30 and 32 and the p-type doped nitride-based semiconductor layers 34 and 36. Exemplary materials for passivation layer 50 may include, but are not limited to, siNx,SiOx,Si3N4, siON, siC, siBN, siCBN, oxides, nitrides, plasma Enhanced Oxides (PEOX), or combinations thereof. In some embodiments, the passivation layer 50 may be a multi-layer structure, such as a composite dielectric layer of Al2O3/SiN,Al2O3/SiO2,AlN/SiN,AlN/SiO2 or a combination thereof.
As described below, fig. 2A, 2B, 2C and 2D show different stages of a method for manufacturing the nitride-based semiconductor device 1A. Hereinafter, deposition techniques may include, but are not limited to, atomic Layer Deposition (ALD), physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), metal Organic CVD (MOCVD), plasma Enhanced CVD (PECVD), low Pressure CVD (LPCVD), plasma-assisted vapor deposition, epitaxial growth, or other processes.
Referring to fig. 2A, a buffer layer 12 is formed on a substrate 10. Nitride-based semiconductor layers 14 and 16 (i.e., a channel layer and a barrier layer) are formed on the buffer layer 12. The nitride-based semiconductor layer 14 has portions 142 and 144 as described above. n-type doped nitride-based semiconductor layers 30 and 32 are formed on portion 144 of nitride-based semiconductor layer 14. The formation of n-doped nitride-based semiconductor layers 30 and 32 includes epitaxial growth. Prior to epitaxial growth, a masking layer is provided to cover nitride-based semiconductor layer 16 and expose portions 144 of nitride-based semiconductor layer 14. Thus, the formation of n-doped nitride-based semiconductor layers 30 and 32 is selective epitaxial growth.
Referring to fig. 2B, a cap p-type doped nitride-based semiconductor layer 60 is formed to cap n-type doped nitride-based semiconductor layers 30 and 32 and nitride-based semiconductor layer 16.
Referring to fig. 2C, a patterning process is performed on the blanket p-type doped nitride-based semiconductor layer 60. Thus, at least a portion of the blanket p-doped nitride-based semiconductor layer 60 is removed. The patterning process may include at least one etching stage. After the patterning process, the doped nitride-based semiconductor layer 20 remains on the nitride-based semiconductor layer 16, and the p-type doped nitride-based semiconductor layers 34 and 36 remain on the n-type doped nitride-based semiconductor layers 30 and 32. In some embodiments, dopants in the p-type doped nitride-based semiconductor layers 34 and 36 may diffuse into the n-type doped nitride-based semiconductor layers 30 and 32 such that the thickness of the n-type doped nitride-based semiconductor layers 30 and 32 may vary. At least one n-type feature in portions of n-doped nitride-based semiconductor layers 30 and 32 may be weakened.
Since the formation of the n-type doped nitride-based semiconductor layers 30 and 32 precedes the formation of the doped nitride-based semiconductor layer 20 and the p-type doped nitride-based semiconductor layers 34 and 36, the risk that dopants in the p-type doped nitride-based semiconductor layers 34 and 36 may diffuse into the channel layer during the formation of the n-type doped nitride-based semiconductor layers 30 and 32 is small. In this way, potential degradation of channel mobility and carrier concentration is avoided.
Referring to fig. 2D, a passivation layer 50 is formed on the nitride-based semiconductor layer 16. Thereafter, a portion of passivation layer 50 is removed to expose p-type doped nitride-based semiconductor layers 34 and 36. A removal process is performed on the p-type doped nitride-based semiconductor layers 34 and 36 to form a via hole in the p-type doped nitride-based semiconductor layers 34 and 36. The removal process may include at least one etching stage. Since the n-type doped nitride-based semiconductor layers 30 and 32 and the p-type doped nitride-based semiconductor layers 34 and 36 have the same or similar materials, it is difficult to avoid removing the n-type doped nitride-based semiconductor layers 30 and 32 in the removal process. Accordingly, a portion of the n-type doped nitride-based semiconductor layers 30 and 32 is removed to form a recess in the n-type doped nitride-based semiconductor layers 30 and 32. Then, the electrode and the gate electrode as described above are formed, and the electrode is formed in the through-hole, thereby obtaining the structure shown in fig. 1.
Fig. 3 is a vertical cross-sectional view of a nitride-based semiconductor device 1B according to some embodiments of the present invention. The nitride-based semiconductor device 1B is similar to the nitride-based semiconductor device 1A in fig. 1, except that the nitride-based semiconductor device 1B has a double channel.
The nitride-based semiconductor device 1B includes III-V layers 70 and 72 disposed alternately with the stacked sub-portions SP1 and SP2 of the nitride-based semiconductor layer 14 in the vertical direction. The III-V layer 70 is located between the sub-portions SP1 and SP2 of the nitride-based semiconductor layer 14. The III-V layer 70 is in contact with the sub-portion SP1 of the nitride-based semiconductor layer 14 to form a heterojunction having the 2DEG region 15A therebetween. The III-V layer 72 is located between the subsection SP2 of the nitride-based semiconductor layer 14 and the nitride-based semiconductor layer 16. The III-V layer 72 is in contact with the nitride-based semiconductor layer 16 to form a heterojunction having the 2DEG region 15B therebetween. III-V layers 70 and 72 overlap the thickness ranges of n-type doped nitride-based semiconductor layers 30 and 32, thereby forming a double channel entirely between n-type doped nitride-based semiconductor layers 30 and 32. In some embodiments, each of III-V layers 70 and 72 includes an aluminum nitride layer. This configuration can be adapted to the requirements of the RF device.
Fig. 4 is a vertical cross-sectional view of a nitride-based semiconductor device 1C according to some embodiments of the present invention. The nitride-based semiconductor device 1C is similar to the nitride-based semiconductor device 1B in fig. 3, except that there is only one III-V layer 74. The III-V layer 74 is located between the sub-portions SP1 and SP2 of the nitride-based semiconductor layer 14. The III-V layer 74 is in contact with the sub-portion SP1 of the nitride-based semiconductor layer 14 to form a heterojunction having the 2DEG region 15C therebetween. The nitride-based semiconductor layer 16 may be in contact with the nitride-based semiconductor layer 14, thereby forming a heterojunction having a 2DEG region 15D therebetween. In some embodiments, the configuration may be achieved by adjusting the band gap of the materials applied to nitride-based semiconductor layers 14 and 16 and III-V layer 74. In some embodiments, this configuration may be achieved by selecting materials for nitride-based semiconductor layers 14 and 16 and III-V layer 74.
Fig. 5 is a vertical cross-sectional view of a nitride-based semiconductor device 1D according to some embodiments of the present invention. The nitride-based semiconductor device 1D is similar to the nitride-based semiconductor device 1A in fig. 1, except that the n-type doped nitride-based semiconductor layers 30 and 32 are replaced with n-type doped nitride-based semiconductor layers 30D and 32D. The n-type doped nitride-based semiconductor layers 30D and 32D have different thicknesses. The n-type doped nitride-based semiconductor layer 32D may extend downward to a deeper position than the n-type doped nitride-based semiconductor layer 30D. This configuration may be considered since the n-type doped nitride-based semiconductor layer 32D may be used to improve the drain contact resistance. At high voltage operation, an excessively high resistance may generate heat, resulting in power loss. Thus, this configuration can improve such defects.
In some embodiments, n-type doped nitride-based semiconductor layers 30D and 32D may have different doping concentrations in order to enhance the improvement of drain contact resistance. For example, the doping concentration of the n-type doped nitride-based semiconductor layer 32D is greater than the doping concentration of the n-type doped nitride-based semiconductor layer 30D.
Fig. 6 is a vertical cross-sectional view of a nitride-based semiconductor device 1E according to some embodiments of the present invention. The nitride-based semiconductor device 1E is similar to the nitride-based semiconductor device 1A in fig. 1, except that the p-type doped nitride-based semiconductor layers 34 and 36 are replaced with p-type doped nitride-based semiconductor layers 34D and 36D. The p-type doped nitride-based semiconductor layers 34D and 36D may further cover sidewalls of the n-type doped nitride-based semiconductor layers 30 and 32. The coverage of the n-type doped nitride-based semiconductor layers 30 and 32 by the p-type doped nitride-based semiconductor layers 34D and 36D may prevent the n-type doped nitride-based semiconductor layers 30 and 32 from being damaged by etching during the patterning process of the p-type doped nitride-based semiconductor layers 34D and 36D.
The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use contemplated.
As used herein and not otherwise defined, the terms "substantially," "essentially," "about," and "approximately" are used to describe and illustrate minor variations. When used in connection with an event or circumstance, the term can include instances where the event or circumstance occurs precisely and instances where it occurs approximately. For example, when used in conjunction with a numerical value, these terms may encompass a variation of less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term "substantially coplanar" may refer to two surfaces lying along a same plane within a micrometer-scale distance, such as within 40 μm, 30 μm, 20 μm, 10 μm, or 1 μm lying along the same plane.
As used herein, the singular terms "a," "an," and "the" may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component disposed "on" or "over" another component may encompass a situation in which a previous component is disposed directly on (e.g., in physical contact with) a subsequent component, as well as a situation in which one or more intermediate components are located between the previous component and the subsequent component.
While the invention has been described and illustrated with reference to specific embodiments thereof, the description and illustration is not intended to be limiting. It will be understood by those skilled in the art that various changes may be made and equivalents substituted without departing from the true spirit and scope of the invention as defined by the appended claims. The illustrations are not necessarily drawn to scale. There may be a distinction between artistic reproductions and actual devices in the present invention due to manufacturing processes and tolerances. Further, it should be understood that the actual devices and layers may deviate from the rectangular layer depiction of the drawings due to fabrication processes such as conformal deposition, etching, etc., and may include corner surfaces or edges, rounded corners, etc. Other embodiments of the invention not specifically shown are possible. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method or process to the objective, spirit and scope of the present invention. All such modifications are intended to be included within the scope of the following claims. Although the methods disclosed herein have been described with reference to particular operations being performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form an equivalent method without departing from the teachings of the present invention. Thus, unless specifically indicated herein, the order and grouping of operations is not limiting.