Detailed Description
The advantages and features of the present invention will become more fully apparent from the following description and appended claims, taken in conjunction with the accompanying drawings and detailed description. It should be noted that the drawings are in a very simplified form and are adapted to non-precise proportions, merely for the purpose of facilitating and clearly aiding in the description of embodiments of the invention.
It should be noted that, in order to clearly illustrate the present invention, various embodiments of the present invention are specifically illustrated by the present embodiments to further illustrate different implementations of the present invention, where the various embodiments are listed and not exhaustive. Furthermore, for simplicity of explanation, what has been mentioned in the previous embodiment is often omitted in the latter embodiment, and therefore, what has not been mentioned in the latter embodiment can be referred to the previous embodiment accordingly.
Example 1
Referring to fig. 1, fig. 1 shows a flight control system based on ZYNQ7 according to the present embodiment. In this embodiment, the system includes: the PS end (PS part) and the PL end are communicated and transmitted through an AXI bus;
The PL end comprises a servo mechanism control IP and an interface IP; the servo mechanism control IP is connected with the servo mechanism; the interface IP is connected with peripheral equipment;
the interface IP is used for realizing communication transmission between the peripheral equipment and the PS terminal;
The servo mechanism control IP is used for collecting information data of the servo mechanism and transmitting the information data to the PS end;
the PS end comprises a first processing core (CPU 0) and a second processing core (CPU 1), and data interaction is realized between the two processing cores through inter-core communication; the first processing core is connected with the servo mechanism control IP; the second processing core is connected with the interface through IP;
the first processing core is used for resolving the received information data of the servo mechanism, generating a flight control signal and outputting the flight control signal to the servo mechanism through the PL end for servo control;
And the second processing core is used for receiving the data of the peripheral equipment and generating the data output to the peripheral equipment.
In this embodiment, the servo control IP is connected to the first processing core through a first AXI line; the interface IP is connected to the second processing core through a second AXI line.
In this embodiment, the second AXI line includes an AXI communication protocol, which is used as a bridge to complete data transmission between the peripheral device and the second processing core;
The AXI communication protocol includes 5 channels, each of which is independent of the other, a read address channel, a read data channel, a write address channel, a write data channel, and a write response channel, respectively.
In this embodiment, each channel includes a set of independent valid signals and ready signals, wherein the valid signals are generated by the information input terminal and the ready signals are generated by the information receiving terminal; when the second processing core determines that the valid signal and the ready signal of the 5 channels are valid, data transmission between the peripheral device and the second processing core is started.
In this embodiment, the valid signal and the ready signal are valid when their corresponding clock signals are rising edges.
Specifically, in terms of external serial ports: the FPGA software needs to realize multi-path external serial port communication and has the functions of configurable baud rate, serial port switching and data caching. The implementation of the serial port function is based on an RS-422 transceiver module, an IP core with FIFO is taken as a data cache center by Xilinx, after data acquisition of data peripheral equipment is completed, a read-write module of an AXI bus is required to be used as a bridge to complete data transmission from the peripheral equipment to a PS end, in the AXI protocol, 5 read-write channels are shared, 2 related read channels (READ ADDRESS read addresses and read data) and 3 related write channels (WRITE ADDRESS write addresses and WRITE DATA write data and write response) are shared. They are called "lanes" because there is a separate set of valid and ready signals at each lane, and data transfer will only occur when the clock signal is rising and both signals are high.
When external equipment data is input, data verification is required to be completed when the data is transmitted to an interface IP core, the data is transmitted to a PS end through an AXI bus, and in the process, a multi-stage handshake mechanism and verification are arranged in intermediate data transmission, so that the integrity and effectiveness of data transmission are ensured. In the data transmission process, a transmission source (an information input end) generates a valid signal to indicate the validity of data or a control signal, a destination source (an information receiving end) generates a ready signal index to be ready for receiving the data or the control signal, the reading and writing processes are independent, the data and the address lines in the reading and writing channels are independent, and when the valid and ready signals of the reading and writing address channels and the data channels are valid, the data transmission can be performed. In the process, after valid and ready signals of 5 channels are valid for 10 handshake signals in total, data transmission can be carried out.
In this embodiment, the servo mechanism control IP includes a PWM control output module and an SPI acquisition module;
The SPI acquisition module is used for acquiring angle information and position information of the servo mechanism and transmitting the angle information and the position information to the first processing core;
and the PWM control output module is used for receiving the flight control signal of the first processing core, generating a PWM control pulse signal and outputting the PWM control pulse signal to the servo mechanism.
Specifically, in terms of servo control interface: the servo mechanism controls IP to acquire 4 paths of angle feedback signals and outputs a specific PWM control pulse signal; in terms of PS part to PL part communication: and realizing communication by using an AXI4 interface protocol special for ZYNQ7, and completing the whole data receiving and the closed loop of control instruction output.
It should be noted that "X4" in fig. 1 indicates that the PWM control output module and the SPI acquisition module are respectively subjected to four-time instantiations, that is, the specific functional requirements are realized by a multi-layer instantiation mode after the module design is completed in the present scheme. In the scheme, 4 paths of signals of the servo mechanism are required to be acquired and 4 paths of PWM pulse control signals are required to be output, so that four times of instantiations are respectively carried out on the PWM control output module and the SPI acquisition module, and the effects of parallel acquisition and parallel output of 4 paths of signals are achieved.
Here, "X6" in the interface IP indicates 6 instantiations of the serial port. Namely, the UART_TX.V module (RS 422 serial port transmitting module), the UART_RX.V module (RS 422 serial port receiving module), the FIFO_RX.V module (FIFO receiving module), the FIFO_TX.V module (FIFO transmitting module), the AXI_WE.V module (AXI bus writing module) and the AXI_RD.V module (AXI bus reading module) are used for data transmission between the peripheral module and the PS end.
The data buffer center is used as a data buffer center, and after the data acquisition of peripheral equipment is completed, the data is buffered, so that the functions of writing data and reading data are realized.
In this embodiment, the interface IP includes a 1-way maintenance port and a 5-way external port, where the maintenance port is connected to a maintenance interface of an external device through a maintenance TX line and a maintenance RX line; each external port is connected to an external interface of the peripheral device via a respective TX line and RX line.
In this embodiment, the interface IP performs serial port switching between the maintenance port and the external port based on a serial port switching instruction generated by the second processing core.
In this embodiment, after receiving the serial port switching instruction output by the second processing core, the interface IP adjusts the working mode to the maintenance mode; and in the maintenance mode, the interface IP disconnects the target external interface of the peripheral equipment to be maintained from the interface IP, and the maintenance TX line and the RX line of the maintenance interface are connected to the external ports corresponding to the target external interface.
Specifically, the axi_uart.v sub-top module in fig. 2 implements the instantiation of 6 serial ports, and the serial port switching function is completed in the sub-top module, and a specific instruction is input to the module, so that serial port switching can be implemented.
For external devices, the interface interacting with the flight control algorithm is interconnected inside the whole device, and if software maintenance is to be performed on the external device, the whole device needs to be disassembled for separate updating of the external device. Serial port switching can solve this problem. For the update of the external equipment software, one external interface can be reserved to realize the update and maintenance of a plurality of external equipment software, thereby effectively improving the convenience. The functional block diagram of the link relation between the external interface and the interface IP core is shown in figure 3.
Thanks to the programmability of the FPGA, serial port switching can be achieved by utilizing the programmable feature of the internal circuit connection. In a normal mode, each external interface is connected with ports of UART_TX and UART_RX modules of an interface IP core through TX and RX lines to realize data transmission; in the maintenance mode, the interface sending and receiving lines (the connection direction of the external interface and the uart_tx and uart_rx modules in fig. 3) which need to be maintained are disconnected, the maintenance TX line and the maintenance RX line of the maintenance interface are connected to the interfaces uart_tx and uart_rx modules which need to be updated, and the connection mode shown in fig. 4 can complete the interconnection of the maintenance interface and the interface of the external equipment so as to realize the software update maintenance of the external equipment. Wherein both the disconnected TX and RX lines are set to a high resistance state.
In this embodiment, according to the analysis of the software design requirement, the hierarchical structure diagram of the FPGA working software shown in fig. 2 can be obtained, and it can be seen from the figure that the structure is designed from top to bottom, and after the design of the bottom module is completed, the function requirement is achieved by adopting a multi-layer instantiation mode. The AXI_UART.V module (interface IP module) and the AXI_SPI.V module (servo mechanism control IP module) are two secondary top layer modules, independent connection is respectively established with two ARM cores of the PS end, data interaction is realized through inter-core communication between the two ARM cores, and instruction calculation and instruction output are completed. The fig. 2 further includes a TOP layer module (TOP. V module) and an SPI interface TOP layer module (top_spi. V module), and the SPI interface TOP layer module (top_spi. V module) is instantiated 4 times to form 4 SPI interface modules (spi_mod. V module) for data acquisition of the servo mechanism. The servo mechanism control IP module (AXI_SPI.V module) is subjected to four-time lower-level fourth-order conversion to form 4 PWM pulse output modules (PWN_OD.V modules) for outputting 4 PWM control pulse signals.
Based on the above, the system is an integrated result of the servo mechanism control IP (SPI+PWM output) and the RS422 interface of the peripheral equipment, and is integrally constructed in the form of an IP core, and only the external interface is required to be connected in use, so that the operation is simple, the IP core is only required to be modified in maintenance, the hierarchical logic is complete, the later maintenance is convenient, the system can be used independently or together, and the system has the distributed characteristic.
The system has the following beneficial effects:
(1) The design of DSP and FPGA is integrated, so that flight control is integrated, layout and wiring space is saved, and cost can be saved on components and space;
(2) PS and PL end software are fused and solidified, so that the later software maintenance is more convenient;
(3) The FPGA is adopted to output control signals, so that the synchronism of the control instruction output is effectively improved;
(4) The communication between PS and PL ends adopts AXI4 communication protocol, so that the data stream transmission is faster and more stable
Based on the above, the scheme is proved by experiments to be capable of effectively detecting the rotating angle position of the motor, outputting specific PWM control information, communicating with peripheral equipment normally and realizing a software maintenance function through serial port switching. The accuracy and stability requirements of the system control requirements are met. The system test result shows that the IP core has reliable design, strong operability and good portability, and can meet the requirements of integration, low cost, portability and the like.
In conclusion, the system integrates the collection of the angle sensor, the collection of the position information and the output of the control signal, wherein the communication between the PS end and the PL end adopts an AXI bus, and compared with the EMIF bus speed adopted by the traditional DSP+FPGA architecture, the system has the advantages of higher speed and higher stability; the whole control process of the system is that the PL part of the ZYNQ chip collects information data of the servo mechanism and transmits the information data to the PS part of the ZYNQ chip for resolving, and flight control signals are generated and then output to the servo mechanism through the PL part to complete closed-loop control; the whole process can complete information acquisition and output of flight control signals only by 1 ZYNQ chip, and compared with a traditional DSP+FPGA architecture, the flight control system has the advantages of higher transmission speed, less chip usage and lower power consumption, thereby solving the problems of high cost, low data transmission efficiency and difficult software later maintenance of the conventional flight control system.
Example 2
Referring to fig. 5, fig. 5 shows an information processing circuit using a flight control system according to the present embodiment. In this embodiment, the circuit includes: the system comprises a ZYNQ7020 processor of the flight control system, DDR, FALSH, JTAG connected with the ZYNQ7020 processor, a crystal oscillator, an information processing circuit power module, an interface circuit and a servo mechanism driving circuit; the ZYNQ7020 processor is connected with the interface circuit through an RS422 interface to realize multi-path external serial port communication; the ZYNQ7020 processor collects angle data information of the servo mechanism driving circuit through SPI communication and outputs PWM control pulse signals to the servo mechanism driving circuit for servo control; the DDR is used for generating a control signal to control the read-write function of the ZYNQ7020 processor; the FLASH is used for storing the data processed by the information processing circuit; JTAG is used for carrying out software design on a flight control system in the ZYNQ7020 processor; the crystal oscillator is used for providing a clock signal for the information processing circuit; the information processing circuit power supply module is used for supplying power to the information processing circuit.
Based on the advantages of the ZYNQ processor platform dual-core ARM+FPGA, wherein ARM is used as a data operation processing and control center and is responsible for outputting flight control instructions and other functions after compensating and calculating the acquired angle information and position information, and the FPGA is responsible for acquiring the angle information and the position information data and transmitting the angle information and the position information data to an ARM part through an AXI4 interface, and performing functions of RS-422 logic control and interface management for external communication and the like. Therefore, the dual ARM+FPGA architecture scheme of the ZYNQ7 platform is utilized to realize flight control, the same functions of the traditional 1 DSP+1 FPGA+4 singlechips are realized, the AXI4 interface based on the ZYNQ7 has a faster transmission speed, PS and PL end software are fused and solidified, and later maintenance is convenient.
The foregoing is merely exemplary of the present application and is not intended to limit the present application. Various modifications and variations of the present application will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. which come within the spirit and principles of the application are to be included in the scope of the claims of the present application.