Low-power-consumption Schmidt trigger structureTechnical Field
The invention relates to the technical field of integrated circuits, in particular to a low-power-consumption Schmitt trigger structure.
Background
A schmitt trigger is a circuit configuration triggered by an input level and having two threshold voltages. The schmitt trigger uses a schmitt inverter as an input stage and a normal inverter as an output stage. The schmitt trigger has an input level that changes from low (ground) to high (power supply voltage), an output that toggles from low to high when the input voltage is equal to Vth_h, and an output that toggles from high to low when the input voltage is equal to Vth_l when the input level changes from high to low. Generally Vth_h>Vth_ l.
The operation power consumption of the schmitt trigger can be used as one of the judging standards of the performance of the schmitt trigger. The schmitt trigger working power consumption comprises static power consumption and dynamic power consumption, wherein the dynamic power consumption accounts for the vast majority of the total power consumption. The dynamic power consumption can be divided into switching power consumption and internal power consumption.
Disclosure of Invention
The invention aims to provide a low-power-consumption Schmitt trigger structure so as to solve the problems in the background technology.
In order to solve the technical problems, the invention provides a low-power-consumption Schmidt trigger structure, which comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube;
The gate end of the first PMOS tube, the gate end of the second PMOS tube, the gate end of the first NMOS tube and the gate end of the second NMOS tube are all connected with an input signal Vin;
The drain end of the second PMOS tube is connected with the drain end of the second NMOS tube, the source end of the second NMOS tube is connected with the drain end of the first NMOS tube, and the source end of the first NMOS tube is grounded;
The source end of the third PMOS tube is simultaneously connected with the drain end of the first PMOS tube and the source end of the second PMOS tube, the gate end of the third PMOS tube is simultaneously connected with the drain end of the second PMOS tube and the drain end of the second NMOS tube, and the drain end of the third PMOS tube is grounded;
the source end of the third NMOS tube is connected with the source end of the second NMOS tube and the drain end of the first NMOS tube at the same time, the gate end of the third NMOS tube is connected with the drain end of the second PMOS tube and the drain end of the second NMOS tube at the same time, and the drain end of the third NMOS tube is connected with the power supply voltage Vdd;
The source end of the fourth PMOS tube is connected with the power supply voltage Vdd, the gate end of the fourth PMOS tube is simultaneously connected with the drain end of the first PMOS tube, the source end of the second PMOS tube and the source end of the third PMOS tube, the drain end of the fourth PMOS tube is connected with the drain end of the fourth NMOS tube, the gate end of the fourth NMOS tube is simultaneously connected with the drain end of the first NMOS tube, the source end of the second NMOS tube and the source end of the third NMOS tube, and the source end of the fourth NMOS tube is grounded.
The low-power-consumption Schmitt trigger structure reduces the dynamic power consumption of the Schmitt trigger under the condition that only the connection is changed, reduces the dynamic power consumption of the Schmitt trigger without increasing the complexity of a circuit, and provides obvious advantages for low-power-consumption application.
Drawings
Fig. 1 is a schematic diagram of a low power consumption schmitt trigger structure according to the present invention.
Detailed Description
The following describes a low power consumption schmitt trigger structure according to the present invention in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
The invention provides a low-power-consumption Schmitt trigger structure, which is shown in FIG. 1 and comprises PMOS (P-channel metal oxide semiconductor) transistors MP 1-MP 4 and NMOS (N-channel metal oxide semiconductor) transistors MN 1-MN 4, wherein the source end of the PMOS transistor MP1 is connected with a power supply voltage Vdd, the drain end of the PMOS transistor MP1 is connected with the source end of the PMOS transistor MP2, the drain end of the PMOS transistor MP2 is connected with the drain end of the NMOS transistor MN2, the source end of the NMOS transistor MN2 is connected with the drain end of the NMOS transistor MN1, the source end of the NMOS transistor MN1 is grounded, and the gate ends of the PMOS transistor MP1, the NMOS transistor MN1 and the NMOS transistor MN2 are all connected with an input signal Vin. The source end of the PMOS tube MP3 is simultaneously connected with the drain end of the PMOS tube MP1 and the source end of the PMOS tube MP2, the gate end of the PMOS tube MP3 is simultaneously connected with the drain end of the PMOS tube MP2 and the drain end of the NMOS tube MN2, and the drain end of the PMOS tube MP3 is grounded. The source end of the NMOS tube MN3 is simultaneously connected with the source end of the NMOS tube MN2 and the drain end of the NMOS tube MN1, the gate end of the NMOS tube MN3 is simultaneously connected with the drain end of the PMOS tube MP2 and the drain end of the NMOS tube MN2, and the drain end of the NMOS tube MN3 is connected with the power supply voltage Vdd. The source end of the PMOS tube MP4 is connected with the power supply voltage Vdd, the gate end of the PMOS tube MP4 is simultaneously connected with the drain end of the PMOS tube MP1, the source end of the PMOS tube MP2 and the source end of the PMOS tube MP3, the drain end of the PMOS tube MP4 is connected with the drain end of the NMOS tube MN4, the gate end of the NMOS tube MN4 is simultaneously connected with the drain end of the NMOS tube MN1, the source end of the NMOS tube MN2 and the source end of the NMOS tube MN3, and the source end of the NMOS tube MN4 is grounded.
The working principle is as follows:
1. Schmitt inverter input stage. The PMOS tube MP1, the PMOS tube MP2 and the PMOS tube MP3 form a Schmidt inverter input stage together with the NMOS tube MN1, the NMOS tube MN2 and the NMOS tube MN 3. When the input Vin is low, vschm = Vschm _p=vdd, vschm _n=vdd-Vthn, vthn is the threshold voltage of the NMOS transistor. When the input Vin is at a high level, vschm = Vschm _n=gnd, vschm _p=vthp, and Vthp is the threshold voltage of the PMOS transistor. When the input Vin is turned from low level to high level, the output turned Vth_h is related to the ratio (W/L)MP1/(W/L)MP3 of the PMOS tube MP1 and the PMOS tube MP3, wherein (W/L)MP1 is the width-to-length ratio of the PMOS tube MP1, (W/L)MP3 is the width-to-length ratio of the PMOS tube MP3, and when the input Vin is turned from high level to low level, the output turned Vth_l is related to the ratio (W/L)MN1/(W/L)MN3 of the NMOS tube MN1 and the NMOS tube MN3, wherein (W/L)MN1 is the width-to-length ratio of the NMOS tube MN1, and (W/L)MN3 is related to the width-to-length ratio of the NMOS tube MN 3. The schmitt inverter drives the PMOS MP4 to have a switching power consumption of 0.5×fc (Vdd-Vthp)2 and drives the NMOS MN4 to have a switching power consumption of 0.5×fc (Vdd-Vthn)2. Wherein F is the switching frequency of the input signal, and C is the equivalent total capacitance of the gate end of the PMOS tube MP 4.
2. An inverter output stage. The PMOS tube MP4 and the NMOS tube MN4 form an inverter output stage. Note that the gate end of the PMOS transistor MP4 is connected to the drain end of the PMOS transistor MP1, the source end of the PMOS transistor MP2, and the source end of the PMOS transistor MP3, while the gate end of the NMOS transistor MN4 is connected to the drain end of the NMOS transistor MN1, the source end of the NMOS transistor MN2, and the source end of the NMOS transistor MN 3. When Vin is turned from low level to high level, vschm _n is turned from high level Vdd-Vthn to low level GND to turn off NMOS transistor MN4, and after a certain delay TD1, vschm _p is turned from high level Vdd to low level Vthp to turn on PMOS transistor MP4 to turn output Vout from low level to high level. Similarly, when Vin is turned from high level to low level, vschm _p will be turned from low level Vthp to high level Vdd to turn off PMOS transistor MP4, and after a certain delay TD2, vschm _n will be turned from low level GND to high level Vdd-Vthn to turn on NMOS transistor MN4 to turn output Vout from high level to low level. Due to the existence of the time delays TD1 and TD2, the time for simultaneously conducting the NMOS tube MN4 and the PMOS tube MP4 is reduced, and therefore the short circuit power consumption of the output inverter is reduced.
The invention uses a new schmitt trigger structure, the gate end of the NMOS tube and the gate end of the PMOS tube in the output stage of the inverter are connected to different signals separately, and lower power consumption is realized under the condition that the logic function and the turnover threshold value of the schmitt trigger are not influenced.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.