技术领域Technical Field
本发明涉及计算机技术领域，特别涉及一种MMIO(Memory-mapped I/O，内存映射I/O)地址资源分配方法、MMIO地址资源分配装置、计算设备和计算机可读存储介质。The present invention relates to the field of computer technology, and in particular to an MMIO (Memory-mapped I/O) address resource allocation method, an MMIO address resource allocation device, a computing device and a computer-readable storage medium.
背景技术Background Art
现在的计算机、服务器等计算设备经常插接有很多种类的PCIE外设，比如声卡、显卡和网卡等。在MMIO技术中，计算机的CPU可以通过控制内存来控制这些外设，因而需要给PCIE设备分配MMIO地址资源，以实现CPU对这些设备的控制。现有的MMIO地址资源分配机制是静态的，无法根据PCIE外设的动态变化来灵活分配MMIO地址资源，经常造成所分配的资源过多或过少的情况发生。因此，本领域亟需一种能够实现MMIO地址资源动态分配的技术，用于灵活适应PCIE设备的插拔等各种变化，防止资源不足或资源浪费等情况出现。Nowadays, computers, servers and other computing devices are often plugged in with many kinds of PCIE peripherals, such as sound cards, graphics cards and network cards. In MMIO technology, the CPU of a computer can control these peripherals by controlling the memory, so it is necessary to allocate MMIO address resources to PCIE devices to realize the control of these devices by the CPU. The existing MMIO address resource allocation mechanism is static and cannot flexibly allocate MMIO address resources according to the dynamic changes of PCIE peripherals, which often causes too many or too few resources to be allocated. Therefore, there is an urgent need in the art for a technology that can realize the dynamic allocation of MMIO address resources, which is used to flexibly adapt to various changes such as the plugging and unplugging of PCIE devices to prevent the occurrence of insufficient resources or waste of resources.
发明内容Summary of the invention
为此，本申请致力于提供一种MMIO地址资源分配方法、MMIO地址资源分配装置、计算设备和计算机可读存储介质，其能够实现MMIO地址资源的动态分配，防止资源不足或资源浪费。To this end, the present application is dedicated to providing an MMIO address resource allocation method, an MMIO address resource allocation device, a computing device and a computer-readable storage medium, which can realize dynamic allocation of MMIO address resources and prevent resource shortage or resource waste.
在一方面，本申请提供一种MMIO地址资源分配方法，包括：通过带外控制器获取与计算设备相连接的PCIE设备的设备信息；基于预设列表，获取PCIE设备的设备信息对应的MMIO地址资源信息，预设列表指示了设备信息与MMIO地址资源信息的对应关系；根据MMIO地址资源信息，确定为PCIE设备分配的MMIO地址资源。On the one hand, the present application provides an MMIO address resource allocation method, including: obtaining device information of a PCIE device connected to a computing device through an out-of-band controller; based on a preset list, obtaining MMIO address resource information corresponding to the device information of the PCIE device, the preset list indicating the correspondence between the device information and the MMIO address resource information; and determining the MMIO address resource allocated to the PCIE device according to the MMIO address resource information.
根据本方面，带外控制器是一套独立的针对计算设备的各个组成部分进行管理的系统，通过带外控制器来获取PCIE设备的信息，能够在计算设备自身的系统之外，以独立方式获取设备信息，带外控制器能够及时知晓PCIE设备的变化情况，从而能够适应PCIE设备的变化，动态获取设备信息，以便有针对性地分配MMIO地址资源。在带外控制器获知板卡上插接的PCIE设备的信息后，根据这些信息在固件中存储的列表当中查询，可以得到所插接的每个PCIE设备所需要的MMIO地址资源大小，从而实现准确的分配。列表由计算设备固件的开发者提前配置在固件中，开发者能够将当时所知晓的所有类型的外设及其所需要的资源大小全部存储在该列表中，从而实现尽可能全面准确的MMIO地址资源分配。According to this aspect, the out-of-band controller is an independent system for managing each component of the computing device. By obtaining the information of the PCIE device through the out-of-band controller, the device information can be obtained in an independent manner outside the system of the computing device itself. The out-of-band controller can know the changes of the PCIE device in a timely manner, so as to adapt to the changes of the PCIE device and dynamically obtain the device information so as to allocate MMIO address resources in a targeted manner. After the out-of-band controller obtains the information of the PCIE device plugged into the board, it can query the list stored in the firmware based on this information to obtain the MMIO address resource size required for each plugged-in PCIE device, thereby achieving accurate allocation. The list is configured in the firmware in advance by the developer of the computing device firmware. The developer can store all types of peripherals known at the time and the resource sizes required in the list, thereby achieving as comprehensive and accurate MMIO address resource allocation as possible.
在一些实施方式中，通过带外控制器获取与计算设备相连接的PCIE设备的设备信息，包括：在计算设备接通电源并启动后的开机阶段，通过带外控制器获取与计算设备相连接的PCIE设备的设备信息，其中带外控制器在计算设备接通电源但未启动的待机阶段从计算设备的板卡获取信息。In some embodiments, device information of a PCIE device connected to a computing device is obtained through an out-of-band controller, including: during a startup phase after the computing device is powered on and started, device information of a PCIE device connected to the computing device is obtained through an out-of-band controller, wherein the out-of-band controller obtains information from a board of the computing device during a standby phase when the computing device is powered on but not started.
根据本实施方式，带外管理启动从计算设备插接到电源上之后就开始运行，不依赖于开机操作，从而能够长时间、实时获知计算机上的PCIE设备的插拔情况，及时知晓PCIE设备的变化，从而在开机阶段为计算设备的固件提供可靠的PCIE设备信息，以便固件在开机启动过程中准确分配MMIO地址资源。According to this embodiment, the out-of-band management startup starts running after the computing device is plugged into the power supply, and is independent of the power-on operation, so that the plug-in and unplugging status of the PCIE device on the computer can be known in real time for a long time, and the changes of the PCIE device can be known in time, thereby providing reliable PCIE device information to the firmware of the computing device during the power-on stage, so that the firmware can accurately allocate MMIO address resources during the power-on process.
在一些实施方式中，带外控制器包括BMC。通过带外控制器获取与计算设备相连接的PCIE设备的设备信息，包括：通过IPMI命令从BMC获取与计算设备相连接的PCIE设备的设备信息。In some implementations, the out-of-band controller includes a BMC. Acquiring device information of a PCIE device connected to the computing device through the out-of-band controller includes: acquiring device information of the PCIE device connected to the computing device from the BMC through an IPMI command.
根据本实施方式，BMC是常用的带外控制器，其对于计算设备特别是服务器具有良好的管理性能，目前已经被广泛采用在各种型号的计算设备上。IPMI命令是BMC经常用于与计算设备各部件相互通信的方式。通过BMC来实现PCIE设备的获取，有利于实现本申请提出的MMIO地址资源分配方法的广泛适用性，增大本申请的应用范围，提高本申请技术方案的实施效果。According to this embodiment, BMC is a commonly used out-of-band controller, which has good management performance for computing devices, especially servers, and has been widely used in various types of computing devices. IPMI commands are a way that BMC often uses to communicate with various components of computing devices. Acquisition of PCIE devices through BMC is conducive to achieving the wide applicability of the MMIO address resource allocation method proposed in this application, increasing the scope of application of this application, and improving the implementation effect of the technical solution of this application.
在一些实施方式中，BMC通过I2C总线或SMBUS从计算设备的板卡获取设备信息。In some implementations, the BMC obtains device information from a board of the computing device via an I2C bus or an SMBUS.
根据本实施方式，I2C总线或SMBUS是广泛应用的计算设备总线，其与计算设备的各种板卡相连，能够通过其准确获知各板卡上的外设插接情况。According to this embodiment, the I2C bus or SMBUS is a widely used computing device bus, which is connected to various boards of the computing device, and the peripheral plug-in status of each board can be accurately known through it.
在一些实施方式中，根据MMIO地址资源信息，确定为PCIE设备分配的MMIO地址资源，包括：根据MMIO地址资源信息，制定资源分配策略；根据资源分配策略，确定为PCIE设备分配的MMIO地址资源。In some implementations, determining the MMIO address resources allocated to the PCIE device according to the MMIO address resource information includes: formulating a resource allocation strategy according to the MMIO address resource information; and determining the MMIO address resources allocated to the PCIE device according to the resource allocation strategy.
根据本实施方式，在获取查询结果以后，可以以查询到的每个PCIE设备所需的MMIO资源大小为基础，制定资源分配策略，而非直接按照所需资源进行分配，可以应对各种可能发生的意外情况，使得分配方式尽可能满足不同情况下的资源需求。According to this embodiment, after obtaining the query results, a resource allocation strategy can be formulated based on the MMIO resource size required by each PCIE device queried, rather than directly allocating according to the required resources. This can cope with various possible unexpected situations and make the allocation method meet the resource requirements in different situations as much as possible.
在一些实施方式中，资源分配策略包括最小分配策略和最大分配策略，最小分配策略用于给PCIE设备分配尽可能少的MMIO地址资源，最大分配策略用于给PCIE设备分配尽可能多的MMIO地址资源。根据MMIO地址资源信息，制定资源分配策略，包括：若PCIE设备的热插拔需求较少，采用最小分配策略；若PCIE设备的热插拔需求较多，采用最大分配策略。In some implementations, the resource allocation strategy includes a minimum allocation strategy and a maximum allocation strategy, wherein the minimum allocation strategy is used to allocate as few MMIO address resources as possible to the PCIE device, and the maximum allocation strategy is used to allocate as many MMIO address resources as possible to the PCIE device. According to the MMIO address resource information, a resource allocation strategy is formulated, including: if the hot-plugging demand of the PCIE device is small, the minimum allocation strategy is adopted; if the hot-plugging demand of the PCIE device is large, the maximum allocation strategy is adopted.
根据本实施方式，根据计算设备热插拔情况来配置MMIO地质资源的分配策略，有利于使分配策略更加合理。热插拔需求多的计算设备，其PCIE设备变动可能性较大，因此需要分配尽可能多的MMIO地址资源，反之则否。这样一来，能够实现资源的合理利用，尽可能避免浪费或资源不足的情况发生。According to this embodiment, the allocation strategy of MMIO geological resources is configured according to the hot plug situation of the computing device, which is conducive to making the allocation strategy more reasonable. For computing devices with many hot plug requirements, the possibility of PCIE device changes is relatively large, so as many MMIO address resources as possible need to be allocated, and vice versa. In this way, it is possible to achieve reasonable utilization of resources and avoid waste or insufficient resources as much as possible.
在一些实施方式中，在根据MMIO地址资源信息，确定为所述PCIE设备分配的MMIO地址资源之后，方法还包括：判断设备信息与PCIE枚举过程中发现的PCIE设备信息是否匹配；若否，将不匹配结果发送至带外控制器，使带外控制器获取与计算设备相连接的PCIE设备的更新设备信息；从带外控制器获取更新设备信息；根据更新设备信息，重新确定为所述PCIE设备分配的MMIO地址资源。In some embodiments, after determining the MMIO address resources allocated to the PCIE device based on the MMIO address resource information, the method further includes: determining whether the device information matches the PCIE device information found during the PCIE enumeration process; if not, sending the mismatch result to the out-of-band controller, so that the out-of-band controller obtains updated device information of the PCIE device connected to the computing device; obtaining the updated device information from the out-of-band controller; and re-determining the MMIO address resources allocated to the PCIE device based on the updated device information.
根据本实施方式，设置有MMIO地址资源分配的检验和反馈过程。通过该过程，可以在PCIE设备意外变化的时候及时变更资源分配策略，使得MMIO地址资源的分配做到符合计算设备当时准确的PCIE设备的插接情况，避免在设备意外或临时插拔的情况下，资源分配错误的情况发生。According to this embodiment, a verification and feedback process of MMIO address resource allocation is provided. Through this process, the resource allocation strategy can be changed in time when the PCIE device changes unexpectedly, so that the allocation of MMIO address resources is consistent with the accurate plug-in status of the PCIE device of the computing device at that time, avoiding the occurrence of resource allocation errors in the case of accidental or temporary plug-in and unplugging of the device.
在一些实施方式中，带外控制器从计算设备的板卡获取并存储信息，信息的存储格式中包括校验位。In some implementations, the out-of-band controller obtains and stores information from a card of the computing device, and the information is stored in a format that includes a check digit.
根据本实施方式，通过将PCIE设备信息储存起来，能够使计算设备的固件随时调取PCIE设备信息，以便随时实现分配动作。在存储的过程中添加校验位，能够保证存储的数据在传输过程中尽量不发生错误，以确保数据的准确性和安全性。According to this embodiment, by storing the PCIE device information, the firmware of the computing device can retrieve the PCIE device information at any time so as to implement the allocation action at any time. Adding a check bit during the storage process can ensure that the stored data does not have errors as much as possible during the transmission process, thereby ensuring the accuracy and security of the data.
在一些实施方式中，通过运行计算设备的固件实现本方法，固件包括BIOS、UEFI、CoreBoot和SlimBootloader中的至少一个。In some implementations, the method is implemented by running firmware of a computing device, the firmware including at least one of BIOS, UEFI, CoreBoot, and SlimBootloader.
根据本实施方式，固件可以采用这几种常用的计算设备固件，它们具有广泛的适用性，具有良好的操作性能，能够与本申请的分配方案结合，实现MMIO地址资源的动态分配。According to this embodiment, the firmware may adopt several commonly used computing device firmwares, which have wide applicability, good operating performance, and can be combined with the allocation scheme of this application to realize dynamic allocation of MMIO address resources.
在另一方面，本申请提供一种MMIO地址资源分配装置，包括：第一获取模块，用于通过带外控制器获取与计算设备相连接的PCIE设备的设备信息；第二获取模块，用于基于预设列表，获取PCIE设备的设备信息对应的MMIO地址资源信息，预设列表指示了设备信息与MMIO地址资源信息的对应关系；确定模块，用于根据MMIO地址资源信息，确定为PCIE设备分配的MMIO地址资源。On the other hand, the present application provides an MMIO address resource allocation device, including: a first acquisition module, used to obtain device information of a PCIE device connected to a computing device through an out-of-band controller; a second acquisition module, used to obtain MMIO address resource information corresponding to the device information of the PCIE device based on a preset list, the preset list indicating the correspondence between the device information and the MMIO address resource information; a determination module, used to determine the MMIO address resources allocated to the PCIE device according to the MMIO address resource information.
在一些实施方式中，获取模块被进一步配置成：在计算设备接通电源并启动后的开机阶段，通过带外控制器获取与计算设备相连接的PCIE设备的设备信息，其中带外控制器在计算设备接通电源但未启动的待机阶段从计算设备的板卡获取信息。In some embodiments, the acquisition module is further configured to: during the power-on phase after the computing device is powered on and started, obtain device information of a PCIE device connected to the computing device through an out-of-band controller, wherein the out-of-band controller obtains information from the board of the computing device during the standby phase when the computing device is powered on but not started.
在一些实施方式中，带外控制器包括BMC，获取模块被进一步配置成：通过IPMI命令从BMC获取与计算设备相连接的PCIE设备的设备信息。In some implementations, the out-of-band controller includes a BMC, and the acquisition module is further configured to: acquire device information of a PCIE device connected to the computing device from the BMC through an IPMI command.
在一些实施方式中，BMC通过I2C总线或SMBUS从计算设备的板卡获取设备信息。In some implementations, the BMC obtains device information from a board of the computing device via an I2C bus or an SMBUS.
在一些实施方式中，装置被进一步配置成：根据MMIO地址资源信息，制定资源分配策略；根据资源分配策略，确定为PCIE设备分配的MMIO地址资源In some embodiments, the apparatus is further configured to: formulate a resource allocation strategy based on the MMIO address resource information; determine the MMIO address resource allocated to the PCIE device based on the resource allocation strategy;
在一些实施方式中，资源分配策略包括最小分配策略和最大分配策略，最小分配策略用于给PCIE设备分配尽可能少的MMIO地址资源，最大分配策略用于给PCIE设备分配尽可能多的MMIO地址资源，装置被进一步配置成：若PCIE设备的热插拔需求较少，采用最小分配策略；若PCIE设备的热插拔需求较多，采用最大分配策略。In some embodiments, the resource allocation strategy includes a minimum allocation strategy and a maximum allocation strategy. The minimum allocation strategy is used to allocate as few MMIO address resources as possible to the PCIE device, and the maximum allocation strategy is used to allocate as many MMIO address resources as possible to the PCIE device. The device is further configured to: if the hot-plug demand of the PCIE device is small, the minimum allocation strategy is adopted; if the hot-plug demand of the PCIE device is large, the maximum allocation strategy is adopted.
在一些实施方式中，装置被进一步配置成：判断设备信息与PCIE枚举过程中发现的PCIE设备信息是否匹配；若否，将不匹配结果发送至带外控制器，使带外控制器获取与计算设备相连接的PCIE设备的更新设备信息；从带外控制器获取更新设备信息；根据更新设备信息，重新针对PCIE设备分配MMIO地址资源。In some embodiments, the apparatus is further configured to: determine whether the device information matches the PCIE device information found during the PCIE enumeration process; if not, send the mismatch result to the out-of-band controller so that the out-of-band controller obtains updated device information of the PCIE device connected to the computing device; obtain the updated device information from the out-of-band controller; and reallocate MMIO address resources for the PCIE device based on the updated device information.
在一些实施方式中，带外控制器从计算设备的板卡获取并存储信息，信息的存储格式中包括校验位。In some implementations, the out-of-band controller obtains and stores information from a card of the computing device, and the information is stored in a format that includes a check digit.
在一些实施方式中，通过运行计算设备的固件实现装置的功能，固件包括BIOS、UEFI、CoreBoot和SlimBootloader中的至少一个。In some implementations, the functionality of the apparatus is implemented by running firmware of the computing device, the firmware including at least one of BIOS, UEFI, CoreBoot, and SlimBootloader.
在另一方面，本申请提供一种计算设备，计算设备包括处理器和存储器，处理器用于执行存储于存储器内的计算机程序以实现上述的MMIO地址资源分配方法。On the other hand, the present application provides a computing device, the computing device comprising a processor and a memory, the processor being configured to execute a computer program stored in the memory to implement the above-mentioned MMIO address resource allocation method.
在另一方面，本申请提供一种计算机可读存储介质，计算机可读存储介质存储有计算机程序，计算机程序用于执行上述的MMIO地址资源分配方法。On the other hand, the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and the computer program is used to execute the above-mentioned MMIO address resource allocation method.
在另一方面，本申请提供一种计算机程序产品，包括程序代码，当计算机运行计算机程序产品时，使得计算机实现上述MMIO地址资源分配方法。On the other hand, the present application provides a computer program product, including program code, which enables a computer to implement the above-mentioned MMIO address resource allocation method when the computer program product is executed on the computer.
上述提供的任一种MMIO地址资源分配装置、计算设备、计算机可读存储介质或计算机程序产品，均用于执行上文所提供的MMIO地址资源分配方法，因此，其所能达到的有益效果可参考上文提供的对应方法中的对应方案的有益效果，此处不再赘述。Any of the MMIO address resource allocation devices, computing devices, computer-readable storage media or computer program products provided above are used to execute the MMIO address resource allocation method provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects of the corresponding schemes in the corresponding methods provided above, and will not be repeated here.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
以下，结合附图详细描述本申请的具体实施方式，其中：The specific implementation of the present application is described in detail below with reference to the accompanying drawings, wherein:
图1示出根据本申请一实施例的MMIO地址资源分配方法的架构示意图；FIG1 is a schematic diagram showing the architecture of a method for allocating MMIO address resources according to an embodiment of the present application;
图2示出根据本申请一实施例的MMIO地址资源分配方法的流程示意图；FIG2 is a schematic diagram showing a flow chart of a method for allocating MMIO address resources according to an embodiment of the present application;
图3示出根据图2实施例的MMIO地址资源分配方法的时间分布示意图；FIG3 is a schematic diagram showing the time distribution of the MMIO address resource allocation method according to the embodiment of FIG2 ;
图4示出根据图2实施例的MMIO地址资源分配方法的硬件架构示意图；FIG4 is a schematic diagram showing a hardware architecture of the MMIO address resource allocation method according to the embodiment of FIG2 ;
图5示出根据本申请一实施例的MMIO地址资源分配方法的流程示意图；FIG5 is a schematic diagram showing a flow chart of a method for allocating MMIO address resources according to an embodiment of the present application;
图6示出根据图5实施例的MMIO地址资源分配方法的流程示意图；FIG6 is a schematic flow chart showing a method for allocating MMIO address resources according to the embodiment of FIG5 ;
图7示出根据本申请一实施例的MMIO地址资源分配方法的架构示意图；FIG7 is a schematic diagram showing the architecture of a method for allocating MMIO address resources according to an embodiment of the present application;
图8示出根据本申请一实施例的MMIO地址资源分配装置的结构示意图；FIG8 is a schematic diagram showing the structure of an MMIO address resource allocation device according to an embodiment of the present application;
图9示出根据本申请一实施例的计算设备的结构示意图。FIG9 shows a schematic diagram of the structure of a computing device according to an embodiment of the present application.
具体实施方式DETAILED DESCRIPTION
为了使本领域技术人员更加清楚地理解本申请的概念和思想，以下结合具体实施例详细描述本申请。应理解，本文给出的实施例都只是本申请可能具有的所有实施例的一部分。本领域技术人员在阅读本申请的说明书以后，有能力对下述实施例的部分或整体作出改进、改造、或替换，这些改进、改造、或替换也都包含在本申请要求保护的范围内。In order to make those skilled in the art understand the concept and thought of the present application more clearly, the present application is described in detail below in conjunction with specific embodiments. It should be understood that the embodiments provided herein are only a part of all embodiments that the present application may have. After reading the specification of the present application, those skilled in the art have the ability to make improvements, transformations, or replacements to part or all of the following embodiments, and these improvements, transformations, or replacements are also included in the scope of the present application.
在本文中，术语“一”、“一个”和其它类似词语并不意在表示只存在一个所述事物，而是表示有关描述仅仅针对所述事物中的一个，所述事物可能具有一个或多个。在本文中，术语“包含”、“包括”和其它类似词语意在表示逻辑上的相互关系，而不能视作表示空间结构上的关系。例如，“A包括B”意在表示在逻辑上B属于A，而不表示在空间上B位于A的内部。另外，术语“包含”、“包括”和其它类似词语的含义应视为开放性的，而非封闭性的。例如，“A包括B”意在表示B属于A，但是B不一定构成A的全部，A还可能包括C、D、E等其它元素。In this document, the terms "one", "an" and other similar words are not intended to indicate that there is only one of the things described, but rather that the relevant description is only for one of the things described, and the things described may have one or more. In this document, the terms "comprises", "includes" and other similar words are intended to indicate logical relationships, and cannot be regarded as indicating spatial structural relationships. For example, "A includes B" is intended to indicate that B logically belongs to A, but does not mean that B is spatially located inside A. In addition, the meanings of the terms "comprises", "includes" and other similar words should be regarded as open, rather than closed. For example, "A includes B" is intended to indicate that B belongs to A, but B does not necessarily constitute the whole of A, and A may also include other elements such as C, D, and E.
在本文中，术语“第一”、“第二”和其它类似词语并不意在暗示任何顺序、数量和重要性，而是仅仅用于对不同的元件进行区分。在本文中，术语“实施例”、“本实施例”、“一实施例”、“一个实施例”并不表示有关描述仅仅适用于一个特定的实施例，而是表示这些描述还可能适用于另外一个或多个实施例中。本领域技术人员应理解，在本文中，任何针对某一个实施例所做的描述都可以与另外一个或多个实施例中的有关描述进行替代、组合、或者以其它方式结合，所述替代、组合、或者以其它方式结合所产生的新实施例是本领域技术人员能够容易想到的，属于本申请的保护范围。In this document, the terms "first", "second" and other similar words are not intended to imply any order, quantity and importance, but are only used to distinguish different elements. In this document, the terms "embodiment", "present embodiment", "one embodiment" and "an embodiment" do not mean that the relevant description is only applicable to a specific embodiment, but rather that these descriptions may also be applicable to one or more other embodiments. Those skilled in the art should understand that in this document, any description made for a certain embodiment can be replaced, combined, or otherwise combined with the relevant description in one or more other embodiments, and the new embodiment produced by the replacement, combination, or other combination is easily conceivable by those skilled in the art and belongs to the scope of protection of this application.
MMIO是指一种计算机硬件和操作系统之间进行通信的机制，占用物理内存地址，其地址长度可视作资源，用以分配给各个PCIE(Peripheral Component InterconnectExpress，外围组件快速互连)设备(包括桥、中断设备等)使用。在MMIO中，特定的输入输出设备(如桥、显卡、网络适配器等)被映射到所被分配到的计算机内存地址空间中，使得处理器能够通过读写内存的方式与这些设备进行通信。通过读写特定的内存地址，OS(Operating System，操作系统)可以触发设备的操作、传输数据或者接收设备的状态信息。MMIO refers to a communication mechanism between computer hardware and the operating system, which occupies physical memory addresses. The address length can be regarded as a resource and is allocated to various PCIE (Peripheral Component Interconnect Express) devices (including bridges, interrupt devices, etc.). In MMIO, specific input and output devices (such as bridges, graphics cards, network adapters, etc.) are mapped to the allocated computer memory address space, so that the processor can communicate with these devices by reading and writing memory. By reading and writing specific memory addresses, the OS (Operating System) can trigger device operations, transmit data, or receive device status information.
计算机启动过程中，BIOS(Basic Input Output System，基本输入输出系统)软件会对硬件和软件运行环境做初始化、自检等动作，然后引导OS的启动，启动前会把初始化、自检的结果以特定形式传递给OS，特定形式例如为ACPI(Advanced Configuration andPower Management Interface，高级配置和电源管理接口)、DT(Device Tree，设备树)等。后续OS，更准确地说位于OS内核空间的设备驱动程序，才能根据BIOS所传递的数据进行正常工作。During the computer startup process, the BIOS (Basic Input Output System) software will initialize and self-check the hardware and software operating environment, and then guide the startup of the OS. Before startup, the initialization and self-check results will be passed to the OS in a specific form, such as ACPI (Advanced Configuration and Power Management Interface), DT (Device Tree), etc. The subsequent OS, or more precisely, the device driver in the OS kernel space, can work normally according to the data passed by the BIOS.
在本领域中，以x86计算机体系结构为例，MMIO的分配动作内嵌于开机启动的过程，以UEFI(Unified Extensible Firmware Interface，统一可拓展固件接口)固件启动流程为例，固件启动过程先后包括SEC(Security Phase，安全验证)、PEI(Pre-EFIInitialization，EFI前期初始化)、DXE(Driver Execution Environment，驱动执行环境)和BDS(Boot Device Selection，启动设备选择)。其中，在PEI阶段的早期，可以进行MMIO分配过程的第1步：将资源参数设定值写入根桥(RootBridge)的控制寄存器。在DXE阶段，可以进行MMIO分配过程的第2步和第3步。其中，第2步：将资源参数写入每个设备的控制寄存器。第3步：PCIE枚举过程中检查资源分配是否正确。固件启动完成后，就是OS的启动和运行过程。In this field, taking the x86 computer architecture as an example, the MMIO allocation action is embedded in the boot process. Taking the UEFI (Unified Extensible Firmware Interface) firmware boot process as an example, the firmware boot process includes SEC (Security Phase), PEI (Pre-EFIInitialization), DXE (Driver Execution Environment) and BDS (Boot Device Selection). Among them, in the early stage of the PEI stage, the first step of the MMIO allocation process can be performed: writing the resource parameter setting value to the control register of the root bridge. In the DXE stage, the second and third steps of the MMIO allocation process can be performed. Among them, step 2: writing the resource parameters to the control register of each device. Step 3: checking whether the resource allocation is correct during the PCIE enumeration process. After the firmware boot is completed, it is the startup and operation process of the OS.
MMIO资源分配方案为静态的、固定的，是开发人员在开发之前就知悉计算机上插接的所有PCIE外设，并取一个大于所需MMIO的取值，分段写入各个PCIE控制器的控制寄存器中。由于分配策略是静态的，一个BIOS仅支持一种硬件插接配置。在开发过程中或终端用户使用过程中如果拔掉、增接、更换PCIE设备，所需的MMIO会出现改变，此时BIOS的静态设定将与硬件配置不再匹配。不匹配的情况有如下两种：1)如果对OS所使用的硬件设备分配过多MMIO资源，会造成整体内存资源的浪费，OS可用内存因此变小，导致计算机系统性能的下降；2)如果有意或无意地分配了过少的MMIO资源，会导致CPU无法与设备进行通信，从而设备无法工作，设备驱动无法正常加载，或设备指令因为无法访问有效内存而不能运行。当出现第二种不匹配现象时，整个计算机系统会处于异常状态。下一次启动过程中BIOS会对这一现象进行处理。The MMIO resource allocation scheme is static and fixed. Before development, the developer knows all the PCIE peripherals plugged into the computer, and takes a value greater than the required MMIO, which is written in sections into the control registers of each PCIE controller. Since the allocation strategy is static, a BIOS only supports one hardware plug-in configuration. If the PCIE device is unplugged, added, or replaced during the development process or during the end user's use, the required MMIO will change, and the static setting of the BIOS will no longer match the hardware configuration. There are two mismatch situations: 1) If too many MMIO resources are allocated to the hardware devices used by the OS, it will cause a waste of overall memory resources, and the available memory of the OS will become smaller, resulting in a decrease in the performance of the computer system; 2) If too few MMIO resources are allocated intentionally or unintentionally, the CPU will be unable to communicate with the device, so that the device cannot work, the device driver cannot be loaded normally, or the device instruction cannot run because it cannot access valid memory. When the second mismatch occurs, the entire computer system will be in an abnormal state. The BIOS will handle this phenomenon during the next startup.
在一些实施方式中，MMIO地址资源分配包括如下步骤。首先需要研发人员预知一个固定配置，并计算出所需MMIO资源。然后将资源参数设定值写入根桥的控制寄存器。然后将资源参数写入每个设备的控制寄存器。然后进行PCIE设备枚举，枚举过程中如果发现分配的MMIO资源不足，则弹出告警框，通知PCIE设备失效，同时进入BIOS的设置页面。此时，需要通知研发人员改变MMIO参数并修改入BIOS，最后再重新启动。这项技术常见于工业类计算机、消费类计算机等产品。In some implementations, MMIO address resource allocation includes the following steps. First, the R&D personnel need to know a fixed configuration in advance and calculate the required MMIO resources. Then write the resource parameter setting value into the control register of the root bridge. Then write the resource parameters into the control register of each device. Then perform PCIE device enumeration. If it is found that the allocated MMIO resources are insufficient during the enumeration process, an alarm box pops up to notify the PCIE device failure and enter the BIOS setting page. At this time, it is necessary to notify the R&D personnel to change the MMIO parameters and modify them into the BIOS, and then restart. This technology is common in industrial computers, consumer computers and other products.
在一些实施方式中，MMIO地址资源分配包括如下步骤。首先需要研发人员预知一个固定配置，并计算出所需MMIO资源。然后将资源参数设定值写入根桥的控制寄存器。然后将资源参数写入每个设备的控制寄存器。然后进行PCIE设备枚举，枚举过程中如果发现分配的MMIO资源不足，则进行冷重启(Cold Reset)。冷重启之后，重新分配MMIO资源给根桥，优先满足资源不足的段。然后再将资源参数写入每个设备的控制寄存器。然后再次进行PCIE设备枚举，如果未发现资源不足，则进入OS启动阶段。这项技术常见于服务器类计算机产品。In some implementations, MMIO address resource allocation includes the following steps. First, the R&D personnel need to know a fixed configuration in advance and calculate the required MMIO resources. Then write the resource parameter setting value into the control register of the root bridge. Then write the resource parameters into the control register of each device. Then perform PCIE device enumeration. If it is found that the allocated MMIO resources are insufficient during the enumeration process, a cold reset is performed. After the cold restart, the MMIO resources are reallocated to the root bridge, giving priority to the segments with insufficient resources. Then write the resource parameters into the control register of each device. Then perform PCIE device enumeration again. If insufficient resources are not found, enter the OS startup phase. This technology is common in server-type computer products.
这些实施方式存在的问题在于：1)为防止出现整个系统的稳定性问题，通常开发人员会将MMIO设置得比实际需要的更大，也就是实际值＝需要值+冗余值，这将造成内存资源浪费，降低系统性能。从理论上讲，不管“冗余值”为多大，都不能避免MMIO不足问题，因为PCIE协议在发展、改变，PCIE外设类型随时间发展、改变。2)静态分配MMIO方法导致服务器对PCIE设备的兼容性相对较弱，一个BIOS版本可能仅支持少数硬件配置策略。3)当出现MMIO资源不足时，重启动作会造成额外的启动时间，重分配动作从理论上无法完全解决资源不足问题。启动时间与重启次数有关，而启动时间与客户使用感受强相关，因此启动时间与资源不足调整次数需要折中，理论上仍然无法彻底解决问题。4)当条件达到无法解决问题时，PCIE设备会失效，出现关键功能缺失。5)需要研发人员、测试人员及前端人员的额外投入，去做诸如BIOS重置、方案验证、停机刷写等动作，造成成本的提升。The problems with these implementations are: 1) To prevent the stability of the entire system, developers usually set MMIO to be larger than actually needed, that is, actual value = required value + redundant value, which will cause a waste of memory resources and reduce system performance. Theoretically, no matter how large the "redundancy value" is, the problem of insufficient MMIO cannot be avoided, because the PCIE protocol is developing and changing, and the types of PCIE peripherals are developing and changing over time. 2) The static allocation of MMIO method leads to relatively weak compatibility of servers with PCIE devices, and a BIOS version may only support a few hardware configuration strategies. 3) When MMIO resources are insufficient, the restart action will cause additional startup time, and the reallocation action cannot completely solve the problem of insufficient resources in theory. The startup time is related to the number of restarts, and the startup time is strongly related to the customer's experience. Therefore, the startup time and the number of resource shortage adjustments need to be compromised, and the problem cannot be completely solved in theory. 4) When the conditions are reached and the problem cannot be solved, the PCIE device will fail and key functions will be missing. 5) It requires additional investment from R&D personnel, testers, and front-end personnel to perform actions such as BIOS reset, solution verification, and shutdown flashing, resulting in increased costs.
本申请一些实施例可以解决不同硬件配置下可能出现的MMIO内存资源分配不足而导致的设备失效、系统稳定性缺失问题。Some embodiments of the present application can solve the problems of device failure and system stability loss caused by insufficient allocation of MMIO memory resources that may occur under different hardware configurations.
在本申请一些实施例中，BMC(Baseboard Management Controller，基板管理控制器)系统通过I2C(Inter-Integrated Circuit，内部集成电路)接口提取背板、立板的型号、位置、数量信息，并以特定编码形式存储于自身NVROM(Non-VolatileRead-Only Memory，非易失性只读存储器)中。数据以特定格式进行编码存储，格式中存在校验位，以确保存储、传输的可靠性。服务器开机阶段，BIOS通过IPMI(Intelligent Platform ManagementInterface，智能平台管理接口)命令从BMC处获取上述信息，并与BIOS的NVROM中的数据库(database)所存储的列表(例如固定硬件配置信息列表)进行对照，计算出详细的MMIO分配策略并用于后续每个阶段合理分配MMIO资源。服务器启动时，BIOS对MMIO资源分配过程中存在设备扫描、检验、设备数据重计算和IPMI命令反馈机制，如有任何形式上的硬件变动，BIOS可做相应的应对调整。In some embodiments of the present application, the BMC (Baseboard Management Controller) system extracts the model, location, and quantity information of the backplane and the vertical board through the I2C (Inter-Integrated Circuit) interface, and stores it in its own NVROM (Non-Volatile Read-Only Memory) in a specific coding form. The data is encoded and stored in a specific format, and there is a check bit in the format to ensure the reliability of storage and transmission. During the server startup phase, the BIOS obtains the above information from the BMC through the IPMI (Intelligent Platform Management Interface) command, and compares it with the list stored in the database (database) in the NVROM of the BIOS (for example, a fixed hardware configuration information list), calculates a detailed MMIO allocation strategy and uses it to reasonably allocate MMIO resources in each subsequent stage. When the server starts, the BIOS has a device scan, inspection, device data recalculation, and IPMI command feedback mechanism in the process of allocating MMIO resources. If there is any form of hardware change, the BIOS can make corresponding adjustments.
在本申请一些实施例中，BMC收集外接板卡插接方案，以特定编码形式传递给BIOS，使得CPU可依照较为准确的设备需求进行MMIO资源分配，节省的物理内存将会被提供给操作系统，减少资源浪费，提高操作系统性能。这些实施例中有硬件配置的自检、反馈功能，可节省测试、开发过程中人工调整MMIO资源造成的额外成本、软件版本的额外管理成本，也可避免前端反复刷写可能造成的各种负面影响。这些实施例设定CPU启动到BDS阶段时进行设备枚举，如发现资源不足(Out of Resource)现象，将以局部增大的方式进行资源重分配，可有效防止PCIE设备资源不足导致的设备失效情况的出现，提高系统稳定性。这些实施例具备MMIO内存资源分配的灵活性，可以有效扩充服务器PCIE外设硬件搭配的可行性，具有更强的设备兼容性，可满足更丰富的客户需求。In some embodiments of the present application, the BMC collects the external board plug-in scheme and passes it to the BIOS in a specific coding form, so that the CPU can allocate MMIO resources according to more accurate device requirements, and the saved physical memory will be provided to the operating system, reducing resource waste and improving operating system performance. In these embodiments, there are self-checking and feedback functions for hardware configuration, which can save the additional cost caused by manual adjustment of MMIO resources during testing and development, the additional management cost of software versions, and can also avoid various negative effects that may be caused by repeated flashing of the front end. These embodiments set the CPU to enumerate the device when it starts to the BDS stage. If the resource shortage (Out of Resource) phenomenon is found, the resource will be redistributed in a local increase manner, which can effectively prevent the occurrence of device failure caused by insufficient PCIE device resources and improve system stability. These embodiments have the flexibility of MMIO memory resource allocation, can effectively expand the feasibility of server PCIE peripheral hardware matching, have stronger device compatibility, and can meet more abundant customer needs.
图1示出根据本申请一实施例的MMIO地址资源分配方法的硬件架构示意图。FIG1 is a schematic diagram showing a hardware architecture of a method for allocating MMIO address resources according to an embodiment of the present application.
如图1所示，多个PCIE设备插接在计算设备的板卡上。图中示出3个PCIE设备，即PCIE设备1、PCIE设备2和PCIE设备3。本领域技术人员应知，图中所示仅为示例，计算设备的板卡上可以插接任意合适数量的PCIE设备。带外控制器与板卡相互通信，因此带外控制器(例如BMC)能够从板卡获取PCIE设备的设备信息，从而知道板卡上插接PCIE设备的数量、类型和型号。计算设备的CPU中运行的固件(例如BIOS)与带外控制器相互通信，因此CPU能够从带外控制器获取PCIE设备的信息。CPU根据从带外控制器获知的PCIE设备的设备信息，通过查询固件中的预设列表确定每个PCIE设备需要多少MMIO地址资源，即确定MMIO地址资源信息，从而给PCIE设备分配MMIO地址资源，满足不同PCIE设备对不同大小的MMIO地址资源的需求。As shown in FIG1 , a plurality of PCIE devices are plugged into a board of a computing device. Three PCIE devices are shown in the figure, namely, PCIE device 1, PCIE device 2 and PCIE device 3. Those skilled in the art should know that what is shown in the figure is only an example, and any suitable number of PCIE devices can be plugged into the board of a computing device. The out-of-band controller communicates with the board, so the out-of-band controller (e.g., BMC) can obtain device information of the PCIE device from the board, thereby knowing the number, type and model of the PCIE devices plugged into the board. The firmware (e.g., BIOS) running in the CPU of the computing device communicates with the out-of-band controller, so the CPU can obtain information of the PCIE device from the out-of-band controller. The CPU determines how many MMIO address resources each PCIE device needs by querying a preset list in the firmware based on the device information of the PCIE device obtained from the out-of-band controller, that is, determining the MMIO address resource information, thereby allocating MMIO address resources to the PCIE device to meet the needs of different PCIE devices for MMIO address resources of different sizes.
在本实施例中，PCIE可以是指一种高速串行计算机扩展总线标准，属于高速串行点对点双通道高带宽传输，所连接的设备分配独享通道带宽，不共享总线带宽，主要支持主动电源管理、错误报告、端对端的可靠性传输、热插拔以及服务质量等功能。PCIE是传统PCI(Peripheral Component Interconnect，外围组件互连)标准的升级版，目的是提供更高的数据传输速率和性能，为各种类型的外部设备提供更快、更稳定的连接。PCIE设备可以是指符合PCIE标准的设备，包括图形卡、声卡、网卡、存储设备等各类硬件设备。In this embodiment, PCIE may refer to a high-speed serial computer expansion bus standard, which belongs to high-speed serial point-to-point dual-channel high-bandwidth transmission. The connected devices are allocated exclusive channel bandwidth and do not share bus bandwidth. It mainly supports active power management, error reporting, end-to-end reliability transmission, hot plug and service quality and other functions. PCIE is an upgraded version of the traditional PCI (Peripheral Component Interconnect) standard, with the purpose of providing higher data transmission rate and performance, and providing faster and more stable connections for various types of external devices. PCIE devices may refer to devices that comply with the PCIE standard, including various hardware devices such as graphics cards, sound cards, network cards, storage devices, etc.
在本实施例中，板卡可以是指计算设备的主板(motherboard)、背板(backplane)、立板(riser)、转接板和插卡等硬件。例如，硬件背板可以用于连接主板和各类硬盘。有的背板上没有桥接芯片，所以对于CPU来讲它是透明的，也就是说PCIE的树结构中，不会有结点与之相关。例如，插卡可以是指经过或不经过转接板的卡，例如OCP网卡是不经过转接板的卡，RTXA6000显卡是经过转接板的卡。In this embodiment, the board may refer to hardware such as the motherboard, backplane, riser, adapter board, and plug-in card of the computing device. For example, the hardware backplane can be used to connect the motherboard and various hard disks. Some backplanes do not have a bridge chip, so it is transparent to the CPU, that is, in the PCIE tree structure, there will be no nodes related to it. For example, a plug-in card may refer to a card that passes through or does not pass through an adapter board, such as an OCP network card that does not pass through an adapter board, and an RTXA6000 graphics card that passes through an adapter board.
在本实施例中，带外控制器可以是指用于运行带外管理系统的控制器。带外管理系统可以是指通过专用的网卡或管理口来实现对计算设备的管理的系统，其可以不受操作系统和硬件故障的影响，提供更加稳定的管理方式。与带外管理不同，带内管理则是在计算设备本身运行的管理软件，需要依赖操作系统提供的API(Application ProgrammingInterface，应用程序编程接口)，受操作系统和硬件故障的影响较大。带外管理可以通过一些专用硬件设备进行实现，也可以通过管理软件和云平台实现。带外管理系统可以实现远程管理和监控，不需要物理接触服务器，同时也不会影响服务器的性能。带外管理可以对服务器进行开关机、重启、系统安装、远程控制等操作，非常适用于远程数据中心、云计算环境等场景。常见的带外控制器例如包括BMC、DRAC(Dell Remote Access Controller，戴尔远程访问控制器)、iLO(Integrated Lights-Out，集成外置管理灯)等。In this embodiment, the out-of-band controller may refer to a controller for running an out-of-band management system. The out-of-band management system may refer to a system that manages a computing device through a dedicated network card or management port, which may not be affected by operating system and hardware failures and provides a more stable management method. Unlike out-of-band management, in-band management is management software that runs on the computing device itself, which needs to rely on the API (Application Programming Interface) provided by the operating system and is greatly affected by operating system and hardware failures. Out-of-band management can be implemented through some dedicated hardware devices, or through management software and cloud platforms. The out-of-band management system can achieve remote management and monitoring without physical contact with the server, and will not affect the performance of the server. Out-of-band management can perform operations such as power on and off, restart, system installation, and remote control on the server, which is very suitable for scenarios such as remote data centers and cloud computing environments. Common out-of-band controllers include, for example, BMC, DRAC (Dell Remote Access Controller), iLO (Integrated Lights-Out), etc.
在本实施例中，计算设备的固件可以是指代码被固定到计算设备的主板上，和硬件很相关，介于软件和硬件之间的一种计算机程序。计算设备的固件是与硬件整体连接的最低软件级别，并且是引导加载程序和操作系统内核，可以与硬件通信并控制硬件的接口。固件是担任着一个系统最基础最底层工作的软件。In this embodiment, the firmware of the computing device may refer to a computer program whose code is fixed to the motherboard of the computing device and is closely related to the hardware, between software and hardware. The firmware of the computing device is the lowest level of software that is connected to the hardware as a whole, and is the interface of the boot loader and the operating system kernel that can communicate with and control the hardware. Firmware is the software that performs the most basic and lowest level work of a system.
作为示例，固件可以包括BIOS、UEFI、CoreBoot和SlimBootloader中的至少一个。As an example, the firmware may include at least one of BIOS, UEFI, CoreBoot, and SlimBootloader.
在本示例中，BIOS可以是指是一组固化到计算机内主板上一个ROM芯片上的程序，它保存着计算机最重要的基本输入输出的程序、开机后自检程序和系统自启动程序，它可从CMOS(Complementary Metal Oxide Semiconductor，互补型金属氧化物半导体)中读写系统设置的具体信息。BIOS主要功能是为计算机提供最底层的、最直接的硬件设置和控制。In this example, BIOS refers to a set of programs that are fixed to a ROM chip on the motherboard of the computer. It stores the most important basic input and output programs of the computer, the self-test program after powering on, and the system self-starting program. It can read and write specific information of system settings from CMOS (Complementary Metal Oxide Semiconductor). The main function of BIOS is to provide the lowest-level and most direct hardware settings and control for the computer.
在本示例中，UEFI可以是指一种可扩展的、标准化的固件接口规范，用来定义操作系统与系统固件之间的软件界面，作为BIOS的替代方案。可扩展固件接口负责加电自检、联系操作系统以及提供连接操作系统与硬件的接口。In this example, UEFI may refer to an extensible, standardized firmware interface specification that defines a software interface between an operating system and system firmware as an alternative to BIOS. The extensible firmware interface is responsible for power-on self-test, contacting the operating system, and providing an interface between the operating system and hardware.
在本示例中，CoreBoot可以是指一种在开源软件项目中诞生的固件，旨在替换大多数计算机中专有的BIOS。CoreBoot会执行一些硬件初始化，然后执行其他引导逻辑。通过分离硬件初始化和以后的启动逻辑，CoreBoot可以直接运行固件，在闪存中运行操作系统，加载自定义引导程序或实现固件标准的专用应用程序扩展。这使系统仅包含目标应用程序中必需的功能，从而减少了所需的代码量和闪存空间。In this example, CoreBoot can refer to a type of firmware that was born out of an open source software project and is designed to replace the proprietary BIOS in most computers. CoreBoot performs some hardware initialization and then performs other boot logic. By separating hardware initialization and later boot logic, CoreBoot can run the firmware directly, run an operating system in flash, load a custom bootloader, or implement a dedicated application extension to the firmware standard. This allows the system to include only the necessary functionality in the target application, reducing the amount of code and flash space required.
在本示例中，SlimBootloader可以是指一种专为物联网应用量身定制的计算机固件，是一款开源的启动固件解决方案，当系统上电时负责初始化系统的核心硬件组件，然后加载和启动所需要的操作系统。其具有安全性、轻量级和高度优化的特点，可以根据系统的特殊需求进行隔离、配置和优化，从而达到良好的启动性能，并最大限度地减少固件所占用的空间，同时具有模块化、可扩展设计的特点。In this example, SlimBootloader can refer to a computer firmware tailored for IoT applications. It is an open source boot firmware solution that is responsible for initializing the core hardware components of the system when the system is powered on, and then loading and starting the required operating system. It is secure, lightweight, and highly optimized. It can be isolated, configured, and optimized according to the special needs of the system to achieve good boot performance and minimize the space occupied by the firmware. It also has the characteristics of modular and scalable design.
图2示出根据本申请一实施例的MMIO地址资源分配方法的硬件架构示意图。FIG. 2 is a schematic diagram showing a hardware architecture of a method for allocating MMIO address resources according to an embodiment of the present application.
如图2所示，计算设备的主板上安装有CPU，并且插接有背板和立板。背板和立板上连接有多个PCIE设备。BMC系统能够独立地对计算设备的各个组件进行管理，因此BMC系统能够获知主板上插接的板卡和板卡上连接的PCIE外设的信息。在图2中，BMC通过I2C总线或SMBUS总线获取背板和立板上的信息，从而得到插接在其上的PCIE设备的数量、类型和型号等数据。As shown in FIG2 , a CPU is installed on the motherboard of the computing device, and a backplane and a vertical board are plugged in. Multiple PCIE devices are connected to the backplane and the vertical board. The BMC system can independently manage each component of the computing device, so the BMC system can obtain information about the boards plugged in the motherboard and the PCIE peripherals connected to the boards. In FIG2 , the BMC obtains information on the backplane and the vertical board through the I2C bus or the SMBUS bus, thereby obtaining data such as the number, type, and model of the PCIE devices plugged in thereon.
具体地，BMC系统通过I2C接口提取背板和立板的位置、数量、型号信息。在此硬件框架中，BMC通过I2C接口遍历所有外设EEPROM的I2C地址，获取到所有背板、立板、转接卡和插卡的板名(Board ID)。Specifically, the BMC system extracts the location, quantity, and model information of the backplane and vertical board through the I2C interface. In this hardware framework, the BMC traverses the I2C addresses of all peripheral EEPROMs through the I2C interface and obtains the board names (Board IDs) of all backplanes, vertical boards, adapter cards, and plug-in cards.
图3示出根据本申请一实施例的MMIO地址资源分配方法的流程示意图。FIG3 is a schematic flow chart of a method for allocating MMIO address resources according to an embodiment of the present application.
根据本实施例，MMIO地址资源分配方法包括步骤S310至步骤S330，以下详述各步骤。According to this embodiment, the MMIO address resource allocation method includes steps S310 to S330, and each step is described in detail below.
S310、通过带外控制器获取与计算设备相连接的PCIE设备的设备信息。S310. Obtain device information of a PCIE device connected to the computing device through an out-of-band controller.
在本实施例中，带外控制器具有针对计算设备的各个组件的各种情况进行独立管理的功能，借助此功能，计算设备的固件可以从带外控制器获取与计算设备相连接的PCIE设备的设备信息。PCIE设备的设备信息可以是指PCIE设备的类型、型号和制造商等信息，根据这些信息可以确定一个PCIE设备的具体种类，以便确定其需要多少MMIO地址资源。其中，PCIE设备的类型信息(例如其是声卡还是网卡)可以通过带内管理系统得到；而PCIE设备的型号(例如DeviceID(设备标识)中表明的设备型号)和制造商信息(例如Vender ID(制造商标识)中表明的制造商信息)可以通过带外管理系统(运行于带外控制器)得到。计算设备上连接的PCIE设备插接在板卡上，带外控制器可以从计算设备的板卡获取相应的设备信息，以向固件提供执行MMIO地址资源分配的依据。In this embodiment, the out-of-band controller has the function of independently managing various situations of various components of the computing device. With this function, the firmware of the computing device can obtain the device information of the PCIE device connected to the computing device from the out-of-band controller. The device information of the PCIE device may refer to the type, model and manufacturer of the PCIE device, and the specific type of a PCIE device can be determined based on this information to determine how many MMIO address resources it needs. Among them, the type information of the PCIE device (for example, whether it is a sound card or a network card) can be obtained through the in-band management system; and the model of the PCIE device (for example, the device model indicated in the DeviceID (device identification)) and the manufacturer information (for example, the manufacturer information indicated in the Vender ID (manufacturer identification)) can be obtained through the out-of-band management system (running on the out-of-band controller). The PCIE device connected to the computing device is plugged into the board, and the out-of-band controller can obtain the corresponding device information from the board of the computing device to provide the firmware with a basis for executing MMIO address resource allocation.
作为示例，为了通过带外控制器获取与计算设备相连接的PCIE设备的设备信息，可以在计算设备接通电源并启动后的开机阶段，通过带外控制器获取与计算设备相连接的PCIE设备的设备信息，其中带外控制器在计算设备接通电源但未启动的待机阶段从计算设备的板卡获取信息。As an example, in order to obtain the device information of a PCIE device connected to a computing device through an out-of-band controller, the device information of the PCIE device connected to the computing device can be obtained through the out-of-band controller during the startup phase after the computing device is powered on and started, wherein the out-of-band controller obtains information from the board of the computing device during the standby phase when the computing device is powered on but not started.
图4示出根据图3实施例的MMIO地址资源分配方法的时间分布示意图。FIG. 4 is a schematic diagram showing the time distribution of the MMIO address resource allocation method according to the embodiment of FIG. 3 .
如图4所示，在时间流逝方向上，计算设备首先处于电源断电状态中。此时，电源不插电，电源插头与电源插座断开。然后，在电源插电之后，进入BMC待机时间，此时进入待机阶段。此时，电源插电，BMC开始正常工作。然后，在用户按下计算设备的电源键之后，进入BIOS启动时间，此时待机阶段结束，进入开机阶段。此时BIOS开始启动，OS尚未启动，BMC和CPU都开始正常工作。BIOS启动完毕后，进入计算设备的运行时间或运行阶段，此时开机阶段结束，电源插电，BMC和CPU都工作正常，BIOS退出工作，OS开始工作。直到后来用户断电或意外断电，计算设备重新进入电源断电状态。As shown in FIG4 , in the direction of time flow, the computing device is first in a power-off state. At this time, the power supply is not plugged in, and the power plug is disconnected from the power socket. Then, after the power supply is plugged in, the BMC standby time is entered, and the standby stage is entered at this time. At this time, the power supply is plugged in, and the BMC starts to work normally. Then, after the user presses the power button of the computing device, the BIOS startup time is entered, and the standby stage ends at this time, and the startup stage is entered. At this time, the BIOS starts to start, the OS has not yet started, and the BMC and CPU both start to work normally. After the BIOS is started, the running time or running stage of the computing device is entered, and the startup stage ends at this time, the power supply is plugged in, the BMC and the CPU both work normally, the BIOS exits work, and the OS starts to work. Until later, the user cuts off the power or the power is cut off accidentally, the computing device re-enters the power-off state.
在BMC待机时间，BMC通过I2C总线读取PCIE设备的信息并存储。在BMC待机时间内，PCIE设备可能出现一次或多次硬件变动，例如发生插拔事件等。此时，BMC可以通过I2C总线重新读取设备信息并存储。在BIOS(或固件)启动过程中，BIOS可以从BMC获取设备参数并执行资源分配，并在后期对设备参数进行校验并执行反馈。During the BMC standby time, the BMC reads and stores the information of the PCIE device through the I2C bus. During the BMC standby time, the PCIE device may undergo one or more hardware changes, such as plug-in and unplug events. At this time, the BMC can re-read the device information through the I2C bus and store it. During the BIOS (or firmware) startup process, the BIOS can obtain device parameters from the BMC and perform resource allocation, and later verify the device parameters and perform feedback.
应理解，BMC是独立于计算设备自身的硬件(例如CPU)和软件(例如OS)的管理系统，计算设备插电时BMC就能工作。因此，BMC获取PCIE设备信息的操作可以在计算设备插电后的任何时间进行，例如开机阶段和运行阶段，并不局限于待机阶段。It should be understood that BMC is a management system independent of the hardware (such as CPU) and software (such as OS) of the computing device itself, and BMC can work when the computing device is plugged in. Therefore, the operation of BMC obtaining PCIE device information can be performed at any time after the computing device is plugged in, such as the boot stage and the running stage, and is not limited to the standby stage.
本申请提出的MMIO地址资源分配方法将从BMC正常工作开始执行，到BIOS启动完成时结束。The MMIO address resource allocation method proposed in the present application will be executed starting from the normal operation of the BMC and ending when the BIOS startup is completed.
作为示例，带外控制器包括BMC。为了通过带外控制器获取与计算设备相连接的PCIE设备的设备信息，可以通过IPMI命令从BMC获取与计算设备相连接的PCIE设备的信息。As an example, the out-of-band controller includes a BMC. In order to obtain device information of a PCIE device connected to the computing device through the out-of-band controller, the information of the PCIE device connected to the computing device may be obtained from the BMC through an IPMI command.
在本示例中，IPMI可以是指用于管理计算设备的周边设备所采用的一种工业标准。例如，IPMI能够横跨不同的操作系统、固件和硬件平台，可以智能的监视、控制和自动回报大量服务器的运作状况，以降低服务器系统成本。用户可以利用IPMI监视服务器的物理健康特征，如温度、电压、风扇工作状态、电源状态等。IPMI的核心是BMC系统。在工作时，所有的IPMI功能都是向BMC发送命令来完成的，命令使用IPMI规范中规定的指令，BMC接收并在系统事件日志中记录事件消息，维护描述系统中传感器情况的传感器数据记录。In this example, IPMI can refer to an industrial standard used to manage peripheral devices of computing devices. For example, IPMI can span different operating systems, firmware, and hardware platforms, and can intelligently monitor, control, and automatically report the operating status of a large number of servers to reduce server system costs. Users can use IPMI to monitor the physical health characteristics of the server, such as temperature, voltage, fan working status, power status, etc. The core of IPMI is the BMC system. When working, all IPMI functions are completed by sending commands to the BMC. The commands use the instructions specified in the IPMI specification. The BMC receives and records event messages in the system event log and maintains sensor data records that describe the status of sensors in the system.
作为示例，BMC通过I2C总线或SMBUS从计算设备的板卡获取信息。As an example, the BMC obtains information from a card of a computing device through an I2C bus or an SMBUS.
在本示例中，I2C总线可以是指一种简单、双线双向的同步串行总线，它利用一根时钟线和一根数据线在连接总线的两个器件之间进行信息的传递，为设备之间数据交换提供了一种简单高效的方法。每个连接到总线上的器件都有唯一的地址，任何器件既可以作为主机也可以作为从机，但同一时刻只允许有一个主机。In this example, the I2C bus can refer to a simple, two-wire bidirectional synchronous serial bus that uses a clock line and a data line to transfer information between two devices connected to the bus, providing a simple and efficient method for data exchange between devices. Each device connected to the bus has a unique address, and any device can act as a host or a slave, but only one host is allowed at the same time.
在本示例中，SMBUS可以是指一种应用于计算设备中的低速率通讯，廉价并且功能强大的总线，用于控制主板上的设备并收集相应的信息。例如，SMBUS为系统和电源管理这样的任务提供了一条控制总线，使用SMBUS的系统，设备之间发送和接收消息都是通过SMBUS，而不是使用单独的控制线，这样可以节省设备的管脚数。使用SMBUS，设备还可以提供它的生产信息，告诉系统它的型号、部件号等，针对挂起事件保存它的状态，报告不同类别的错误，接收控制参数，并返回它的状态等。In this example, SMBUS can refer to a low-speed communication, cheap and powerful bus used in computing devices to control devices on the motherboard and collect corresponding information. For example, SMBUS provides a control bus for tasks such as system and power management. In a system using SMBUS, messages are sent and received between devices through SMBUS instead of using separate control lines, which can save the number of device pins. Using SMBUS, a device can also provide its production information, tell the system its model, part number, etc., save its status for suspend events, report different types of errors, receive control parameters, and return its status, etc.
作为示例，带外控制器从计算设备的板卡获取并存储信息，信息的存储格式中包括校验位。As an example, the out-of-band controller obtains and stores information from a card of a computing device, and the information is stored in a format that includes a check bit.
在本示例中，PCIE外设的具体数据以特定格式进行编码存储，格式中存在校验位，确保数据存储、传输可靠性。In this example, the specific data of the PCIE peripheral is encoded and stored in a specific format, and there is a check bit in the format to ensure the reliability of data storage and transmission.
S320、基于预设列表，获取PCIE设备的设备信息对应的MMIO地址资源信息，预设列表指示了设备信息与MMIO地址资源信息的对应关系。S320: Based on a preset list, obtain MMIO address resource information corresponding to the device information of the PCIE device, where the preset list indicates a correspondence between the device information and the MMIO address resource information.
在本实施例中，预设列表可以是指开发者在开发过程中将所有市面上已知的PCIE设备所需MMIO地址资源大小的信息罗列出来的列表，该预设列表可以与固件存储在一起，作为固件的一部分。在预设列表中，记载有每种已知的PCIE设备与其所需要的MMIO地址资源大小之间的对应关系。根据这种对应关系，固件可以根据从带外控制器获取到的PCIE设备信息，查找到每种设备所需要的资源大小，从而进行准确的分配。在一些实施方式中，固件可以查到在不同策略下每种PCIE设备所需的MMIO资源大小，从而根据相应策略进行分配。In this embodiment, the preset list may refer to a list in which the developer lists the information of the MMIO address resource size required for all known PCIE devices on the market during the development process, and the preset list may be stored together with the firmware as part of the firmware. In the preset list, the corresponding relationship between each known PCIE device and the MMIO address resource size required by it is recorded. According to this corresponding relationship, the firmware can find the resource size required for each device based on the PCIE device information obtained from the out-of-band controller, so as to accurately allocate it. In some embodiments, the firmware can find the MMIO resource size required for each PCIE device under different strategies, so as to allocate it according to the corresponding strategy.
具体地，在计算设备的开机阶段，BIOS通过IPMI命令从BMC处获取PCIE设备信息，并与BIOS的NVROM中数据库(database)所存储的列表(例如设备基础信息列表)进行对照，制定出详细的MMIO分配策略并用于后续每个阶段合理分配MMIO资源。Specifically, during the startup phase of a computing device, BIOS obtains PCIE device information from BMC through IPMI commands, and compares it with the list stored in the database in the NVROM of BIOS (e.g., the basic device information list), formulates a detailed MMIO allocation strategy, and uses it to reasonably allocate MMIO resources in each subsequent phase.
S330、根据MMIO地址资源信息，确定为PCIE设备分配的MMIO地址资源。S330: Determine the MMIO address resources allocated to the PCIE device according to the MMIO address resource information.
在本实施例中，获取到PCIE设备的设备信息之后，可以确定其MMIO地址资源信息，从而可以知晓其所需要的MMIO地址资源大小，使得可以根据设备相应的资源需求进行MMIO地址资源的分配。In this embodiment, after the device information of the PCIE device is obtained, its MMIO address resource information can be determined, so that the required MMIO address resource size can be known, so that the MMIO address resource can be allocated according to the corresponding resource requirements of the device.
图5示出根据本申请一实施例的MMIO地址资源分配方法的流程示意图。FIG5 is a schematic flow chart showing a method for allocating MMIO address resources according to an embodiment of the present application.
根据本实施例，MMIO地址资源分配方法包括步骤S510至步骤S560，以下详述各步骤。According to this embodiment, the MMIO address resource allocation method includes steps S510 to S560, and each step is described in detail below.
S510、通过带外控制器获取与计算设备相连接的PCIE设备的设备信息。S510. Obtain device information of a PCIE device connected to the computing device through an out-of-band controller.
S520、基于预设列表，获取PCIE设备的设备信息对应的MMIO地址资源信息，预设列表指示了设备信息与MMIO地址资源信息的对应关系。S520: Based on a preset list, obtain MMIO address resource information corresponding to the device information of the PCIE device, where the preset list indicates a correspondence between the device information and the MMIO address resource information.
关于S510和S520的细节，请参见图3实施例中关于S310和S320的详细描述，这里不再赘述。For details of S510 and S520, please refer to the detailed description of S310 and S320 in the embodiment of FIG. 3, which will not be repeated here.
S530、根据查询结果，制定资源分配策略。S530: Formulate a resource allocation strategy based on the query results.
在本实施例中，查询到每个PCIE设备所需要的MMIO地址资源大小后，可以根据此查询结果分配资源。具体分配方式可以直接根据每个设备所需要的资源大小进行分配，也可以在查询结果的基础上进行一定的更改，然后再进行分配。可以根据实际情况制定多种灵活的分配策略，以应对PCIE设备可能出现的各种情况。In this embodiment, after the MMIO address resource size required by each PCIE device is queried, the resources can be allocated according to the query result. The specific allocation method can be directly allocated according to the resource size required by each device, or it can be allocated after making certain changes based on the query result. A variety of flexible allocation strategies can be formulated according to actual conditions to cope with various situations that may occur in PCIE devices.
作为示例，资源分配策略包括最小分配策略和最大分配策略，最小分配策略用于给PCIE设备分配尽可能少的MMIO地址资源，最大分配策略用于给PCIE设备分配尽可能多的MMIO地址资源。为了根据MMIO地址资源信息制定资源分配策略，可以在PCIE设备的热插拔需求较少时，采用最小分配策略；在PCIE设备的热插拔需求较多时，采用最大分配策略。As an example, the resource allocation strategy includes a minimum allocation strategy and a maximum allocation strategy. The minimum allocation strategy is used to allocate as few MMIO address resources as possible to the PCIE device, and the maximum allocation strategy is used to allocate as many MMIO address resources as possible to the PCIE device. In order to formulate a resource allocation strategy based on the MMIO address resource information, the minimum allocation strategy can be used when the hot-plug demand of the PCIE device is small; the maximum allocation strategy can be used when the hot-plug demand of the PCIE device is large.
在一些应用场景中，热插拔需求较少，意味着该计算设备在使用过程中基本或很少发生热插拔操作，导致其PCIE设备的变化可能性较小，因此可以按照查询得到的MMIO地址资源，以尽可能节约的方式分配资源，使资源基本不冗余。热插拔需求较多，意味着该计算设备在使用过程中经常会发生热插拔操作，导致其PCIE设备变换或拔插的可能性较大，因此在分配MMIO地址资源时要尽量多分配一些，形成较多的冗余，以应对PCIE设备变化导致其所需资源变大的情况。In some application scenarios, there is less demand for hot-plugging, which means that the computing device basically or rarely undergoes hot-plugging operations during use, resulting in a small possibility of changes in its PCIE devices. Therefore, resources can be allocated in a way that is as economical as possible according to the queried MMIO address resources, so that resources are basically non-redundant. There is more demand for hot-plugging, which means that the computing device often undergoes hot-plugging operations during use, resulting in a high possibility of changes or plugging of its PCIE devices. Therefore, when allocating MMIO address resources, try to allocate as many as possible to form more redundancy to cope with the situation where the required resources increase due to changes in PCIE devices.
在一些应用场景中，MMIO资源分配策略可根据研发需要而细化、替换为多种分配策略。比如对于多GPU图形计算机型，可按照最小分配策略分配，因为这种机型基本不涉及热插拔的应用场景。而对于存储类的24NVME(Non-Volatile Memory Express，非易失性内存主机控制器接口规范)直通机型，可按照最大策略分配，因为当硬盘损坏时，用户可能将旧NVME硬盘以热插拔的形式置换为需要更多MMIO资源的另一型号，导致所需MMIO资源增加。In some application scenarios, the MMIO resource allocation strategy can be refined and replaced with multiple allocation strategies according to R&D needs. For example, for multi-GPU graphics computer models, the minimum allocation strategy can be used, because this type of model basically does not involve hot-swap application scenarios. For storage-type 24NVME (Non-Volatile Memory Express, non-volatile memory host controller interface specification) pass-through models, the maximum strategy can be used, because when the hard disk is damaged, the user may replace the old NVME hard disk with another model that requires more MMIO resources in a hot-swap manner, resulting in an increase in the required MMIO resources.
在一些应用场景中，针对不同分配策略的选择，可以制作BIOS的SETUP(设置)选项，供操作人员手动选择，也可以自动选择，例如作为动态策略，在BIOS启动的BDS阶段进行自动对照和重分配决策。在自动选择时，可以在BMC获取到板卡上的PCIE设备的信息之后，查询软硬件接口文档，确定当前计算设备采用的是哪种硬件插接配置或机型。软硬件接口文档中记载有多种硬件插接配置，每种配置包括一整套PCIE设备的搭配，可以采用不同的MMIO资源分配策略。在一些配置中，PCIE设备需要按照最大分配策略来进行分配。例如，当PCIE设备是硬盘时，由于硬盘经常需要更换，并且可能更换成为需要更多MMIO资源的型号，因此需要给插接硬盘的接口或根端口分配尽可能多的MMIO资源。例如，可以按照已知的或市场上在售的所有硬盘中所需MMIO地址资源的最大值来分配。在一些配置中，PCIE设备可以按照最小分配策略来进行分配。例如，当PCIE设备是GPU时，由于GPU很少发生热插拔应用场景，因此直接按照查询列表得到的GPU所需MMIO地址资源进行分配即可，无需留有余量。In some application scenarios, for the selection of different allocation strategies, a BIOS SETUP option can be created for manual selection by the operator, or it can be automatically selected, for example, as a dynamic strategy, in the BDS stage of BIOS startup, automatic comparison and reallocation decision-making. When automatically selecting, after the BMC obtains the information of the PCIE device on the board, the software and hardware interface document can be queried to determine which hardware plug-in configuration or model the current computing device uses. The software and hardware interface document records a variety of hardware plug-in configurations, each of which includes a complete set of PCIE device combinations, and different MMIO resource allocation strategies can be adopted. In some configurations, the PCIE device needs to be allocated according to the maximum allocation strategy. For example, when the PCIE device is a hard disk, since the hard disk often needs to be replaced and may be replaced with a model that requires more MMIO resources, it is necessary to allocate as many MMIO resources as possible to the interface or root port where the hard disk is plugged in. For example, it can be allocated according to the maximum value of the required MMIO address resources among all hard disks known or on the market. In some configurations, the PCIE device can be allocated according to the minimum allocation strategy. For example, when the PCIE device is a GPU, since hot-plugging of GPUs is rarely used, the MMIO address resources required by the GPU obtained from the query list can be directly allocated without leaving any margin.
S540、根据资源分配策略，确定为所述PCIE设备分配的MMIO地址资源。S540: Determine the MMIO address resources allocated to the PCIE device according to the resource allocation strategy.
在本实施例中，制定好资源分配策略之后，可以确定每个PCIE设备所要分配的MMIO地址资源，使得计算设备的固件可以在开机后的固件启动阶段针对PCIE设备进行资源分配。这里的分配可以是指直接针对具体设备的分配，也可以是指针对PCIE设备树形结构的根节点或其它节点的分配。In this embodiment, after the resource allocation strategy is formulated, the MMIO address resources to be allocated to each PCIE device can be determined, so that the firmware of the computing device can allocate resources to the PCIE device during the firmware startup phase after booting. The allocation here can refer to allocation directly to a specific device, or to allocation to the root node or other nodes of the PCIE device tree structure.
S550、判断设备信息与PCIE枚举过程中发现的PCIE设备信息是否匹配。S550: Determine whether the device information matches the PCIE device information found during the PCIE enumeration process.
在本实施例中，PCIE枚举可以是指CPU启动后找到并认出PCIE设备的过程。在枚举过程中，CPU对PCIE设备采用深度优先算法进行扫描，对每一个可能的分支路径深入到不能再深入为止，而且每个节点只能访问一次。例如，PCIE枚举过程一般包括：创建根节点；扫描根节点下设备；为根节点下设备分配资源。In this embodiment, PCIE enumeration may refer to the process of finding and recognizing PCIE devices after the CPU is started. During the enumeration process, the CPU uses a depth-first algorithm to scan PCIE devices, and goes deep into each possible branch path until it cannot go deeper, and each node can only be accessed once. For example, the PCIE enumeration process generally includes: creating a root node; scanning devices under the root node; and allocating resources to the devices under the root node.
图6示出根据图5实施例的MMIO地址资源分配方法的流程示意图。FIG. 6 is a schematic flow chart showing a method for allocating MMIO address resources according to the embodiment of FIG. 5 .
具体地，如图6所示，计算设备的固件在启动后，通过IPMI命令从BMC获取PCIE设备的信息数据。获取到数据后，固件开始解析数据并根据数据准确分配MMIO地址资源。然后进行PCIE枚举过程。在枚举过程中，固件会将从BMC读取到的设备数据与枚举过程中发现的设备数据进行比较，判断BMC提供的数据与实际发现的数据是否匹配。Specifically, as shown in FIG6 , after the firmware of the computing device is started, it obtains the information data of the PCIE device from the BMC through the IPMI command. After obtaining the data, the firmware begins to parse the data and accurately allocates MMIO address resources according to the data. Then the PCIE enumeration process is performed. During the enumeration process, the firmware compares the device data read from the BMC with the device data found during the enumeration process to determine whether the data provided by the BMC matches the actual found data.
在本实施例中，计算设备启动时的MMIO资源分配过程中存在设备扫描、检验、设备数据重计算和IPMI命令反馈机制，确保MMIO资源分配过程不被启动过程中的硬件损坏所影响。In this embodiment, the MMIO resource allocation process when the computing device is started includes device scanning, checking, device data recalculation and IPMI command feedback mechanisms to ensure that the MMIO resource allocation process is not affected by hardware damage during the startup process.
S560、若否，将不匹配结果发送至带外控制器，使带外控制器获取与计算设备相连接的PCIE设备的更新设备信息。S560: If not, send the mismatch result to the out-of-band controller, so that the out-of-band controller obtains the updated device information of the PCIE device connected to the computing device.
具体地，如图6所示，如果在PCIE设备枚举过程中，发现从BMC读取的设备信息数据与枚举过程中发现的设备信息数据不匹配，则通过IPMI命令将数据错误信息上报给BMC，使BMC重新扫描I2C或SMBUS，获取新的设备信息。除了通过PCIE枚举启动BMC的重新扫描动作或自检动作以外，还可以在BMC待机时间中，定时轮询各个板卡上的PCIE设备信息，如果发现设备变动可以启动重新扫描。另外，由硬件产生的变化比如线缆拔插也可以通过CPLD中断启动BMC的重新扫描或自检操作。Specifically, as shown in FIG6 , if during the PCIE device enumeration process, it is found that the device information data read from the BMC does not match the device information data found during the enumeration process, the data error information is reported to the BMC through the IPMI command, so that the BMC rescans the I2C or SMBUS to obtain new device information. In addition to initiating the BMC rescanning action or self-test action through PCIE enumeration, the PCIE device information on each board can also be periodically polled during the BMC standby time, and a rescan can be initiated if a device change is found. In addition, changes caused by hardware, such as cable plugging and unplugging, can also initiate a BMC rescan or self-test operation through a CPLD interrupt.
此后，在计算设备的下一个运行周期(例如下一次开机启动)中的待机阶段，可以从带外控制器获取更新设备信息，然后根据更新设备信息，重新确定为所述PCIE设备分配的MMIO地址资源。Thereafter, in the standby phase of the next operating cycle (eg, the next boot) of the computing device, the updated device information can be obtained from the out-of-band controller, and then the MMIO address resources allocated to the PCIE device can be re-determined based on the updated device information.
具体地，如图6所示，通过IPMI命令将数据不匹配的情况上报给BMC之后，BMC重新扫描I2C或SMBUS，获取PCIE设备的更新信息，将新的数据写入BMC系统的ROM中。此时，计算设备的固件再次从BMC系统获取PCIE设备的信息，得到更新后的信息。当通过IPMI命令重新获取到更新信息之后，可以再次解析PCIE设备的信息数据并据此准确分配MMIO地址资源。Specifically, as shown in FIG6 , after the data mismatch is reported to the BMC through the IPMI command, the BMC rescans the I2C or SMBUS to obtain the update information of the PCIE device and writes the new data into the ROM of the BMC system. At this time, the firmware of the computing device obtains the information of the PCIE device from the BMC system again to obtain the updated information. After the update information is re-obtained through the IPMI command, the information data of the PCIE device can be parsed again and the MMIO address resources can be accurately allocated accordingly.
图7示出根据本申请一实施例的MMIO地址资源分配方法的架构示意图。FIG. 7 is a schematic diagram showing the architecture of a method for allocating MMIO address resources according to an embodiment of the present application.
如图7所示，在MMIO技术中，从抽象行为上看，CPU通过内存控制PCIE设备。而实际行为是，CPU的IO指令会通过PCIE物理电路进行传输，链路的上层协议程序会解析IO指令。As shown in Figure 7, in MMIO technology, from an abstract behavior point of view, the CPU controls the PCIE device through the memory. The actual behavior is that the CPU's IO instructions will be transmitted through the PCIE physical circuit, and the upper layer protocol program of the link will parse the IO instructions.
在本实施例中，PCIE设备与CPU之间的通信结构构成树形结构。树形结构的根部可以称为根桥(RootBridge)，例如AMD公司采用此术语。一些本领域技术中，例如根据Intel公司采用的术语，树形结构的根节点的可以称为stack(栈)。在BIOS领域，树形结构的根节点也可称为RootComplex(根复合体)。In this embodiment, the communication structure between the PCIE device and the CPU forms a tree structure. The root of the tree structure can be called a root bridge (RootBridge), for example, AMD uses this term. In some technical fields, for example, according to the terminology used by Intel, the root node of the tree structure can be called a stack. In the BIOS field, the root node of the tree structure can also be called a RootComplex.
CPU与根桥之间通常包含多个通道(lane)。根据硬件的设计，可以将根桥分为多个根端口(RootPort)，每个根端口包含多个通道。通过往PCIE的Root管理芯片里写寄存器，可以把根桥分配成不同的根端口。例如，一个具有16个通道(即x16)的根桥，硬件将它分成3个根端口，其中1个根端口具有8个通道(即x8)，用来插接GPU(Graphics Processing Unit，图形处理器)或显卡；另外2个根端口分别具有4个通道，分别用来插接1个网卡和1个OCP(OpenCompute Project，开源计算机项目)网卡。其中8+4+4＝16。1个根桥就被分配成了3个根端口。根端口上可以插接任何与之匹配的PCIE设备，上述例子中插接了3个末端设备(EndDevice)，但其实也可以插接转接桥，比如可以将1个具有4个通道的根端口转接成4个具有1个通道的根端口，就可以把4个只需要1个通道的PCIE设备插接在这些根端口上。There are usually multiple lanes between the CPU and the root bridge. According to the hardware design, the root bridge can be divided into multiple root ports, each of which contains multiple lanes. By writing registers to the PCIE root management chip, the root bridge can be assigned to different root ports. For example, a root bridge with 16 lanes (i.e. x16) is divided into 3 root ports by hardware, one of which has 8 lanes (i.e. x8) and is used to plug in a GPU (Graphics Processing Unit) or graphics card; the other two root ports have 4 lanes each, which are used to plug in a network card and an OCP (Open Compute Project) network card respectively. Among them, 8+4+4=16. One root bridge is assigned to 3 root ports. Any matching PCIE device can be plugged into the root port. In the above example, three end devices (EndDevice) are plugged in, but in fact, a transfer bridge can also be plugged in. For example, a root port with 4 channels can be transferred into 4 root ports with 1 channel, and 4 PCIE devices that only need 1 channel can be plugged into these root ports.
在本实施例中，在分配MMIO地址资源时，包括两个步骤。第一步是给根桥分配MMIO地址资源，第二步是给根端口分配MMIO地址资源。在本实施例中，针对根桥分配MMIO地址资源时，可以采用本申请的分配方法；针对根端口的分配，可以采用传统方法或其它方法分配。由于针对根桥的分配会影响针对根端口的分配，因此本实施例的MMIO地址资源分配方法仍然能够影响每个PCIE设备最终分到的MMIO地址资源的大小。In this embodiment, when allocating MMIO address resources, two steps are included. The first step is to allocate MMIO address resources to the root bridge, and the second step is to allocate MMIO address resources to the root port. In this embodiment, when allocating MMIO address resources to the root bridge, the allocation method of this application can be used; for the allocation of the root port, the traditional method or other methods can be used. Since the allocation to the root bridge will affect the allocation to the root port, the MMIO address resource allocation method of this embodiment can still affect the size of the MMIO address resources ultimately allocated to each PCIE device.
在本实施例中，以一台服务器为例，其主板插接1个硬盘背板BC15NHBA，另外插接3个立板(例如IoRiser转接卡)分别是BC15PRUE、BC15PRUI、BC15PRUC。In this embodiment, taking a server as an example, its mainboard is plugged with a hard disk backplane BC15NHBA, and three risers (such as IoRiser adapter cards) are plugged in, namely BC15PRUE, BC15PRUI, and BC15PRUC.
在本实施例中，每个CPU具有4个根端口，比如CPU1的P0、P1、P2、P3。每个根端口可以对应一个或多个线缆接口。例如，CPU1的P0根端口对应UBC1-1和UBC1-2两个线缆接口。对于没有桥接结构的主板，1个根端口对应1个线缆接口；对于有桥主板，比如具有1转2、或1转4的桥接芯片，芯片会把1个根端口分为2或4个线缆接口。In this embodiment, each CPU has four root ports, such as P0, P1, P2, and P3 of CPU1. Each root port can correspond to one or more cable interfaces. For example, the P0 root port of CPU1 corresponds to two cable interfaces, UBC1-1 and UBC1-2. For a motherboard without a bridge structure, one root port corresponds to one cable interface; for a motherboard with a bridge, such as a 1-to-2 or 1-to-4 bridge chip, the chip will divide one root port into 2 or 4 cable interfaces.
在本实施例中，UBC1-1可能会插接SATA(Serial Advanced TechnologyAttachment，串行高技术配置)背板，其不占用MMIO资源。UBC1-2可能会插接RAID(Redundant Arrays of Independent Disks，独立冗余磁盘阵列)卡，最大可占用12MB的MMIO地址空间。In this embodiment, UBC1-1 may be plugged into a SATA (Serial Advanced Technology Attachment) backplane, which does not occupy MMIO resources. UBC1-2 may be plugged into a RAID (Redundant Arrays of Independent Disks) card, which can occupy up to 12MB of MMIO address space.
在初始情况下，以CPU上的根端口为单位进行分配，按照平均分配原则，各自分发10MB，共占用80MB的MMIO地址空间。如表1所示。Initially, the root ports on the CPU are used as units for allocation, and 10 MB is allocated to each port according to the principle of average allocation, occupying a total of 80 MB of MMIO address space, as shown in Table 1.
表1Table 1
在插接电源之后，服务器从断电状态进入BMC待机状态，此状态下BMC通过I2C总线访问各个背板、立板上的EEPROM芯片，获取到各个背板的名称(例如BoardID)及线缆插接情况。After the power is plugged in, the server enters the BMC standby state from the power-off state. In this state, the BMC accesses the EEPROM chips on each backplane and riser through the I2C bus to obtain the name of each backplane (such as BoardID) and the cable plug-in status.
点击开机按钮，CPU在初始化过程中通过IPMI命令获取到信息，根据此信息可分析出本机使用的是软硬件接口文档中的特定搭配，然后根据BIOS预置的关于此搭配的数据，知悉每个接口上可能插接的设备。When you click the power button, the CPU obtains information through IPMI commands during initialization. Based on this information, it can be analyzed that the machine uses a specific combination in the software and hardware interface document. Then, based on the data about this combination preset by the BIOS, it can be known what devices may be plugged into each interface.
在本实施例中，软硬件接口文档可以是指BIOS的数据库(database)中存储的一种文档，其记载有多种硬件插接配置(或搭配)，每种硬件插接配置包括计算设备的各个接口所需插接的一整套PCIE设备。不同的配置可以对应不同的机型。在不同的配置中，计算设备的各个接口所插接的PCIE设备可能不同。因此，通过BMC获取到PCIE设备的信息后，通过对照软硬件接口文档，可以确定计算设备采取的是哪种硬件配置，根据该配置可以确定计算设备采用的是哪种机型，也可以用于帮助确定相应接口(例如线缆接口或根端口)应当分配的MMIO资源大小。In this embodiment, the software and hardware interface document may refer to a document stored in the database of the BIOS, which records a variety of hardware plug-in configurations (or combinations), and each hardware plug-in configuration includes a complete set of PCIE devices that need to be plugged into each interface of the computing device. Different configurations may correspond to different models. In different configurations, the PCIE devices plugged into each interface of the computing device may be different. Therefore, after obtaining the information of the PCIE device through the BMC, by comparing the software and hardware interface document, it can be determined which hardware configuration the computing device adopts, and based on the configuration, it can be determined which model the computing device adopts, and it can also be used to help determine the size of MMIO resources that should be allocated to the corresponding interface (such as a cable interface or a root port).
软硬件接口文档可以和BIOS中存储的列表(例如设备基础信息列表)配合使用。在一些情况下，如果能够获知线缆接口上插接的设备型号，则可以直接通过设备基础信息列表进行查找，确认其所需要的MMIO地址资源大小。如果此时线缆接口上没有插接设备，则可以通过软硬件接口文档进行查找，确定此时计算设备所采用的硬件插接配置，从而根据特定配置中的信息预判此接口上将要或可能插接什么样的设备，从而提前确认其所需要的MMIO地址资源大小。The software and hardware interface documents can be used in conjunction with the lists stored in the BIOS (such as the device basic information list). In some cases, if the model of the device plugged into the cable interface is known, it can be directly searched through the device basic information list to confirm the required MMIO address resource size. If there is no device plugged into the cable interface at this time, the software and hardware interface documents can be searched to determine the hardware plug-in configuration used by the computing device at this time, so as to predict what kind of device will or may be plugged into this interface based on the information in the specific configuration, thereby confirming the required MMIO address resource size in advance.
然后，针对每个根桥进行MMIO资源的预分配。此次分配是总分配，分配结果如表2所示。然后针对根端口再次进行细化的分配，细节分配结果不再赘述。Then, MMIO resources are pre-allocated for each root bridge. This allocation is a total allocation, and the allocation results are shown in Table 2. Then, detailed allocation is performed again for the root port, and the detailed allocation results are not repeated here.
表2Table 2
本实施例通过带外管理芯片的I2C通信接口遍历板卡EEPROM获取的插接信息，让CPU通过IPMI命令在CPU启动的早期阶段就能获取具体的硬件配置，从而针对性地给各个根桥分配MMIO物理内存资源。相较于初始状态，本实施例节省MMIO物理内存资源28MB，是初始分配状态的35％，可提高操作系统性能。另外，本实施例消除由个别PCIE设备所带来的资源不足(out of resource)的错误风险，可提高机器运行的稳定性。This embodiment uses the I2C communication interface of the out-of-band management chip to traverse the board EEPROM to obtain the plug-in information, so that the CPU can obtain the specific hardware configuration through the IPMI command in the early stage of CPU startup, so as to allocate MMIO physical memory resources to each root bridge in a targeted manner. Compared with the initial state, this embodiment saves 28MB of MMIO physical memory resources, which is 35% of the initial allocation state, and can improve the performance of the operating system. In addition, this embodiment eliminates the error risk of insufficient resources (out of resource) caused by individual PCIE devices, which can improve the stability of machine operation.
基于前述图2所述的方法实施例，本申请实施例还提供一种MMIO地址资源分配装置，其结构示意图如图8所示。该装置用于执行前述图2中的各个步骤。Based on the method embodiment shown in FIG2 , the present application also provides an MMIO address resource allocation device, the structure diagram of which is shown in FIG8 . The device is used to execute each step in FIG2 .
根据本实施例，装置包括第一获取模块810、第二获取模块820和确定模块830。第一获取模块810用于通过带外控制器获取与计算设备相连接的PCIE设备的设备信息。第二获取模块820用于基于预设列表，获取PCIE设备的设备信息对应的MMIO地址资源信息，预设列表指示了设备信息与MMIO地址资源信息的对应关系。确定模块830用于根据MMIO地址资源信息，确定为PCIE设备分配的MMIO地址资源According to this embodiment, the device includes a first acquisition module 810, a second acquisition module 820 and a determination module 830. The first acquisition module 810 is used to obtain device information of a PCIE device connected to a computing device through an out-of-band controller. The second acquisition module 820 is used to obtain MMIO address resource information corresponding to the device information of the PCIE device based on a preset list, and the preset list indicates the correspondence between the device information and the MMIO address resource information. The determination module 830 is used to determine the MMIO address resource information allocated to the PCIE device according to the MMIO address resource information.
需要说明的是，图8所示实施例提供的MMIO地址资源分配装置800在执行方法时，仅以上述各功能模块的划分举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能模块完成，即将装置的内部结构划分成不同的功能模块，以完成以上描述的全部或者部分功能。另外，上述实施例提供的装置800与图2所示的方法实施例分别属于同一构思，其具体实现过程详见方法实施例，这里不再赘述。It should be noted that, when the MMIO address resource allocation device 800 provided in the embodiment shown in FIG8 executes the method, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functional allocation can be completed by different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the device 800 provided in the above embodiment and the method embodiment shown in FIG2 belong to the same concept, and the specific implementation process is detailed in the method embodiment, which will not be repeated here.
图9是本申请实施例提供一种计算设备900的硬件结构示意图。FIG. 9 is a schematic diagram of the hardware structure of a computing device 900 provided in an embodiment of the present application.
参见图9，该计算设备900包括处理器910、存储器920、通信接口930和总线940，处理器910、存储器920和通信接口930通过总线940彼此连接。处理器910、存储器920和通信接口930也可以采用除了总线940之外的其他连接方式连接。9 , the computing device 900 includes a processor 910, a memory 920, a communication interface 930, and a bus 940, wherein the processor 910, the memory 920, and the communication interface 930 are connected to each other via the bus 940. The processor 910, the memory 920, and the communication interface 930 may also be connected in other connection modes besides the bus 940.
其中，存储器920可以是各种类型的存储介质，例如随机存取存储器(randomaccess memory，RAM)、只读存储器(read-only memory，ROM)、非易失性RAM(non-volatileRAM，NVRAM)、可编程ROM(programmable ROM，PROM)、可擦除PROM(erasable PROM，EPROM)、电可擦除PROM(electrically erasable PROM，EEPROM)、闪存、光存储器、硬盘等。Among them, the memory 920 can be various types of storage media, such as random access memory (RAM), read-only memory (ROM), non-volatile RAM (NVRAM), programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), flash memory, optical storage, hard disk, etc.
其中，处理器910可以是通用处理器，通用处理器可以是通过读取并执行存储器(例如存储器920)中存储的内容来执行特定步骤和/或操作的处理器。例如，通用处理器可以是中央处理器(central processing unit，CPU)。处理器910可以包括至少一个电路，以执行图2所示实施例提供的MMIO地址资源分配方法的全部或部分步骤。The processor 910 may be a general-purpose processor, which may be a processor that performs specific steps and/or operations by reading and executing the contents stored in a memory (e.g., memory 920). For example, the general-purpose processor may be a central processing unit (CPU). The processor 910 may include at least one circuit to perform all or part of the steps of the MMIO address resource allocation method provided in the embodiment shown in FIG. 2.
其中，通信接口930包括输入/输出(input/output，I/O)接口、物理接口和逻辑接口等用于实现计算设备900内部的器件互连的接口，以及用于实现计算设备900与其他设备(例如其他计算设备或用户设备)互连的接口。物理接口可以是以太网接口，光纤接口，ATM接口等。通信接口930可以外接输入装置和输出装置。例如，输入装置可以是麦克风或麦克风阵列，用于捕捉语音输入信号；可以是通信网络连接器，用于从云端或其它设备接收所采集的输入信号；还可以包括例如键盘、鼠标等等。输出装置可以向外部输出各种信息，包括确定出的距离信息、方向信息等。输出装置可以包括例如显示器、扬声器、打印机、以及通信网络及其所连接的远程输出设备等等。Among them, the communication interface 930 includes input/output (I/O) interfaces, physical interfaces, and logical interfaces for interconnecting devices within the computing device 900, as well as interfaces for interconnecting the computing device 900 with other devices (such as other computing devices or user devices). The physical interface can be an Ethernet interface, an optical fiber interface, an ATM interface, etc. The communication interface 930 can be connected to an external input device and an output device. For example, the input device can be a microphone or a microphone array for capturing voice input signals; it can be a communication network connector for receiving collected input signals from the cloud or other devices; it can also include, for example, a keyboard, a mouse, etc. The output device can output various information to the outside, including determined distance information, direction information, etc. The output device can include, for example, a display, a speaker, a printer, a communication network and a remote output device connected thereto, etc.
其中，总线940可以是任何类型的，用于实现处理器910、存储器920和通信接口930互连的通信总线，例如系统总线。The bus 940 may be any type of communication bus for interconnecting the processor 910 , the memory 920 , and the communication interface 930 , such as a system bus.
上述器件可以分别设置在彼此独立的芯片上，也可以至少部分的或者全部的设置在同一块芯片上。将各个器件独立设置在不同的芯片上，还是整合设置在一个或者多个芯片上，往往取决于产品设计的需要。本申请实施例对上述器件的具体实现形式不做限定。The above devices may be arranged on independent chips, or at least partially or completely on the same chip. Whether to arrange each device independently on different chips or to integrate them on one or more chips often depends on the needs of product design. The embodiments of the present application do not limit the specific implementation form of the above devices.
图9所示的计算设备900仅仅是示例性的，在实现过程中，计算设备900还可以包括其他组件，本文不再一一列举。The computing device 900 shown in FIG. 9 is merely exemplary. During implementation, the computing device 900 may further include other components, which are not listed one by one herein.
本申请的实施例还可以是计算机可读存储介质，其上存储有计算机程序指令，所述计算机程序指令在被处理器运行时使得所述处理器执行本说明书上文中描述的根据本申请各种实施例的MMIO地址资源分配方法中的步骤。The embodiment of the present application may also be a computer-readable storage medium having computer program instructions stored thereon. When the computer program instructions are executed by a processor, the processor executes the steps of the MMIO address resource allocation method according to various embodiments of the present application described above in this specification.
所述计算机可读存储介质可以采用一个或多个可读介质的任意组合。可读介质可以是可读信号介质或者可读存储介质。可读存储介质例如可以包括但不限于电、磁、光、电磁、红外线、或半导体的系统、装置或器件，或者任意以上的组合。可读存储介质的更具体的例子(非穷举的列表)包括：具有一个或多个导线的电连接、便携式盘、硬盘、随机存取存储器(RAM)、只读存储器(ROM)、可擦式可编程只读存储器(EPROM或闪存)、光纤、便携式紧凑盘只读存储器(CD-ROM)、光存储器件、磁存储器件、或者上述的任意合适的组合。The computer readable storage medium can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium can include, for example, but is not limited to, a system, device or device of electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.
以上结合具体实施方式(包括实施例和实例)详细描述了本申请的概念、原理和思想。本领域技术人员应理解，本申请的实施方式不止上文给出的这几种形式，本领域技术人员在阅读本申请文件以后，可以对上述实施方式中的步骤、方法、装置、部件做出任何可能的改进、替换和等同形式，这些改进、替换和等同形式应视为落入在本申请的范围内。本申请的保护范围仅以权利要求书为准。The concepts, principles and ideas of the present application are described in detail above in conjunction with specific implementation methods (including embodiments and examples). Those skilled in the art should understand that the implementation methods of the present application are more than the several forms given above. After reading the application documents, those skilled in the art can make any possible improvements, replacements and equivalent forms to the steps, methods, devices and components in the above-mentioned implementation methods, and these improvements, replacements and equivalent forms should be deemed to fall within the scope of the present application. The scope of protection of the present application shall be subject only to the claims.
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| TA01 | Transfer of patent application right | Effective date of registration:20250721 Address after:10/F, Chuangzhi Tiandi Building, Dongshigeng Street, Zhongdao East Road, Longzihu Wisdom Island, Zhengdong New District, Zhengzhou City, Henan Province, 450000 Applicant after:Henan Kunlun Technology Co.,Ltd. Country or region after:China Address before:450000 Floor 9, building 1, Zhengshang Boya Plaza, Longzihu smart Island, Zhengdong New District, Zhengzhou City, Henan Province Applicant before:xFusion Digital Technologies Co., Ltd. Country or region before:China | |
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