Detailed Description
Embodiments of the present invention are described below. It is noted that an embodiment of the present invention is not limited to the following description, and one of ordinary skill in the art can easily understand the fact that the manner and details thereof can be changed into various forms without departing from the spirit and scope of the present invention. Therefore, one embodiment of the present invention should not be construed as being limited to the description of the embodiments described below.
Note that, in this specification and the like, ordinal numbers such as "first", "second", "third", and the like are added to avoid confusion of constituent elements. Therefore, the ordinal words do not limit the number of constituent elements. The ordinal words do not limit the order of the constituent elements. For example, in the present specification and the like, a constituent element referred to as "first" in one embodiment may be set as a constituent element referred to as "second" in other embodiments or claims. For example, in the present specification and the like, the constituent element referred to as "first" in one embodiment may be omitted in other embodiments or claims.
In the drawings, the same reference numerals are used to denote the same components, components having the same functions, components made of the same materials, components formed simultaneously, or the like, and overlapping descriptions may be omitted.
In this specification, the power supply potential VDD may be simply referred to as potential VDD, or the like. Other components (e.g., signals, voltages, circuits, elements, electrodes, wiring, etc.) are also similar.
When the same symbol is used for a plurality of elements and it is necessary to distinguish them, a symbol for identification such as "_1", "_2", "[ n ]", and "[ m, n ]" may be added to the symbol. For example, the second gate line GL is denoted as gate line GL [2].
(Embodiment 1)
A configuration example of a display device according to an embodiment of the present invention will be described with reference to fig. 1A to 22.
< Structural example of display device 1>
A structure of a display device according to an embodiment of the present invention will be described with reference to fig. 1A and 1B. Fig. 1A and 1B are schematic perspective views of a display device 200.
The display device 200 includes a substrate 11 and a substrate 12. The display device 200 includes a display portion 13 constituted by elements provided between the substrate 11 and the substrate 12. The display unit 13 is divided into a plurality of sections, and any one of the sections is referred to as a sub-display unit 13A.
In addition, in the display device 200, the layer 20, the layer 50, and the layer 60 are provided between the substrate 11 and the substrate 12. The display device 200 can display various signals and power supply potentials by being externally input through the terminal portion 14.
The layer 20 is provided with a plurality of gate line driving circuits for driving the display device 200. In the driving circuit section 30 provided with a plurality of gate line driving circuits, the gate line driving circuits are provided for the respective sections 39 provided in the layer 20. The section 39 is a region corresponding to the sub display unit 13A. In addition, the layer 20 is provided with a source line driving circuit 40 or a driving circuit section 30 for driving the display device 200, and a control circuit 41 for controlling the source line driving circuit.
The control circuit 41 may also include an LVDS (Low Voltage DIFFERENTIAL SIGNALING: low Voltage differential signaling) circuit, an MIPI (Mobile Industry Processor Interface: mobile industry processor interface) circuit, a D/a (Digital to Analog: analog-to-digital) conversion circuit, or the like having a function as an interface for receiving image data or the like from outside the display device 200. The control circuit 41 may include a circuit for compressing and decompressing image data, a power supply circuit, and the like.
Since the driving circuit portion 30 provided with the gate line driving circuit is disposed so as to overlap the display portion 13, the width of a non-display region (also referred to as a frame) existing on the outer periphery of the display portion of the display device 200 can be made extremely narrow, compared with the case where the driving circuit portion 30 and the display portion 13 are disposed side by side, and thus the display device 200 can be miniaturized.
By disposing the region 39 where the gate line driver circuit is provided, the source line driver circuit 40, and the control circuit 41 so as to be close to each other, wiring for electrically connecting the circuits can be shortened. Therefore, the charge/discharge time of the control signal for controlling each circuit becomes short, and power consumption can be reduced.
The layer 20 is a layer provided with transistors included in the gate line driver circuit. Silicon is used for the semiconductor layer including the channel formation region in the transistor provided in the layer 20. In particular, as a transistor provided in the layer 20, a transistor including polysilicon in a semiconductor layer including a channel formation region (also referred to as a "Poly-Si transistor") is used. As the polysilicon, low temperature polysilicon (LTPS: low Temperature Poly Silicon) is preferably used. A transistor including LTPS in a channel formation region is also referred to as an "LTPS transistor". By using LTPS transistors as transistors included in the layer 20, a glass substrate can be used as the substrate 11, and thus, the display device 200 can be reduced in cost and increased in area. The substrate 11 may be a flexible substrate such as a resin film.
As a transistor provided in the layer 20, a transistor (an OS transistor) including a metal oxide (also referred to as an oxide semiconductor) in a semiconductor layer including a channel formation region can also be used.
The source line driver circuit 40 or the control circuit 41 may be configured to have a connector such as an FPC (Flexible Printed Circuit: flexible printed circuit) or a TCP (TAPE CARRIER PACKAGE: tape carrier package) mounted thereon, or may be configured to directly mount an IC (integrated circuit) On the substrate 11 by a COG (Chip On Glass) method.
The layer 50 is provided with a plurality of pixel circuits for independently controlling a plurality of display elements provided in the layer 60. In the pixel circuit section 57 provided with a plurality of pixel circuits, a pixel circuit is provided for each of the sections 59 provided in the layer 50. Like the section 39, the section 59 is a region corresponding to the sub display section 13A.
The layer 50 is a layer provided with transistors included in a pixel circuit. As a transistor provided in the layer 50, an OS transistor is preferably used. When the transistor included in the layer 50 is an OS transistor, the transistor may be provided so as to overlap with a layer including another transistor such as an LTPS transistor. By overlapping the transistors, the occupied area of the pixel circuit is reduced. Accordingly, the definition of the display device 200 can be improved. Note that the structure of the combination LTPS transistor and OS transistor is sometimes referred to as LTPO.
The OS transistor has a characteristic of extremely small off-state current. Therefore, particularly when an OS transistor is used as a transistor provided in a pixel circuit, analog data written in the pixel circuit can be held for a long period of time, which is preferable.
Examples of the metal oxide used for the OS transistor include Zn oxide, zn—sn oxide, ga—sn oxide, in—ga oxide, in—zn oxide, and in—m—zn oxide (M is Ti, ga, Y, zr, la, ce, nd, sn or Hf). In particular, when a metal oxide using Ga as M is used for an OS transistor, a transistor having excellent electrical characteristics such as field effect mobility can be formed by adjusting the element ratio, which is preferable. In addition, the oxide containing indium and zinc may further contain one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like.
A plurality of display elements 61 are provided on the layer 60. The substrate 12 on the layer 60 is preferably a substrate using a material having light transmittance. The display element 61 may be a light emitting device. As the light-emitting device, for example, an organic electroluminescent element (also referred to as an organic EL element) or the like can be used. However, the light-emitting device is not limited thereto, and for example, an inorganic EL element made of an inorganic material may be used. Note that "organic EL element" and "inorganic EL element" are sometimes collectively referred to as "EL element". The light emitting device may also contain an inorganic compound such as a quantum dot. For example, by using quantum dots for the light emitting layer, the quantum dots can be used as a light emitting material.
In this specification and the like, the "element" may be sometimes referred to as a "device". For example, the display element and the light-emitting element may be referred to as a display device and a light-emitting device, respectively.
In one embodiment of the present invention, an example in which the transistor included in the pixel circuit is an OS transistor is described, but other structures may be employed. For example, as a transistor included in the pixel circuit, an LTPS transistor may be included in addition to an OS transistor.
For example, since an N-type (N-channel type) metal oxide typified by an in—ga—zn oxide is used for an OS transistor, a CMOS (Complementary Metal Oxide Semiconductor: complementary metal oxide semiconductor) circuit can be configured by combining with an LTPS transistor to configure a pixel circuit. By employing a pixel circuit including a CMOS circuit, a circuit with high driving capability and low power consumption can be realized. In addition, since LTPS transistors of N type (N channel type) and P type (P channel type) do not need to be separately manufactured, the process cost of the display device 200 can be reduced.
In addition, although a structure using an OS transistor or an LTPS transistor is shown as a transistor included in the gate line driver circuit, other structures may be employed. As the transistor included in the gate line driving circuit, an OS transistor may be included in addition to the LTPS transistor. In this case, the gate line driver circuit can be a CMOS circuit using an n-channel type OS transistor and a p-channel type LTPS transistor, and thus the CMOS circuit can be realized without using an n-channel type LTPS transistor. Therefore, as compared with the case where the gate line driver circuit is configured using only an n-channel transistor, a circuit having both the feature of high driving capability when an LTPS transistor is used and the feature of low power consumption due to small off-state current of an OS transistor can be realized. In addition, since LTPS transistors of N type (N channel type) and P type (P channel type) do not need to be separately manufactured, the process cost of the display device 200 can be reduced.
Fig. 2A shows a configuration example of the pixel circuit portion 57 included in the display device 200. Fig. 2B shows a configuration example of the driving circuit portion 30 included in the display device 200. Each of the sections 59 and 39 is arranged in a matrix of m rows and n columns (m and n are integers of 1 or more). In the present specification, the 1 st row and 1 st column section 59 is denoted as section 59[1,1], and the mth row and n column section 59 is denoted as section 59[ m, n ]. Similarly, row 1, column 1, section 39 is denoted as section 39[1,1], and row m, column n, section 39 is denoted as section 39[ m, n ]. Fig. 2A and 2B show the case where m and n are 4 and 8, respectively. That is, the pixel circuit section 57 and the driving circuit section 30 are each divided into 32.
Each of the plurality of sections 59 includes a plurality of source lines SL and a plurality of gate lines GL (not shown) in addition to the plurality of pixel circuits 51. In each of the plurality of sections 59, one of the plurality of pixel circuits 51 is electrically connected to at least one of the plurality of source lines SL and at least one of the plurality of gate lines GL.
One of the sections 59 is provided so as to overlap with one of the sections 39 (see fig. 2C). For example, the sections 59[ i, j ] (i is an integer of 1 to m, j is an integer of 1 to n) are provided so as to overlap with the sections 39[ i, j ]. The source driver circuit 31 is electrically connected to a source line SL included in the section 59[ i, j ]. The gate line driving circuit 33 included in the section 39[ i, j ] is electrically connected to the gate line GL included in the section 59[ i, j ]. The gate line driving circuit 33 included in the section 39[ i, j ] has a function of controlling the plurality of pixel circuits 51 included in the section 59[ i, j ].
By providing the sections 59[ i, j ] and the sections 39[ i, j ] in an overlapping manner, the connection distance (wiring length) between the pixel circuit 51 included in the section 59[ i, j ] and the gate line driving circuit 33 included in the section 39[ i, j ] can be made extremely short. As a result, the wiring resistance and parasitic capacitance are reduced, and therefore the time required for charge and discharge is reduced, and high-speed driving can be realized. In addition, power consumption can be reduced. In addition, miniaturization and weight reduction can be realized.
The display device 200 includes the gate line driving circuit 33 for each section 39. Therefore, the display unit 13 is divided for each section 59 corresponding to the section 39, and the image can be rewritten for each sub-display unit 13A. For example, only the image data of the region in which the image is changed may be rewritten in the display unit 13, and the image data of the region in which the image is not changed may be held, and thus the power consumption may be reduced.
In the present embodiment and the like, one of the display units 13 divided for each section 59 is referred to as a sub display unit. The display device 200 described with reference to fig. 1A, 1B, 2A, and 2B shows a case where the display unit 13 is divided into 32 sub-display units 13A (see fig. 1A). The sub display section 13A includes a plurality of pixels each including a pixel circuit and a display element. Specifically, one sub display section 13A includes one of the sections 59 having the plurality of pixel circuits 51 and a plurality of display elements 61. In addition, one section 39 has a function of controlling the potential of the gate line of a plurality of pixels included in one sub-display section 13A.
In the display device 200, the driving frequency (also referred to as a frame rate, a refresh rate, or the like) at the time of displaying an image can be arbitrarily set for each sub-display section 13A by a timing controller included in the control circuit 41. The control circuit 41 has a function of controlling the operation of each of the plurality of sections 39 and the plurality of sections 59. That is, the control circuit 41 has a function of controlling the driving frequency and the operation timing of each of the plurality of sub-display sections 13A arranged in a matrix. The control circuit 41 also has a function of performing synchronization adjustment between the sub-displays.
Note that in fig. 1A to 2C, the layer 20 and the layer 50 are different layers, but the structure of one embodiment of the present invention is not limited thereto. By using an OS transistor as a transistor included in the layer 20 and an OS transistor as a transistor included in the layer 50, a transistor included in the pixel circuit and a transistor included in the gate line driver circuit can be provided in the same region.
The display device 200A shown in fig. 3A is an example of a structure of a display device in which the layer 20 and the layer 50 are the same layer. The layer 20A is provided with the circuit portion 30A in which the driving circuit portion 30 and the pixel circuit portion 57 are integrated. The circuit unit 30A is provided with a section 39A corresponding to the section 39 and the section 59. The section 39A is a region corresponding to the sub display unit 13A. In addition, the layer 20A is provided with a source line driving circuit 40 or a driving circuit portion 30 for driving the display device 200A, and a control circuit 41 for controlling the source line driving circuit 40.
The layer 20A is a layer provided with transistors included in a pixel circuit and a gate line driver circuit. As a transistor provided in the layer 20A, an OS transistor is used. Unlike the above-described structure in which the OS transistor and the LTPS transistor are provided in different layers, since the layers including the OS transistor are not stacked, reduction in manufacturing cost and thinning of the layers including the transistors can be achieved. Further, by using metal oxides or the like having different thicknesses of insulating layers or different atomic numbers of metal elements, OS transistors having different characteristics can be used as OS transistors provided in the same layer.
As shown in fig. 3B, the region 39A included in the layer 20A is provided with a pixel circuit 51 and a gate line driver circuit 33 which are configured by OS transistors. Note that although the gate line driving circuit 33 in the region 39A is shown in fig. 3B, it is preferable that a plurality of transistors included in the gate line driving circuit 33 be distributed in the region 39A where the pixel circuit 51 is provided.
In the display device according to one embodiment of the present invention, the pixel circuit and the driving circuit are stacked, and the driving frequency of each sub-display section 13A is made different, whereby the power consumption can be reduced. For example, the driving frequency of each sub display section 13A is made different according to the line of sight shift. For example, information (gaze point G) about gaze transition may be obtained by a gaze measurement (eye tracking) method such as a pupil cornea reflection (Pupil Center Corneal Reflection) method or a Bright/dark pupil effect (Bright/Dark Pupil Effect) method. Alternatively, the information may be acquired by a line-of-sight measurement method using laser, ultrasonic, or the like.
Fig. 4A shows the display section 13 including the sub display sections 13A of 4 rows and 8 columns. In addition, fig. 4A shows the first to third areas S1 to S3 centered on the gaze point G. The display device 200 assigns each of the plurality of sub-display sections 13A to one of the first region 29A overlapping the first region S1 or the second region S2 and the second region 29B overlapping the third region S3. That is, the display device 200 assigns the plurality of sub-display sections 13A to the first section 29A or the second section 29B, respectively. At this time, the first section 29A overlapping the first area S1 or the second area S2 is a sub-display section including an area overlapping the gaze point G, and the second section 29B is a sub-display section located outside the first section 29A and away from the gaze point G of the user (see fig. 4B).
The operation of the gate line driving circuit included in each of the plurality of sub display sections 13A is controlled by the control circuit 41. For example, the sub display unit corresponding to the second section 29B is a section overlapping with the third area S3 including the steady viewing field, the guide field, and the auxiliary field, that is, a section having low recognition ability for the user. Therefore, even if the number of times of rewriting the image data per unit time (hereinafter, also referred to as "image rewriting number") of the sub-display section belonging to the second section 29B is made smaller than that of the sub-display section corresponding to the first section 29A when displaying the image, the substantial display quality perceived by the user (hereinafter, also referred to as "substantial display quality") is hardly reduced. That is, even if the driving frequency of the sub display section corresponding to the second section 29B is made lower than the driving frequency of the sub display section corresponding to the first section 29A, the substantial display quality is hardly degraded.
When the driving frequency is reduced, power consumption of the display device can be reduced. On the other hand, when the driving frequency is lowered, the display quality is also lowered. In particular, the display quality is degraded when displaying moving images. According to one aspect of the present invention, by making the driving frequency of the sub display section corresponding to the second section 29B lower than the driving frequency of the sub display section corresponding to the first section 29A, it is possible to suppress substantial degradation of display quality while reducing power consumption of a section with low visibility for a user. According to one embodiment of the present invention, both maintenance of display quality and reduction of power consumption can be achieved.
The driving frequency of the sub display section corresponding to the first section 29A may be 30Hz to 500Hz, preferably 60Hz to 500 Hz. The driving frequency of the sub display section corresponding to the second section 29B is preferably not more than the driving frequency of the sub display section corresponding to the first section 29A, more preferably not more than 1/2 of the driving frequency of the sub display section corresponding to the first section 29A, and still more preferably not more than 1/5 of the driving frequency of the sub display section corresponding to the first section 29A.
In the sub-display section corresponding to the third region S3, the outer side of the second section 29B may be set to the third section 29C (see fig. 4C), or the driving frequency of the sub-display section corresponding to the third section 29C may be set lower than that of the sub-display section corresponding to the second section 29B. The driving frequency of the sub display section corresponding to the third section 29C is preferably not more than the driving frequency of the sub display section corresponding to the second section 29B, more preferably not more than 1/2 of the driving frequency of the sub display section corresponding to the second section 29B, and still more preferably not more than 1/5 of the driving frequency of the sub display section corresponding to the second section 29B. By making the number of image rewrites extremely small, power consumption can be further reduced. In addition, rewriting of the image data may be stopped as needed. By stopping rewriting the image data, power consumption can be further reduced.
In the case of using such a driving method, a transistor with a very small off-state current is preferably used as the transistor constituting the pixel circuit 51. For example, an OS transistor is preferably used as a transistor constituting the pixel circuit 51. Since the off-state current of the OS transistor is extremely small, the image data supplied to the pixel circuit 51 can be held for a long period of time by stopping the output signal output from the gate line driving circuit.
In addition, an image whose brightness, contrast, hue, or the like is greatly different from that of the previous image may be displayed on the display section 13, such as a change in the video scene displayed on the display section 13. In this case, since the timing of image transition is deviated between the first region 29A and the region whose driving frequency is lower than that of the first region 29A, the brightness, contrast, color tone, and the like between the two regions are greatly different, and there is a possibility that the display quality is substantially lowered. In such a case of changing the video scene, the image of the region other than the first region 29A may be rewritten at the same driving frequency as the first region 29A, and then the driving frequency of the region other than the first region 29A may be reduced.
When it is determined that the amount of fluctuation of the gaze point G exceeds a predetermined amount, the image in the sub-display section other than the sub-display section corresponding to the first section 29A may be rewritten at the same driving frequency as the sub-display section corresponding to the first section 29A, and when it is determined that the amount of fluctuation is within a predetermined amount, the driving frequency of the sub-display section other than the sub-display section corresponding to the first section 29A may be reduced. In addition, when it is determined that the amount of fluctuation of the gaze point G is small, the driving frequency of the sub display section other than the sub display section corresponding to the first section 29A may be further reduced.
Note that the sections corresponding to the sub-display section constituting the display section 13 are not limited to the three sections of the first section 29A, the second section 29B, and the third section 29C. Four or more compartments may be set in the display unit 13. By setting a plurality of regions in the display unit 13 and gradually decreasing the driving frequency, a substantial decrease in display quality can be further reduced.
In addition, by rewriting the image data of all the sub-display sections 13A at once when rewriting the image data of each sub-display section 13A, high-speed rewriting can be achieved. That is, by rewriting the image data of all the sections 39 at once when rewriting the image data of each section 39, high-speed rewriting can be achieved.
In the display device 200 according to the present embodiment, the display portion 13 is divided into eight in the column direction, and therefore the length of the gate line GL electrically connecting the gate line driving circuit and the pixel circuit becomes one eighth. Therefore, the resistance value and parasitic capacitance of the gate line GL are each one eighth, and the degradation and delay of the signal are improved, so that it is easy to secure a time to rewrite the image data.
The display device 200 according to one embodiment of the present invention has a short time for writing image data, and thus can realize high-speed rewriting of a display image. Therefore, a display device with high display quality can be realized. In particular, a display device excellent in displaying a moving image can be realized.
In addition, according to the display device 200 of the embodiment of the present invention, the output signals outputted from the gate line driving circuits can be independently controlled for each sub display section 13A, and thus the shape or size of the sub display section 13A can be made different from each other. In other words, the display unit 13 may be constituted by sub-display units having different shapes or sizes. Therefore, the display unit 13 is not limited to a rectangular shape, and a display unit having excellent design such as a circular shape can be realized.
Fig. 5A is a diagram showing an example of a configuration in which the display device 200 described in fig. 1A to 4C is used in a head-mounted display (HMD) type electronic apparatus to detect a line-of-sight shift. The example shown in fig. 5A shows a perspective view of the HMD type electronic device 100.
The electronic apparatus 100 shown in fig. 5A includes a pair of display devices 200_l, 200_r in a housing 251. In addition, fig. 5A shows an eye 252 of a user (user) when the electronic apparatus 100 is worn. In addition, a pair of imaging devices 253_l, 253_r for imaging the eyes 252 of the user are included in fig. 5A. The imaging devices 253_l and 253_r can capture the movement around the eyeball such as eyelid, glabella, inner canthus, outer canthus, and the like in addition to the eyes 252 of the user. As shown in fig. 5A, a pair of imaging devices 253_l, 253_r are disposed at, for example, the position of the imaging eye 252. In addition, by providing an acceleration sensor such as a gyro sensor in the housing 251, the head direction of the user can be detected and an image corresponding to the direction can be displayed.
As with the display device 200 described above, the display devices 200_l and 200_r shown in fig. 5A can have a structure in which the pixel circuit portion 57 and the drive circuit portion 30 are stacked, and therefore the aperture ratio (effective display area ratio) of the pixels can be greatly increased. For example, the aperture ratio of the pixel may be 40% or more and less than 100%, preferably 50% or more and 95% or less, and more preferably 60% or more and 95% or less.
The display devices 200_l and 200_r can have extremely high definition, and are therefore suitable for VR devices such as head mount display type electronic devices and glasses type AR devices. For example, since the display device 200 has a display portion with extremely high definition, in a structure in which the display portion of the display device 200 is seen through an optical member such as a lens, a user cannot see pixels even if the display portion is enlarged with the lens, whereby display with high immersion can be realized.
When the display device 200 is used as a wearable VR display device or an AR display device, the diagonal size of the display portion may be set to 0.1 inch or more and 5.0 inches or less, preferably 0.5 inch or more and 2.0 inches or less, and more preferably 1 inch or more and 1.7 inches or less. For example, the diagonal size of the display portion may be set to be 1.5 inches or around 1.5 inches. By setting the diagonal dimension of the display unit to 2.0 inches or less, preferably around 1.5 inches, the display unit can be processed by one exposure process by an exposure device (typically, a scanner), and thus the productivity of the manufacturing process can be improved.
Fig. 5B shows a case where the user 130 wearing the electronic apparatus 100 shown in fig. 5A sees the image 24 on the line of sight 131. Fig. 5B shows a first region S1 including a gaze point G, a second region S2 adjacent to the first region S1, and a third region S3 outside the second region.
Although there are individual differences, generally, the human visual field is roughly divided into the following five. The first is to distinguish the field of view, as the following: visual functions such as eyesight and color recognition are most excellent; and includes a gaze point within about 5 of the center of the field of view. The second is the effective field of view, which is the following area: the specified information can be identified instantaneously as long as there is eye movement; is within about 30 ° of parallel and within about 20 ° of perpendicular of the center of the field of view (gaze point); and is adjacent to the outside of the field of view. The third is a stable gaze field, which is the following area: the prescribed information can be recognized without difficulty by the head movement; is within about 90 ° parallel and within about 70 ° perpendicular to the center of the field of view; and is adjacent to the outside of the effective field of view. Fourth, the pilot field of view is the following: although the presence of a prescribed object can be perceived, the recognition ability is low; is within about 100 ° parallel and within about 85 ° perpendicular to the center of the field of view; and is adjacent to the outside of the stable gaze field. Fifth, the auxiliary field of view is the following: specifying that the recognition capability of the subject is extremely low to the extent that the presence of stimulus can only be perceived; is within about 100 ° to 200 ° parallel and about 85 ° to 130 ° perpendicular to the center of the field of view; and is adjacent to the outside of the pilot field of view.
It can be seen that in the image 24, it is important to distinguish the image quality from the visual field to the effective visual field. It is particularly important to discern the image quality of the field of view.
The gaze point G also shifts when the line of sight 131 of the user 130 shifts. Thereby, the first region S1 and the second region S2 are also transferred. For example, when the amount of fluctuation of the line of sight 131 exceeds a certain amount, it is determined that the line of sight 131 is shifted. In other words, when the amount of fluctuation of the gaze point G exceeds a certain amount, it is determined that the gaze point G shifts. When the change in the line of sight 131 becomes equal to or less than a predetermined amount, it is determined that the transition of the line of sight 131 is stopped, and the first to third areas S1 to S3 are determined. In other words, when the change in the gaze point G becomes equal to or smaller than a predetermined amount, it is determined that the movement of the gaze point G is stopped, and the first to third areas S1 to S3 can be determined.
Fig. 6 is a schematic diagram illustrating the structure of the pixel circuit 51 and the gate line driving circuit 33 adjacent to each other in the sub-display portion of the display device 200 in which the sections 39 and 59 are stacked. In FIG. 6, the adjacent sections 39[ i, j ], 39[ i+1, j ] and sections 59[ i, j ], 59[ i+1, j ] are shown.
Fig. 6 shows the x-direction, y-direction and z-direction. As shown in fig. 6, the x direction is a direction parallel to the gate line GL. The y-direction is a direction parallel to the source line (not shown). As shown in fig. 6, the z direction is a direction perpendicular to a plane defined by the x direction and the y direction. That is, fig. 6 shows a case where the pixel circuit 51 and the gate line driving circuit 33 are provided on the xy plane and the sections 39 and 59 are stacked in the z direction. The configuration shown in fig. 6 is an example, and a part of the circuit of the pixel circuit 51 or the gate line driving circuit 33 may be provided in an upper layer or a lower layer.
The gate line driving circuits 33 provided in the sections 39[ i, j ] and the sections 59[ i+1, j ] each include a plurality of pulse output circuits 34. The pulse output circuit 34 outputs a signal for simultaneously selecting the pixel circuits 51 arranged in the x-direction through the gate lines GL extending in the z-direction. By disposing the gate line driving circuit 33 under the pixel circuit 51, the design flexibility such as the narrow frame can be improved.
Note that the number of pulse output circuits 34 in the gate line driving circuits 33 provided in the sections 39[ i, j ] and 39[ i+1, j ] is shown as the same, but the number may be different. The number of pixels in the y direction can be made different by making the number of pulse output circuits 34 included in the gate line driving circuit 33 different between the sections 39[ i, j ] and the sections 39[ i+1, j ]. Therefore, the degree of freedom in shape of the display portion can be improved. Therefore, the display portion 13 including the sub display portion 13A corresponding to the section 39[ i, j ] and the section 39[ i+1, j ] can be a display portion excellent in design.
< Structural example of Pixel Circuit >
Fig. 7 to 9 show a structural example of a pixel circuit usable for the pixel circuit 51 and a display element 61 connected to the pixel circuit 51. Note that in the following description, the display element 61 is described as a light-emitting device such as an Organic LIGHT EMITTING Diode (OLED).
Note that the light-emitting device described in one embodiment of the present invention is not limited to an organic EL element, and may be a self-light-emitting device such as an LED (LIGHT EMITTING Diode), a Micro LED, a QLED (Quantum-dot LIGHT EMITTING Diode), or a semiconductor laser.
The pixel circuit 51A shown in fig. 7A includes a transistor 55A, a transistor 55B, and a capacitor 56. Fig. 7A shows a display element 61 connected to the pixel circuit 51A. Fig. 7A shows a source line SL, a gate line GL, a power supply line ANO, and a power supply line VCOM.
In the transistor 55A, the gate is electrically connected to the gate line GL, one of the source and the drain is electrically connected to the source line SL, and the other is electrically connected to the gate of the transistor 55B and one electrode of the capacitor 56. In the transistor 55B, one of a source and a drain is electrically connected to the power supply line ANO, and the other is electrically connected to an anode of the display element 61. The other electrode of the capacitor C1 is electrically connected to the anode of the display element 61. The cathode of the display element 61 is electrically connected to the power supply line VCOM. Note that the anode and the cathode of the display element 61 can be appropriately replaced by changing the magnitudes of the potentials supplied to the power supply line ANO and the power supply line VCOM.
The pixel circuit 51B shown in fig. 7B has a structure in which a transistor 55C is added to the pixel circuit 51A. In the transistor 55C, the gate electrode is electrically connected to the gate line GL, one of the source electrode and the drain electrode is electrically connected to the anode electrode of the display element 61, and the other of the source electrode and the drain electrode is electrically connected to the wiring V0.
The pixel circuit 51C shown in fig. 7C is an example in which a transistor including a pair of gates is used for the transistor 55A and the transistor 55B of the pixel circuit 51A. The pixel circuit 51D shown in fig. 7D is an example in the case where the transistor is used for the pixel circuit 51B. Therefore, a current that can flow through the transistor can be increased. Note that it is shown here that all transistors employ a transistor including a pair of gates, but is not limited thereto. In addition, a transistor including a pair of gates, each of which is electrically connected to a different wiring may be used. For example, by using a transistor in which one gate is electrically connected to the source, reliability can be improved.
The pixel circuit 51E shown in fig. 8A has a structure in which a transistor 55D is added to the pixel circuit 51B. The pixel circuit 51E is electrically connected to three gate lines (gate line GL1, gate line GL2, and gate line GL 3).
In the transistor 55D, the gate is electrically connected to the gate line GL3, one of the source and the drain is electrically connected to the gate of the transistor 55B, and the other is electrically connected to the wiring V0. The gate of the transistor 55A is electrically connected to the gate line GL1, and the gate of the transistor 55C is electrically connected to the gate line GL 2.
By simultaneously placing the transistor 55C and the transistor 55D in a conductive state, the source and the gate of the transistor 55B have the same potential, and thus the transistor 55B can be placed in a non-conductive state when the threshold voltage of the transistor 55B is greater than 0V. This can forcibly interrupt the current flowing through the display element 61. Such a pixel circuit is suitable for a case where a display method in which a display period and a light-off period are alternately set is used.
The pixel circuit 51F shown in fig. 8B has an example in which a capacitor 56A is added to the pixel circuit 51E. The capacitor 56A is used as a holding capacitor.
The pixel circuit 51G shown in fig. 8C and the pixel circuit 51H shown in fig. 8D are examples in the case where a transistor including a pair of gates is used for the pixel circuit 51E or the pixel circuit 51F, respectively. The transistors 55A, 55C, and 55D are a pair of transistors each having a gate electrically connected to each other, and the transistor 55B is a transistor having a gate electrically connected to a source.
In the above, fig. 7A to 8D show examples of the structure in which the circuit can be configured using only the OS transistor as an n-channel transistor as each transistor, but one embodiment of the present invention is not limited thereto. For example, as shown in fig. 9A to 9C, a pixel circuit including an OS transistor and an LTPS transistor may be used.
The pixel circuit 51I shown in fig. 9A includes a transistor 55A, a transistor 55P, and a capacitor 56. The pixel circuit 51I shown in fig. 9A is an example in which the transistor 55B in the pixel circuit 51A is replaced with a transistor 55P which is a P-channel LTPS transistor. The pixel circuit 51I shown in fig. 9A can hold an analog potential by placing the transistor 55A as an OS transistor in a non-conductive state. In addition, in the pixel circuit 51I, by using the transistor 55P as an LTPS transistor as a driving transistor, the amount of current flowing through the display element 61 can be increased.
The pixel circuit 51J shown in fig. 9B includes a transistor 55A, a transistor 55B, a transistor 55P, and a capacitor 56. The pixel circuit 51J shown in fig. 9B is an example in which the transistor 55B in the pixel circuit 51B is replaced with a transistor 55P which is a P-channel LTPS transistor. The pixel circuit 51J shown in fig. 9B can hold an analog potential by placing the transistor 55A as an OS transistor in a non-conductive state. In addition, in the pixel circuit 51J, by using the transistor 55P as an LTPS transistor as a driving transistor, the amount of current flowing through the display element 61 can be increased.
The pixel circuit 51K shown in fig. 9C includes a transistor 55A, a transistor 55P to a transistor 55T, and a capacitor 56. The pixel circuit 51K shown in fig. 9C is an example of a pixel circuit including transistors 55P to 55T as n-channel LTPS transistors. The pixel circuit 51K shown in fig. 9C can hold an analog potential by placing the transistor 55A as an OS transistor in a non-conductive state. In addition, in the pixel circuit 51K, by using the transistors 55P to T as LTPS transistors as driving transistors or switching transistors, the amount of current flowing through the display element 61 can be increased.
Fig. 9D shows an operation timing chart of the pixel circuit 51K shown in fig. 9C. By supplying the signals shown in fig. 9D to the gate lines GL1 to GL4, light emission according to the image data D (N) of the source line SL can be controlled. Note that, as shown in fig. 9D, the gate lines GL1 and GL3 are supplied with a selection signal and an inversion signal thereof, and the gate lines GL2 and GL4 are supplied with a selection signal and an inversion signal thereof.
< Structural example of Gate line drive Circuit >
Fig. 10A to 10C show an example of the gate line driving circuit 33 described in fig. 2B and 6, the pulse output circuit 34 that can be used for the gate line driving circuit 33, and a timing chart.
Fig. 10A is an example of a shift register included in the gate line driving circuit 33. Fig. 10A shows the pulse output circuits 34_1 to 34—n+2, wirings for supplying the gate clock signal gck_a, wirings for supplying the gate clock signal gck_b, and wirings for supplying the gate start pulse GSP. Note that the wiring between the pulse output circuits 34_1 and 34_2 is connected to the gate line GL. The output signals of the pulse output circuits 34_n+1 and 34_n+2 are signals for resetting the pulse output circuit of the previous stage.
Fig. 10B is an example of a circuit configuration of a pulse output circuit that can be used for the pulse output circuits 34_1 to 34—n+2 shown in fig. 10A. The pulse output circuit 34 shown in fig. 10B includes transistors M11 to M14 and a capacitive element C11. In fig. 10B, the gate clock signal gck_a, the gate clock signal gck_b, the output signal GP, the gate start pulse GSP (or the output signal Former GP of the previous pulse output circuit 34), the output signal Next GP of the Next pulse output circuit 34, and the voltage VSS are shown as signals and voltages supplied to the transistors. In fig. 10B, a node to which the transistors M11, M12, and M13 and the capacitor element C11 are connected is referred to as net a.
Fig. 10C is a timing chart for explaining the operation of the pulse output circuit shown in fig. 10B. At time T1 in fig. 10C, gck_a is at a low level and gck_b is at a high level, and GSP is at a high level at this time, so that the voltage of net a increases. Then, when GSP is changed to low level at time T2, net a is in a floating state. At time T2, since gck_a is at a high level and gck_b is at a low level, the voltage of net a in the floating state rises by capacitive coupling of capacitive element C11. Accordingly, the transistor M13 becomes an on state, and GP becomes a high level. At time T3, next GL goes high and net a goes low, gck_b goes high and GP goes low.
In addition, when driving the pixel circuit 51K shown in fig. 9C, etc., an inversion signal of the output signal GP of fig. 10C is required. The inverted signal of the output signal GP is preferably generated by an inverter circuit constituted by a CMOS circuit. That is, as shown in fig. 11A, in the configuration of the pulse output circuit illustrated in fig. 10B, it is preferable to provide the p-channel transistor M15 and the n-channel transistor M16 constituting the inverter circuit for generating the inversion signal of the output signal GP. The transistor M15 may be formed using an LTPS transistor, and the transistor M16 may be formed using an LTPS transistor or an OS transistor.
Fig. 11B is a timing chart for explaining the operation of the pulse output circuit shown in fig. 11A. As shown in fig. 11B, a signal may be generated that causes GPB, which is an inversion signal, to go low when GP goes high.
Note that the configuration of the pulse output circuit is not limited to the circuit configuration shown in fig. 10B and 11A, and other configurations may be adopted. Fig. 12 shows transistors M21 to M33, and capacitive elements C21 to C23. In fig. 12, LIN is a previous stage output signal or a strobe start pulse, CLK1 to CLK3 are strobe clock signals, RES is a reset signal, RIN is a next stage output signal, and PWCA is a pulse width control signal. Note that the output signal GP is a signal output to the gate line GL, and the output signal 34N is a signal output to the next-stage pulse output circuit.
As shown in fig. 12, the pulse output circuit may have a circuit configuration configured using only n-channel transistors. In fig. 12, the transistors M21 to M33 are n-channel transistors, and a circuit structure formed using an OS transistor or an n-channel LTPS transistor or a circuit structure formed by combining an OS transistor and an n-channel LTPS transistor may be employed.
Note that the configuration of the pulse output circuit is not limited to the circuit configuration shown in fig. 10B, 11A, and 12, and other configurations may be adopted. Fig. 13 shows transistors M41 to M63. In fig. 13, LIN is a previous stage output signal or a strobe start pulse, CLK1 and CLK2 are strobe clock signals, and PWCA is a pulse width control signal. Note that the output signal GP is a signal output to the gate line GL, and the output signal 34N is a signal output to the next-stage pulse output circuit.
As shown in fig. 13, the pulse output circuit may have a circuit structure formed by combining an n-channel transistor and a p-channel transistor. As for the n-channel type transistor and the p-channel type transistor, a circuit structure using an n-channel type OS transistor and a p-channel type LTPS transistor or a circuit structure using a p-channel type LTPS transistor and an n-channel type LTPS transistor may be employed.
Fig. 14 shows a configuration example in which the pixel circuit 51A in fig. 7A and the pulse output circuit in fig. 10B are stacked using circuit symbols. Note that in fig. 14, the x direction, the y direction, and the z direction are shown as in fig. 6. Fig. 14 shows a pulse output circuit, a pixel circuit, and a light-emitting element as a display element so as to correspond to the layers 20, 50, and 60 described in fig. 1B.
Note that when the structure in which the pixel circuit and the gate line driver circuit are provided in the same layer as those described in fig. 3A and 3B is employed as the structure in fig. 14, the structure of the structural example shown in fig. 15 is employed. Fig. 15 shows a configuration example in which the pixel circuit 51A of fig. 7A and the pulse output circuit of fig. 10B are arranged in the layer 20A by using circuit symbols. Note that in fig. 15, the x direction, the y direction, and the z direction are shown as in fig. 14. Fig. 15 shows a pulse output circuit, a pixel circuit, and a light-emitting element as a display element so as to correspond to the layers 20A and 60 described with reference to fig. 3A and 3B.
In fig. 16, a circuit symbol is used to illustrate an example of a configuration when the pixel circuit 51J of fig. 9B and the pulse output circuit of fig. 10B are stacked. Note that in fig. 16, the x direction, the y direction, and the z direction are shown as in fig. 6. As in fig. 14 and 15, fig. 16 shows a pulse output circuit, a pixel circuit, and a light-emitting element as a display element so as to correspond to the layers 20, 50, and 60 described in fig. 1B.
The difference from fig. 14 in the drawing shown in fig. 16 is that: the layer 20 is provided with a transistor 55P constituting a pixel circuit. In the structure of one embodiment of the present invention, a circuit other than the pulse output circuit, for example, a part of the pixel circuit may be provided in the layer 20. Since the number of transistors in the layer 50 can be reduced, the area of the pixel circuit can be reduced, whereby a high-definition display device can be realized.
In fig. 17, a circuit symbol is used to illustrate an example of a configuration when the pixel circuit 51A in fig. 7A and the pulse output circuit in fig. 11A are stacked. Note that in fig. 17, the x direction, the y direction, and the z direction are shown as in fig. 14 to 16. As in fig. 14 to 16, fig. 17 shows a pulse output circuit, a pixel circuit, and a light-emitting element as a display element so as to correspond to the layers 20, 50, and 60 described in fig. 1B.
The drawings shown in fig. 17 differ from fig. 14 to 16 in that: the transistor M16 constituting the pulse output circuit is provided in the layer 50. In the structure according to one embodiment of the present invention, a circuit other than the pixel circuit, for example, a part of the pulse output circuit may be provided in the layer 50. Since the number of transistors of the layer 20 can be reduced, the area of the pulse output circuit can be reduced.
As described above, the circuit configuration of the pulse output circuit included in the pixel circuit and the gate line driving circuit according to one embodiment of the present invention is not limited to the circuit configuration using only the OS transistor or only the LTPS transistor, and a circuit configuration combining the OS transistor and the LTPS transistor may be employed. Accordingly, in one embodiment of the present invention, the degree of freedom in arrangement of the pulse output circuit included in the pixel circuit and the gate line driver circuit can be increased, and thus the degree of freedom in shape of the display portion can be increased, and a display device having excellent design can be realized.
< Working example of display device >
Fig. 18A shows a schematic diagram of a display device in which the region of the pixel circuit section 57 and the region 39 of the driving circuit section 30 described in fig. 2A and 2B are arranged in m=4, n=4, that is, 4 rows and 4 columns, and the display section 13 in fig. 1A is divided into 16 sub-display sections 13A. Note that in fig. 18A, symbols (1, 1) to (4, 4) and the like are given to the sub-display section 13A divided into 16 pieces. Fig. 18A shows a case where the sub display sections 13A are each provided with a gate line driving circuit 33 and the outside of the display section 13 is provided with a source line driving circuit 31.
Fig. 18B is a schematic diagram for explaining signals output to the gate lines by the gate line driving circuit 33 corresponding to the sub display section 13A shown in fig. 18A. Note that (1, x) shown in fig. 18B indicates the sub display section 13A as any one of (1, 1) to (1, 4) of the first-row sub display section 13A. That is, (2, 1) to (2, 4) as the second-row sub display section 13A may be expressed as (2, x). Similarly, (3, 1) to (3, 4) as the third-row sub-display section 13A may be denoted as (3, x), and (4, 1) to (4, 4) as the fourth-row sub-display section 13A may be denoted as (4, x).
In addition, (1, x) _sp shown in fig. 18B represents a start pulse signal supplied to each of the gate line driving circuits 33 of (1, 1) to (1, 4) as the first row sub-display section 13A. Further, (1, x) _1 to (1, x) _n (n is a natural number) represent output signals sequentially output from the pulse output circuits of the gate line driving circuits 33 of (1, 1) to (1, 4) as the first row sub-display section 13A.
In the case of the configuration of fig. 18A, the scanning of the screen is set to one direction, but only the gate driver of the block to be rewritten is operated, so that the rewriting can be partially performed.
Next, an operation method of the gate line driving circuit when rewriting image data will be described with reference to a timing chart. Here, a timing chart will be described when rewriting the image data in all the sub-display sections 13A of the display section 13 (schematic diagram shown in fig. 19A) and when rewriting only the image data in the sub-display section 13A of 3 rows and 3 columns of the display section 13 (hatched portions indicated by (3, 3) in the drawing) (schematic diagram shown in fig. 19B).
Fig. 20 shows start pulse signals (1, x) _sp to (4, x) _sp supplied to the gate line driving circuits of each row and output signals (1, x) _1 to (1, x) _n, (2, x) _1 to (2, x) _n, (3, x) _1 to (3, x) _n, and (4, x) _1 to (4, x) _n) of the gate line driving circuits of each row corresponding to the schematic diagram shown in fig. 19A when image data is rewritten.
As shown in fig. 20, in the image data rewriting corresponding to the schematic diagram shown in fig. 19A, the start pulse signal (1, x) is input to the gate line driving circuits of the sub display sections (1, 1), (1, 2), (1, 3), (1, 4), and the gate line driving circuits are operated to sequentially output the output signals. Next, a start pulse signal (2, x) is input to the gate line driving circuits of the sub-display sections (2, 1), (2, 2), (2, 3), (2, 4), and the gate line driving circuits are operated so as to sequentially output signals. Next, a start pulse signal (3, x) is input to the gate line driving circuits of the sub-display sections (3, 1), (3, 2), (3, 3), (3, 4), and the gate line driving circuits are operated so as to sequentially output signals. Next, a start pulse signal (4, x) is input to the gate line driving circuits of the sub-display sections (4, 1), (4, 2), (4, 3), (4, 4), and the gate line driving circuits are operated so as to sequentially output signals.
According to the operation shown in fig. 20, an output signal can be generated in the gate line driver circuit so that image data output from the source line driver circuit is selected in a row and written into each pixel.
Fig. 21 shows start pulse signals (1, x) _sp to (4, x) _sp supplied to the gate line driving circuits of each row and output signals (1, x) _1 to (1, x) _n, (2, x) _1 to (2, x) _n, (3, x) _1 to (3, x) _n, and (4, x) _1 to (4, x) _n) of the gate line driving circuits of each row corresponding to the schematic diagram shown in fig. 19B when image data is rewritten.
As shown in fig. 21, in the image data rewriting corresponding to the schematic diagram shown in fig. 19B, the start pulse signal (3, 3) _sp is input to the gate line driving circuits of the sub display sections (3, 3), and the gate line driving circuits of the sub display sections (3, 3) are operated so as to sequentially output the output signals. The gate line driving circuits of the other sub display sections are not supplied with the start pulse signal, and the corresponding gate line driving circuits are operated so as not to sequentially supply the output signals.
According to the operation shown in fig. 21, the operation of the gate line driving circuit of the non-rewritten sub display part can be stopped, whereby power consumption can be reduced.
Note that, as shown in fig. 18A, the gate line driving circuits are arranged in each sub-display section, but the gate line driving circuits may be commonly used in adjacent sub-display sections.
For example, in the configuration in which the display unit shown in fig. 18A is divided into 4×4 blocks, the first-row sub-display unit and the second-row sub-display unit may use a shift register of the gate line driving circuit in common, and the third-row sub-display unit and the fourth-row sub-display unit may use a shift register of the gate driver in common. Fig. 22 shows a schematic diagram of this case.
As shown in fig. 22, the shift register SR in the gate line driving circuit is commonly used by the plurality of sub-display sections, but by disposing the buffers BUF (portions to which selection signals are supplied to the pixels) in each sub-display section, for example, when only the image data of the sub-display section 13A of (1, 2) is rewritten, only the sub-display section of (1, 2) can be rewritten by stopping the signal supplied to the buffers BUF of the sub-display section 13A of (1, 1).
< Structural example of Source line drive Circuit >
Fig. 23A and 23B show a modified example of the source line driving circuit 31 described in fig. 2B and the like.
Fig. 23A shows an example of a configuration in which a plurality of source line driver circuits 31 described in fig. 2B and the like are provided. Fig. 23A shows a structure in which a source line driver circuit 31A and a source line driver circuit 31B are provided in regions corresponding to the upper and lower sides of a driver circuit unit 30 including a plurality of partitions 39 in which gate line driver circuits 33 are provided. With this configuration, the regions of the pixel circuit portion for supplying the image data can be divided by the source line driving circuit 31A and the source line driving circuit 31B, and thus the operation of the source line driving circuit can be stopped so as to correspond to the operation in which the gate line driving circuit does not sequentially output the output signals.
Note that although fig. 23A shows a structure in which two source line driving circuits are provided, the source line driving circuits are preferably provided in a divided manner according to the number of sub display portions. For example, as shown in fig. 23B, the source line driving circuits 31 are preferably provided in the number equivalent to the number of n column sections 39 corresponding to the sub display section. With this configuration, the gate line driver circuit corresponding to the active sub-display section and the source line driver circuit corresponding to the column in which the active sub-display section is present can be operated, and the operation of the other gate line driver circuit and source line driver circuit can be stopped, whereby the power consumption of the display device can be reduced.
< Structural example of display device 2>
In fig. 24 to 25, a configuration example of a display device combining a plurality of display panels is described.
Fig. 24 illustrates an example of a case where a display panel 400 shown below is combined to form the display unit 13 of the display device. Fig. 25 is a schematic plan view of the display unit 13 and the display panel 400 when viewed from the display surface side.
The display panel 400 includes the sub display portion 13A, the pixel circuit portion 57, the source line driving circuit 31, the gate line driving circuit 33, the region 401 transmitting visible light, the terminal portion 14, and the like. Fig. 24 shows an example in which the display panel 400 includes two terminal portions 14 and the FPC21 is connected to each terminal portion 14.
Note that the gate line driving circuit 33 is provided around the pixel circuit section 57 in fig. 24, but is not limited to this structure. For example, as described with reference to fig. 1A to 2B, transistors may be arranged in a plurality of layers, and the gate line driver circuit and the pixel circuit portion may be arranged in a stacked manner. As another configuration, as described in fig. 3A and 3B, the gate line driver circuit may be disposed in a region where the pixel circuit portion including the layer of the transistor is disposed.
In the case where the sub display section 13A is the sub display section 13A of m rows and n columns, the sub display sections 13A [1,1] to 13A [ m, n ] are provided in the display section 13. That is, by combining the display panel 400, a display device including a plurality of sub display sections 13A can be realized.
The region 401 is a region transmitting visible light. As the member provided in the region 401, a material that transmits visible light can be used. In addition, a light shielding material processed to be thin to an extent not visible (for example, 5 μm or less in width) may be used.
Fig. 25A and 25B show a configuration example of a display device 200X including four display panels (a display panel 400a, a display panel 400B, a display panel 400c, and a display panel 400 d). Fig. 25A is a schematic plan view of the display device 200X seen from the display surface side, and fig. 25B is a schematic plan view of the display device seen from the side opposite to the display surface (also referred to as the back surface side).
Note that, unless otherwise specified below, the symbols a to d are given for the explanation of each display panel or the constituent elements of the display panel. In the description of the content common to the display panels and the components of the display panels, these symbols may not be given.
In fig. 25A and 25B, a display panel 400a, a display panel 400B, a display panel 400c, and a display panel 400d are stacked in this order from the back side. The display panel 400a is located on the back side, and the display panel 400d is located on the side closest to the display surface.
Here, a part of the region 401b included in the display panel 400b is provided so as to overlap with a part of the pixel circuit portion 57a in the region overlapping the display element. In the portion overlapping with the region 401b in the pixel circuit portion 57a, the light from the display element is emitted to the display surface side through the region 401 b.
Similarly, a part of the region 401c included in the display panel 400c is provided so as to overlap with a part of the pixel circuit portion 57 a. A part of the region 401d included in the display panel 400d is provided so as to overlap with a part of the pixel circuit portion 57a, another part is provided so as to overlap with a part of the pixel circuit portion 57b, and another part is provided so as to overlap with a part of the pixel circuit portion 57 c.
That is, the display unit 13 of the display device 200X is constituted by the pixel circuit portion 57a, the pixel circuit portion 57b, the pixel circuit portion 57c, and the pixel circuit portion 57 d. Thus, a display device using the pixel circuit portion 57a, the pixel circuit portion 57b, the pixel circuit portion 57c, and the pixel circuit portion 57d of each of the display panels 400a to 400d as sub-display portions can be realized.
As shown in fig. 25B, the FPC21a connected to the display panel 400a and the FPC21B connected to the display panel 400B are provided so as to overlap with the display panel 400c or the display panel 400d, respectively.
Here, since the source line driving circuit 31 and the gate line driving circuit 33 are provided in each display panel 400, the number of signals to be supplied to each display panel 400 can be reduced. Thereby, the number of FPCs 21 connected to one display panel 400 can be reduced to reduce the number of components. In addition, as shown in fig. 25B, by making the lengths of the FPCs 21 connected to the respective display panels 400 different and concentrating the end portions of the FPCs 21 on one side of the display device 200X, it is possible to concentrate a driving circuit for supplying signals and the like to the display device 200X in one portion. This can simplify the structure of the back surface of the display device 200X.
Fig. 25C is a schematic cross-sectional view when the display device 200X is cut along the dash-dot line X-Y in fig. 25B.
The portion of the display panel 400a overlapping the display panel 400c is bent in the back direction, and the FPC21a is connected to the terminal portion 14a at this portion. At this time, the source line driver circuit 31A and the terminal portion 14A of the display panel 400a are arranged so as to overlap the pixel circuit portion 57c of the display panel 400 c. Accordingly, no seam is generated in the display portion 13 of the display device 200X, and an image with high display quality can be displayed.
Fig. 26A to 26C illustrate another configuration example of a display device in which a plurality of display panels are combined. The display panel 450 shown in fig. 26A includes the pixel circuit portion 57, the region 401, and the region 22. The region 22 is a region that shields visible light. The region 401 and the region 22 are provided adjacent to the pixel circuit section 57. Fig. 26A shows an example in which the display panel 450 is provided with the FPC 21. Note that the gate line driver circuit and the source line driver circuit are not provided in the display panel, and image data and other signals are input from the outside through the FPC.
Note that in fig. 26A to 26C, a structure in which the gate line driver circuit and the source line driver circuit are provided outside the display panel is described, but the structure is not limited thereto. For example, the source line driver circuit may be provided outside the display panel, and the gate line driver circuit may be provided in a region overlapping with the pixel circuit. In this case, as described with reference to fig. 1A to 2B, transistors may be arranged in a plurality of layers, and the gate line driver circuit and the pixel circuit portion may be arranged in a stacked manner. As another configuration, as described in fig. 3A and 3B, the gate line driver circuit may be disposed in a region where the pixel circuit portion including the layer of the transistor is disposed.
The pixel circuit section 57 includes a plurality of pixel circuits. A pair of substrates constituting the display panel 450, a sealant for sealing a display element sandwiched between the pair of substrates, and the like are provided in the region 401. At this time, as a member provided in the region 401, a material having transparency to visible light is used. The region 22 is provided with wirings and the like electrically connected to pixels included in the pixel circuit portion 57. The region 22 may be provided with a terminal connected to the FPC21, a wiring connected to the terminal, and the like.
Fig. 26B and 26C show an example in which the display panels 450 shown in fig. 26A are arranged in a matrix (two display panels 450 are arranged in the vertical and horizontal directions, respectively) so as to be configured of 2×2 sub-display units. Fig. 26B is a perspective view of the display surface side of the display panel 450, and fig. 26C is a perspective view of the display panel 450 on the opposite side of the display surface.
The four display panels 450 (display panels 450a, 450b, 450c, 450 d) are arranged in such a manner as to have regions overlapping each other. Specifically, the display panels 450a, 450b, 450c, and 450d are arranged such that the region 401 in one display panel 450 has a region overlapping the pixel circuit portion 57 (display surface side) in the other display panel 450. The display panels 450a, 450b, 450c, and 450d are arranged such that the visible light shielding region 22 of one display panel 450 is not overlapped with the pixel circuit portion 57 of the other display panel 450. In the overlapping portion of the four display panels 450, the display panel 450b overlaps the display panel 450a, the display panel 450c overlaps the display panel 450b, and the display panel 450d overlaps the display panel 450 c.
Short sides of the display panels 450a and 450b overlap each other, and a part of the pixel circuit portion 57a overlaps a part of the region 401 b. The long sides of the display panels 450a and 450c overlap each other, and a part of the pixel circuit portion 57a overlaps a part of the region 401 c.
A part of the pixel circuit portion 57b overlaps with a part of the region 401 d. In addition, a part of the pixel circuit portion 57c overlaps a part of the region 401 d.
Accordingly, the display portion 13 of the display device in which the region where the pixel circuit portions 57a to 57d are arranged with almost no seam is used as the sub display portion can be realized.
Here, the display panel 450 preferably has flexibility. For example, a pair of substrates constituting the display panel 450 preferably have flexibility.
As a result, for example, as shown in fig. 26B and 26C, the vicinity of the FPC21a of the display panel 450a can be bent, and a part of the display panel 450a and a part of the FPC21a can be disposed below the pixel circuit portion 57B of the display panel 450B adjacent to the FPC21 a. As a result, the FPC21a can be disposed so as not to physically interfere with the back surface of the display panel 450 b. In addition, when the display panel 450a and the display panel 450b are overlapped and fixed, the thickness of the FPC21a does not need to be considered, so that the difference in height between the top surface of the region 401b through which visible light passes and the top surface of the display panel 450a can be reduced. As a result, the end portion of the display panel 450b located on the pixel circuit portion 57a can be made less visible.
Further, by providing flexibility to each display panel 450, the display panel 450b can be gently bent so that the height of the top surface of the pixel circuit portion 57b of the display panel 450b matches the height of the top surface of the pixel circuit portion 57a of the display panel 450 a. Therefore, the height of each display region can be made uniform except in the vicinity of the region where the display panel 450a and the display panel 450b overlap, and the display quality of the image displayed on the display region 79 can be improved.
In the above example, the relationship between the display panel 450a and the display panel 450b is described as an example, but the relationship between other adjacent two display panels 450 is the same.
Note that in order to reduce the step between two adjacent display panels 450, the thickness of the display panel 450 is preferably small. For example, the thickness of the display panel 450 is preferably 1mm or less, more preferably 300 μm or less, and further preferably 100 μm or less.
Note that in the above-described configuration example, the FPC21 is provided on the terminal portion 14 provided on the side where the display portion 13 is seen (the front surface side), and a plurality of display panels are combined to construct the display device, but the present invention is not limited thereto. For example, the terminal portion 14 electrically connected to the FPC21 may be exposed on the back surface (back surface side) of the display portion 13.
Fig. 27A to 27C are diagrams illustrating the following structures: the terminal 14 is exposed on the back surface side, and the terminal 14 and the FPC21 are connected by an electrode (through electrode) penetrating the substrate 11. For convenience of explanation, the transistor MT provided in the pixel circuit portion 57 and the terminal portion 14 including the conductive layers 15A and 15B are shown as constituent elements of the display panel 450 in fig. 27A to 27C.
Fig. 27A is a schematic cross-sectional view of the display panel before the conductive layers 15A and 15B are exposed in the terminal portion 14. The transistor MT and the terminal portion 14 are provided between the substrate 11A and the substrate 12. A peeling layer 11B is provided between the substrate 11A and the transistor MT and between the substrate and the terminal portion 14.
As the substrate 11A, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, a metal substrate, a semiconductor substrate, or the like can be used. Further, a heat-resistant plastic substrate which can withstand the processing temperature of the present embodiment may be used. The peeling layer 11B can be formed using an element selected from tungsten, molybdenum, titanium, tantalum, niobium, nickel, cobalt, zirconium, ruthenium, rhodium, palladium, osmium, iridium, and silicon, an alloy material containing the element, or a compound material containing the element. In addition, a single layer or a stacked layer of the above materials may be used for formation.
Fig. 27B is a schematic cross-sectional view of the display panel when the substrate 11A is peeled off from the peeling layer 11B so that the conductive layer 15A and the conductive layer 15B are exposed at the terminal portion 14. Examples of the method for peeling the substrate 11A from the peeling layer 11B include application of mechanical force (peeling by a human hand or a tool, separation by rotating a roller, ultrasonic waves, and the like).
Fig. 27C is a schematic cross-sectional view of a display panel in which the substrate 11 is bonded to the conductive layers 15A and 15B exposed at the terminal portion 14 together with the adhesive layer 11C, and the through electrode DE and the FPC21 are provided. The opening of the substrate 11 where the through electrode DE is provided is preferably provided by processing the substrate 11 before bonding the substrate 11.
As the adhesive layer 11C, a light-curable adhesive, a reaction-curable adhesive, a heat-curable adhesive, or an anaerobic adhesive can be used. In addition, an adhesive sheet or the like may be used. As the substrate 11 attached to the above-described display panel, an organic resin material, a glass material whose thickness allows flexibility, or a metal material (including an alloy material) whose thickness allows flexibility, or the like can be used.
The through electrode DE may be formed using various anisotropic conductive films (ACF: anisotropic Conductive Film), anisotropic conductive pastes (ACP: anisotropic Conductive Paste), or the like. The through electrode DE is formed by curing a paste-like or sheet-like material of conductive particles mixed with a thermosetting resin or a thermosetting resin and a photocurable resin. The through electrode DE is formed of a material exhibiting anisotropic conductivity by light irradiation or thermocompression bonding. Examples of the conductive particles used for the through electrode DE include particles obtained by coating spherical organic resin with a thin film metal such as Au, ni, or Co.
As shown in fig. 27A to 27C, the plurality of display panels may have a structure in which the terminal portions are exposed on the back surface side. By adopting this structure, the following structure can be realized: a driving IC (integrated circuit) for driving the display panel, such as the source line driving circuit 31, is attached to the back surface side of each of the plurality of display panels, and is connected via the through electrode. That is, in each display panel, a driver IC may be provided on the back surface of the side where the display portion 13 is seen (the front surface side).
Fig. 27D is a schematic cross-sectional view showing the display panels 450A, 450B as a plurality of adjacent display panels. In fig. 27D, the direction of light emission due to the display image is shown by an arrow on the side (surface side) where the display portion 13 is seen.
The display panel 450A shown in fig. 27D includes a region 401A transmitting visible light, a pixel circuit portion 57A, a terminal portion 14A, and a driver IC35A, FPC a. The display panel 450B shown in fig. 27D includes a region 401B transmitting visible light, a pixel circuit portion 57B, a terminal portion 14B, and a driver IC35B, FPC B. In fig. 27D, each display panel is provided with a through electrode, and the drive IC is connected to the pixel circuit section through the through electrode. With this configuration, since the driver ICs 35A and 35B using the gate line driver circuit 33 as the source line driver circuit 31 can be disposed in each display panel as a divided region, driving with different driving frequencies (frame frequency, refresh frequency, etc.) can be performed for each display panel.
In the display device according to one embodiment of the present invention, each of the sub-display sections divided among the display sections may include a gate line driving circuit and/or a source line driving circuit. This allows the image to be rewritten for each sub display unit. For example, only the image data of the region in which the image is changed may be rewritten in the display unit, and the image data of the region in which the image is not changed may be held, and thus the power consumption may be reduced.
In the display device according to one embodiment of the present invention, the drive frequency (frame frequency, refresh frequency, etc.) at the time of displaying an image can be arbitrarily set for each sub-display section. Therefore, by combining with line-of-sight measurement (eye tracking) or the like, annotation point rendering (Foveated Rendering) which is one of the drawings in which the frame rates of the respective areas are different according to the line of sight of the user can be adopted. Therefore, it is possible to output an image with high display quality at a low load.
At least a part of the structural example shown in the present embodiment and the drawings corresponding to the structural example may be appropriately combined with other structural examples, drawings, and the like.
(Embodiment 2)
In this embodiment, a display device according to an embodiment of the present invention will be described with reference to fig. 28, 29A, and 29B.
The display device of the present embodiment may be a high-resolution display device or a large-sized display device. Therefore, for example, the display device of the present embodiment can be used for a display portion of: electronic devices having a large screen such as a television set, a desktop or notebook type personal computer, a display for a computer or the like, a digital signage, a large-sized game machine such as a pachinko machine, and the like; a digital camera; a digital video camera; a digital photo frame; a mobile telephone; a portable game machine; a portable information terminal; and a sound reproducing device.
[ Display device ]
Fig. 28 shows a perspective view of the display device 300A, and fig. 29A shows a cross-sectional view of the display device 300A.
The display device 300A has a structure in which the substrate 12 and the substrate 11 are bonded. In fig. 28, the substrate 12 is shown in dashed lines.
The display device 300A includes the display portion 13, the connection portion 340, the wiring 365, and the like. The display section 13 includes a plurality of sub-display sections 13A. Fig. 28 shows an example in which an IC373 and an FPC372 are mounted in the display device 300A. Accordingly, the structure shown in fig. 28 may also be referred to as a display module including the display device 300A, IC (integrated circuit) and an FPC.
The connection portion 340 is provided outside the display portion 13. The connection part 340 may be disposed along one or more sides of the display part 13. The number of the connection parts 340 may be one or more. Fig. 28 shows an example in which the connection portion 340 is provided so as to surround the display portion. In the connection part 340, the common electrode of the light emitting device is electrically connected to the conductive layer, and power can be supplied to the common electrode.
The wiring 365 has a function of supplying signals and power to the display portion 13. The signal and power are input to the wiring 365 from the outside through the FPC372 or input to the wiring 365 from the IC 373.
Fig. 28 shows an example in which an IC373 is provided over the substrate 11 by COG method, COF (Chip On Film) method, or the like. As the IC373, for example, an IC including a source line driver circuit or the like can be used. Note that the display device 300A and the display module are not necessarily provided with ICs. Further, the IC may be mounted on the FPC by COF method or the like.
Fig. 29A shows an example of a cross section of a portion of a region including the FPC372, a portion of the display portion 13, a portion of the 340 connection portion 340, and a portion of a region including an end portion of the display device 300A.
The display device 300A shown in fig. 29A includes a transistor 201, a transistor 205, a light-emitting device 330A that emits red light, a light-emitting device 330b that emits green light, a light-emitting device 330c that emits blue light, and the like between the substrate 11 and the substrate 12.
The light emitting device 330a includes a conductive layer 311a, a conductive layer 312a over the conductive layer 311a, and a conductive layer 326a over the conductive layer 312 a. The conductive layer 311a, the conductive layer 312a, and the conductive layer 326a may be referred to as pixel electrodes, or some of the conductive layer 311a, the conductive layer 312a, and the conductive layer 326a may be referred to as pixel electrodes.
The conductive layer 311a is connected to the conductive layer 222b included in the transistor 205 through an opening provided in the insulating layer 324. The end of the conductive layer 312a is located outside the end of the conductive layer 311 a. The end of conductive layer 312a is aligned or substantially aligned with the end of conductive layer 326 a. For example, a conductive layer functioning as a reflective electrode is used as the conductive layer 311a and the conductive layer 312a, and a conductive layer functioning as a transparent electrode is used as the conductive layer 326 a.
The light emitting device 330b includes a conductive layer 311b, a conductive layer 312b over the conductive layer 311b, and a conductive layer 326b over the conductive layer 312 b.
The light emitting device 330c includes a conductive layer 311c, a conductive layer 312c over the conductive layer 311c, and a conductive layer 326c over the conductive layer 312 c.
The conductive layer 311b, the conductive layers 312b and 326b in the light-emitting device 330b, and the conductive layer 311c, the conductive layer 312c, and the conductive layer 326c in the light-emitting device 330c are the same as the conductive layer 311a, the conductive layer 312a, and the conductive layer 326a in the light-emitting device 330a, and thus detailed descriptions thereof are omitted.
A recess is formed in the conductive layer 311a, the conductive layer 311b, and the conductive layer 311c so as to cover an opening provided in the insulating layer 324. The recess is filled with a layer 328.
The layer 328 has a function of planarizing the concave portions of the conductive layer 311a, the conductive layer 311b, and the conductive layer 311 c. The conductive layers 311a, 311b, 311c, and 328 are provided with a conductive layer 312a, 312b, and 312c electrically connected to the conductive layers 311a, 311b, and 311 c. Therefore, a region overlapping with the concave portions of the conductive layer 311a, the conductive layer 311b, and the conductive layer 311c can also be used as a light-emitting region, whereby the aperture ratio of the pixel can be improved.
Layer 328 may be an insulating layer or a conductive layer. Various inorganic insulating materials, organic insulating materials, and conductive materials can be used as the layer 328 as appropriate. In particular, layer 328 is preferably formed using an insulating material.
The layer 328 may suitably use an insulating layer containing an organic material. For example, an acrylic resin, a polyimide resin, an epoxy resin, a polyamide resin, a polyimide amide resin, a silicone resin, a benzocyclobutene resin, a phenol resin, a precursor of the above-described resin, or the like can be used as the layer 328. Further, as the layer 328, a photosensitive resin may be used. The photosensitive resin may use a positive type material or a negative type material.
By using the photosensitive resin, the layer 328 can be manufactured only by the steps of exposure and development, and the influence of dry etching, wet etching, or the like on the surfaces of the conductive layer 311a, the conductive layer 311b, and the conductive layer 311c can be reduced. Further, by using the negative type photosensitive resin formation layer 328, the same photomask (exposure mask) as that used to form the opening of the insulating layer 324 may sometimes be used to form the layer 328.
The top and side surfaces of conductive layer 312a and the top and side surfaces of conductive layer 326a are covered by first layer 313 a. The top and side surfaces of conductive layer 312b and the top and side surfaces of conductive layer 326b are covered by second layer 313 b. In addition, the top and side surfaces of the conductive layer 312c and the top and side surfaces of the conductive layer 326c are covered with the third layer 313 c. Accordingly, the entire region where the conductive layer 312a, the conductive layer 312b, or the conductive layer 312c is provided can be used as a light-emitting region of the light-emitting device 330a, the light-emitting device 330b, or the light-emitting device 330c, so that the aperture ratio of the pixel can be improved.
The side surfaces of the first layer 313a, the second layer 313b, and the third layer 313c are covered with the insulating layer 325 and the insulating layer 327. The sacrificial layer 318a is located between the first layer 313a and the insulating layer 325, the sacrificial layer 318b is located between the second layer 313b and the insulating layer 325, and the sacrificial layer 318c is located between the third layer 313c and the insulating layer 325. A fourth layer 314 is provided over the first layer 313a, the second layer 313b, the third layer 313c, the insulating layer 325, and the insulating layer 327, and a common electrode 315 is provided over the fourth layer 314. The fourth layer 314 and the common electrode 315 are continuous films commonly provided in the light-receiving device and the light-emitting device. In addition, a protective layer 331 is provided over the light emitting devices 330a, 330b, and 330 c.
The protective layer 331 and the substrate 12 are bonded by the adhesive layer 342. As the sealing of the light emitting device, a solid sealing structure, a hollow sealing structure, or the like may be employed. In fig. 29A, a space between the substrate 12 and the substrate 11 is filled with an adhesive layer 342, that is, a solid sealing structure is employed. Alternatively, a hollow sealing structure may be employed in which the space is filled with an inert gas (nitrogen, argon, or the like). At this time, the adhesive layer 342 may be provided so as not to overlap with the light emitting device. In addition, the space may be filled with a resin different from the adhesive layer 342 provided in a frame shape.
In the connection portion 340, a conductive layer 323 is provided over the insulating layer 324. The following examples are shown: the conductive layer 323 has a stacked-layer structure of a conductive film obtained by processing the same conductive film as the conductive layer 311a, the conductive layer 311b, and the conductive layer 311c, a conductive film obtained by processing the same conductive film as the conductive layer 312a, the conductive layer 312b, and the conductive layer 312c, and a conductive film obtained by processing the same conductive film as the conductive layer 326a, the conductive layer 326b, and the conductive layer 326 c. The end portion of the conductive layer 323 is covered with a sacrificial layer, an insulating layer 325, and an insulating layer 327. Further, a fourth layer 314 is provided over the conductive layer 323, and a common electrode 315 is provided over the fourth layer 314. The conductive layer 323 is electrically connected to the common electrode 315 through the fourth layer 314. The fourth layer 314 may not be formed on the connection portion 340. In this case, the conductive layer 323 is in direct contact with and electrically connected to the common electrode 315.
The display device 300A adopts a top emission type. The light emitting device emits light to one side of the substrate 12. The substrate 12 is preferably made of a material having high transparency to visible light. The pixel electrode includes a material that reflects visible light, and the counter electrode (common electrode 315) includes a material that transmits visible light.
The insulating layer 215 is provided so as to cover the transistor. The insulating layer 324 is provided so as to cover the transistor, and is used as a planarizing layer. The number of insulating layers covering the transistor is not particularly limited, and may be one or two or more.
Preferably, a material which is not easily diffused by impurities such as water and hydrogen is used for at least one of insulating layers covering the transistor. Thereby, the insulating layer can be used as a blocking insulating layer. By adopting such a structure, diffusion of impurities into the transistor from the outside can be effectively suppressed, so that the reliability of the display device can be improved.
The insulating layer 215 is preferably an inorganic insulating film. As the inorganic insulating film, for example, a silicon nitride film, a silicon oxynitride film, a silicon oxide film, a silicon nitride oxide film, an aluminum nitride film, or the like can be used. Further, a hafnium oxide film, an yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, a neodymium oxide film, or the like can be used. Further, two or more of the insulating films may be stacked.
The insulating layer 324 serving as a planarizing layer may be an organic insulating film as appropriate. Examples of the material that can be used for the organic insulating film include acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimide amide resin, silicone resin, benzocyclobutene resin, phenol resin, and precursors of these resins. The insulating layer 324 may have a stacked-layer structure of an organic insulating film and an inorganic insulating film. The outermost layer of the insulating layer 324 is preferably used as an etching protective film. Thus, formation of a recess in the insulating layer 324 can be suppressed when the conductive layer 311b, the conductive layer 312b, the conductive layer 326b, or the like is processed. Alternatively, a concave portion may be provided in the insulating layer 324 when the conductive layer 311b, the conductive layer 312b, the conductive layer 326b, or the like is formed.
The connection portion 204 is provided in a region of the substrate 11 which does not overlap with the substrate 12. In the connection portion 204, the wiring 365 is electrically connected to the FPC372 through the conductive layer 366 and the connection layer 203. The following examples are shown: the conductive layer 366 has a stacked structure of a conductive film obtained by processing the same conductive films as the conductive layers 311a, 311b, and 311c, a conductive film obtained by processing the same conductive films as the conductive layers 312a, 312b, and 312c, and a conductive film obtained by processing the same conductive films as the conductive layers 326a, 326b, and 326 c. The conductive layer 366 is exposed on the top surface of the connection portion 204. Therefore, the connection portion 204 can be electrically connected to the FPC372 through the connection layer 203.
The light shielding layer 317 is preferably provided on the substrate 11 side surface of the substrate 12. The light shielding layer 317 may be disposed between adjacent light emitting devices and in the connection portion 340, etc. Further, various optical members may be arranged outside the substrate 12. As the optical member, a polarizing plate, a retardation plate, a light diffusion layer (diffusion film or the like), an antireflection layer, a condensing film (condensing film) and the like can be used. Further, an antistatic film that suppresses adhesion of dust, a film having water repellency that is less likely to be stained, a hard coat film that suppresses damage during use, an impact absorbing layer, and the like may be disposed on the outside of the substrate 12.
By forming the protective layer 331 covering the light emitting device and the light receiving device, entry of impurities such as water into the light emitting device and the light receiving device can be suppressed, and thus the reliability of the light emitting device and the light receiving device can be improved.
As the substrate 11 and the substrate 12, glass, quartz, ceramics, sapphire, resin, metal, alloy, semiconductor, or the like can be used. The substrate on the side from which light from the light-emitting device is extracted uses a material that transmits the light. By using a material having flexibility for the substrate 11 and the substrate 12, the flexibility of the display device can be improved. As the substrate 11 or the substrate 12, a polarizing plate can be used.
As the substrate 11 and the substrate 12, the following materials can be used: polyester resins such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile resins, acrylic resins, polyimide resins, polymethyl methacrylate resins, polycarbonate (PC) resins, polyethersulfone (PES) resins, polyamide resins (nylon, aramid, etc.), polysiloxane resins, cycloolefin resins, polystyrene resins, polyamide-imide resins, polyurethane resins, polyvinyl chloride resins, polyvinylidene chloride resins, polypropylene resins, polytetrafluoroethylene (PTFE) resins, ABS resins, cellulose nanofibers, and the like. Further, glass having a thickness of a degree of flexibility may be used as one or both of the substrate 11 and the substrate 12.
In the case of overlapping the circularly polarizing plate on the display device, a substrate having high optical isotropy is preferably used as the substrate included in the display device. Substrates with high optical isotropy have lower birefringence (also referred to as lower birefringence).
The absolute value of the phase difference value (retardation value) of the substrate having high optical isotropy is preferably 30nm or less, more preferably 20nm or less, and further preferably 10nm or less.
Examples of the film having high optical isotropy include a cellulose triacetate (TAC, also referred to as Cellulose triacetate) film, a cycloolefin polymer (COP) film, a cycloolefin copolymer (COC) film, and an acrylic film.
When a film is used as a substrate, there is a possibility that shape changes such as wrinkles in the display panel occur due to water absorption of the film. Therefore, a film having low water absorption is preferably used as the substrate. For example, a film having a water absorption of 1% or less is preferably used, a film having a water absorption of 0.1% or less is more preferably used, and a film having a water absorption of 0.01% or less is more preferably used.
The adhesive layer 342 may be formed using various types of cured adhesives such as a photo-cured adhesive such as an ultraviolet-cured adhesive, a reaction-cured adhesive, a heat-cured adhesive, and an anaerobic adhesive. Examples of such binders include epoxy resins, acrylic resins, silicone resins, phenolic resins, polyimide resins, imide resins, PVC (polyvinyl chloride) resins, PVB (polyvinyl butyral) resins, and EVA (ethylene-vinyl acetate) resins. In particular, a material having low moisture permeability such as epoxy resin is preferably used. In addition, a two-liquid mixed type resin may be used. In addition, an adhesive sheet or the like may be used.
The connection layer 203 may use ACF, ACP, or the like.
Examples of materials that can be used for the gate electrode, source electrode, drain electrode, various wirings constituting a display device, and conductive layers such as electrodes include metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, and tungsten, and alloys containing the metals as main components. A single layer or a stack of films comprising these materials may be used.
As the conductive material having light transmittance, a conductive oxide such as indium oxide, indium tin oxide, indium zinc oxide, or zinc oxide containing gallium, or graphene can be used. Alternatively, a metal material such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, or titanium, or an alloy material containing the metal material may be used. Or a nitride (e.g., titanium nitride) of the metal material, or the like may also be used. Further, when a metal material or an alloy material (or their nitrides) is used, it is preferable to form it thin so as to have light transmittance. In addition, a laminated film of the above materials can be used as the conductive layer. For example, a laminate film of an alloy of silver and magnesium and indium tin oxide is preferable because conductivity can be improved. The above material can be used for conductive layers such as various wirings and electrodes constituting a display device and conductive layers included in a light-emitting device (conductive layers serving as a pixel electrode or a common electrode).
Examples of the insulating material that can be used for each insulating layer include resins such as acrylic resin and epoxy resin, and inorganic insulating materials such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, and aluminum oxide.
< Transistor >
Fig. 29B is an enlarged view of a cross section including the transistor 201 and the transistor 205.
The transistor 205 includes a semiconductor layer 108, an insulating layer 117, an insulating layer 110, and a conductive layer 112 stacked in this order. The insulating layer 117 and a part of the insulating layer 110 are used as gate insulating layers of the transistor 201. The conductive layer 112 is used as a gate electrode of the transistor 201. The transistor 201 is a so-called top gate transistor in which a gate electrode is provided over the semiconductor layer 108.
The transistor 201 includes a semiconductor layer 208, an insulating layer 110, and a conductive layer 212 stacked in this order. A portion of the insulating layer 110 is used as a gate insulating layer of the transistor 205. Conductive layer 212 is used as a gate electrode of transistor 205. The transistor 205 is a top gate transistor provided with a gate electrode over the semiconductor layer 208. The formed surface of the semiconductor layer of the transistor 205 is different from that of the transistor 201. Further, the structure of the gate insulating layer of the transistor 205 is different from that of the transistor 201.
The transistor 201 and the transistor 205 can be formed by the same process except for the semiconductor layer. Thus, even if two kinds of transistors are mixed, an increase in the number of steps can be suppressed.
The transistor 205 shown in fig. 29B includes the conductive layer 106 functioning as a back gate. Further, the transistor 201 illustrated in fig. 29B includes a conductive layer 206 functioning as a back gate.
In fig. 29B, a conductive layer 106 is provided so as to be in contact with the substrate 11. An insulating layer 103 is provided so as to be in contact with the conductive layer 106 and the substrate 11. A semiconductor layer 108 is provided so as to be in contact with the insulating layer 103. An insulating layer 117 is provided so as to be in contact with the top surface of the substrate 11 of the insulating layer 103 and the top and side surfaces of the semiconductor layer 108. A semiconductor layer 208 is provided so as to be in contact with the insulating layer 117. That is, the semiconductor layer 208 is provided on a different face from the semiconductor layer 108. The insulating layer 117 is used as a base film in the transistor 201. The insulating layer 110 is provided so as to be in contact with the top surface of the insulating layer 117 and the top and side surfaces of the semiconductor layer 208. A conductive layer 112 and a conductive layer 212 are provided so as to be in contact with the insulating layer 110. The conductive layer 112 has a region overlapping with the semiconductor layer 108 through the insulating layer 117 and the insulating layer 110. The conductive layer 212 has a region overlapping with the semiconductor layer 208 through the insulating layer 110.
As shown in fig. 29B, the transistor 201 and the transistor 205 preferably further include an insulating layer 118. The insulating layer 118 is provided so as to cover the insulating layer 110, the conductive layer 112, and the conductive layer 212, and is used as a protective layer for protecting the transistor 201 and the transistor 205.
The transistor 205 may also include a conductive layer 222a and a conductive layer 222b over the insulating layer 118. The conductive layer 222a is used as one of a source electrode and a drain electrode of the transistor 205, and the conductive layer 222b is used as the other of the source electrode and the drain electrode of the transistor 205. The conductive layer 222a and the conductive layer 222b are electrically connected to the low-resistance region 108N in the semiconductor layer 108 through openings provided in the insulating layer 118, the insulating layer 110, and the insulating layer 117, respectively.
Transistor 201 may also include conductive layer 365a and conductive layer 365b over insulating layer 118. The conductive layer 365a is used as one of a source electrode and a drain electrode of the transistor 201, and the conductive layer 365b is used as the other of the source electrode and the drain electrode of the transistor 201. Conductive layer 365a and conductive layer 365b are electrically connected to low-resistance region 208N in semiconductor layer 208 through openings provided in insulating layer 118 and insulating layer 110, respectively.
Here, the semiconductor layer 108 and the semiconductor layer 208 preferably contain metal oxides having different compositions. The semiconductor layer 108 and the semiconductor layer 208 may be formed by processing metal oxide films having different compositions. The display device according to one embodiment of the present invention includes a plurality of transistors having different semiconductor layer compositions over the same substrate, and constituent elements other than the semiconductor layer can be formed by the same process.
As described above, the electrical characteristics and reliability of the transistor differ according to the composition of the metal oxide used for the semiconductor layer. Therefore, by making the composition of the metal oxide different depending on the electric characteristics and reliability required for the transistor, a display device having both excellent electric characteristics and high reliability can be realized.
The case where the transistor 201 is used as a transistor required to have a large on-state current will be described as an example. For example, when in—ga—zn oxide is used for both the semiconductor layer 108 and the semiconductor layer 208, a metal oxide having a higher ratio of the atomic number of indium relative to the atomic number of indium containing a metal element than the semiconductor layer 108 can be used for the semiconductor layer 208. Further, for example, the semiconductor layer 108 may use a metal oxide having a higher atomic number ratio of gallium to the atomic number of the metal element contained than the semiconductor layer 208.
In the same manner as In the case where an In-Ga-Zn oxide is used for the semiconductor layer 108 and a metal oxide containing indium other than the In-Ga-Zn oxide is used for the semiconductor layer 208, a metal oxide having a higher ratio of the number of atoms of indium to the number of atoms of a metal element than the semiconductor layer 108 may be used for the semiconductor layer 208.
The semiconductor layer 108 may be formed using a metal oxide containing indium other than In-Ga-Zn oxide. In this case, as well, as described above, a metal oxide having a higher atomic ratio of indium to the atomic ratio of the metal element can be used for the semiconductor layer 208 than for the semiconductor layer 108.
Alternatively, a metal oxide having a higher atomic ratio of indium to the atomic ratio of the metal element can be used for the semiconductor layer 108 than for the semiconductor layer 208.
The semiconductor layer 108 includes a region overlapping with the conductive layer 112 and a pair of low-resistance regions 108N sandwiching the region. The region of the semiconductor layer 108 overlapping with the conductive layer 112 is used as a channel formation region of the transistor 205. A pair of low resistance regions 108N are used as source and drain regions of the transistor 205. Similarly, the semiconductor layer 208 includes a channel formation region overlapping with the conductive layer 212 and a pair of low-resistance regions 208N sandwiching the region.
The low-resistance region 108N in the transistor 205 can also be said to be a region having lower resistance, a region having higher carrier concentration, a region having higher oxygen vacancy density, a region having higher impurity concentration, or a region exhibiting N-type than a channel formation region of the transistor 205. Similarly, the low-resistance region 208N in the transistor 201 can be said to be a region having a lower resistance, a region having a higher carrier concentration, a region having a higher oxygen vacancy density, a region having a higher impurity concentration, or a region exhibiting an N-type property as compared with a channel formation region of the transistor 201.
The low-resistance region 108N and the low-resistance region 208N are regions containing impurity elements. Examples of the impurity element include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, and a rare gas. Typical examples of the rare gas include helium, neon, argon, krypton, and xenon. In particular, the low resistance region 108N and the low resistance region 208N preferably include boron or phosphorus. The low-resistance region 108N and the low-resistance region 208N may include two or more of the above elements. The low-resistance region 108N and the low-resistance region 208N may contain impurity elements different from each other.
For example, the low-resistance region 108N and the low-resistance region 208N may be formed by adding impurities to the insulating layer 110 using the conductive layer 112 or the conductive layer 212 as a mask.
The display device 300B shown in fig. 30 is an example in which the transistor 201 and the transistor 205 are used as transistors constituting the display portion 13. By including the transistor 201 and the transistor 205 in the pixel circuit in the display portion 13, a display device having high display quality and excellent reliability can be realized. In addition, the manufacturing process of the display device can be simplified as compared with fig. 31 described later.
The display device 300C shown in fig. 31 is an example in which the transistor 201, the transistor 205, and the transistor 202 are used as transistors constituting the display portion 13. By making the pixel circuit in the display portion 13 include the transistor 201, the transistor 202, and the transistor 205, a display device having high display quality and excellent reliability can be realized.
The transistor 202 includes a semiconductor layer 411, an insulating layer 412, a conductive layer 413, and the like. The semiconductor layer 411 includes a channel formation region 411i and a low resistance region 411n. The semiconductor layer 411 contains silicon. The semiconductor layer 411 preferably contains polysilicon. As the polysilicon, LTPS can be used, for example. A portion of the insulating layer 412 is used as a gate insulating layer. A portion of the conductive layer 413 is used as a gate electrode.
The low-resistance region 311n is a region containing an impurity element. For example, when the transistor 202 is an n-channel transistor, phosphorus, arsenic, or the like may be added to the low-resistance region 311 n. On the other hand, when the transistor 202 is a p-channel transistor, boron, aluminum, or the like may be added to the low-resistance region 311 n. In addition, in order to control the threshold voltage of the transistor 202, the impurity described above may be added to the channel formation region 311i.
The transistor 202 may also include a conductive layer 421a and a conductive layer 421b over the insulating layer 118. The conductive layer 421a is used as one of a source electrode and a drain electrode of the transistor 202, and the conductive layer 421b is used as the other of the source electrode and the drain electrode of the transistor 202. The conductive layers 421a and 421b are electrically connected to the low-resistance region 411n through openings provided in the insulating layers 118, 110, 117, and 412, respectively.
Here, the conductive layers 421a and 421b which are electrically connected to the transistor 202 are preferably formed by processing the same conductive film as the conductive layers 222a, 222b, 365a, and 365 b. This is preferable because the manufacturing process can be simplified.
Further, the conductive layer 413 functioning as the gate electrode of the transistor 202, the conductive layer 206 functioning as the second gate electrode of the transistor 201, and the conductive layer 106 functioning as the second gate electrode of the transistor 205 are preferably formed by processing the same conductive film. This is preferable because the manufacturing process can be simplified.
In addition, the transistor 202 may also include a second gate electrode. When the transistor 202 includes a second gate electrode, for example, a conductive layer serving as the second gate electrode is provided over the substrate 11, an insulating layer is provided so as to be in contact with the conductive layer and the top surface of the substrate 11, and the semiconductor layer 411 is provided over the insulating layer. In addition, the conductive layer 413 and the conductive layer functioning as the second gate electrode preferably have regions overlapping each other.
At least a part of this embodiment can be implemented in appropriate combination with other embodiments described in this specification.
Embodiment 3
In this embodiment, a light-emitting device which can be used in a display device according to one embodiment of the present invention will be described.
As shown in fig. 32A, the light-emitting device includes an EL layer 786 between a pair of electrodes (a lower electrode 772, an upper electrode 788). The EL layer 786 may be formed of a plurality of layers such as the layer 4420, the light-emitting layer 4411, and the layer 4430. The layer 4420 may include, for example, a layer containing a substance having high electron injection property (an electron injection layer), a layer containing a substance having high electron transport property (an electron transport layer), or the like. The light-emitting layer 4411 includes, for example, a light-emitting compound. The layer 4430 may include, for example, a layer containing a substance having high hole injection property (a hole injection layer) and a layer containing a substance having high hole transport property (a hole transport layer).
The structure including the layer 4420, the light-emitting layer 4411, and the layer 4430 which are provided between a pair of electrodes can be used as a single light-emitting unit, and the structure of fig. 32A is referred to as a single structure in this specification.
Fig. 32B shows a modified example of the EL layer 786 included in the light-emitting device shown in fig. 32A. Specifically, the light-emitting device shown in fig. 32B includes a layer 4431 over a lower electrode 772, a layer 4432 over a layer 4431, a light-emitting layer 4411 over a layer 4432, a layer 4421 over the light-emitting layer 4411, a layer 4422 over the layer 4421, and an upper electrode 788 over the layer 4422. For example, when the lower electrode 772 is used as an anode and the upper electrode 788 is used as a cathode, the layer 4431 is used as a hole injection layer, the layer 4432 is used as a hole transport layer, the layer 4421 is used as an electron transport layer, and the layer 4422 is used as an electron injection layer. Or when the lower electrode 772 is used as a cathode and the upper electrode 788 is used as an anode, the layer 4431 is used as an electron injection layer, the layer 4432 is used as an electron transport layer, the layer 4421 is used as a hole transport layer, and the layer 4422 is used as a hole injection layer. By adopting the above layer structure, carriers can be efficiently injected into the light-emitting layer 4411, whereby recombination efficiency of carriers in the light-emitting layer 4411 can be improved.
As shown in fig. 32C and 32D, a structure in which a plurality of light-emitting layers (light-emitting layers 4411, 4412, and 4413) are provided between the layers 4420 and 4430 is also a modification example of a single structure.
As shown in fig. 32E and 32F, a structure in which a plurality of light emitting units (EL layers 786a and 786 b) are connected in series with a charge generation layer 4440 interposed therebetween is referred to as a series structure in this specification. In addition, the series structure may be referred to as a stacked structure. By adopting the series structure, a light-emitting device capable of emitting light with high luminance can be realized.
In fig. 32C and 32D, a light-emitting material which emits light of the same color, or even the same light-emitting material may be used for the light-emitting layer 4411, the light-emitting layer 4412, and the light-emitting layer 4413. For example, a light-emitting material which emits blue light may be used for the light-emitting layer 4411, the light-emitting layer 4412, and the light-emitting layer 4413. As the layer 785 shown in fig. 32D, a color conversion layer may be provided. By using quantum dots as the color conversion layer, a light-emitting device having good color purity and good external quantum efficiency can be realized.
In addition, light-emitting materials having different light-emitting colors may be used for the light-emitting layer 4411, the light-emitting layer 4412, and the light-emitting layer 4413. When the light emitted from each of the light-emitting layers 4411, 4412, and 4413 is in a complementary color relationship, white light emission can be obtained. As the layer 785 shown in fig. 32D, a color filter (also referred to as a coloring layer) may be provided. When the white light passes through the color filter, light of a desired color can be obtained.
In fig. 32E and 32F, a light-emitting material which emits light of the same color, or even the same light-emitting material may be used for the light-emitting layer 4411 and the light-emitting layer 4412. Alternatively, light-emitting materials having different light-emitting colors may be used for the light-emitting layer 4411 and the light-emitting layer 4412. When the light emitted from the light-emitting layer 4411 and the light emitted from the light-emitting layer 4412 are in a complementary color relationship, white light emission can be obtained. Fig. 32F shows an example in which a layer 785 is also provided. One or both of a color conversion layer and a color filter (coloring layer) can be used as the layer 785.
Note that in fig. 32C, 32D, 32E, and 32F, as shown in fig. 32B, the layers 4420 and 4430 may have a stacked structure including two or more layers.
A structure in which light emission colors (for example, blue (B), green (G), and red (R)) are formed for each light emitting device is referred to as a SBS (Side By Side) structure.
The light emitting color of the light emitting device can be red, green, blue, cyan, magenta, yellow, white, or the like depending on the material constituting the EL layer 786. In addition, when the light emitting device has a microcavity structure, color purity can be further improved.
The white light emitting device preferably has a structure in which the light emitting layer contains two or more kinds of light emitting substances. In order to obtain white light emission, two or more kinds of light-emitting substances each having a complementary color relationship may be selected. For example, by placing the light-emitting color of the first light-emitting layer and the light-emitting color of the second light-emitting layer in a complementary relationship, a light-emitting device that emits light in white color as a whole can be obtained. In addition, the same applies to a light-emitting device including three or more light-emitting layers.
The light-emitting layer preferably contains two or more kinds of light-emitting substances each of which emits light such as R (red), G (green), B (blue), Y (yellow), O (orange), and the like. Or preferably comprises two or more luminescent materials each of which comprises two or more spectral components in R, G, B.
This embodiment mode can be combined with other embodiment modes as appropriate.
Embodiment 4
In this embodiment mode, an electronic device including a display device manufactured by using one embodiment mode of the present invention will be described.
The electronic device described below is an electronic device including the display device according to one embodiment of the present invention in a display portion, and thus can realize high definition. In addition, high definition and large screen electronic devices can be realized at the same time.
An image having a resolution of, for example, 4K2K, 8K4K, 16K8K or higher can be displayed on the display portion of the electronic device according to one embodiment of the present invention.
Examples of the electronic device include a large-sized electronic device having a relatively large screen such as a television set, a notebook-sized personal computer, a display device, a digital signage, a pachinko machine, and a game machine, and a digital camera, a digital video camera, a digital photo frame, a mobile phone, a portable game machine, a portable information terminal, and a sound reproducing device.
An electronic device according to an embodiment of the present invention can be assembled along a plane or a curved surface of an inner wall or an outer wall of a house, a building, or the like, an interior or an exterior of an automobile, or the like.
Fig. 33A is an external view of a camera 8000 mounted with a viewfinder 8100.
The camera 8000 includes a housing 8001, a display portion 8002, operation buttons 8003, shutter buttons 8004, and the like. Further, a detachable lens 8006 is attached to the camera 8000.
In the camera 8000, the lens 8006 and the housing may be formed integrally.
The camera 8000 can perform imaging by pressing a shutter button 8004 or touching a display portion 8002 serving as a touch panel.
The housing 8001 includes an interposer having electrodes, and may be connected to a flash device or the like in addition to the viewfinder 8100.
The viewfinder 8100 includes a housing 8101, a display portion 8102, buttons 8103, and the like.
The housing 8101 is attached to the camera 8000 by an embedder that is embedded in the embedder of the camera 8000. The viewfinder 8100 may display an image or the like received from the camera 8000 on the display portion 8102.
The button 8103 is used as a power button or the like.
The display device according to one embodiment of the present invention can be used for the display portion 8002 of the camera 8000 and the display portion 8102 of the viewfinder 8100. The camera 8000 may have a viewfinder.
Fig. 33B is an external view of the head mounted display 8200.
The head mount display 8200 includes a mounting portion 8201, a lens 8202, a main body 8203, a display portion 8204, a cable 8205, and the like. Further, a battery 8206 is incorporated in the mounting portion 8201.
Power is supplied from the battery 8206 to the main body 8203 via the cable 8205. The main body 8203 includes a wireless receiver or the like, and can display received image information or the like on the display unit 8204. Further, since the main body 8203 includes a camera, the actions of the eyeball and the eyelid of the user can be used as an input method.
In addition, a plurality of electrodes may be provided to the mounting portion 8201 at positions contacted by the user to detect a current flowing through the electrodes according to the movement of the eyeballs of the user, thereby realizing a function of recognizing the line of sight of the user. Further, the electrode may have a function of monitoring the pulse of the user based on the current flowing through the electrode. The mounting portion 8201 may have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, or may have a function of displaying biological information of the user on the display portion 8204, a function of changing an image displayed on the display portion 8204 in synchronization with the operation of the head of the user, or the like.
The display device according to one embodiment of the present invention can be used for the display portion 8204.
Fig. 33C, 33D, and 33E are external views of the head mounted display 8300. The head mount display 8300 includes a frame body 8301, a display portion 8302, a band-shaped fixing tool 8304, and a pair of lenses 8305.
The user can see the display on the display portion 8302 through the lens 8305. It is preferable that the display portion 8302 be curved because the user can feel a high sense of realism. Further, the images displayed on different areas of the display portion 8302 are seen through the lenses 8305, respectively, and three-dimensional display or the like using parallax can be performed. In addition, one embodiment of the present invention is not limited to the configuration in which one display portion 8302 is provided, and two display portions 8302 may be provided so that two different display portions are respectively arranged for a pair of eyes of a user.
The display device according to one embodiment of the present invention can be used for the display portion 8302. Since the display device including the semiconductor device according to one embodiment of the present invention has extremely high resolution, even if the display device is enlarged by using the lens 8305 as shown in fig. 33E, an image with a higher sense of reality can be displayed without making the user see the pixels.
The electronic apparatus shown in fig. 34A to 34G includes a housing 9000, a display portion 9001, a speaker 9003, an operation key 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (the sensor has a function of measuring a force, a displacement, a position, a speed, an acceleration, an angular velocity, a rotation speed, a distance, light, liquid, magnetism, temperature, a chemical substance, sound, time, hardness, an electric field, electric current, voltage, electric power, radiation, flow, humidity, inclination, vibration, smell, or infrared), a microphone 9008, or the like.
The electronic devices shown in fig. 34A to 34G have various functions. For example, it may have the following functions: a function of displaying various information (still image, moving image, character image, etc.) on the display section; a function of the touch panel; a function of displaying a calendar, date, time, or the like; functions of controlling processing by using various software (programs); a function of performing wireless communication; a function of reading out a program or data stored in the storage medium to process; etc. Note that the functions of the electronic apparatus are not limited to the above functions, but may have various functions. The electronic device may include a plurality of display portions. In addition, the electronic device may be provided with a camera or the like so as to have the following functions: a function of capturing a still image or a moving image to store the captured image in a storage medium (an external storage medium or a storage medium built in a camera); a function of displaying the photographed image on a display section; etc.
Next, the electronic devices shown in fig. 34A to 34G are described in detail.
Fig. 34A is a perspective view showing the television device 9100. The large display portion 9001, which is 50 inches or more or 100 inches or more, for example, can be incorporated into the television set 9100.
Fig. 34B is a perspective view showing the portable information terminal 9101. The portable information terminal 9101 can be used as a smart phone, for example. The portable information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, and the like. Further, the portable information terminal 9101 may display text or image information on a plurality of sides thereof. Fig. 34B shows an example in which three icons 9050 are displayed. Further, information 9051 indicated by a dotted rectangle may be displayed on the other surface of the display portion 9001. As an example of the information 9051, information indicating the receipt of an email, SNS, a telephone, or the like can be given; a title of an email, SNS, or the like; a sender name; a date; time; a battery balance; and antenna received signal strength, etc. Or an icon 9050 or the like may be displayed at a position where the information 9051 is displayed.
Fig. 34C is a perspective view showing the portable information terminal 9102. The portable information terminal 9102 has a function of displaying information on three or more surfaces of the display portion 9001. Here, examples are shown in which the information 9052, the information 9053, and the information 9054 are displayed on different surfaces. For example, the user may confirm the information 9053 displayed at a position that can be seen from above the portable information terminal 9102 in a state where the portable information terminal 9102 is placed in a coat pocket. The user can confirm the display without taking out the portable information terminal 9102 from the pocket, whereby it is possible to determine whether to answer a call, for example.
Fig. 34D is a perspective view showing the wristwatch-type portable information terminal 9200. The display surface of the display portion 9001 is curved, and can display on the curved display surface. For example, the portable information terminal 9200 can perform handsfree call by communicating with a headset which can perform wireless communication. The portable information terminal 9200 includes a connection terminal 9006, and can exchange data with other information terminals or can be charged. In addition, the charging operation can also be performed by using wireless power supply.
Fig. 34E, 34F, and 34G are perspective views showing the portable information terminal 9201 that can be folded. Fig. 34E is a perspective view of the portable information terminal 9201 in an expanded state, fig. 34G is a perspective view of the portable information terminal 9201 in a folded state, and fig. 34F is a perspective view of the portable information terminal 9201 in a state in the middle of changing from one state to the other state in fig. 34E and 34G. The portable information terminal 9201 has good portability in a folded state and excellent display versatility in an unfolded state because it has a large display area that is seamlessly spliced. The display portion 9001 included in the portable information terminal 9201 is supported by three housings 9000 connected to the hinge 9055. For example, the display portion 9001 may be curved with a radius of curvature of 1mm or more and 150mm or less.
Fig. 35A shows an example of a television apparatus. The display portion 7500 of the television device 7100 is assembled in the housing 7101. Here, a structure in which the housing 7101 is supported by a bracket 7103 is shown.
The television device 7100 shown in fig. 35A can be operated by an operation switch provided in the housing 7101 or a remote control operation device 7111 provided separately. Further, the touch panel may be applied to the display portion 7500, and the operation of the television device 7100 may be performed by touching the display portion 7500 with a finger or the like. The remote controller 7111 may include a display unit in addition to the operation buttons.
Further, the television device 7100 may include not only a receiver of television broadcasting but also a communication device for connecting to a communication network.
Fig. 35B shows a notebook personal computer 7200. The notebook personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, and the like. The display portion 7500 is incorporated in the housing 7211.
Fig. 35C shows an example of a digital signage (DIGITAL SIGNAGE).
The digital signage 7300 shown in fig. 35C includes a housing 7301, a display portion 7500, a speaker 7303, and the like. Further, an LED lamp, an operation key (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like may be included.
The larger the display portion 7500 is, the larger the amount of information that can be provided at a time is, and the attention is easily drawn, whereby, for example, the advertising effect can be improved.
The touch panel is preferably used for the display portion 7500 so that a user can operate the touch panel. Thus, the advertisement system can be used not only for advertisement, but also for providing route information, traffic information, guidance of commercial facilities, and other information required by users.
As shown in fig. 35C, the digital signage 7300 can be preferably interlocked with an information terminal apparatus 7311 such as a smart phone carried by a user by wireless communication. For example, information of an advertisement displayed on the display portion 7500 may be displayed on the screen of the information terminal device 7311, and by operating the information terminal device 7311, the display of the display portion 7500 may be switched.
Further, a game can be executed on the digital signage 7300 with the information terminal apparatus 7311 as an operation unit (controller). Thus, a plurality of unspecified users can participate in the game at the same time, and enjoy the game.
Fig. 35D shows a digital signage 7400 provided on an inner wall 7401 of a cylindrical space. The digital signage 7400 includes a plurality of imaging devices 7402 and a plurality of acoustic devices 7403 in addition to a display portion 7500 provided along a curved surface of the inner wall 7401. The digital signage 7400 can be linked to the operation of the display 7500 and the audio device 7403 by a plurality of imaging devices 7402 for performing line-of-sight measurement (eye tracking) or detecting gestures of the user. For example, the display portion 7500 can be switched and the sound of the audio device 7403 can be switched by the user's line of sight to the information of the advertisement displayed on the display portion 7500. Thus, the user can enjoy highly realistic display, sound, and the like.
The display device according to one embodiment of the present invention can be applied to the display portion 7500 shown in fig. 35A to 35D.
At least a part of this embodiment can be implemented in combination with other embodiments described in this specification as appropriate.
(Additional description of the descriptions of the present specification and the like)
Next, explanation will be given of the above embodiment and each structure in the embodiment.
The structure shown in each embodiment mode can be combined with the structure shown in other embodiment modes as appropriate to constitute one embodiment mode of the present invention. Further, when a plurality of structural examples are shown in one embodiment, these structural examples may be appropriately combined.
In addition, the content (or a part thereof) described in one embodiment may be applied, combined, or replaced with other content (or a part thereof) described in the embodiment and/or content (or a part thereof) described in one or more other embodiments.
Note that the content described in the embodiments refers to the content described in the various drawings or the content described in the specification.
Further, by combining the drawing (or a part thereof) shown in one embodiment with other parts of the drawing, other drawings (or a part thereof) shown in the embodiment, and/or drawings (or a part thereof) shown in one or more other embodiments, more drawings can be constituted.
In this specification and the like, constituent elements are classified according to functions and are represented by blocks independent of each other in a block diagram. However, it is difficult to classify constituent elements by function in an actual circuit or the like, and one circuit may involve a plurality of functions or a plurality of circuits may involve one function. Accordingly, the division of blocks in the block diagrams is not limited to the constituent elements described in the specification, and may be appropriately different according to circumstances.
In the drawings, the size, thickness of layers, or regions are sometimes exaggerated for clarity of illustration. Accordingly, the present invention is not limited to the dimensions in the drawings. The drawings are shown in any size for clarity, and are not limited to the shapes, values, etc. shown in the drawings. For example, unevenness of signals, voltages, or currents due to noise, timing deviation, or the like may be included.
In this specification and the like, when describing a connection relation of a transistor, expressions of "one of a source and a drain" (a first electrode or a first terminal), "the other of the source and the drain" (a second electrode or a second terminal) are used. This is because the source and drain of the transistor are interchanged according to the structure, operating conditions, or the like of the transistor. Note that the source and the drain of the transistor may be appropriately referred to as a source (drain) terminal, a source (drain) electrode, or the like, as the case may be.
In this specification and the like, the "electrode" or the "wiring" does not limit the functions of the constituent elements. For example, an "electrode" is sometimes used as part of a "wiring" and vice versa. Further, "electrode" or "wiring" includes a case where a plurality of "electrodes" or "wirings" are formed integrally, and the like.
In this specification and the like, the voltage and the potential can be appropriately changed. The voltage refers to a potential difference from a reference potential, and when the reference potential is, for example, a ground voltage (ground voltage), the voltage may be referred to as a potential. The ground potential does not necessarily mean 0V. Note that the potentials are opposite, and the potential supplied to the wiring or the like sometimes varies according to the reference potential.
In this specification and the like, words such as "film" and "layer" may be exchanged with each other according to the situation or state. For example, the "conductive layer" may be replaced with the "conductive film" in some cases. In addition, the "insulating film" may be replaced with an "insulating layer" in some cases.
In this specification and the like, a switch means an element having a function of controlling whether or not to flow a current by changing to a conductive state (on state) or a nonconductive state (off state). Or a switch refers to an element having a function of selecting and switching a current path.
In this specification and the like, for example, a channel length refers to a distance between a source and a drain in a region where a semiconductor (or a portion where a current flows in the semiconductor when the transistor is in an on state) and a gate overlap or a region where a channel is formed in a top view of the transistor.
In this specification and the like, for example, a channel width refers to a length of a region where a semiconductor (or a portion where a current flows in the semiconductor when a transistor is in an on state) and a gate electrode overlap, or a portion where a source and a drain oppose each other in a region where a channel is formed.
In this specification and the like, "a and B connected" includes a case where a and B are electrically connected in addition to a case where a and B are directly connected. The description of "electrically connecting a and B" refers to a case where an object having a certain electric action is present between a and B, and the transmission and reception of electric signals of a and B are enabled.
[ Description of the symbols ]
11: Substrate, 12: substrate, 13A: secondary display unit, 13: display unit, 14: terminal portion, 20: layer, 30: drive circuit portion, 31: source line driving circuit, 33: gate line driving circuit, 34: pulse output circuit, 39: division, 40: source line driving circuit, 41: control circuit, 50: layer, 51: pixel circuit, 55A: transistor, 55B: transistor, 55C: transistor, 55D: transistor, 57: pixel circuit sections 56A: capacitor, 56: capacitor, 59: division, 60: layer, 61: a display element.