Disclosure of Invention
The embodiment of the invention aims to provide an excitation signal generation method, an excitation signal generation device, chip test equipment and a storage medium, so as to realize quick generation of an excitation signal. The specific technical scheme is as follows:
In a first aspect, an embodiment of the present invention provides a method for generating an excitation signal, which is applied to a chip test device, where the method includes:
Obtaining a target value change dump VCD file;
Determining the time when the level value of the excitation signal changes and the level value after the change according to the waveform information of the excitation signal recorded in the target VCD file, and determining the waveform time sequence relation of the excitation signal;
And generating an excitation signal according to the waveform time sequence relation.
In one embodiment of the present invention, the target VCD file is obtained by:
generating waveform description text describing the waveform timing relationship based on the pre-constructed excitation signal waveform timing relationship;
and generating a target VCD file based on the waveform description text.
In one embodiment of the present invention, after generating the excitation signal according to the waveform timing relationship, the method further includes:
Performing simulation test on the DUT to be designed based on the generated excitation signal;
Collecting the output signal of the DUT;
Comparing the output signal with a desired output signal represented by desired information recorded in the target VCD file;
And stopping the simulation test under the condition that the output signal and the expected output signal do not meet the preset matching condition.
In one embodiment of the present invention, the comparing the output signal with the desired output signal represented by the desired information recorded in the target VCD file includes:
and comparing the output signal with a desired output signal represented by desired information recorded in the target VCD file when the output signal is a non-preset ignore signal.
In one embodiment of the present invention, after generating the excitation signal according to the waveform timing relationship, the method further includes:
Determining the corresponding relation between different excitation signals and different interfaces of the DUT;
and inputting an excitation signal into the interface of the corresponding DUT according to the corresponding relation, and performing simulation test on the DUT.
In a second aspect, an embodiment of the present invention provides an excitation signal generating device applied to a chip test apparatus, where the device includes:
the acquisition module is used for acquiring a target value change dump VCD file;
The first determining module is used for determining the moment when the level value of the excitation signal changes and the level value after the change according to the waveform information of the excitation signal recorded in the target VCD file, and determining the waveform time sequence relation of the excitation signal;
And the generating module is used for generating an excitation signal according to the waveform time sequence relation.
In one embodiment of the present invention, the acquiring module is specifically configured to:
generating waveform description text describing the waveform timing relationship based on the pre-constructed excitation signal waveform timing relationship;
and generating a target VCD file based on the waveform description text.
In one embodiment of the present invention, the apparatus further includes:
the first test module is used for performing simulation test on the design DUT to be tested based on the generated excitation signals;
the acquisition module is used for acquiring the output signal of the DUT;
the comparison module is used for comparing the output signal with an expected output signal represented by expected information recorded in the target VCD file;
And the stopping module is used for stopping the simulation test under the condition that the output signal and the expected output signal do not meet the preset matching condition.
In one embodiment of the present invention, the comparison module is specifically configured to:
and comparing the output signal with a desired output signal represented by desired information recorded in the target VCD file when the output signal is a non-preset ignore signal.
In one embodiment of the present invention, the apparatus further includes:
The second determining module is used for determining the corresponding relation between different excitation signals and different interfaces of the DUT;
And the second test module is used for inputting an excitation signal into the interface of the corresponding DUT according to the corresponding relation and carrying out simulation test on the DUT.
In a third aspect, an embodiment of the present invention provides a chip test apparatus, including a processor, a communication interface, a memory, and a communication bus, where the processor, the communication interface, and the memory complete communication with each other through the communication bus;
a memory for storing a computer program;
A processor for implementing the method steps of any of the first aspects when executing a program stored on a memory.
In a fourth aspect, embodiments of the present invention provide a computer readable storage medium having a computer program stored therein, the computer program implementing the method steps of any of the first aspects when executed by a processor.
The embodiment of the invention has the beneficial effects that:
The embodiment of the invention provides an excitation signal generation method, which is applied to chip test equipment and comprises the following steps: acquiring a target VCD (Value Change Dump ) file; determining the time when the level value of the excitation signal changes and the level value after the change according to the waveform information of the excitation signal recorded in the target VCD file, and determining the waveform time sequence relation of the excitation signal; and generating an excitation signal according to the waveform time sequence relation.
Therefore, in the scheme provided by the embodiment of the invention, because the moment when the excitation signal changes and the level value after the excitation signal changes are recorded in the target VCD file, the waveform time sequence relation of the excitation signal in the target VCD file can be obtained based on the moment, and the corresponding excitation signal is generated according to the waveform time sequence relation. In the whole process described above, the long-time repeated debugging programming is not needed to generate the excitation signal, and the rapid generation of the excitation signal can be realized.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by the person skilled in the art based on the present invention are included in the scope of protection of the present invention.
In simulation testing of DUTs, it is often desirable to quickly generate stimulus signals for simulation. Therefore, the embodiment of the invention provides a method and a device for generating an excitation signal, chip testing equipment and a storage medium, and the method and the device are respectively described in detail below.
First, an excitation signal generation method provided by an embodiment of the present invention is described.
Referring to fig. 1, a flowchart of a first excitation signal generation method according to an embodiment of the present invention is provided, and the method is applied to a chip test apparatus, and includes the following steps S101 to S103.
Step S101: and acquiring a target VCD file.
In simulation testing of DUTs, the VCD file is used primarily to record the change information of the signals involved in the simulation test process. Specifically, the VCD file includes time information for simulation test, definition of an excitation signal and variation information of an excitation signal value, definition of a DUT output signal and variation information of a DUT output signal value, and the like.
In some cases, a simulation test is performed on the DUT, and a VCD file corresponding to the simulation test is generated, and the VCD file may be used as the target VCD file in the embodiment of the present invention, and based on information obtained by analyzing the target VCD file, the simulation test is performed on the DUT again. If the DUT has completed a simulation test, the content of the file generated by the simulation test includes time information of the simulation test, definition of the stimulus signal, variation information of the stimulus signal value, definition of the DUT output signal, variation information of the DUT output signal value, etc., but the format of the file generated by the simulation test is not the VCD file format, for example, the file generated by the simulation test is FSDB (FAST SIGNAL DATA Base ) file, and at this time, the format of the file generated by the simulation test can be converted into the VCD file format by using a general-purpose tool according to the related art, thereby obtaining the target VCD file.
In one embodiment of the present invention, the target VCD file is obtained through the following steps a to B.
Step A: based on a pre-constructed excitation signal waveform timing relationship, a waveform description text describing the waveform timing relationship is generated.
In the embodiment of the invention, firstly, according to the preset excitation signal requirement, an excitation signal waveform time sequence relation is constructed, the excitation signal waveform time sequence relation can be embodied in the forms of graphs or tables, and the like, and the excitation signal waveform time sequence relation mainly describes the change of the level value of an excitation signal along with time. Exemplary, referring to fig. 2, a waveform timing diagram of an excitation signal according to an embodiment of the present invention is shown. In fig. 2, "clk" is a clock signal, "req" is a request signal, "res" is a response signal, "data" is a data signal, that is, a stimulus signal, where "head" represents a stimulus signal header, "body" represents a stimulus signal data body, and "tail" represents a stimulus signal tail. It can be seen that fig. 2 depicts the variation of the stimulus signal with the clock signal.
After the pre-constructed excitation signal waveform time sequence relation is obtained, analyzing the time-dependent change condition of the excitation signals in the excitation signal waveform time sequence relation, determining the excitation signals corresponding to each clock signal and other related signals, and generating waveform description text describing the excitation signal waveform time sequence relation by using a related programming language. Taking the waveform timing diagram of the excitation signal shown in fig. 2 as an example, the corresponding waveform description text can be as follows:
{signal:[
{name:’clk’,wave:’p.....|...’ },
{name:’data’,wave:’x.345x|x..,data:[‘head’,’body’]’},
{name:’req’,wave:’0.1..0|1.0’},
{name:’res’,wave:’1.....|01.’}
]}
where "signal" means "signal", "name" means "name", and "wave" means "waveform".
Specifically, the above waveform description text is only an example, and in actual situations, the generated waveform description text is not the same due to differences in format, parameters, and the like, that is, the generated waveform description text is matched with the actual situation.
For example, a waveform timing diagram of the excitation signal may be constructed using related software, such as Wavedrom, and then a waveform description text describing the waveform timing diagram may be generated using the software according to the constructed waveform timing diagram of the excitation signal.
In addition, similar to generating the corresponding waveform description text based on the preconfigured excitation signal waveform timing relationship, the waveform timing relationship of the desired output signal may also be preconfigured, and the corresponding desired output signal waveform description text may be generated; wherein the desired output signal is a signal that the DUT theoretically should output, as a result of the application of a pre-constructed excitation signal to the DUT.
And (B) step (B): and generating a target VCD file based on the waveform description text.
After the waveform description text is obtained, analyzing and determining each signal type in the waveform description text and the change relation of each signal along with a clock signal, and generating a target VCD file according to the format of the VCD file. In the case where the desired output signal waveform description text is generated, the target VCD file naturally includes information indicating the desired output signal.
Step S102: and determining the time when the level value of the excitation signal changes and the level value after the change according to the waveform information of the excitation signal recorded in the target VCD file, and determining the waveform time sequence relation of the excitation signal.
Specifically, the change condition of the excitation signal in the whole simulation test time is recorded in the target VCD file, if the level value of the excitation signal becomes 1 at time t1, the level value of the excitation signal is recorded in the target VCD file to be 1 at time t 1; after time t1, the level value of the excitation signal changes again, and when time t2 becomes 2, the level value of the excitation signal is recorded in the target VCD file, and is 2 at time t2, so that it can be known that the level value of the excitation signal is 1 between t1 and t 2. By the method, the moment when the level value of the excitation signal changes and the level value after the change can be extracted from the target VCD file, so that the waveform time sequence relation of the excitation signal is determined, and the change information of the excitation signal along with time is obtained.
Step S103: and generating an excitation signal according to the waveform time sequence relation.
After the waveform time sequence relation of the excitation signals is obtained, corresponding excitation signals can be generated according to the level values of the corresponding excitation signals at all time points in the waveform time sequence relation so as to be used for the subsequent simulation test of the DUT.
Therefore, in the scheme provided by the embodiment of the invention, because the moment when the excitation signal changes and the level value after the excitation signal changes are recorded in the target VCD file, the waveform time sequence relation of the excitation signal in the target VCD file can be obtained based on the moment, and the corresponding excitation signal is generated according to the waveform time sequence relation. In the whole process described above, the long-time repeated debugging programming is not needed to generate the excitation signal, and the rapid generation of the excitation signal can be realized. Especially for the situation of the camera scene excitation, the related technology generates excitation time by verifying language programming, but the excitation is fast in the scheme of the embodiment of the invention, so that the requirement of fast implementation of camera scene excitation items can be effectively met.
After the stimulus signal is generated, the stimulus signal is transmitted to the DUT for simulation testing of the DUT. Referring to fig. 3, a flow chart of a second excitation signal generation method according to an embodiment of the present invention, compared with the embodiment shown in fig. 1, further includes the following steps S104 to S107 after the step S103.
Step S104: simulation testing is performed on the DUT based on the generated stimulus signals.
After the stimulus signal is generated, the stimulus signal is input to the DUT and the response of the DUT under the action of the stimulus signal is tested.
Step S105: the output signal of the DUT is collected.
In the event that an stimulus signal is applied to the DUT, the DUT will respond to the stimulus signal, which the DUT processes and produces a corresponding output signal. To evaluate the test conditions on a DUT, it is necessary to collect the output signal of the DUT. A specialized output signal document can be created for storing information representative of the acquired DUT output signal.
Step S106: comparing the output signal with a desired output signal represented by desired information recorded in the target VCD file.
Specifically, the target VCD file includes not only waveform information of the excitation signal but also desired information indicating a desired output signal; the desired output signal is a signal which the DUT theoretically should output after inputting the excitation signal generated in the embodiment of the present invention to the DUT.
After the output signal of the DUT is collected in step S105, in order to verify whether the performance of the DUT meets the expectations, the collected output signal is compared with the expected output signal represented by the expected information recorded in the target VCD file, and the DUT under test is evaluated according to the comparison result.
If the DUT output signal completely matches the desired output signal represented by the desired information recorded in the target VCD file, the waveform representing the DUT output signal is aligned with the starting point of the waveform representing the desired output signal, so that it is possible to find that the two waveforms match and overlap. By way of example, the way the DUT output signal is compared to the desired output signal represented by the desired information recorded in the target VCD file may be: firstly, acquiring waveforms representing output signals of a DUT and waveforms representing expected output signals, aligning starting points of the two waveforms, recording data points with inconsistent level values of the two waveforms, and counting the number of the data points finally obtained. In addition, after the waveforms representing the output signals of the DUT, the waveforms representing the expected output signals and the starting points of the two waveforms are aligned, the time length of the inconsistent two waveform level values is counted, so that the proportion of the time length of the inconsistent two waveform level values to the whole test time length can be obtained, and specifically, the whole test time length is the time length from the start of recording the output signals of the DUT to the end of recording the output signals of the DUT.
In actual testing of the DUT, some of the output signals of the DUT are inconsequential to the DUT performance, i.e., a comparison of all of the output signals collected by the DUT is not required. In one embodiment of the present invention, the above step S106 may be implemented by the following step C.
Step C: and comparing the output signal with a desired output signal represented by desired information recorded in the target VCD file when the output signal is a non-preset ignore signal.
In testing a DUT, some output signals that are not critical to DUT performance, such as noise signals: DUTs may generate random or low amplitude noise signals during testing that typically do not significantly impact the overall performance of the device, and these noise signals are typically negligible during testing of the DUT. Or an auxiliary and debug signal: these signals are primarily used for DUT internal diagnostics or problem investigation and not for final product testing, and therefore there is no need to compare these signals to the desired output signals in DUT testing.
Specifically, the preset ignore signal can be determined according to the actual requirement, and the preset ignore signal information is stored in the configuration file. Before comparing the output signal with the expected output signal, firstly reading preset neglected signal information in the configuration file, and comparing the output signal with the expected output signal represented by the expected information recorded in the target VCD file under the condition that the output signal is confirmed to be a non-preset neglected signal.
By comparing the output signal with the expected output signal only when the output signal is a non-preset neglected signal, the comparison process of the output signal and the expected output signal can be accelerated under the condition that the evaluation result of the DUT performance is not affected, and the evaluation efficiency of the DUT performance can be improved.
Step S107: and stopping the simulation test under the condition that the output signal and the expected output signal do not meet the preset matching condition.
After comparing the output signal with the desired output signal, if the output signal is found to be consistent with the desired output signal, it is naturally indicated that the DUT under test meets the preset requirement. In practical situations, there may be a case where there is a difference between the DUT output signal and the desired output signal, and in this case, it may be determined whether the comparison result between the output signal and the desired output signal satisfies a preset matching condition.
In one example, the preset matching condition may be set as: the correlation coefficient between the waveform representing the output signal and the waveform representing the desired output signal reaches a preset correlation coefficient value, which can be set according to actual requirements. For example, the correlation coefficient may be a pearson correlation coefficient, and for the waveform representing the output signal and the waveform representing the desired output signal, data points in the two waveforms are collected respectively, and for each data point of the collected waveform, an average value of the data points is calculated, and then the data points are substituted into a pearson correlation coefficient calculation formula, so that the pearson correlation coefficient representing the waveform of the output signal and the waveform representing the desired output signal can be calculated. The closer the pearson correlation coefficient is to 1, the more similar the two waveforms are.
In another example, the above-mentioned preset matching condition may also be set as: the mean square error between the waveform representing the output signal and the waveform representing the desired output signal is less than a preset mean square error value, which may be set according to actual requirements. In particular, the smaller the mean square error between the two waveforms, the more similar the two waveforms are.
Of course, other preset matching conditions may be set as desired, provided that the preset matching conditions are effective to evaluate the difference between the DUT output signal and the desired output signal.
If the DUT output signal and the expected output signal meet a preset matching condition, the DUT to be tested meets a preset requirement; if the DUT output signal and the expected output signal do not meet the preset matching condition, the design problem of the tested DUT or other unknown errors possibly occur in the test, in this case, the simulation test of the DUT is stopped, and the design and the whole test scheme of the DUT are checked again so as to carry out the simulation test on the DUT again later.
From the above, in the scheme provided by the embodiment of the invention, simulation test is performed on the DUT by using the generated excitation signal, and the output signal of the DUT is compared with the expected output signal. If the output signal of the DUT and the expected output signal do not meet the preset matching condition, the current simulation test is stopped and simulation test resources are not occupied.
In the simulation test of the DUT, since the DUT often has multiple interfaces of different types, the requirements of the interfaces of different types on the input excitation signals are different, and for this reason, in one embodiment of the present invention, after the step S103, the following steps D and E are further included.
Step D: and determining the corresponding relation between different excitation signals and different interfaces of the DUT.
Among the different interfaces of the DUT, some interfaces may require the excitation signal to be a pulse signal and some interfaces may require the excitation signal to be a square wave signal; some interfaces may require the level range of the stimulus signal to be a first level range and some interfaces may require the level range of the stimulus signal to be a second level range; some interfaces may require the source impedance of the stimulus signal to be a first impedance value and some interfaces may require the source impedance of the stimulus signal to be a second impedance value. The requirements of this are not listed here. In summary, different interfaces of the DUT correspond to different stimulus signals.
Therefore, after obtaining a series of excitation signals, for each excitation signal, the interface of the DUT corresponding to the excitation signal needs to be determined first, so that in the subsequent simulation test, the excitation signal is transmitted to the interface of the DUT corresponding to the excitation signal, and correct excitation signal input to the DUT is ensured. Specifically, before simulation test is performed on the DUT input excitation signals, a corresponding relation configuration file indicating the corresponding relation between different excitation signals and different interfaces of the DUT is generated in advance according to the design structure of the DUT and various excitation signals required by the DUT. The corresponding relation configuration file is stored in chip test equipment for testing the DUT or a storage medium which can be read by the chip test equipment, so that the chip test equipment can read the corresponding relation configuration file in the process of testing the DUT, and the corresponding relation between different excitation signals and different interfaces of the DUT is determined.
Step E: and inputting an excitation signal into the interface of the corresponding DUT according to the corresponding relation, and performing simulation test on the DUT.
After the corresponding relation between different excitation signals and different interfaces of the DUT is determined, the chip testing equipment inputs the excitation signals into the corresponding interfaces of the DUT according to the corresponding relation, and then simulation test is carried out on the DUT.
From the above, in the scheme provided by the embodiment of the invention, the input correctness of the excitation signals can be ensured by determining the corresponding relation between different excitation signals and different interfaces of the DUT, so that the normal operation of the simulation test of the DUT is ensured.
Referring to fig. 4, a flowchart of a method for obtaining a target VCD file according to an embodiment of the present invention is shown. Two ways of obtaining the target VCD are shown in fig. 4, one is to convert FSDB files obtained in the last simulation test into target VCD files; the other is to construct the waveform timing relation of the excitation signal in advance, generate waveform description text describing the waveform timing relation, and finally generate the target VCD file based on the waveform description text.
Referring to fig. 5, a flow chart of a third excitation signal generation method according to an embodiment of the present invention is shown. The Configuration file of the CFG (Configuration information) in fig. 5 may include the Configuration information such as the preset ignore signal information, the correspondence between different excitation signals and different interfaces of the DUT, and the desired information indicating the desired output signal; the QSG (Quick Stimulus Generator ) is a subprogram running on the chip test equipment and is used for analyzing the received target VCD file and CFG configuration file, generating stimulus signals, and transmitting corresponding relation information between different stimulus signals and different interfaces of the DUT to an ITF (Interface) component through a CFG configuration channel so that each stimulus signal can be transmitted to the Interface of the corresponding DUT through the ITF component. In addition, the QSG also collects information of the output signal in the current DUT test process, and compares the output signal with an expected output signal represented by expected information recorded in a target VCD file under the condition that the output signal is a non-preset neglected signal.
Corresponding to the excitation signal generation method, the embodiment of the invention also provides an excitation signal generation device.
Referring to fig. 6, a schematic structural diagram of an excitation signal generating device according to an embodiment of the present invention is provided, where the device is applied to a chip testing apparatus, and includes:
The obtaining module 601 is configured to obtain a target VCD file.
The first determining module 602 is configured to determine, according to the waveform information of the excitation signal recorded in the target VCD file, a time when the level value of the excitation signal changes and the level value after the change, and determine a waveform timing relationship of the excitation signal.
The generating module 603 is configured to generate an excitation signal according to the waveform timing relationship.
Therefore, in the scheme provided by the embodiment of the invention, because the moment when the excitation signal changes and the level value after the excitation signal changes are recorded in the target VCD file, the waveform time sequence relation of the excitation signal in the target VCD file can be obtained based on the moment, and the corresponding excitation signal is generated according to the waveform time sequence relation. In the whole process described above, the long-time repeated debugging programming is not needed to generate the excitation signal, and the rapid generation of the excitation signal can be realized.
In one embodiment of the present invention, the obtaining module 601 is specifically configured to:
generating waveform description text describing the waveform timing relationship based on the pre-constructed excitation signal waveform timing relationship;
and generating a target VCD file based on the waveform description text.
In one embodiment of the present invention, the apparatus further includes:
A first test module 604 for performing a simulation test on the DUT based on the generated stimulus signal.
And the acquisition module 605 is used for acquiring the output signal of the DUT.
A comparing module 606, configured to compare the output signal with a desired output signal represented by desired information recorded in the target VCD file.
A stopping module 607, configured to stop the simulation test when the output signal and the expected output signal do not meet a preset matching condition.
From the above, in the scheme provided by the embodiment of the invention, simulation test is performed on the DUT by using the generated excitation signal, and the output signal of the DUT is compared with the expected output signal. If the output signal of the DUT and the expected output signal do not meet the preset matching condition, the current simulation test is stopped and simulation test resources are not occupied.
In one embodiment of the present invention, the comparison module 606 is specifically configured to:
and comparing the output signal with a desired output signal represented by desired information recorded in the target VCD file when the output signal is a non-preset ignore signal.
By comparing the output signal with the expected output signal only when the output signal is a non-preset neglected signal, the comparison process of the output signal and the expected output signal can be accelerated under the condition that the evaluation result of the DUT performance is not affected, and the evaluation efficiency of the DUT performance can be improved.
In one embodiment of the present invention, the apparatus further includes:
a second determining module 608 is configured to determine correspondence between different stimulus signals and different interfaces of the DUT.
And a second test module 609, configured to input an excitation signal to the interface of the DUT according to the correspondence relationship, and perform a simulation test on the DUT.
From the above, in the scheme provided by the embodiment of the invention, the input correctness of the excitation signals can be ensured by determining the corresponding relation between different excitation signals and different interfaces of the DUT, so that the normal operation of the simulation test of the DUT is ensured.
Referring to fig. 7, a schematic structural diagram of a chip testing device according to an embodiment of the present invention includes a processor 701, a communication interface 702, a memory 703 and a communication bus 704, where the processor 701, the communication interface 702 and the memory 703 complete communication with each other through the communication bus 704;
a memory 703 for storing a computer program;
The processor 701 is configured to implement any one of the steps of the excitation signal generation method described above when executing the program stored in the memory 703.
Therefore, in the scheme provided by the embodiment of the invention, because the moment when the excitation signal changes and the level value after the excitation signal changes are recorded in the target VCD file, the waveform time sequence relation of the excitation signal in the target VCD file can be obtained based on the moment, and the corresponding excitation signal is generated according to the waveform time sequence relation. In the whole process described above, the long-time repeated debugging programming is not needed to generate the excitation signal, and the rapid generation of the excitation signal can be realized.
The communication bus mentioned by the above-mentioned chip test apparatus may be a peripheral component interconnect standard (PERIPHERAL COMPONENT INTERCONNECT, PCI) bus or an extended industry standard architecture (Extended Industry Standard Architecture, EISA) bus, or the like. The communication bus may be classified as an address bus, a data bus, a control bus, or the like. For ease of illustration, the figures are shown with only one bold line, but not with only one bus or one type of bus.
The communication interface is used for communication between the chip testing device and other devices.
The Memory may include random access Memory (Random Access Memory, RAM) or may include Non-Volatile Memory (NVM), such as at least one disk Memory. Optionally, the memory may also be at least one memory device located remotely from the aforementioned processor.
The processor may be a general-purpose processor, including a central processing unit (Central Processing Unit, CPU), a network processor (Network Processor, NP), etc.; but may also be a digital signal Processor (DIGITAL SIGNAL Processor, DSP), application SPECIFIC INTEGRATED Circuit (ASIC), field-Programmable gate array (Field-Programmable GATE ARRAY, FPGA) or other Programmable logic device, discrete gate or transistor logic device, discrete hardware components.
In yet another embodiment of the present invention, there is also provided a computer-readable storage medium having stored therein a computer program which, when executed by a processor, implements the steps of any of the excitation signal generation methods described above.
When the computer program stored in the computer readable storage medium provided by the embodiment of the invention is used for generating the excitation signal, the time when the excitation signal changes and the level value after the excitation signal changes are recorded in the target VCD file, so that the waveform time sequence relation of the excitation signal in the target VCD file can be obtained based on the time when the excitation signal changes, and the corresponding excitation signal is generated according to the waveform time sequence relation. In the whole process described above, the long-time repeated debugging programming is not needed to generate the excitation signal, and the rapid generation of the excitation signal can be realized.
In yet another embodiment of the present invention, there is also provided a computer program product containing instructions which, when run on a computer, cause the computer to perform the excitation signal generation method of any of the above embodiments.
When the computer program product provided by the embodiment of the invention is used for generating the excitation signal, the waveform time sequence relation of the excitation signal in the target VCD file can be obtained based on the moment when the excitation signal changes and the level value after the excitation signal changes, and the corresponding excitation signal is generated according to the waveform time sequence relation. In the whole process described above, the long-time repeated debugging programming is not needed to generate the excitation signal, and the rapid generation of the excitation signal can be realized.
In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present invention, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in or transmitted from one computer-readable storage medium to another, for example, by wired (e.g., coaxial cable, optical fiber, digital Subscriber Line (DSL)), or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk Solid STATE DISK (SSD)), etc.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
In this specification, each embodiment is described in a related manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for the apparatus, chip test device, computer readable storage medium and computer program product embodiments, the description is relatively simple, as it is substantially similar to the method embodiments, and relevant places are referred to in the section of the method embodiments.
The foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.